if_ed.c revision 52783
1/* 2 * Copyright (c) 1995, David Greenman 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD: head/sys/dev/ed/if_ed.c 52783 1999-11-02 02:19:24Z jmb $ 28 */ 29 30/* 31 * Device driver for National Semiconductor DS8390/WD83C690 based ethernet 32 * adapters. By David Greenman, 29-April-1993 33 * 34 * Currently supports the Western Digital/SMC 8003 and 8013 series, 35 * the SMC Elite Ultra (8216), the 3Com 3c503, the NE1000 and NE2000, 36 * and a variety of similar clones. 37 * 38 */ 39 40#include <sys/param.h> 41#include <sys/systm.h> 42#include <sys/kernel.h> 43#include <sys/sockio.h> 44#include <sys/malloc.h> 45#include <sys/mbuf.h> 46#include <sys/socket.h> 47#include <sys/syslog.h> 48 49#include <sys/module.h> 50#include <sys/bus.h> 51 52#include <machine/bus.h> 53#include <sys/rman.h> 54#include <machine/resource.h> 55 56#include <net/ethernet.h> 57#include <net/if.h> 58#include <net/if_arp.h> 59#include <net/if_dl.h> 60#include <net/if_mib.h> 61 62#include <net/bpf.h> 63#include "opt_bdg.h" 64#ifdef BRIDGE 65#include <net/bridge.h> 66#endif 67 68#include <machine/clock.h> 69#include <machine/md_var.h> 70 71#include <dev/ed/if_edreg.h> 72#include <dev/ed/if_edvar.h> 73 74static void ed_init __P((void *)); 75static int ed_ioctl __P((struct ifnet *, u_long, caddr_t)); 76static void ed_start __P((struct ifnet *)); 77static void ed_reset __P((struct ifnet *)); 78static void ed_watchdog __P((struct ifnet *)); 79static void ed_stop __P((struct ed_softc *)); 80 81static void ds_getmcaf __P((struct ed_softc *, u_long *)); 82 83static void ed_get_packet __P((struct ed_softc *, char *, /* u_short */ int, int)); 84 85static __inline void ed_rint __P((struct ed_softc *)); 86static __inline void ed_xmit __P((struct ed_softc *)); 87static __inline char * ed_ring_copy __P((struct ed_softc *, char *, char *, 88 /* u_short */ int)); 89static void ed_hpp_set_physical_link __P((struct ed_softc *)); 90static void ed_hpp_readmem __P((struct ed_softc *, int, unsigned char *, 91 /* u_short */ int)); 92static u_short ed_hpp_write_mbufs __P((struct ed_softc *, struct mbuf *, 93 int)); 94 95static void ed_pio_readmem __P((struct ed_softc *, int, unsigned char *, 96 /* u_short */ int)); 97static void ed_pio_writemem __P((struct ed_softc *, char *, 98 /* u_short */ int, /* u_short */ int)); 99static u_short ed_pio_write_mbufs __P((struct ed_softc *, struct mbuf *, 100 int)); 101 102static void ed_setrcr __P((struct ed_softc *)); 103 104static u_long ds_crc __P((u_char *ep)); 105 106static u_short ed_get_Linksys __P((struct ed_softc *)); 107 108/* 109 * Interrupt conversion table for WD/SMC ASIC/83C584 110 */ 111static unsigned short ed_intr_val[] = { 112 9, 113 3, 114 5, 115 7, 116 10, 117 11, 118 15, 119 4 120}; 121 122/* 123 * Interrupt conversion table for 83C790 124 */ 125static unsigned short ed_790_intr_val[] = { 126 0, 127 9, 128 3, 129 5, 130 7, 131 10, 132 11, 133 15 134}; 135 136/* 137 * Interrupt conversion table for the HP PC LAN+ 138 */ 139 140static unsigned short ed_hpp_intr_val[] = { 141 0, /* 0 */ 142 0, /* 1 */ 143 0, /* 2 */ 144 3, /* 3 */ 145 4, /* 4 */ 146 5, /* 5 */ 147 6, /* 6 */ 148 7, /* 7 */ 149 0, /* 8 */ 150 9, /* 9 */ 151 10, /* 10 */ 152 11, /* 11 */ 153 12, /* 12 */ 154 0, /* 13 */ 155 0, /* 14 */ 156 15 /* 15 */ 157}; 158 159/* 160 * Generic probe routine for testing for the existance of a DS8390. 161 * Must be called after the NIC has just been reset. This routine 162 * works by looking at certain register values that are guaranteed 163 * to be initialized a certain way after power-up or reset. Seems 164 * not to currently work on the 83C690. 165 * 166 * Specifically: 167 * 168 * Register reset bits set bits 169 * Command Register (CR) TXP, STA RD2, STP 170 * Interrupt Status (ISR) RST 171 * Interrupt Mask (IMR) All bits 172 * Data Control (DCR) LAS 173 * Transmit Config. (TCR) LB1, LB0 174 * 175 * We only look at the CR and ISR registers, however, because looking at 176 * the others would require changing register pages (which would be 177 * intrusive if this isn't an 8390). 178 * 179 * Return 1 if 8390 was found, 0 if not. 180 */ 181 182int 183ed_probe_generic8390(sc) 184 struct ed_softc *sc; 185{ 186 if ((inb(sc->nic_addr + ED_P0_CR) & 187 (ED_CR_RD2 | ED_CR_TXP | ED_CR_STA | ED_CR_STP)) != 188 (ED_CR_RD2 | ED_CR_STP)) 189 return (0); 190 if ((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RST) != ED_ISR_RST) 191 return (0); 192 193 return (1); 194} 195 196/* 197 * Probe and vendor-specific initialization routine for SMC/WD80x3 boards 198 */ 199int 200ed_probe_WD80x3(dev) 201 device_t dev; 202{ 203 struct ed_softc *sc = device_get_softc(dev); 204 int error; 205 int i; 206 int flags = device_get_flags(dev); 207 u_int memsize, maddr; 208 u_char iptr, isa16bit, sum; 209 u_long conf_maddr, conf_msize, irq, junk; 210 211 error = ed_alloc_port(dev, 0, ED_WD_IO_PORTS); 212 if (error) 213 return (error); 214 215 sc->asic_addr = rman_get_start(sc->port_res); 216 sc->nic_addr = sc->asic_addr + ED_WD_NIC_OFFSET; 217 sc->is790 = 0; 218 219#ifdef TOSH_ETHER 220 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_POW); 221 DELAY(10000); 222#endif 223 224 /* 225 * Attempt to do a checksum over the station address PROM. If it 226 * fails, it's probably not a SMC/WD board. There is a problem with 227 * this, though: some clone WD boards don't pass the checksum test. 228 * Danpex boards for one. 229 */ 230 for (sum = 0, i = 0; i < 8; ++i) 231 sum += inb(sc->asic_addr + ED_WD_PROM + i); 232 233 if (sum != ED_WD_ROM_CHECKSUM_TOTAL) { 234 235 /* 236 * Checksum is invalid. This often happens with cheap WD8003E 237 * clones. In this case, the checksum byte (the eighth byte) 238 * seems to always be zero. 239 */ 240 if (inb(sc->asic_addr + ED_WD_CARD_ID) != ED_TYPE_WD8003E || 241 inb(sc->asic_addr + ED_WD_PROM + 7) != 0) 242 return (ENXIO); 243 } 244 /* reset card to force it into a known state. */ 245#ifdef TOSH_ETHER 246 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_RST | ED_WD_MSR_POW); 247#else 248 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_RST); 249#endif 250 DELAY(100); 251 outb(sc->asic_addr + ED_WD_MSR, inb(sc->asic_addr + ED_WD_MSR) & ~ED_WD_MSR_RST); 252 /* wait in the case this card is reading its EEROM */ 253 DELAY(5000); 254 255 sc->vendor = ED_VENDOR_WD_SMC; 256 sc->type = inb(sc->asic_addr + ED_WD_CARD_ID); 257 258 /* 259 * Set initial values for width/size. 260 */ 261 memsize = 8192; 262 isa16bit = 0; 263 switch (sc->type) { 264 case ED_TYPE_WD8003S: 265 sc->type_str = "WD8003S"; 266 break; 267 case ED_TYPE_WD8003E: 268 sc->type_str = "WD8003E"; 269 break; 270 case ED_TYPE_WD8003EB: 271 sc->type_str = "WD8003EB"; 272 break; 273 case ED_TYPE_WD8003W: 274 sc->type_str = "WD8003W"; 275 break; 276 case ED_TYPE_WD8013EBT: 277 sc->type_str = "WD8013EBT"; 278 memsize = 16384; 279 isa16bit = 1; 280 break; 281 case ED_TYPE_WD8013W: 282 sc->type_str = "WD8013W"; 283 memsize = 16384; 284 isa16bit = 1; 285 break; 286 case ED_TYPE_WD8013EP: /* also WD8003EP */ 287 if (inb(sc->asic_addr + ED_WD_ICR) 288 & ED_WD_ICR_16BIT) { 289 isa16bit = 1; 290 memsize = 16384; 291 sc->type_str = "WD8013EP"; 292 } else { 293 sc->type_str = "WD8003EP"; 294 } 295 break; 296 case ED_TYPE_WD8013WC: 297 sc->type_str = "WD8013WC"; 298 memsize = 16384; 299 isa16bit = 1; 300 break; 301 case ED_TYPE_WD8013EBP: 302 sc->type_str = "WD8013EBP"; 303 memsize = 16384; 304 isa16bit = 1; 305 break; 306 case ED_TYPE_WD8013EPC: 307 sc->type_str = "WD8013EPC"; 308 memsize = 16384; 309 isa16bit = 1; 310 break; 311 case ED_TYPE_SMC8216C: /* 8216 has 16K shared mem -- 8416 has 8K */ 312 case ED_TYPE_SMC8216T: 313 if (sc->type == ED_TYPE_SMC8216C) { 314 sc->type_str = "SMC8216/SMC8216C"; 315 } else { 316 sc->type_str = "SMC8216T"; 317 } 318 319 outb(sc->asic_addr + ED_WD790_HWR, 320 inb(sc->asic_addr + ED_WD790_HWR) | ED_WD790_HWR_SWH); 321 switch (inb(sc->asic_addr + ED_WD790_RAR) & ED_WD790_RAR_SZ64) { 322 case ED_WD790_RAR_SZ64: 323 memsize = 65536; 324 break; 325 case ED_WD790_RAR_SZ32: 326 memsize = 32768; 327 break; 328 case ED_WD790_RAR_SZ16: 329 memsize = 16384; 330 break; 331 case ED_WD790_RAR_SZ8: 332 /* 8216 has 16K shared mem -- 8416 has 8K */ 333 if (sc->type == ED_TYPE_SMC8216C) { 334 sc->type_str = "SMC8416C/SMC8416BT"; 335 } else { 336 sc->type_str = "SMC8416T"; 337 } 338 memsize = 8192; 339 break; 340 } 341 outb(sc->asic_addr + ED_WD790_HWR, 342 inb(sc->asic_addr + ED_WD790_HWR) & ~ED_WD790_HWR_SWH); 343 344 isa16bit = 1; 345 sc->is790 = 1; 346 break; 347#ifdef TOSH_ETHER 348 case ED_TYPE_TOSHIBA1: 349 sc->type_str = "Toshiba1"; 350 memsize = 32768; 351 isa16bit = 1; 352 break; 353 case ED_TYPE_TOSHIBA4: 354 sc->type_str = "Toshiba4"; 355 memsize = 32768; 356 isa16bit = 1; 357 break; 358#endif 359 default: 360 sc->type_str = ""; 361 break; 362 } 363 364 /* 365 * Make some adjustments to initial values depending on what is found 366 * in the ICR. 367 */ 368 if (isa16bit && (sc->type != ED_TYPE_WD8013EBT) 369#ifdef TOSH_ETHER 370 && (sc->type != ED_TYPE_TOSHIBA1) && (sc->type != ED_TYPE_TOSHIBA4) 371#endif 372 && ((inb(sc->asic_addr + ED_WD_ICR) & ED_WD_ICR_16BIT) == 0)) { 373 isa16bit = 0; 374 memsize = 8192; 375 } 376 377 error = bus_get_resource(dev, SYS_RES_MEMORY, 0, 378 &conf_maddr, &conf_msize); 379 if (error) 380 return (error); 381 382#if ED_DEBUG 383 printf("type = %x type_str=%s isa16bit=%d memsize=%d id_msize=%d\n", 384 sc->type, sc->type_str, isa16bit, memsize, conf_msize); 385 for (i = 0; i < 8; i++) 386 printf("%x -> %x\n", i, inb(sc->asic_addr + i)); 387#endif 388 389 /* 390 * Allow the user to override the autoconfiguration 391 */ 392 if (conf_msize > 1) 393 memsize = conf_msize; 394 395 maddr = conf_maddr; 396 if (maddr < 0xa0000 || maddr + memsize > 0x1000000) { 397 device_printf(dev, "Invalid ISA memory address range configured: 0x%x - 0x%x\n", 398 maddr, maddr + memsize); 399 return (ENXIO); 400 } 401 402 /* 403 * (note that if the user specifies both of the following flags that 404 * '8bit' mode intentionally has precedence) 405 */ 406 if (flags & ED_FLAGS_FORCE_16BIT_MODE) 407 isa16bit = 1; 408 if (flags & ED_FLAGS_FORCE_8BIT_MODE) 409 isa16bit = 0; 410 411 /* 412 * If possible, get the assigned interrupt number from the card and 413 * use it. 414 */ 415 if ((sc->type & ED_WD_SOFTCONFIG) && (!sc->is790)) { 416 417 /* 418 * Assemble together the encoded interrupt number. 419 */ 420 iptr = (inb(sc->asic_addr + ED_WD_ICR) & ED_WD_ICR_IR2) | 421 ((inb(sc->asic_addr + ED_WD_IRR) & 422 (ED_WD_IRR_IR0 | ED_WD_IRR_IR1)) >> 5); 423 424 /* 425 * If no interrupt specified (or "?"), use what the board tells us. 426 */ 427 error = bus_get_resource(dev, SYS_RES_IRQ, 0, 428 &irq, &junk); 429 if (error) { 430 bus_set_resource(dev, SYS_RES_IRQ, 0, 431 ed_intr_val[iptr], 1); 432 } 433 434 /* 435 * Enable the interrupt. 436 */ 437 outb(sc->asic_addr + ED_WD_IRR, 438 inb(sc->asic_addr + ED_WD_IRR) | ED_WD_IRR_IEN); 439 } 440 if (sc->is790) { 441 outb(sc->asic_addr + ED_WD790_HWR, 442 inb(sc->asic_addr + ED_WD790_HWR) | ED_WD790_HWR_SWH); 443 iptr = (((inb(sc->asic_addr + ED_WD790_GCR) & ED_WD790_GCR_IR2) >> 4) | 444 (inb(sc->asic_addr + ED_WD790_GCR) & 445 (ED_WD790_GCR_IR1 | ED_WD790_GCR_IR0)) >> 2); 446 outb(sc->asic_addr + ED_WD790_HWR, 447 inb(sc->asic_addr + ED_WD790_HWR) & ~ED_WD790_HWR_SWH); 448 449 /* 450 * If no interrupt specified (or "?"), use what the board tells us. 451 */ 452 error = bus_get_resource(dev, SYS_RES_IRQ, 0, 453 &irq, &junk); 454 if (error) { 455 bus_set_resource(dev, SYS_RES_IRQ, 0, 456 ed_790_intr_val[iptr], 1); 457 } 458 459 /* 460 * Enable interrupts. 461 */ 462 outb(sc->asic_addr + ED_WD790_ICR, 463 inb(sc->asic_addr + ED_WD790_ICR) | ED_WD790_ICR_EIL); 464 } 465 error = bus_get_resource(dev, SYS_RES_IRQ, 0, 466 &irq, &junk); 467 if (error) { 468 device_printf(dev, "%s cards don't support auto-detected/assigned interrupts.\n", 469 sc->type_str); 470 return (ENXIO); 471 } 472 sc->isa16bit = isa16bit; 473 sc->mem_shared = 1; 474 475 error = ed_alloc_memory(dev, 0, memsize); 476 if (error) { 477 printf("*** ed_alloc_memory() failed! (%d)\n", error); 478 return (error); 479 } 480 sc->mem_start = (caddr_t) rman_get_virtual(sc->mem_res); 481 482 /* 483 * allocate one xmit buffer if < 16k, two buffers otherwise 484 */ 485 if ((memsize < 16384) || 486 (flags & ED_FLAGS_NO_MULTI_BUFFERING)) { 487 sc->txb_cnt = 1; 488 } else { 489 sc->txb_cnt = 2; 490 } 491 sc->tx_page_start = ED_WD_PAGE_OFFSET; 492 sc->rec_page_start = ED_WD_PAGE_OFFSET + ED_TXBUF_SIZE * sc->txb_cnt; 493 sc->rec_page_stop = ED_WD_PAGE_OFFSET + memsize / ED_PAGE_SIZE; 494 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * sc->rec_page_start); 495 sc->mem_size = memsize; 496 sc->mem_end = sc->mem_start + memsize; 497 498 /* 499 * Get station address from on-board ROM 500 */ 501 for (i = 0; i < ETHER_ADDR_LEN; ++i) 502 sc->arpcom.ac_enaddr[i] = inb(sc->asic_addr + ED_WD_PROM + i); 503 504 /* 505 * Set upper address bits and 8/16 bit access to shared memory. 506 */ 507 if (isa16bit) { 508 if (sc->is790) { 509 sc->wd_laar_proto = inb(sc->asic_addr + ED_WD_LAAR); 510 } else { 511 sc->wd_laar_proto = ED_WD_LAAR_L16EN | 512 ((kvtop(sc->mem_start) >> 19) & ED_WD_LAAR_ADDRHI); 513 } 514 /* 515 * Enable 16bit access 516 */ 517 outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto | 518 ED_WD_LAAR_M16EN); 519 } else { 520 if (((sc->type & ED_WD_SOFTCONFIG) || 521#ifdef TOSH_ETHER 522 (sc->type == ED_TYPE_TOSHIBA1) || (sc->type == ED_TYPE_TOSHIBA4) || 523#endif 524 (sc->type == ED_TYPE_WD8013EBT)) && (!sc->is790)) { 525 sc->wd_laar_proto = (kvtop(sc->mem_start) >> 19) & 526 ED_WD_LAAR_ADDRHI; 527 outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto); 528 } 529 } 530 531 /* 532 * Set address and enable interface shared memory. 533 */ 534 if (!sc->is790) { 535#ifdef TOSH_ETHER 536 outb(sc->asic_addr + ED_WD_MSR + 1, ((kvtop(sc->mem_start) >> 8) & 0xe0) | 4); 537 outb(sc->asic_addr + ED_WD_MSR + 2, ((kvtop(sc->mem_start) >> 16) & 0x0f)); 538 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_MENB | ED_WD_MSR_POW); 539 540#else 541 outb(sc->asic_addr + ED_WD_MSR, ((kvtop(sc->mem_start) >> 13) & 542 ED_WD_MSR_ADDR) | ED_WD_MSR_MENB); 543#endif 544 sc->cr_proto = ED_CR_RD2; 545 } else { 546 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_MENB); 547 outb(sc->asic_addr + ED_WD790_HWR, (inb(sc->asic_addr + ED_WD790_HWR) | ED_WD790_HWR_SWH)); 548 outb(sc->asic_addr + ED_WD790_RAR, ((kvtop(sc->mem_start) >> 13) & 0x0f) | 549 ((kvtop(sc->mem_start) >> 11) & 0x40) | 550 (inb(sc->asic_addr + ED_WD790_RAR) & 0xb0)); 551 outb(sc->asic_addr + ED_WD790_HWR, (inb(sc->asic_addr + ED_WD790_HWR) & ~ED_WD790_HWR_SWH)); 552 sc->cr_proto = 0; 553 } 554 555#if 0 556 printf("starting memory performance test at 0x%x, size %d...\n", 557 sc->mem_start, memsize*16384); 558 for (i = 0; i < 16384; i++) 559 bzero(sc->mem_start, memsize); 560 printf("***DONE***\n"); 561#endif 562 563 /* 564 * Now zero memory and verify that it is clear 565 */ 566 bzero(sc->mem_start, memsize); 567 568 for (i = 0; i < memsize; ++i) { 569 if (sc->mem_start[i]) { 570 device_printf(dev, "failed to clear shared memory at %lx - check configuration\n", 571 kvtop(sc->mem_start + i)); 572 573 /* 574 * Disable 16 bit access to shared memory 575 */ 576 if (isa16bit) { 577 if (sc->is790) { 578 outb(sc->asic_addr + ED_WD_MSR, 0x00); 579 } 580 outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto & 581 ~ED_WD_LAAR_M16EN); 582 } 583 return (ENXIO); 584 } 585 } 586 587 /* 588 * Disable 16bit access to shared memory - we leave it 589 * disabled so that 1) machines reboot properly when the board 590 * is set 16 bit mode and there are conflicting 8bit 591 * devices/ROMS in the same 128k address space as this boards 592 * shared memory. and 2) so that other 8 bit devices with 593 * shared memory can be used in this 128k region, too. 594 */ 595 if (isa16bit) { 596 if (sc->is790) { 597 outb(sc->asic_addr + ED_WD_MSR, 0x00); 598 } 599 outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto & 600 ~ED_WD_LAAR_M16EN); 601 } 602 return (0); 603} 604 605/* 606 * Probe and vendor-specific initialization routine for 3Com 3c503 boards 607 */ 608int 609ed_probe_3Com(dev) 610 device_t dev; 611{ 612 struct ed_softc *sc = device_get_softc(dev); 613 int error; 614 int i; 615 int flags = device_get_flags(dev); 616 u_int memsize; 617 u_char isa16bit; 618 u_long conf_maddr, conf_msize, irq, junk; 619 620 error = ed_alloc_port(dev, 0, ED_3COM_IO_PORTS); 621 if (error) 622 return (error); 623 624 sc->asic_addr = rman_get_start(sc->port_res) + ED_3COM_ASIC_OFFSET; 625 sc->nic_addr = rman_get_start(sc->port_res) + ED_3COM_NIC_OFFSET; 626 627 /* 628 * Verify that the kernel configured I/O address matches the board 629 * configured address 630 */ 631 switch (inb(sc->asic_addr + ED_3COM_BCFR)) { 632 case ED_3COM_BCFR_300: 633 if (rman_get_start(sc->port_res) != 0x300) 634 return (ENXIO); 635 break; 636 case ED_3COM_BCFR_310: 637 if (rman_get_start(sc->port_res) != 0x310) 638 return (ENXIO); 639 break; 640 case ED_3COM_BCFR_330: 641 if (rman_get_start(sc->port_res) != 0x330) 642 return (ENXIO); 643 break; 644 case ED_3COM_BCFR_350: 645 if (rman_get_start(sc->port_res) != 0x350) 646 return (ENXIO); 647 break; 648 case ED_3COM_BCFR_250: 649 if (rman_get_start(sc->port_res) != 0x250) 650 return (ENXIO); 651 break; 652 case ED_3COM_BCFR_280: 653 if (rman_get_start(sc->port_res) != 0x280) 654 return (ENXIO); 655 break; 656 case ED_3COM_BCFR_2A0: 657 if (rman_get_start(sc->port_res) != 0x2a0) 658 return (ENXIO); 659 break; 660 case ED_3COM_BCFR_2E0: 661 if (rman_get_start(sc->port_res) != 0x2e0) 662 return (ENXIO); 663 break; 664 default: 665 return (ENXIO); 666 } 667 668 error = bus_get_resource(dev, SYS_RES_MEMORY, 0, 669 &conf_maddr, &conf_msize); 670 if (error) 671 return (error); 672 673 /* 674 * Verify that the kernel shared memory address matches the board 675 * configured address. 676 */ 677 switch (inb(sc->asic_addr + ED_3COM_PCFR)) { 678 case ED_3COM_PCFR_DC000: 679 if (conf_maddr != 0xdc000) 680 return (ENXIO); 681 break; 682 case ED_3COM_PCFR_D8000: 683 if (conf_maddr != 0xd8000) 684 return (ENXIO); 685 break; 686 case ED_3COM_PCFR_CC000: 687 if (conf_maddr != 0xcc000) 688 return (ENXIO); 689 break; 690 case ED_3COM_PCFR_C8000: 691 if (conf_maddr != 0xc8000) 692 return (ENXIO); 693 break; 694 default: 695 return (ENXIO); 696 } 697 698 699 /* 700 * Reset NIC and ASIC. Enable on-board transceiver throughout reset 701 * sequence because it'll lock up if the cable isn't connected if we 702 * don't. 703 */ 704 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_RST | ED_3COM_CR_XSEL); 705 706 /* 707 * Wait for a while, then un-reset it 708 */ 709 DELAY(50); 710 711 /* 712 * The 3Com ASIC defaults to rather strange settings for the CR after 713 * a reset - it's important to set it again after the following outb 714 * (this is done when we map the PROM below). 715 */ 716 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL); 717 718 /* 719 * Wait a bit for the NIC to recover from the reset 720 */ 721 DELAY(5000); 722 723 sc->vendor = ED_VENDOR_3COM; 724 sc->type_str = "3c503"; 725 sc->mem_shared = 1; 726 sc->cr_proto = ED_CR_RD2; 727 728 /* 729 * Hmmm...a 16bit 3Com board has 16k of memory, but only an 8k window 730 * to it. 731 */ 732 memsize = 8192; 733 734 /* 735 * Get station address from on-board ROM 736 */ 737 738 /* 739 * First, map ethernet address PROM over the top of where the NIC 740 * registers normally appear. 741 */ 742 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_EALO | ED_3COM_CR_XSEL); 743 744 for (i = 0; i < ETHER_ADDR_LEN; ++i) 745 sc->arpcom.ac_enaddr[i] = inb(sc->nic_addr + i); 746 747 /* 748 * Unmap PROM - select NIC registers. The proper setting of the 749 * tranceiver is set in ed_init so that the attach code is given a 750 * chance to set the default based on a compile-time config option 751 */ 752 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL); 753 754 /* 755 * Determine if this is an 8bit or 16bit board 756 */ 757 758 /* 759 * select page 0 registers 760 */ 761 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STP); 762 763 /* 764 * Attempt to clear WTS bit. If it doesn't clear, then this is a 16bit 765 * board. 766 */ 767 outb(sc->nic_addr + ED_P0_DCR, 0); 768 769 /* 770 * select page 2 registers 771 */ 772 outb(sc->nic_addr + ED_P0_CR, ED_CR_PAGE_2 | ED_CR_RD2 | ED_CR_STP); 773 774 /* 775 * The 3c503 forces the WTS bit to a one if this is a 16bit board 776 */ 777 if (inb(sc->nic_addr + ED_P2_DCR) & ED_DCR_WTS) 778 isa16bit = 1; 779 else 780 isa16bit = 0; 781 782 /* 783 * select page 0 registers 784 */ 785 outb(sc->nic_addr + ED_P2_CR, ED_CR_RD2 | ED_CR_STP); 786 787 error = ed_alloc_memory(dev, 0, memsize); 788 if (error) 789 return (error); 790 791 sc->mem_start = (caddr_t) rman_get_virtual(sc->mem_res); 792 sc->mem_size = memsize; 793 sc->mem_end = sc->mem_start + memsize; 794 795 /* 796 * We have an entire 8k window to put the transmit buffers on the 797 * 16bit boards. But since the 16bit 3c503's shared memory is only 798 * fast enough to overlap the loading of one full-size packet, trying 799 * to load more than 2 buffers can actually leave the transmitter idle 800 * during the load. So 2 seems the best value. (Although a mix of 801 * variable-sized packets might change this assumption. Nonetheless, 802 * we optimize for linear transfers of same-size packets.) 803 */ 804 if (isa16bit) { 805 if (flags & ED_FLAGS_NO_MULTI_BUFFERING) 806 sc->txb_cnt = 1; 807 else 808 sc->txb_cnt = 2; 809 810 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_16BIT; 811 sc->rec_page_start = ED_3COM_RX_PAGE_OFFSET_16BIT; 812 sc->rec_page_stop = memsize / ED_PAGE_SIZE + 813 ED_3COM_RX_PAGE_OFFSET_16BIT; 814 sc->mem_ring = sc->mem_start; 815 } else { 816 sc->txb_cnt = 1; 817 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_8BIT; 818 sc->rec_page_start = ED_TXBUF_SIZE + ED_3COM_TX_PAGE_OFFSET_8BIT; 819 sc->rec_page_stop = memsize / ED_PAGE_SIZE + 820 ED_3COM_TX_PAGE_OFFSET_8BIT; 821 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * ED_TXBUF_SIZE); 822 } 823 824 sc->isa16bit = isa16bit; 825 826 /* 827 * Initialize GA page start/stop registers. Probably only needed if 828 * doing DMA, but what the hell. 829 */ 830 outb(sc->asic_addr + ED_3COM_PSTR, sc->rec_page_start); 831 outb(sc->asic_addr + ED_3COM_PSPR, sc->rec_page_stop); 832 833 /* 834 * Set IRQ. 3c503 only allows a choice of irq 2-5. 835 */ 836 error = bus_get_resource(dev, SYS_RES_IRQ, 0, 837 &irq, &junk); 838 if (error) 839 return (error); 840 841 switch (irq) { 842 case 2: 843 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ2); 844 break; 845 case 3: 846 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ3); 847 break; 848 case 4: 849 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ4); 850 break; 851 case 5: 852 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ5); 853 break; 854 default: 855 device_printf(dev, "Invalid irq configuration (%ld) must be 3-5,9 for 3c503\n", 856 irq); 857 return (ENXIO); 858 } 859 860 /* 861 * Initialize GA configuration register. Set bank and enable shared 862 * mem. 863 */ 864 outb(sc->asic_addr + ED_3COM_GACFR, ED_3COM_GACFR_RSEL | 865 ED_3COM_GACFR_MBS0); 866 867 /* 868 * Initialize "Vector Pointer" registers. These gawd-awful things are 869 * compared to 20 bits of the address on ISA, and if they match, the 870 * shared memory is disabled. We set them to 0xffff0...allegedly the 871 * reset vector. 872 */ 873 outb(sc->asic_addr + ED_3COM_VPTR2, 0xff); 874 outb(sc->asic_addr + ED_3COM_VPTR1, 0xff); 875 outb(sc->asic_addr + ED_3COM_VPTR0, 0x00); 876 877 /* 878 * Zero memory and verify that it is clear 879 */ 880 bzero(sc->mem_start, memsize); 881 882 for (i = 0; i < memsize; ++i) 883 if (sc->mem_start[i]) { 884 device_printf(dev, "failed to clear shared memory at %lx - check configuration\n", 885 kvtop(sc->mem_start + i)); 886 return (ENXIO); 887 } 888 return (0); 889} 890 891/* 892 * Probe the Ethernet MAC addrees for PCMCIA Linksys EtherFast 10/100 893 * and compatible cards (DL10019C Ethernet controller). 894 * 895 * Note: The PAO patches try to use more memory for the card, but that 896 * seems to fail for my card. A future optimization would add this back 897 * conditionally. 898 */ 899static u_short 900ed_get_Linksys(sc) 901 struct ed_softc *sc; 902{ 903 u_char LinksysOUI1[] = {0x00, 0xe0, 0x98}; 904 u_char LinksysOUI2[] = {0x00, 0x80, 0xc8}; 905 u_char sum; 906 int i; 907 908 /* 909 * Linksys registers(offset from ASIC base) 910 * 911 * 0x04-0x09 : Physical Address Register 0-5 (PAR0-PAR5) 912 * 0x0A : Card ID Register (CIR) 913 * 0x0B : Check Sum Register (SR) 914 */ 915 for (sum = 0, i = 0x04; i < 0x0c; i++) 916 sum += inb(sc->asic_addr + i); 917 if (sum != 0xff) 918 return (0); /* invalid DL10019C */ 919 for (i = 0; i < ETHER_ADDR_LEN; i++) { 920 sc->arpcom.ac_enaddr[i] = inb(sc->asic_addr + 0x04 + i); 921 } 922 if (bcmp(sc->arpcom.ac_enaddr, LinksysOUI1, sizeof(LinksysOUI1)) && 923 bcmp(sc->arpcom.ac_enaddr, LinksysOUI2, sizeof(LinksysOUI2))) 924 return (0); 925 return (1); 926} 927 928/* 929 * Probe and vendor-specific initialization routine for NE1000/2000 boards 930 */ 931int 932ed_probe_Novell_generic(dev, port_rid, flags) 933 device_t dev; 934 int port_rid; 935 int flags; 936{ 937 struct ed_softc *sc = device_get_softc(dev); 938 u_int memsize, n; 939 u_char romdata[16], tmp; 940 static char test_pattern[32] = "THIS is A memory TEST pattern"; 941 char test_buffer[32]; 942 int linksys = 0; 943 int error; 944 945 error = ed_alloc_port(dev, port_rid, ED_NOVELL_IO_PORTS); 946 if (error) 947 return (error); 948 949 sc->asic_addr = rman_get_start(sc->port_res) + ED_NOVELL_ASIC_OFFSET; 950 sc->nic_addr = rman_get_start(sc->port_res) + ED_NOVELL_NIC_OFFSET; 951 952 /* XXX - do Novell-specific probe here */ 953 954 /* Reset the board */ 955#ifdef GWETHER 956 outb(sc->asic_addr + ED_NOVELL_RESET, 0); 957 DELAY(200); 958#endif /* GWETHER */ 959 tmp = inb(sc->asic_addr + ED_NOVELL_RESET); 960 961 /* 962 * I don't know if this is necessary; probably cruft leftover from 963 * Clarkson packet driver code. Doesn't do a thing on the boards I've 964 * tested. -DG [note that a outb(0x84, 0) seems to work here, and is 965 * non-invasive...but some boards don't seem to reset and I don't have 966 * complete documentation on what the 'right' thing to do is...so we 967 * do the invasive thing for now. Yuck.] 968 */ 969 outb(sc->asic_addr + ED_NOVELL_RESET, tmp); 970 DELAY(5000); 971 972 /* 973 * This is needed because some NE clones apparently don't reset the 974 * NIC properly (or the NIC chip doesn't reset fully on power-up) XXX 975 * - this makes the probe invasive! ...Done against my better 976 * judgement. -DLG 977 */ 978 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STP); 979 980 DELAY(5000); 981 982 /* Make sure that we really have an 8390 based board */ 983 if (!ed_probe_generic8390(sc)) 984 return (ENXIO); 985 986 sc->vendor = ED_VENDOR_NOVELL; 987 sc->mem_shared = 0; 988 sc->cr_proto = ED_CR_RD2; 989 990 /* 991 * Test the ability to read and write to the NIC memory. This has the 992 * side affect of determining if this is an NE1000 or an NE2000. 993 */ 994 995 /* 996 * This prevents packets from being stored in the NIC memory when the 997 * readmem routine turns on the start bit in the CR. 998 */ 999 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_MON); 1000 1001 /* Temporarily initialize DCR for byte operations */ 1002 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS); 1003 1004 outb(sc->nic_addr + ED_P0_PSTART, 8192 / ED_PAGE_SIZE); 1005 outb(sc->nic_addr + ED_P0_PSTOP, 16384 / ED_PAGE_SIZE); 1006 1007 sc->isa16bit = 0; 1008 1009 /* 1010 * Write a test pattern in byte mode. If this fails, then there 1011 * probably isn't any memory at 8k - which likely means that the board 1012 * is an NE2000. 1013 */ 1014 ed_pio_writemem(sc, test_pattern, 8192, sizeof(test_pattern)); 1015 ed_pio_readmem(sc, 8192, test_buffer, sizeof(test_pattern)); 1016 1017 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern)) == 0) { 1018 /* could be either an NE1000 or a Linksys ethernet controller */ 1019 linksys = ed_get_Linksys(sc); 1020 if (linksys) { 1021 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_WTS | ED_DCR_FT1 | ED_DCR_LS); 1022 sc->isa16bit = 1; 1023 sc->type = ED_TYPE_NE2000; 1024 sc->type_str = "Linksys"; 1025 } else { 1026 sc->type = ED_TYPE_NE1000; 1027 sc->type_str = "NE1000"; 1028 } 1029 } else { 1030 1031 /* neither an NE1000 nor a Linksys - try NE2000 */ 1032 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_WTS | ED_DCR_FT1 | ED_DCR_LS); 1033 outb(sc->nic_addr + ED_P0_PSTART, 16384 / ED_PAGE_SIZE); 1034 outb(sc->nic_addr + ED_P0_PSTOP, 32768 / ED_PAGE_SIZE); 1035 1036 sc->isa16bit = 1; 1037 1038 /* 1039 * Write a test pattern in word mode. If this also fails, then 1040 * we don't know what this board is. 1041 */ 1042 ed_pio_writemem(sc, test_pattern, 16384, sizeof(test_pattern)); 1043 ed_pio_readmem(sc, 16384, test_buffer, sizeof(test_pattern)); 1044 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern)) == 0) { 1045 sc->type = ED_TYPE_NE2000; 1046 sc->type_str = "NE2000"; 1047 } else { 1048 return (ENXIO); 1049 } 1050 } 1051 1052 1053 /* 8k of memory plus an additional 8k if 16bit */ 1054 memsize = 8192 + sc->isa16bit * 8192; 1055 1056#if 0 /* probably not useful - NE boards only come two ways */ 1057 /* allow kernel config file overrides */ 1058 if (isa_dev->id_msize) 1059 memsize = isa_dev->id_msize; 1060#endif 1061 1062 sc->mem_size = memsize; 1063 1064 /* NIC memory doesn't start at zero on an NE board */ 1065 /* The start address is tied to the bus width */ 1066 sc->mem_start = (char *) 8192 + sc->isa16bit * 8192; 1067 sc->mem_end = sc->mem_start + memsize; 1068 sc->tx_page_start = memsize / ED_PAGE_SIZE; 1069 1070#ifdef GWETHER 1071 { 1072 int x, i, mstart = 0, msize = 0; 1073 char pbuf0[ED_PAGE_SIZE], pbuf[ED_PAGE_SIZE], tbuf[ED_PAGE_SIZE]; 1074 1075 for (i = 0; i < ED_PAGE_SIZE; i++) 1076 pbuf0[i] = 0; 1077 1078 /* Clear all the memory. */ 1079 for (x = 1; x < 256; x++) 1080 ed_pio_writemem(sc, pbuf0, x * 256, ED_PAGE_SIZE); 1081 1082 /* Search for the start of RAM. */ 1083 for (x = 1; x < 256; x++) { 1084 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE); 1085 if (bcmp(pbuf0, tbuf, ED_PAGE_SIZE) == 0) { 1086 for (i = 0; i < ED_PAGE_SIZE; i++) 1087 pbuf[i] = 255 - x; 1088 ed_pio_writemem(sc, pbuf, x * 256, ED_PAGE_SIZE); 1089 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE); 1090 if (bcmp(pbuf, tbuf, ED_PAGE_SIZE) == 0) { 1091 mstart = x * ED_PAGE_SIZE; 1092 msize = ED_PAGE_SIZE; 1093 break; 1094 } 1095 } 1096 } 1097 1098 if (mstart == 0) { 1099 device_printf(dev, "Cannot find start of RAM.\n"); 1100 return (ENXIO); 1101 } 1102 /* Search for the start of RAM. */ 1103 for (x = (mstart / ED_PAGE_SIZE) + 1; x < 256; x++) { 1104 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE); 1105 if (bcmp(pbuf0, tbuf, ED_PAGE_SIZE) == 0) { 1106 for (i = 0; i < ED_PAGE_SIZE; i++) 1107 pbuf[i] = 255 - x; 1108 ed_pio_writemem(sc, pbuf, x * 256, ED_PAGE_SIZE); 1109 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE); 1110 if (bcmp(pbuf, tbuf, ED_PAGE_SIZE) == 0) 1111 msize += ED_PAGE_SIZE; 1112 else { 1113 break; 1114 } 1115 } else { 1116 break; 1117 } 1118 } 1119 1120 if (msize == 0) { 1121 device_printf(dev, "Cannot find any RAM, start : %d, x = %d.\n", mstart, x); 1122 return (ENXIO); 1123 } 1124 device_printf(dev, "RAM start at %d, size : %d.\n", mstart, msize); 1125 1126 sc->mem_size = msize; 1127 sc->mem_start = (char *) mstart; 1128 sc->mem_end = (char *) (msize + mstart); 1129 sc->tx_page_start = mstart / ED_PAGE_SIZE; 1130 } 1131#endif /* GWETHER */ 1132 1133 /* 1134 * Use one xmit buffer if < 16k, two buffers otherwise (if not told 1135 * otherwise). 1136 */ 1137 if ((memsize < 16384) || (flags & ED_FLAGS_NO_MULTI_BUFFERING)) 1138 sc->txb_cnt = 1; 1139 else 1140 sc->txb_cnt = 2; 1141 1142 sc->rec_page_start = sc->tx_page_start + sc->txb_cnt * ED_TXBUF_SIZE; 1143 sc->rec_page_stop = sc->tx_page_start + memsize / ED_PAGE_SIZE; 1144 1145 sc->mem_ring = sc->mem_start + sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE; 1146 1147 if (!linksys) { 1148 ed_pio_readmem(sc, 0, romdata, 16); 1149 for (n = 0; n < ETHER_ADDR_LEN; n++) 1150 sc->arpcom.ac_enaddr[n] = romdata[n * (sc->isa16bit + 1)]; 1151 } 1152 1153#ifdef GWETHER 1154 if (sc->arpcom.ac_enaddr[2] == 0x86) { 1155 sc->type_str = "Gateway AT"; 1156 } 1157#endif /* GWETHER */ 1158 1159 /* clear any pending interrupts that might have occurred above */ 1160 outb(sc->nic_addr + ED_P0_ISR, 0xff); 1161 1162 return (0); 1163} 1164 1165int 1166ed_probe_Novell(dev) 1167 device_t dev; 1168{ 1169 return ed_probe_Novell_generic(dev, 0, device_get_flags(dev)); 1170} 1171 1172#define ED_HPP_TEST_SIZE 16 1173 1174/* 1175 * Probe and vendor specific initialization for the HP PC Lan+ Cards. 1176 * (HP Part nos: 27247B and 27252A). 1177 * 1178 * The card has an asic wrapper around a DS8390 core. The asic handles 1179 * host accesses and offers both standard register IO and memory mapped 1180 * IO. Memory mapped I/O allows better performance at the expense of greater 1181 * chance of an incompatibility with existing ISA cards. 1182 * 1183 * The card has a few caveats: it isn't tolerant of byte wide accesses, only 1184 * short (16 bit) or word (32 bit) accesses are allowed. Some card revisions 1185 * don't allow 32 bit accesses; these are indicated by a bit in the software 1186 * ID register (see if_edreg.h). 1187 * 1188 * Other caveats are: we should read the MAC address only when the card 1189 * is inactive. 1190 * 1191 * For more information; please consult the CRYNWR packet driver. 1192 * 1193 * The AUI port is turned on using the "link2" option on the ifconfig 1194 * command line. 1195 */ 1196int 1197ed_probe_HP_pclanp(dev) 1198 device_t dev; 1199{ 1200 struct ed_softc *sc = device_get_softc(dev); 1201 int error; 1202 int n; /* temp var */ 1203 int memsize; /* mem on board */ 1204 u_char checksum; /* checksum of board address */ 1205 u_char irq; /* board configured IRQ */ 1206 char test_pattern[ED_HPP_TEST_SIZE]; /* read/write areas for */ 1207 char test_buffer[ED_HPP_TEST_SIZE]; /* probing card */ 1208 u_long conf_maddr, conf_msize, conf_irq, junk; 1209 1210 error = ed_alloc_port(dev, 0, ED_HPP_IO_PORTS); 1211 if (error) 1212 return (error); 1213 1214 /* Fill in basic information */ 1215 sc->asic_addr = rman_get_start(sc->port_res) + ED_HPP_ASIC_OFFSET; 1216 sc->nic_addr = rman_get_start(sc->port_res) + ED_HPP_NIC_OFFSET; 1217 sc->is790 = 0; 1218 sc->isa16bit = 0; /* the 8390 core needs to be in byte mode */ 1219 1220 /* 1221 * Look for the HP PCLAN+ signature: "0x50,0x48,0x00,0x53" 1222 */ 1223 1224 if ((inb(sc->asic_addr + ED_HPP_ID) != 0x50) || 1225 (inb(sc->asic_addr + ED_HPP_ID + 1) != 0x48) || 1226 ((inb(sc->asic_addr + ED_HPP_ID + 2) & 0xF0) != 0) || 1227 (inb(sc->asic_addr + ED_HPP_ID + 3) != 0x53)) 1228 return ENXIO; 1229 1230 /* 1231 * Read the MAC address and verify checksum on the address. 1232 */ 1233 1234 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_MAC); 1235 for (n = 0, checksum = 0; n < ETHER_ADDR_LEN; n++) 1236 checksum += (sc->arpcom.ac_enaddr[n] = 1237 inb(sc->asic_addr + ED_HPP_MAC_ADDR + n)); 1238 1239 checksum += inb(sc->asic_addr + ED_HPP_MAC_ADDR + ETHER_ADDR_LEN); 1240 1241 if (checksum != 0xFF) 1242 return ENXIO; 1243 1244 /* 1245 * Verify that the software model number is 0. 1246 */ 1247 1248 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_ID); 1249 if (((sc->hpp_id = inw(sc->asic_addr + ED_HPP_PAGE_4)) & 1250 ED_HPP_ID_SOFT_MODEL_MASK) != 0x0000) 1251 return ENXIO; 1252 1253 /* 1254 * Read in and save the current options configured on card. 1255 */ 1256 1257 sc->hpp_options = inw(sc->asic_addr + ED_HPP_OPTION); 1258 1259 sc->hpp_options |= (ED_HPP_OPTION_NIC_RESET | 1260 ED_HPP_OPTION_CHIP_RESET | 1261 ED_HPP_OPTION_ENABLE_IRQ); 1262 1263 /* 1264 * Reset the chip. This requires writing to the option register 1265 * so take care to preserve the other bits. 1266 */ 1267 1268 outw(sc->asic_addr + ED_HPP_OPTION, 1269 (sc->hpp_options & ~(ED_HPP_OPTION_NIC_RESET | 1270 ED_HPP_OPTION_CHIP_RESET))); 1271 1272 DELAY(5000); /* wait for chip reset to complete */ 1273 1274 outw(sc->asic_addr + ED_HPP_OPTION, 1275 (sc->hpp_options | (ED_HPP_OPTION_NIC_RESET | 1276 ED_HPP_OPTION_CHIP_RESET | 1277 ED_HPP_OPTION_ENABLE_IRQ))); 1278 1279 DELAY(5000); 1280 1281 if (!(inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RST)) 1282 return ENXIO; /* reset did not complete */ 1283 1284 /* 1285 * Read out configuration information. 1286 */ 1287 1288 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_HW); 1289 1290 irq = inb(sc->asic_addr + ED_HPP_HW_IRQ); 1291 1292 /* 1293 * Check for impossible IRQ. 1294 */ 1295 1296 if (irq >= (sizeof(ed_hpp_intr_val) / sizeof(ed_hpp_intr_val[0]))) 1297 return ENXIO; 1298 1299 /* 1300 * If the kernel IRQ was specified with a '?' use the cards idea 1301 * of the IRQ. If the kernel IRQ was explicitly specified, it 1302 * should match that of the hardware. 1303 */ 1304 error = bus_get_resource(dev, SYS_RES_IRQ, 0, 1305 &conf_irq, &junk); 1306 if (error) { 1307 bus_set_resource(dev, SYS_RES_IRQ, 0, 1308 ed_hpp_intr_val[irq], 1); 1309 } else { 1310 if (conf_irq != ed_hpp_intr_val[irq]) 1311 return (ENXIO); 1312 } 1313 1314 /* 1315 * Fill in softconfig info. 1316 */ 1317 1318 sc->vendor = ED_VENDOR_HP; 1319 sc->type = ED_TYPE_HP_PCLANPLUS; 1320 sc->type_str = "HP-PCLAN+"; 1321 1322 sc->mem_shared = 0; /* we DON'T have dual ported RAM */ 1323 sc->mem_start = 0; /* we use offsets inside the card RAM */ 1324 1325 sc->hpp_mem_start = NULL;/* no memory mapped I/O by default */ 1326 1327 /* 1328 * The board has 32KB of memory. Is there a way to determine 1329 * this programmatically? 1330 */ 1331 1332 memsize = 32768; 1333 1334 /* 1335 * Check if memory mapping of the I/O registers possible. 1336 */ 1337 1338 if (sc->hpp_options & ED_HPP_OPTION_MEM_ENABLE) 1339 { 1340 u_long mem_addr; 1341 1342 /* 1343 * determine the memory address from the board. 1344 */ 1345 1346 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_HW); 1347 mem_addr = (inw(sc->asic_addr + ED_HPP_HW_MEM_MAP) << 8); 1348 1349 /* 1350 * Check that the kernel specified start of memory and 1351 * hardware's idea of it match. 1352 */ 1353 error = bus_get_resource(dev, SYS_RES_MEMORY, 0, 1354 &conf_maddr, &conf_msize); 1355 if (error) 1356 return (error); 1357 1358 if (mem_addr != conf_maddr) 1359 return ENXIO; 1360 1361 error = ed_alloc_memory(dev, 0, memsize); 1362 if (error) 1363 return (error); 1364 1365 sc->hpp_mem_start = rman_get_virtual(sc->mem_res); 1366 } 1367 1368 /* 1369 * Fill in the rest of the soft config structure. 1370 */ 1371 1372 /* 1373 * The transmit page index. 1374 */ 1375 1376 sc->tx_page_start = ED_HPP_TX_PAGE_OFFSET; 1377 1378 if (device_get_flags(dev) & ED_FLAGS_NO_MULTI_BUFFERING) 1379 sc->txb_cnt = 1; 1380 else 1381 sc->txb_cnt = 2; 1382 1383 /* 1384 * Memory description 1385 */ 1386 1387 sc->mem_size = memsize; 1388 sc->mem_ring = sc->mem_start + 1389 (sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE); 1390 sc->mem_end = sc->mem_start + sc->mem_size; 1391 1392 /* 1393 * Receive area starts after the transmit area and 1394 * continues till the end of memory. 1395 */ 1396 1397 sc->rec_page_start = sc->tx_page_start + 1398 (sc->txb_cnt * ED_TXBUF_SIZE); 1399 sc->rec_page_stop = (sc->mem_size / ED_PAGE_SIZE); 1400 1401 1402 sc->cr_proto = 0; /* value works */ 1403 1404 /* 1405 * Set the wrap registers for string I/O reads. 1406 */ 1407 1408 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_HW); 1409 outw(sc->asic_addr + ED_HPP_HW_WRAP, 1410 ((sc->rec_page_start / ED_PAGE_SIZE) | 1411 (((sc->rec_page_stop / ED_PAGE_SIZE) - 1) << 8))); 1412 1413 /* 1414 * Reset the register page to normal operation. 1415 */ 1416 1417 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_PERF); 1418 1419 /* 1420 * Verify that we can read/write from adapter memory. 1421 * Create test pattern. 1422 */ 1423 1424 for (n = 0; n < ED_HPP_TEST_SIZE; n++) 1425 { 1426 test_pattern[n] = (n*n) ^ ~n; 1427 } 1428 1429#undef ED_HPP_TEST_SIZE 1430 1431 /* 1432 * Check that the memory is accessible thru the I/O ports. 1433 * Write out the contents of "test_pattern", read back 1434 * into "test_buffer" and compare the two for any 1435 * mismatch. 1436 */ 1437 1438 for (n = 0; n < (32768 / ED_PAGE_SIZE); n ++) { 1439 1440 ed_pio_writemem(sc, test_pattern, (n * ED_PAGE_SIZE), 1441 sizeof(test_pattern)); 1442 ed_pio_readmem(sc, (n * ED_PAGE_SIZE), 1443 test_buffer, sizeof(test_pattern)); 1444 1445 if (bcmp(test_pattern, test_buffer, 1446 sizeof(test_pattern))) 1447 return ENXIO; 1448 } 1449 1450 return (ED_HPP_IO_PORTS); 1451 1452} 1453 1454/* 1455 * HP PC Lan+ : Set the physical link to use AUI or TP/TL. 1456 */ 1457 1458void 1459ed_hpp_set_physical_link(struct ed_softc *sc) 1460{ 1461 struct ifnet *ifp = &sc->arpcom.ac_if; 1462 int lan_page; 1463 1464 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_LAN); 1465 lan_page = inw(sc->asic_addr + ED_HPP_PAGE_0); 1466 1467 if (ifp->if_flags & IFF_ALTPHYS) { 1468 1469 /* 1470 * Use the AUI port. 1471 */ 1472 1473 lan_page |= ED_HPP_LAN_AUI; 1474 1475 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_LAN); 1476 outw(sc->asic_addr + ED_HPP_PAGE_0, lan_page); 1477 1478 1479 } else { 1480 1481 /* 1482 * Use the ThinLan interface 1483 */ 1484 1485 lan_page &= ~ED_HPP_LAN_AUI; 1486 1487 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_LAN); 1488 outw(sc->asic_addr + ED_HPP_PAGE_0, lan_page); 1489 1490 } 1491 1492 /* 1493 * Wait for the lan card to re-initialize itself 1494 */ 1495 1496 DELAY(150000); /* wait 150 ms */ 1497 1498 /* 1499 * Restore normal pages. 1500 */ 1501 1502 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_PERF); 1503 1504} 1505 1506/* 1507 * Allocate a port resource with the given resource id. 1508 */ 1509int 1510ed_alloc_port(dev, rid, size) 1511 device_t dev; 1512 int rid; 1513 int size; 1514{ 1515 struct ed_softc *sc = device_get_softc(dev); 1516 struct resource *res; 1517 1518 res = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 1519 0ul, ~0ul, size, RF_ACTIVE); 1520 if (res) { 1521 sc->port_rid = rid; 1522 sc->port_res = res; 1523 sc->port_used = 1; 1524 return (0); 1525 } else { 1526 return (ENOENT); 1527 } 1528} 1529 1530/* 1531 * Allocate a memory resource with the given resource id. 1532 */ 1533int 1534ed_alloc_memory(dev, rid, size) 1535 device_t dev; 1536 int rid; 1537 int size; 1538{ 1539 struct ed_softc *sc = device_get_softc(dev); 1540 struct resource *res; 1541 1542 res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 1543 0ul, ~0ul, size, RF_ACTIVE); 1544 if (res) { 1545 sc->mem_rid = rid; 1546 sc->mem_res = res; 1547 sc->mem_used = 1; 1548 return (0); 1549 } else { 1550 return (ENOENT); 1551 } 1552} 1553 1554/* 1555 * Allocate an irq resource with the given resource id. 1556 */ 1557int 1558ed_alloc_irq(dev, rid, flags) 1559 device_t dev; 1560 int rid; 1561 int flags; 1562{ 1563 struct ed_softc *sc = device_get_softc(dev); 1564 struct resource *res; 1565 1566 res = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 1567 0ul, ~0ul, 1, (RF_ACTIVE | flags)); 1568 if (res) { 1569 sc->irq_rid = rid; 1570 sc->irq_res = res; 1571 return (0); 1572 } else { 1573 return (ENOENT); 1574 } 1575} 1576 1577/* 1578 * Release all resources 1579 */ 1580void 1581ed_release_resources(dev) 1582 device_t dev; 1583{ 1584 struct ed_softc *sc = device_get_softc(dev); 1585 1586 if (sc->port_res) { 1587 bus_release_resource(dev, SYS_RES_IOPORT, 1588 sc->port_rid, sc->port_res); 1589 sc->port_res = 0; 1590 } 1591 if (sc->mem_res) { 1592 bus_release_resource(dev, SYS_RES_MEMORY, 1593 sc->mem_rid, sc->mem_res); 1594 sc->mem_res = 0; 1595 } 1596 if (sc->irq_res) { 1597 bus_release_resource(dev, SYS_RES_IRQ, 1598 sc->irq_rid, sc->irq_res); 1599 sc->irq_res = 0; 1600 } 1601} 1602 1603/* 1604 * Install interface into kernel networking data structures 1605 */ 1606int 1607ed_attach(sc, unit, flags) 1608 struct ed_softc *sc; 1609 int unit; 1610 int flags; 1611{ 1612 struct ifnet *ifp = &sc->arpcom.ac_if; 1613 1614 /* 1615 * Set interface to stopped condition (reset) 1616 */ 1617 ed_stop(sc); 1618 1619 if (!ifp->if_name) { 1620 /* 1621 * Initialize ifnet structure 1622 */ 1623 ifp->if_softc = sc; 1624 ifp->if_unit = unit; 1625 ifp->if_name = "ed"; 1626 ifp->if_output = ether_output; 1627 ifp->if_start = ed_start; 1628 ifp->if_ioctl = ed_ioctl; 1629 ifp->if_watchdog = ed_watchdog; 1630 ifp->if_init = ed_init; 1631 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 1632 ifp->if_linkmib = &sc->mibdata; 1633 ifp->if_linkmiblen = sizeof sc->mibdata; 1634 /* 1635 * XXX - should do a better job. 1636 */ 1637 if (sc->is790) 1638 sc->mibdata.dot3StatsEtherChipSet = 1639 DOT3CHIPSET(dot3VendorWesternDigital, 1640 dot3ChipSetWesternDigital83C790); 1641 else 1642 sc->mibdata.dot3StatsEtherChipSet = 1643 DOT3CHIPSET(dot3VendorNational, 1644 dot3ChipSetNational8390); 1645 sc->mibdata.dot3Compliance = DOT3COMPLIANCE_COLLS; 1646 1647 /* 1648 * Set default state for ALTPHYS flag (used to disable the 1649 * tranceiver for AUI operation), based on compile-time 1650 * config option. 1651 */ 1652 if (flags & ED_FLAGS_DISABLE_TRANCEIVER) 1653 ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX | 1654 IFF_MULTICAST | IFF_ALTPHYS); 1655 else 1656 ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX | 1657 IFF_MULTICAST); 1658 1659 /* 1660 * Attach the interface 1661 */ 1662 if_attach(ifp); 1663 ether_ifattach(ifp); 1664 } 1665 /* device attach does transition from UNCONFIGURED to IDLE state */ 1666 1667 /* 1668 * Print additional info when attached 1669 */ 1670 printf("%s%d: address %6D, ", ifp->if_name, ifp->if_unit, 1671 sc->arpcom.ac_enaddr, ":"); 1672 1673 if (sc->type_str && (*sc->type_str != 0)) 1674 printf("type %s ", sc->type_str); 1675 else 1676 printf("type unknown (0x%x) ", sc->type); 1677 1678 if (sc->vendor == ED_VENDOR_HP) 1679 printf("(%s %s IO)", (sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS) ? 1680 "16-bit" : "32-bit", 1681 sc->hpp_mem_start ? "memory mapped" : "regular"); 1682 else 1683 printf("%s ", sc->isa16bit ? "(16 bit)" : "(8 bit)"); 1684 1685 printf("%s\n", (((sc->vendor == ED_VENDOR_3COM) || 1686 (sc->vendor == ED_VENDOR_HP)) && 1687 (ifp->if_flags & IFF_ALTPHYS)) ? " tranceiver disabled" : ""); 1688 1689 /* 1690 * If BPF is in the kernel, call the attach for it 1691 */ 1692 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header)); 1693 return (0); 1694} 1695 1696/* 1697 * Reset interface. 1698 */ 1699static void 1700ed_reset(ifp) 1701 struct ifnet *ifp; 1702{ 1703 struct ed_softc *sc = ifp->if_softc; 1704 int s; 1705 1706 if (sc->gone) 1707 return; 1708 s = splimp(); 1709 1710 /* 1711 * Stop interface and re-initialize. 1712 */ 1713 ed_stop(sc); 1714 ed_init(sc); 1715 1716 (void) splx(s); 1717} 1718 1719/* 1720 * Take interface offline. 1721 */ 1722static void 1723ed_stop(sc) 1724 struct ed_softc *sc; 1725{ 1726 int n = 5000; 1727 1728 if (sc->gone) 1729 return; 1730 /* 1731 * Stop everything on the interface, and select page 0 registers. 1732 */ 1733 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP); 1734 1735 /* 1736 * Wait for interface to enter stopped state, but limit # of checks to 1737 * 'n' (about 5ms). It shouldn't even take 5us on modern DS8390's, but 1738 * just in case it's an old one. 1739 */ 1740 while (((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RST) == 0) && --n); 1741} 1742 1743/* 1744 * Device timeout/watchdog routine. Entered if the device neglects to 1745 * generate an interrupt after a transmit has been started on it. 1746 */ 1747static void 1748ed_watchdog(ifp) 1749 struct ifnet *ifp; 1750{ 1751 struct ed_softc *sc = ifp->if_softc; 1752 1753 if (sc->gone) 1754 return; 1755 log(LOG_ERR, "ed%d: device timeout\n", ifp->if_unit); 1756 ifp->if_oerrors++; 1757 1758 ed_reset(ifp); 1759} 1760 1761/* 1762 * Initialize device. 1763 */ 1764static void 1765ed_init(xsc) 1766 void *xsc; 1767{ 1768 struct ed_softc *sc = xsc; 1769 struct ifnet *ifp = &sc->arpcom.ac_if; 1770 int i, s; 1771 1772 if (sc->gone) 1773 return; 1774 1775 /* address not known */ 1776 if (TAILQ_EMPTY(&ifp->if_addrhead)) /* unlikely? XXX */ 1777 return; 1778 1779 /* 1780 * Initialize the NIC in the exact order outlined in the NS manual. 1781 * This init procedure is "mandatory"...don't change what or when 1782 * things happen. 1783 */ 1784 s = splimp(); 1785 1786 /* reset transmitter flags */ 1787 sc->xmit_busy = 0; 1788 ifp->if_timer = 0; 1789 1790 sc->txb_inuse = 0; 1791 sc->txb_new = 0; 1792 sc->txb_next_tx = 0; 1793 1794 /* This variable is used below - don't move this assignment */ 1795 sc->next_packet = sc->rec_page_start + 1; 1796 1797 /* 1798 * Set interface for page 0, Remote DMA complete, Stopped 1799 */ 1800 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP); 1801 1802 if (sc->isa16bit) { 1803 1804 /* 1805 * Set FIFO threshold to 8, No auto-init Remote DMA, byte 1806 * order=80x86, word-wide DMA xfers, 1807 */ 1808 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1 | ED_DCR_WTS | ED_DCR_LS); 1809 } else { 1810 1811 /* 1812 * Same as above, but byte-wide DMA xfers 1813 */ 1814 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS); 1815 } 1816 1817 /* 1818 * Clear Remote Byte Count Registers 1819 */ 1820 outb(sc->nic_addr + ED_P0_RBCR0, 0); 1821 outb(sc->nic_addr + ED_P0_RBCR1, 0); 1822 1823 /* 1824 * For the moment, don't store incoming packets in memory. 1825 */ 1826 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_MON); 1827 1828 /* 1829 * Place NIC in internal loopback mode 1830 */ 1831 outb(sc->nic_addr + ED_P0_TCR, ED_TCR_LB0); 1832 1833 /* 1834 * Initialize transmit/receive (ring-buffer) Page Start 1835 */ 1836 outb(sc->nic_addr + ED_P0_TPSR, sc->tx_page_start); 1837 outb(sc->nic_addr + ED_P0_PSTART, sc->rec_page_start); 1838 /* Set lower bits of byte addressable framing to 0 */ 1839 if (sc->is790) 1840 outb(sc->nic_addr + 0x09, 0); 1841 1842 /* 1843 * Initialize Receiver (ring-buffer) Page Stop and Boundry 1844 */ 1845 outb(sc->nic_addr + ED_P0_PSTOP, sc->rec_page_stop); 1846 outb(sc->nic_addr + ED_P0_BNRY, sc->rec_page_start); 1847 1848 /* 1849 * Clear all interrupts. A '1' in each bit position clears the 1850 * corresponding flag. 1851 */ 1852 outb(sc->nic_addr + ED_P0_ISR, 0xff); 1853 1854 /* 1855 * Enable the following interrupts: receive/transmit complete, 1856 * receive/transmit error, and Receiver OverWrite. 1857 * 1858 * Counter overflow and Remote DMA complete are *not* enabled. 1859 */ 1860 outb(sc->nic_addr + ED_P0_IMR, 1861 ED_IMR_PRXE | ED_IMR_PTXE | ED_IMR_RXEE | ED_IMR_TXEE | ED_IMR_OVWE); 1862 1863 /* 1864 * Program Command Register for page 1 1865 */ 1866 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP); 1867 1868 /* 1869 * Copy out our station address 1870 */ 1871 for (i = 0; i < ETHER_ADDR_LEN; ++i) 1872 outb(sc->nic_addr + ED_P1_PAR(i), sc->arpcom.ac_enaddr[i]); 1873 1874 /* 1875 * Set Current Page pointer to next_packet (initialized above) 1876 */ 1877 outb(sc->nic_addr + ED_P1_CURR, sc->next_packet); 1878 1879 /* 1880 * Program Receiver Configuration Register and multicast filter. CR is 1881 * set to page 0 on return. 1882 */ 1883 ed_setrcr(sc); 1884 1885 /* 1886 * Take interface out of loopback 1887 */ 1888 outb(sc->nic_addr + ED_P0_TCR, 0); 1889 1890 /* 1891 * If this is a 3Com board, the tranceiver must be software enabled 1892 * (there is no settable hardware default). 1893 */ 1894 if (sc->vendor == ED_VENDOR_3COM) { 1895 if (ifp->if_flags & IFF_ALTPHYS) { 1896 outb(sc->asic_addr + ED_3COM_CR, 0); 1897 } else { 1898 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL); 1899 } 1900 } 1901 1902 /* 1903 * Set 'running' flag, and clear output active flag. 1904 */ 1905 ifp->if_flags |= IFF_RUNNING; 1906 ifp->if_flags &= ~IFF_OACTIVE; 1907 1908 /* 1909 * ...and attempt to start output 1910 */ 1911 ed_start(ifp); 1912 1913 (void) splx(s); 1914} 1915 1916/* 1917 * This routine actually starts the transmission on the interface 1918 */ 1919static __inline void 1920ed_xmit(sc) 1921 struct ed_softc *sc; 1922{ 1923 struct ifnet *ifp = (struct ifnet *)sc; 1924 unsigned short len; 1925 1926 if (sc->gone) 1927 return; 1928 len = sc->txb_len[sc->txb_next_tx]; 1929 1930 /* 1931 * Set NIC for page 0 register access 1932 */ 1933 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA); 1934 1935 /* 1936 * Set TX buffer start page 1937 */ 1938 outb(sc->nic_addr + ED_P0_TPSR, sc->tx_page_start + 1939 sc->txb_next_tx * ED_TXBUF_SIZE); 1940 1941 /* 1942 * Set TX length 1943 */ 1944 outb(sc->nic_addr + ED_P0_TBCR0, len); 1945 outb(sc->nic_addr + ED_P0_TBCR1, len >> 8); 1946 1947 /* 1948 * Set page 0, Remote DMA complete, Transmit Packet, and *Start* 1949 */ 1950 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_TXP | ED_CR_STA); 1951 sc->xmit_busy = 1; 1952 1953 /* 1954 * Point to next transmit buffer slot and wrap if necessary. 1955 */ 1956 sc->txb_next_tx++; 1957 if (sc->txb_next_tx == sc->txb_cnt) 1958 sc->txb_next_tx = 0; 1959 1960 /* 1961 * Set a timer just in case we never hear from the board again 1962 */ 1963 ifp->if_timer = 2; 1964} 1965 1966/* 1967 * Start output on interface. 1968 * We make two assumptions here: 1969 * 1) that the current priority is set to splimp _before_ this code 1970 * is called *and* is returned to the appropriate priority after 1971 * return 1972 * 2) that the IFF_OACTIVE flag is checked before this code is called 1973 * (i.e. that the output part of the interface is idle) 1974 */ 1975static void 1976ed_start(ifp) 1977 struct ifnet *ifp; 1978{ 1979 struct ed_softc *sc = ifp->if_softc; 1980 struct mbuf *m0, *m; 1981 caddr_t buffer; 1982 int len; 1983 1984 if (sc->gone) { 1985 printf("ed_start(%p) GONE\n",ifp); 1986 return; 1987 } 1988outloop: 1989 1990 /* 1991 * First, see if there are buffered packets and an idle transmitter - 1992 * should never happen at this point. 1993 */ 1994 if (sc->txb_inuse && (sc->xmit_busy == 0)) { 1995 printf("ed: packets buffered, but transmitter idle\n"); 1996 ed_xmit(sc); 1997 } 1998 1999 /* 2000 * See if there is room to put another packet in the buffer. 2001 */ 2002 if (sc->txb_inuse == sc->txb_cnt) { 2003 2004 /* 2005 * No room. Indicate this to the outside world and exit. 2006 */ 2007 ifp->if_flags |= IFF_OACTIVE; 2008 return; 2009 } 2010 IF_DEQUEUE(&ifp->if_snd, m); 2011 if (m == 0) { 2012 2013 /* 2014 * We are using the !OACTIVE flag to indicate to the outside 2015 * world that we can accept an additional packet rather than 2016 * that the transmitter is _actually_ active. Indeed, the 2017 * transmitter may be active, but if we haven't filled all the 2018 * buffers with data then we still want to accept more. 2019 */ 2020 ifp->if_flags &= ~IFF_OACTIVE; 2021 return; 2022 } 2023 2024 /* 2025 * Copy the mbuf chain into the transmit buffer 2026 */ 2027 2028 m0 = m; 2029 2030 /* txb_new points to next open buffer slot */ 2031 buffer = sc->mem_start + (sc->txb_new * ED_TXBUF_SIZE * ED_PAGE_SIZE); 2032 2033 if (sc->mem_shared) { 2034 2035 /* 2036 * Special case setup for 16 bit boards... 2037 */ 2038 if (sc->isa16bit) { 2039 switch (sc->vendor) { 2040 2041 /* 2042 * For 16bit 3Com boards (which have 16k of 2043 * memory), we have the xmit buffers in a 2044 * different page of memory ('page 0') - so 2045 * change pages. 2046 */ 2047 case ED_VENDOR_3COM: 2048 outb(sc->asic_addr + ED_3COM_GACFR, 2049 ED_3COM_GACFR_RSEL); 2050 break; 2051 2052 /* 2053 * Enable 16bit access to shared memory on 2054 * WD/SMC boards. 2055 */ 2056 case ED_VENDOR_WD_SMC:{ 2057 outb(sc->asic_addr + ED_WD_LAAR, 2058 sc->wd_laar_proto | ED_WD_LAAR_M16EN); 2059 if (sc->is790) { 2060 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_MENB); 2061 } 2062 break; 2063 } 2064 } 2065 } 2066 for (len = 0; m != 0; m = m->m_next) { 2067 bcopy(mtod(m, caddr_t), buffer, m->m_len); 2068 buffer += m->m_len; 2069 len += m->m_len; 2070 } 2071 2072 /* 2073 * Restore previous shared memory access 2074 */ 2075 if (sc->isa16bit) { 2076 switch (sc->vendor) { 2077 case ED_VENDOR_3COM: 2078 outb(sc->asic_addr + ED_3COM_GACFR, 2079 ED_3COM_GACFR_RSEL | ED_3COM_GACFR_MBS0); 2080 break; 2081 case ED_VENDOR_WD_SMC:{ 2082 if (sc->is790) { 2083 outb(sc->asic_addr + ED_WD_MSR, 0x00); 2084 } 2085 outb(sc->asic_addr + ED_WD_LAAR, 2086 sc->wd_laar_proto & ~ED_WD_LAAR_M16EN); 2087 break; 2088 } 2089 } 2090 } 2091 } else { 2092 len = ed_pio_write_mbufs(sc, m, (int)buffer); 2093 if (len == 0) 2094 goto outloop; 2095 } 2096 2097 sc->txb_len[sc->txb_new] = max(len, (ETHER_MIN_LEN-ETHER_CRC_LEN)); 2098 2099 sc->txb_inuse++; 2100 2101 /* 2102 * Point to next buffer slot and wrap if necessary. 2103 */ 2104 sc->txb_new++; 2105 if (sc->txb_new == sc->txb_cnt) 2106 sc->txb_new = 0; 2107 2108 if (sc->xmit_busy == 0) 2109 ed_xmit(sc); 2110 2111 /* 2112 * Tap off here if there is a bpf listener. 2113 */ 2114 if (ifp->if_bpf) { 2115 bpf_mtap(ifp, m0); 2116 } 2117 2118 m_freem(m0); 2119 2120 /* 2121 * Loop back to the top to possibly buffer more packets 2122 */ 2123 goto outloop; 2124} 2125 2126/* 2127 * Ethernet interface receiver interrupt. 2128 */ 2129static __inline void 2130ed_rint(sc) 2131 struct ed_softc *sc; 2132{ 2133 struct ifnet *ifp = &sc->arpcom.ac_if; 2134 u_char boundry; 2135 u_short len; 2136 struct ed_ring packet_hdr; 2137 char *packet_ptr; 2138 2139 if (sc->gone) 2140 return; 2141 2142 /* 2143 * Set NIC to page 1 registers to get 'current' pointer 2144 */ 2145 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA); 2146 2147 /* 2148 * 'sc->next_packet' is the logical beginning of the ring-buffer - 2149 * i.e. it points to where new data has been buffered. The 'CURR' 2150 * (current) register points to the logical end of the ring-buffer - 2151 * i.e. it points to where additional new data will be added. We loop 2152 * here until the logical beginning equals the logical end (or in 2153 * other words, until the ring-buffer is empty). 2154 */ 2155 while (sc->next_packet != inb(sc->nic_addr + ED_P1_CURR)) { 2156 2157 /* get pointer to this buffer's header structure */ 2158 packet_ptr = sc->mem_ring + 2159 (sc->next_packet - sc->rec_page_start) * ED_PAGE_SIZE; 2160 2161 /* 2162 * The byte count includes a 4 byte header that was added by 2163 * the NIC. 2164 */ 2165 if (sc->mem_shared) 2166 packet_hdr = *(struct ed_ring *) packet_ptr; 2167 else 2168 ed_pio_readmem(sc, (int)packet_ptr, (char *) &packet_hdr, 2169 sizeof(packet_hdr)); 2170 len = packet_hdr.count; 2171 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring)) || 2172 len < (ETHER_MIN_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring))) { 2173 /* 2174 * Length is a wild value. There's a good chance that 2175 * this was caused by the NIC being old and buggy. 2176 * The bug is that the length low byte is duplicated in 2177 * the high byte. Try to recalculate the length based on 2178 * the pointer to the next packet. 2179 */ 2180 /* 2181 * NOTE: sc->next_packet is pointing at the current packet. 2182 */ 2183 len &= ED_PAGE_SIZE - 1; /* preserve offset into page */ 2184 if (packet_hdr.next_packet >= sc->next_packet) { 2185 len += (packet_hdr.next_packet - sc->next_packet) * ED_PAGE_SIZE; 2186 } else { 2187 len += ((packet_hdr.next_packet - sc->rec_page_start) + 2188 (sc->rec_page_stop - sc->next_packet)) * ED_PAGE_SIZE; 2189 } 2190 /* 2191 * because buffers are aligned on 256-byte boundary, 2192 * the length computed above is off by 256 in almost 2193 * all cases. Fix it... 2194 */ 2195 if (len & 0xff) 2196 len -= 256 ; 2197 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN 2198 + sizeof(struct ed_ring))) 2199 sc->mibdata.dot3StatsFrameTooLongs++; 2200 } 2201 /* 2202 * Be fairly liberal about what we allow as a "reasonable" length 2203 * so that a [crufty] packet will make it to BPF (and can thus 2204 * be analyzed). Note that all that is really important is that 2205 * we have a length that will fit into one mbuf cluster or less; 2206 * the upper layer protocols can then figure out the length from 2207 * their own length field(s). 2208 */ 2209 if ((len > sizeof(struct ed_ring)) && 2210 (len <= MCLBYTES) && 2211 (packet_hdr.next_packet >= sc->rec_page_start) && 2212 (packet_hdr.next_packet < sc->rec_page_stop)) { 2213 /* 2214 * Go get packet. 2215 */ 2216 ed_get_packet(sc, packet_ptr + sizeof(struct ed_ring), 2217 len - sizeof(struct ed_ring), packet_hdr.rsr & ED_RSR_PHY); 2218 ifp->if_ipackets++; 2219 } else { 2220 /* 2221 * Really BAD. The ring pointers are corrupted. 2222 */ 2223 log(LOG_ERR, 2224 "ed%d: NIC memory corrupt - invalid packet length %d\n", 2225 ifp->if_unit, len); 2226 ifp->if_ierrors++; 2227 ed_reset(ifp); 2228 return; 2229 } 2230 2231 /* 2232 * Update next packet pointer 2233 */ 2234 sc->next_packet = packet_hdr.next_packet; 2235 2236 /* 2237 * Update NIC boundry pointer - being careful to keep it one 2238 * buffer behind. (as recommended by NS databook) 2239 */ 2240 boundry = sc->next_packet - 1; 2241 if (boundry < sc->rec_page_start) 2242 boundry = sc->rec_page_stop - 1; 2243 2244 /* 2245 * Set NIC to page 0 registers to update boundry register 2246 */ 2247 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA); 2248 2249 outb(sc->nic_addr + ED_P0_BNRY, boundry); 2250 2251 /* 2252 * Set NIC to page 1 registers before looping to top (prepare 2253 * to get 'CURR' current pointer) 2254 */ 2255 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA); 2256 } 2257} 2258 2259/* 2260 * Ethernet interface interrupt processor 2261 */ 2262void 2263edintr(arg) 2264 void *arg; 2265{ 2266 struct ed_softc *sc = (struct ed_softc*) arg; 2267 struct ifnet *ifp = (struct ifnet *)sc; 2268 u_char isr; 2269 2270 if (sc->gone) 2271 return; 2272 /* 2273 * Set NIC to page 0 registers 2274 */ 2275 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA); 2276 2277 /* 2278 * loop until there are no more new interrupts 2279 */ 2280 while ((isr = inb(sc->nic_addr + ED_P0_ISR)) != 0) { 2281 2282 /* 2283 * reset all the bits that we are 'acknowledging' by writing a 2284 * '1' to each bit position that was set (writing a '1' 2285 * *clears* the bit) 2286 */ 2287 outb(sc->nic_addr + ED_P0_ISR, isr); 2288 2289 /* 2290 * Handle transmitter interrupts. Handle these first because 2291 * the receiver will reset the board under some conditions. 2292 */ 2293 if (isr & (ED_ISR_PTX | ED_ISR_TXE)) { 2294 u_char collisions = inb(sc->nic_addr + ED_P0_NCR) & 0x0f; 2295 2296 /* 2297 * Check for transmit error. If a TX completed with an 2298 * error, we end up throwing the packet away. Really 2299 * the only error that is possible is excessive 2300 * collisions, and in this case it is best to allow 2301 * the automatic mechanisms of TCP to backoff the 2302 * flow. Of course, with UDP we're screwed, but this 2303 * is expected when a network is heavily loaded. 2304 */ 2305 (void) inb(sc->nic_addr + ED_P0_TSR); 2306 if (isr & ED_ISR_TXE) { 2307 u_char tsr; 2308 2309 /* 2310 * Excessive collisions (16) 2311 */ 2312 tsr = inb(sc->nic_addr + ED_P0_TSR); 2313 if ((tsr & ED_TSR_ABT) 2314 && (collisions == 0)) { 2315 2316 /* 2317 * When collisions total 16, the 2318 * P0_NCR will indicate 0, and the 2319 * TSR_ABT is set. 2320 */ 2321 collisions = 16; 2322 sc->mibdata.dot3StatsExcessiveCollisions++; 2323 sc->mibdata.dot3StatsCollFrequencies[15]++; 2324 } 2325 if (tsr & ED_TSR_OWC) 2326 sc->mibdata.dot3StatsLateCollisions++; 2327 if (tsr & ED_TSR_CDH) 2328 sc->mibdata.dot3StatsSQETestErrors++; 2329 if (tsr & ED_TSR_CRS) 2330 sc->mibdata.dot3StatsCarrierSenseErrors++; 2331 if (tsr & ED_TSR_FU) 2332 sc->mibdata.dot3StatsInternalMacTransmitErrors++; 2333 2334 /* 2335 * update output errors counter 2336 */ 2337 ifp->if_oerrors++; 2338 } else { 2339 2340 /* 2341 * Update total number of successfully 2342 * transmitted packets. 2343 */ 2344 ifp->if_opackets++; 2345 } 2346 2347 /* 2348 * reset tx busy and output active flags 2349 */ 2350 sc->xmit_busy = 0; 2351 ifp->if_flags &= ~IFF_OACTIVE; 2352 2353 /* 2354 * clear watchdog timer 2355 */ 2356 ifp->if_timer = 0; 2357 2358 /* 2359 * Add in total number of collisions on last 2360 * transmission. 2361 */ 2362 ifp->if_collisions += collisions; 2363 switch(collisions) { 2364 case 0: 2365 case 16: 2366 break; 2367 case 1: 2368 sc->mibdata.dot3StatsSingleCollisionFrames++; 2369 sc->mibdata.dot3StatsCollFrequencies[0]++; 2370 break; 2371 default: 2372 sc->mibdata.dot3StatsMultipleCollisionFrames++; 2373 sc->mibdata. 2374 dot3StatsCollFrequencies[collisions-1] 2375 ++; 2376 break; 2377 } 2378 2379 /* 2380 * Decrement buffer in-use count if not zero (can only 2381 * be zero if a transmitter interrupt occured while 2382 * not actually transmitting). If data is ready to 2383 * transmit, start it transmitting, otherwise defer 2384 * until after handling receiver 2385 */ 2386 if (sc->txb_inuse && --sc->txb_inuse) 2387 ed_xmit(sc); 2388 } 2389 2390 /* 2391 * Handle receiver interrupts 2392 */ 2393 if (isr & (ED_ISR_PRX | ED_ISR_RXE | ED_ISR_OVW)) { 2394 2395 /* 2396 * Overwrite warning. In order to make sure that a 2397 * lockup of the local DMA hasn't occurred, we reset 2398 * and re-init the NIC. The NSC manual suggests only a 2399 * partial reset/re-init is necessary - but some chips 2400 * seem to want more. The DMA lockup has been seen 2401 * only with early rev chips - Methinks this bug was 2402 * fixed in later revs. -DG 2403 */ 2404 if (isr & ED_ISR_OVW) { 2405 ifp->if_ierrors++; 2406#ifdef DIAGNOSTIC 2407 log(LOG_WARNING, 2408 "ed%d: warning - receiver ring buffer overrun\n", 2409 ifp->if_unit); 2410#endif 2411 2412 /* 2413 * Stop/reset/re-init NIC 2414 */ 2415 ed_reset(ifp); 2416 } else { 2417 2418 /* 2419 * Receiver Error. One or more of: CRC error, 2420 * frame alignment error FIFO overrun, or 2421 * missed packet. 2422 */ 2423 if (isr & ED_ISR_RXE) { 2424 u_char rsr; 2425 rsr = inb(sc->nic_addr + ED_P0_RSR); 2426 if (rsr & ED_RSR_CRC) 2427 sc->mibdata.dot3StatsFCSErrors++; 2428 if (rsr & ED_RSR_FAE) 2429 sc->mibdata.dot3StatsAlignmentErrors++; 2430 if (rsr & ED_RSR_FO) 2431 sc->mibdata.dot3StatsInternalMacReceiveErrors++; 2432 ifp->if_ierrors++; 2433#ifdef ED_DEBUG 2434 printf("ed%d: receive error %x\n", ifp->if_unit, 2435 inb(sc->nic_addr + ED_P0_RSR)); 2436#endif 2437 } 2438 2439 /* 2440 * Go get the packet(s) XXX - Doing this on an 2441 * error is dubious because there shouldn't be 2442 * any data to get (we've configured the 2443 * interface to not accept packets with 2444 * errors). 2445 */ 2446 2447 /* 2448 * Enable 16bit access to shared memory first 2449 * on WD/SMC boards. 2450 */ 2451 if (sc->isa16bit && 2452 (sc->vendor == ED_VENDOR_WD_SMC)) { 2453 2454 outb(sc->asic_addr + ED_WD_LAAR, 2455 sc->wd_laar_proto | ED_WD_LAAR_M16EN); 2456 if (sc->is790) { 2457 outb(sc->asic_addr + ED_WD_MSR, 2458 ED_WD_MSR_MENB); 2459 } 2460 } 2461 ed_rint(sc); 2462 2463 /* disable 16bit access */ 2464 if (sc->isa16bit && 2465 (sc->vendor == ED_VENDOR_WD_SMC)) { 2466 2467 if (sc->is790) { 2468 outb(sc->asic_addr + ED_WD_MSR, 0x00); 2469 } 2470 outb(sc->asic_addr + ED_WD_LAAR, 2471 sc->wd_laar_proto & ~ED_WD_LAAR_M16EN); 2472 } 2473 } 2474 } 2475 2476 /* 2477 * If it looks like the transmitter can take more data, 2478 * attempt to start output on the interface. This is done 2479 * after handling the receiver to give the receiver priority. 2480 */ 2481 if ((ifp->if_flags & IFF_OACTIVE) == 0) 2482 ed_start(ifp); 2483 2484 /* 2485 * return NIC CR to standard state: page 0, remote DMA 2486 * complete, start (toggling the TXP bit off, even if was just 2487 * set in the transmit routine, is *okay* - it is 'edge' 2488 * triggered from low to high) 2489 */ 2490 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA); 2491 2492 /* 2493 * If the Network Talley Counters overflow, read them to reset 2494 * them. It appears that old 8390's won't clear the ISR flag 2495 * otherwise - resulting in an infinite loop. 2496 */ 2497 if (isr & ED_ISR_CNT) { 2498 (void) inb(sc->nic_addr + ED_P0_CNTR0); 2499 (void) inb(sc->nic_addr + ED_P0_CNTR1); 2500 (void) inb(sc->nic_addr + ED_P0_CNTR2); 2501 } 2502 } 2503} 2504 2505/* 2506 * Process an ioctl request. This code needs some work - it looks 2507 * pretty ugly. 2508 */ 2509static int 2510ed_ioctl(ifp, command, data) 2511 register struct ifnet *ifp; 2512 u_long command; 2513 caddr_t data; 2514{ 2515 struct ed_softc *sc = ifp->if_softc; 2516 int s, error = 0; 2517 2518 if (sc->gone) { 2519 ifp->if_flags &= ~IFF_RUNNING; 2520 return ENXIO; 2521 } 2522 s = splimp(); 2523 2524 switch (command) { 2525 2526 case SIOCSIFADDR: 2527 case SIOCGIFADDR: 2528 case SIOCSIFMTU: 2529 error = ether_ioctl(ifp, command, data); 2530 break; 2531 2532 case SIOCSIFFLAGS: 2533 2534 /* 2535 * If the interface is marked up and stopped, then start it. 2536 * If it is marked down and running, then stop it. 2537 */ 2538 if (ifp->if_flags & IFF_UP) { 2539 if ((ifp->if_flags & IFF_RUNNING) == 0) 2540 ed_init(sc); 2541 } else { 2542 if (ifp->if_flags & IFF_RUNNING) { 2543 ed_stop(sc); 2544 ifp->if_flags &= ~IFF_RUNNING; 2545 } 2546 } 2547 2548 /* 2549 * Promiscuous flag may have changed, so reprogram the RCR. 2550 */ 2551 ed_setrcr(sc); 2552 2553 /* 2554 * An unfortunate hack to provide the (required) software 2555 * control of the tranceiver for 3Com boards. The ALTPHYS flag 2556 * disables the tranceiver if set. 2557 */ 2558 if (sc->vendor == ED_VENDOR_3COM) { 2559 if (ifp->if_flags & IFF_ALTPHYS) { 2560 outb(sc->asic_addr + ED_3COM_CR, 0); 2561 } else { 2562 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL); 2563 } 2564 } else if (sc->vendor == ED_VENDOR_HP) 2565 ed_hpp_set_physical_link(sc); 2566 break; 2567 2568 case SIOCADDMULTI: 2569 case SIOCDELMULTI: 2570 /* 2571 * Multicast list has changed; set the hardware filter 2572 * accordingly. 2573 */ 2574 ed_setrcr(sc); 2575 error = 0; 2576 break; 2577 2578 default: 2579 error = EINVAL; 2580 } 2581 (void) splx(s); 2582 return (error); 2583} 2584 2585/* 2586 * Given a source and destination address, copy 'amount' of a packet from 2587 * the ring buffer into a linear destination buffer. Takes into account 2588 * ring-wrap. 2589 */ 2590static __inline char * 2591ed_ring_copy(sc, src, dst, amount) 2592 struct ed_softc *sc; 2593 char *src; 2594 char *dst; 2595 u_short amount; 2596{ 2597 u_short tmp_amount; 2598 2599 /* does copy wrap to lower addr in ring buffer? */ 2600 if (src + amount > sc->mem_end) { 2601 tmp_amount = sc->mem_end - src; 2602 2603 /* copy amount up to end of NIC memory */ 2604 if (sc->mem_shared) 2605 bcopy(src, dst, tmp_amount); 2606 else 2607 ed_pio_readmem(sc, (int)src, dst, tmp_amount); 2608 2609 amount -= tmp_amount; 2610 src = sc->mem_ring; 2611 dst += tmp_amount; 2612 } 2613 if (sc->mem_shared) 2614 bcopy(src, dst, amount); 2615 else 2616 ed_pio_readmem(sc, (int)src, dst, amount); 2617 2618 return (src + amount); 2619} 2620 2621/* 2622 * Retreive packet from shared memory and send to the next level up via 2623 * ether_input(). If there is a BPF listener, give a copy to BPF, too. 2624 */ 2625static void 2626ed_get_packet(sc, buf, len, multicast) 2627 struct ed_softc *sc; 2628 char *buf; 2629 u_short len; 2630 int multicast; 2631{ 2632 struct ether_header *eh; 2633 struct mbuf *m; 2634 2635 /* Allocate a header mbuf */ 2636 MGETHDR(m, M_DONTWAIT, MT_DATA); 2637 if (m == NULL) 2638 return; 2639 m->m_pkthdr.rcvif = &sc->arpcom.ac_if; 2640 m->m_pkthdr.len = m->m_len = len; 2641 2642 /* 2643 * We always put the received packet in a single buffer - 2644 * either with just an mbuf header or in a cluster attached 2645 * to the header. The +2 is to compensate for the alignment 2646 * fixup below. 2647 */ 2648 if ((len + 2) > MHLEN) { 2649 /* Attach an mbuf cluster */ 2650 MCLGET(m, M_DONTWAIT); 2651 2652 /* Insist on getting a cluster */ 2653 if ((m->m_flags & M_EXT) == 0) { 2654 m_freem(m); 2655 return; 2656 } 2657 } 2658 2659 /* 2660 * The +2 is to longword align the start of the real packet. 2661 * This is important for NFS. 2662 */ 2663 m->m_data += 2; 2664 eh = mtod(m, struct ether_header *); 2665 2666#ifdef BRIDGE 2667 /* 2668 * Get link layer header, invoke brige_in, then 2669 * depending on the outcome of the test fetch the rest of the 2670 * packet and either pass up or call bdg_forward. 2671 */ 2672 if (do_bridge) { 2673 struct ifnet *ifp ; 2674 int need_more = 1 ; /* in case not bpf */ 2675 2676 if (sc->arpcom.ac_if.if_bpf) { 2677 need_more = 0 ; 2678 ed_ring_copy(sc, buf, (char *)eh, len); 2679 bpf_mtap(&sc->arpcom.ac_if, m); 2680 } else 2681 ed_ring_copy(sc, buf, (char *)eh, 14); 2682 ifp = bridge_in(m); 2683 if (ifp == BDG_DROP) { 2684 m_freem(m); 2685 return ; 2686 } 2687 /* else fetch rest of pkt and continue */ 2688 if (need_more && len > 14) 2689 ed_ring_copy(sc, buf+14, (char *)(eh+1), len - 14); 2690 if (ifp != BDG_LOCAL ) 2691 bdg_forward(&m, ifp); /* not local, need forwarding */ 2692 if (ifp == BDG_LOCAL || ifp == BDG_BCAST || ifp == BDG_MCAST) 2693 goto getit ; 2694 /* not local and not multicast, just drop it */ 2695 if (m) 2696 m_freem(m); 2697 return ; 2698 } 2699#endif 2700 /* 2701 * Get packet, including link layer address, from interface. 2702 */ 2703 ed_ring_copy(sc, buf, (char *)eh, len); 2704 2705 /* 2706 * Check if there's a BPF listener on this interface. If so, hand off 2707 * the raw packet to bpf. 2708 */ 2709 if (sc->arpcom.ac_if.if_bpf) 2710 bpf_mtap(&sc->arpcom.ac_if, m); 2711 /* 2712 * If we are in promiscuous mode, we have to check whether 2713 * this packet is really for us. 2714 */ 2715 if ((sc->arpcom.ac_if.if_flags & IFF_PROMISC) && 2716 bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr, 2717 sizeof(eh->ether_dhost)) != 0 && multicast == 0) { 2718 m_freem(m); 2719 return; 2720 } 2721 2722#ifdef BRIDGE 2723getit: 2724#endif 2725 /* 2726 * Remove link layer address. 2727 */ 2728 m->m_pkthdr.len = m->m_len = len - sizeof(struct ether_header); 2729 m->m_data += sizeof(struct ether_header); 2730 2731 ether_input(&sc->arpcom.ac_if, eh, m); 2732 return; 2733} 2734 2735/* 2736 * Supporting routines 2737 */ 2738 2739/* 2740 * Given a NIC memory source address and a host memory destination 2741 * address, copy 'amount' from NIC to host using Programmed I/O. 2742 * The 'amount' is rounded up to a word - okay as long as mbufs 2743 * are word sized. 2744 * This routine is currently Novell-specific. 2745 */ 2746static void 2747ed_pio_readmem(sc, src, dst, amount) 2748 struct ed_softc *sc; 2749 int src; 2750 unsigned char *dst; 2751 unsigned short amount; 2752{ 2753 /* HP cards need special handling */ 2754 if (sc->vendor == ED_VENDOR_HP && sc->type == ED_TYPE_HP_PCLANPLUS) { 2755 ed_hpp_readmem(sc, src, dst, amount); 2756 return; 2757 } 2758 2759 /* Regular Novell cards */ 2760 /* select page 0 registers */ 2761 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STA); 2762 2763 /* round up to a word */ 2764 if (amount & 1) 2765 ++amount; 2766 2767 /* set up DMA byte count */ 2768 outb(sc->nic_addr + ED_P0_RBCR0, amount); 2769 outb(sc->nic_addr + ED_P0_RBCR1, amount >> 8); 2770 2771 /* set up source address in NIC mem */ 2772 outb(sc->nic_addr + ED_P0_RSAR0, src); 2773 outb(sc->nic_addr + ED_P0_RSAR1, src >> 8); 2774 2775 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD0 | ED_CR_STA); 2776 2777 if (sc->isa16bit) { 2778 insw(sc->asic_addr + ED_NOVELL_DATA, dst, amount / 2); 2779 } else 2780 insb(sc->asic_addr + ED_NOVELL_DATA, dst, amount); 2781 2782} 2783 2784/* 2785 * Stripped down routine for writing a linear buffer to NIC memory. 2786 * Only used in the probe routine to test the memory. 'len' must 2787 * be even. 2788 */ 2789static void 2790ed_pio_writemem(sc, src, dst, len) 2791 struct ed_softc *sc; 2792 char *src; 2793 unsigned short dst; 2794 unsigned short len; 2795{ 2796 int maxwait = 200; /* about 240us */ 2797 2798 if (sc->vendor == ED_VENDOR_NOVELL) { 2799 2800 /* select page 0 registers */ 2801 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STA); 2802 2803 /* reset remote DMA complete flag */ 2804 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC); 2805 2806 /* set up DMA byte count */ 2807 outb(sc->nic_addr + ED_P0_RBCR0, len); 2808 outb(sc->nic_addr + ED_P0_RBCR1, len >> 8); 2809 2810 /* set up destination address in NIC mem */ 2811 outb(sc->nic_addr + ED_P0_RSAR0, dst); 2812 outb(sc->nic_addr + ED_P0_RSAR1, dst >> 8); 2813 2814 /* set remote DMA write */ 2815 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD1 | ED_CR_STA); 2816 2817 if (sc->isa16bit) 2818 outsw(sc->asic_addr + ED_NOVELL_DATA, src, len / 2); 2819 else 2820 outsb(sc->asic_addr + ED_NOVELL_DATA, src, len); 2821 2822 /* 2823 * Wait for remote DMA complete. This is necessary because on the 2824 * transmit side, data is handled internally by the NIC in bursts and 2825 * we can't start another remote DMA until this one completes. Not 2826 * waiting causes really bad things to happen - like the NIC 2827 * irrecoverably jamming the ISA bus. 2828 */ 2829 while (((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait); 2830 2831 } else if ((sc->vendor == ED_VENDOR_HP) && 2832 (sc->type == ED_TYPE_HP_PCLANPLUS)) { 2833 2834 /* HP PCLAN+ */ 2835 2836 /* reset remote DMA complete flag */ 2837 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC); 2838 2839 /* program the write address in RAM */ 2840 outw(sc->asic_addr + ED_HPP_PAGE_0, dst); 2841 2842 if (sc->hpp_mem_start) { 2843 u_short *s = (u_short *) src; 2844 volatile u_short *d = (u_short *) sc->hpp_mem_start; 2845 u_short *const fence = s + (len >> 1); 2846 2847 /* 2848 * Enable memory mapped access. 2849 */ 2850 2851 outw(sc->asic_addr + ED_HPP_OPTION, 2852 sc->hpp_options & 2853 ~(ED_HPP_OPTION_MEM_DISABLE | 2854 ED_HPP_OPTION_BOOT_ROM_ENB)); 2855 2856 /* 2857 * Copy to NIC memory. 2858 */ 2859 2860 while (s < fence) 2861 *d = *s++; 2862 2863 /* 2864 * Restore Boot ROM access. 2865 */ 2866 2867 outw(sc->asic_addr + ED_HPP_OPTION, 2868 sc->hpp_options); 2869 2870 } else { 2871 /* write data using I/O writes */ 2872 outsw(sc->asic_addr + ED_HPP_PAGE_4, src, len / 2); 2873 } 2874 2875 } 2876} 2877 2878/* 2879 * Write an mbuf chain to the destination NIC memory address using 2880 * programmed I/O. 2881 */ 2882static u_short 2883ed_pio_write_mbufs(sc, m, dst) 2884 struct ed_softc *sc; 2885 struct mbuf *m; 2886 int dst; 2887{ 2888 struct ifnet *ifp = (struct ifnet *)sc; 2889 unsigned short total_len, dma_len; 2890 struct mbuf *mp; 2891 int maxwait = 200; /* about 240us */ 2892 2893 /* HP PC Lan+ cards need special handling */ 2894 if ((sc->vendor == ED_VENDOR_HP) && 2895 (sc->type == ED_TYPE_HP_PCLANPLUS)) { 2896 return ed_hpp_write_mbufs(sc, m, dst); 2897 } 2898 2899 /* First, count up the total number of bytes to copy */ 2900 for (total_len = 0, mp = m; mp; mp = mp->m_next) 2901 total_len += mp->m_len; 2902 2903 dma_len = total_len; 2904 if (sc->isa16bit && (dma_len & 1)) 2905 dma_len++; 2906 2907 /* select page 0 registers */ 2908 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STA); 2909 2910 /* reset remote DMA complete flag */ 2911 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC); 2912 2913 /* set up DMA byte count */ 2914 outb(sc->nic_addr + ED_P0_RBCR0, dma_len); 2915 outb(sc->nic_addr + ED_P0_RBCR1, dma_len >> 8); 2916 2917 /* set up destination address in NIC mem */ 2918 outb(sc->nic_addr + ED_P0_RSAR0, dst); 2919 outb(sc->nic_addr + ED_P0_RSAR1, dst >> 8); 2920 2921 /* set remote DMA write */ 2922 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD1 | ED_CR_STA); 2923 2924 /* 2925 * Transfer the mbuf chain to the NIC memory. 2926 * 16-bit cards require that data be transferred as words, and only words. 2927 * So that case requires some extra code to patch over odd-length mbufs. 2928 */ 2929 2930 if (!sc->isa16bit) { 2931 /* NE1000s are easy */ 2932 while (m) { 2933 if (m->m_len) { 2934 outsb(sc->asic_addr + ED_NOVELL_DATA, 2935 m->m_data, m->m_len); 2936 } 2937 m = m->m_next; 2938 } 2939 } else { 2940 /* NE2000s are a pain */ 2941 unsigned char *data; 2942 int len, wantbyte; 2943 unsigned char savebyte[2]; 2944 2945 wantbyte = 0; 2946 2947 while (m) { 2948 len = m->m_len; 2949 if (len) { 2950 data = mtod(m, caddr_t); 2951 /* finish the last word */ 2952 if (wantbyte) { 2953 savebyte[1] = *data; 2954 outw(sc->asic_addr + ED_NOVELL_DATA, *(u_short *)savebyte); 2955 data++; 2956 len--; 2957 wantbyte = 0; 2958 } 2959 /* output contiguous words */ 2960 if (len > 1) { 2961 outsw(sc->asic_addr + ED_NOVELL_DATA, 2962 data, len >> 1); 2963 data += len & ~1; 2964 len &= 1; 2965 } 2966 /* save last byte, if necessary */ 2967 if (len == 1) { 2968 savebyte[0] = *data; 2969 wantbyte = 1; 2970 } 2971 } 2972 m = m->m_next; 2973 } 2974 /* spit last byte */ 2975 if (wantbyte) { 2976 outw(sc->asic_addr + ED_NOVELL_DATA, *(u_short *)savebyte); 2977 } 2978 } 2979 2980 /* 2981 * Wait for remote DMA complete. This is necessary because on the 2982 * transmit side, data is handled internally by the NIC in bursts and 2983 * we can't start another remote DMA until this one completes. Not 2984 * waiting causes really bad things to happen - like the NIC 2985 * irrecoverably jamming the ISA bus. 2986 */ 2987 while (((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait); 2988 2989 if (!maxwait) { 2990 log(LOG_WARNING, "ed%d: remote transmit DMA failed to complete\n", 2991 ifp->if_unit); 2992 ed_reset(ifp); 2993 return(0); 2994 } 2995 return (total_len); 2996} 2997 2998/* 2999 * Support routines to handle the HP PC Lan+ card. 3000 */ 3001 3002/* 3003 * HP PC Lan+: Read from NIC memory, using either PIO or memory mapped 3004 * IO. 3005 */ 3006 3007static void 3008ed_hpp_readmem(sc, src, dst, amount) 3009 struct ed_softc *sc; 3010 unsigned short src; 3011 unsigned char *dst; 3012 unsigned short amount; 3013{ 3014 3015 int use_32bit_access = !(sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS); 3016 3017 3018 /* Program the source address in RAM */ 3019 outw(sc->asic_addr + ED_HPP_PAGE_2, src); 3020 3021 /* 3022 * The HP PC Lan+ card supports word reads as well as 3023 * a memory mapped i/o port that is aliased to every 3024 * even address on the board. 3025 */ 3026 3027 if (sc->hpp_mem_start) { 3028 3029 /* Enable memory mapped access. */ 3030 outw(sc->asic_addr + ED_HPP_OPTION, 3031 sc->hpp_options & 3032 ~(ED_HPP_OPTION_MEM_DISABLE | 3033 ED_HPP_OPTION_BOOT_ROM_ENB)); 3034 3035 if (use_32bit_access && (amount > 3)) { 3036 u_long *dl = (u_long *) dst; 3037 volatile u_long *const sl = 3038 (u_long *) sc->hpp_mem_start; 3039 u_long *const fence = dl + (amount >> 2); 3040 3041 /* Copy out NIC data. We could probably write this 3042 as a `movsl'. The currently generated code is lousy. 3043 */ 3044 3045 while (dl < fence) 3046 *dl++ = *sl; 3047 3048 dst += (amount & ~3); 3049 amount &= 3; 3050 3051 } 3052 3053 /* Finish off any words left, as a series of short reads */ 3054 if (amount > 1) { 3055 u_short *d = (u_short *) dst; 3056 volatile u_short *const s = 3057 (u_short *) sc->hpp_mem_start; 3058 u_short *const fence = d + (amount >> 1); 3059 3060 /* Copy out NIC data. */ 3061 3062 while (d < fence) 3063 *d++ = *s; 3064 3065 dst += (amount & ~1); 3066 amount &= 1; 3067 } 3068 3069 /* 3070 * read in a byte; however we need to always read 16 bits 3071 * at a time or the hardware gets into a funny state 3072 */ 3073 3074 if (amount == 1) { 3075 /* need to read in a short and copy LSB */ 3076 volatile u_short *const s = 3077 (volatile u_short *) sc->hpp_mem_start; 3078 3079 *dst = (*s) & 0xFF; 3080 } 3081 3082 /* Restore Boot ROM access. */ 3083 3084 outw(sc->asic_addr + ED_HPP_OPTION, 3085 sc->hpp_options); 3086 3087 3088 } else { 3089 /* Read in data using the I/O port */ 3090 if (use_32bit_access && (amount > 3)) { 3091 insl(sc->asic_addr + ED_HPP_PAGE_4, dst, amount >> 2); 3092 dst += (amount & ~3); 3093 amount &= 3; 3094 } 3095 if (amount > 1) { 3096 insw(sc->asic_addr + ED_HPP_PAGE_4, dst, amount >> 1); 3097 dst += (amount & ~1); 3098 amount &= 1; 3099 } 3100 if (amount == 1) { /* read in a short and keep the LSB */ 3101 *dst = inw(sc->asic_addr + ED_HPP_PAGE_4) & 0xFF; 3102 } 3103 } 3104} 3105 3106/* 3107 * Write to HP PC Lan+ NIC memory. Access to the NIC can be by using 3108 * outsw() or via the memory mapped interface to the same register. 3109 * Writes have to be in word units; byte accesses won't work and may cause 3110 * the NIC to behave wierdly. Long word accesses are permitted if the ASIC 3111 * allows it. 3112 */ 3113 3114static u_short 3115ed_hpp_write_mbufs(struct ed_softc *sc, struct mbuf *m, int dst) 3116{ 3117 int len, wantbyte; 3118 unsigned short total_len; 3119 unsigned char savebyte[2]; 3120 volatile u_short * const d = 3121 (volatile u_short *) sc->hpp_mem_start; 3122 int use_32bit_accesses = !(sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS); 3123 3124 /* select page 0 registers */ 3125 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA); 3126 3127 /* reset remote DMA complete flag */ 3128 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC); 3129 3130 /* program the write address in RAM */ 3131 outw(sc->asic_addr + ED_HPP_PAGE_0, dst); 3132 3133 if (sc->hpp_mem_start) /* enable memory mapped I/O */ 3134 outw(sc->asic_addr + ED_HPP_OPTION, sc->hpp_options & 3135 ~(ED_HPP_OPTION_MEM_DISABLE | 3136 ED_HPP_OPTION_BOOT_ROM_ENB)); 3137 3138 wantbyte = 0; 3139 total_len = 0; 3140 3141 if (sc->hpp_mem_start) { /* Memory mapped I/O port */ 3142 while (m) { 3143 total_len += (len = m->m_len); 3144 if (len) { 3145 caddr_t data = mtod(m, caddr_t); 3146 /* finish the last word of the previous mbuf */ 3147 if (wantbyte) { 3148 savebyte[1] = *data; 3149 *d = *((ushort *) savebyte); 3150 data++; len--; wantbyte = 0; 3151 } 3152 /* output contiguous words */ 3153 if ((len > 3) && (use_32bit_accesses)) { 3154 volatile u_long *const dl = 3155 (volatile u_long *) d; 3156 u_long *sl = (u_long *) data; 3157 u_long *fence = sl + (len >> 2); 3158 3159 while (sl < fence) 3160 *dl = *sl++; 3161 3162 data += (len & ~3); 3163 len &= 3; 3164 } 3165 /* finish off remain 16 bit writes */ 3166 if (len > 1) { 3167 u_short *s = (u_short *) data; 3168 u_short *fence = s + (len >> 1); 3169 3170 while (s < fence) 3171 *d = *s++; 3172 3173 data += (len & ~1); 3174 len &= 1; 3175 } 3176 /* save last byte if needed */ 3177 if ((wantbyte = (len == 1)) != 0) 3178 savebyte[0] = *data; 3179 } 3180 m = m->m_next; /* to next mbuf */ 3181 } 3182 if (wantbyte) /* write last byte */ 3183 *d = *((u_short *) savebyte); 3184 } else { 3185 /* use programmed I/O */ 3186 while (m) { 3187 total_len += (len = m->m_len); 3188 if (len) { 3189 caddr_t data = mtod(m, caddr_t); 3190 /* finish the last word of the previous mbuf */ 3191 if (wantbyte) { 3192 savebyte[1] = *data; 3193 outw(sc->asic_addr + ED_HPP_PAGE_4, 3194 *((u_short *)savebyte)); 3195 data++; 3196 len--; 3197 wantbyte = 0; 3198 } 3199 /* output contiguous words */ 3200 if ((len > 3) && use_32bit_accesses) { 3201 outsl(sc->asic_addr + ED_HPP_PAGE_4, 3202 data, len >> 2); 3203 data += (len & ~3); 3204 len &= 3; 3205 } 3206 /* finish off remaining 16 bit accesses */ 3207 if (len > 1) { 3208 outsw(sc->asic_addr + ED_HPP_PAGE_4, 3209 data, len >> 1); 3210 data += (len & ~1); 3211 len &= 1; 3212 } 3213 if ((wantbyte = (len == 1)) != 0) 3214 savebyte[0] = *data; 3215 3216 } /* if len != 0 */ 3217 m = m->m_next; 3218 } 3219 if (wantbyte) /* spit last byte */ 3220 outw(sc->asic_addr + ED_HPP_PAGE_4, 3221 *(u_short *)savebyte); 3222 3223 } 3224 3225 if (sc->hpp_mem_start) /* turn off memory mapped i/o */ 3226 outw(sc->asic_addr + ED_HPP_OPTION, 3227 sc->hpp_options); 3228 3229 return (total_len); 3230} 3231 3232static void 3233ed_setrcr(sc) 3234 struct ed_softc *sc; 3235{ 3236 struct ifnet *ifp = (struct ifnet *)sc; 3237 int i; 3238 3239 /* set page 1 registers */ 3240 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP); 3241 3242 if (ifp->if_flags & IFF_PROMISC) { 3243 3244 /* 3245 * Reconfigure the multicast filter. 3246 */ 3247 for (i = 0; i < 8; i++) 3248 outb(sc->nic_addr + ED_P1_MAR(i), 0xff); 3249 3250 /* 3251 * And turn on promiscuous mode. Also enable reception of 3252 * runts and packets with CRC & alignment errors. 3253 */ 3254 /* Set page 0 registers */ 3255 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP); 3256 3257 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_PRO | ED_RCR_AM | 3258 ED_RCR_AB | ED_RCR_AR | ED_RCR_SEP); 3259 } else { 3260 /* set up multicast addresses and filter modes */ 3261 if (ifp->if_flags & IFF_MULTICAST) { 3262 u_long mcaf[2]; 3263 3264 if (ifp->if_flags & IFF_ALLMULTI) { 3265 mcaf[0] = 0xffffffff; 3266 mcaf[1] = 0xffffffff; 3267 } else 3268 ds_getmcaf(sc, mcaf); 3269 3270 /* 3271 * Set multicast filter on chip. 3272 */ 3273 for (i = 0; i < 8; i++) 3274 outb(sc->nic_addr + ED_P1_MAR(i), ((u_char *) mcaf)[i]); 3275 3276 /* Set page 0 registers */ 3277 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP); 3278 3279 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_AM | ED_RCR_AB); 3280 } else { 3281 3282 /* 3283 * Initialize multicast address hashing registers to 3284 * not accept multicasts. 3285 */ 3286 for (i = 0; i < 8; ++i) 3287 outb(sc->nic_addr + ED_P1_MAR(i), 0x00); 3288 3289 /* Set page 0 registers */ 3290 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP); 3291 3292 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_AB); 3293 } 3294 } 3295 3296 /* 3297 * Start interface. 3298 */ 3299 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA); 3300} 3301 3302/* 3303 * Compute crc for ethernet address 3304 */ 3305static u_long 3306ds_crc(ep) 3307 u_char *ep; 3308{ 3309#define POLYNOMIAL 0x04c11db6 3310 register u_long crc = 0xffffffffL; 3311 register int carry, i, j; 3312 register u_char b; 3313 3314 for (i = 6; --i >= 0;) { 3315 b = *ep++; 3316 for (j = 8; --j >= 0;) { 3317 carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01); 3318 crc <<= 1; 3319 b >>= 1; 3320 if (carry) 3321 crc = ((crc ^ POLYNOMIAL) | carry); 3322 } 3323 } 3324 return crc; 3325#undef POLYNOMIAL 3326} 3327 3328/* 3329 * Compute the multicast address filter from the 3330 * list of multicast addresses we need to listen to. 3331 */ 3332static void 3333ds_getmcaf(sc, mcaf) 3334 struct ed_softc *sc; 3335 u_long *mcaf; 3336{ 3337 register u_int index; 3338 register u_char *af = (u_char *) mcaf; 3339 struct ifmultiaddr *ifma; 3340 3341 mcaf[0] = 0; 3342 mcaf[1] = 0; 3343 3344 for (ifma = sc->arpcom.ac_if.if_multiaddrs.lh_first; ifma; 3345 ifma = ifma->ifma_link.le_next) { 3346 if (ifma->ifma_addr->sa_family != AF_LINK) 3347 continue; 3348 index = ds_crc(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)) 3349 >> 26; 3350 af[index >> 3] |= 1 << (index & 7); 3351 } 3352} 3353