if_ed.c revision 52542
1/* 2 * Copyright (c) 1995, David Greenman 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD: head/sys/dev/ed/if_ed.c 52542 1999-10-26 23:03:45Z jmb $ 28 */ 29 30/* 31 * Device driver for National Semiconductor DS8390/WD83C690 based ethernet 32 * adapters. By David Greenman, 29-April-1993 33 * 34 * Currently supports the Western Digital/SMC 8003 and 8013 series, 35 * the SMC Elite Ultra (8216), the 3Com 3c503, the NE1000 and NE2000, 36 * and a variety of similar clones. 37 * 38 */ 39 40#include <sys/param.h> 41#include <sys/systm.h> 42#include <sys/kernel.h> 43#include <sys/sockio.h> 44#include <sys/malloc.h> 45#include <sys/mbuf.h> 46#include <sys/socket.h> 47#include <sys/syslog.h> 48 49#include <sys/module.h> 50#include <sys/bus.h> 51 52#include <machine/bus.h> 53#include <sys/rman.h> 54#include <machine/resource.h> 55 56#include <net/ethernet.h> 57#include <net/if.h> 58#include <net/if_arp.h> 59#include <net/if_dl.h> 60#include <net/if_mib.h> 61 62#include <net/bpf.h> 63#include "opt_bdg.h" 64#ifdef BRIDGE 65#include <net/bridge.h> 66#endif 67 68#include <machine/clock.h> 69#include <machine/md_var.h> 70 71#include <dev/ed/if_edreg.h> 72#include <dev/ed/if_edvar.h> 73 74static void ed_init __P((void *)); 75static int ed_ioctl __P((struct ifnet *, u_long, caddr_t)); 76static void ed_start __P((struct ifnet *)); 77static void ed_reset __P((struct ifnet *)); 78static void ed_watchdog __P((struct ifnet *)); 79static void ed_stop __P((struct ed_softc *)); 80 81static void ds_getmcaf __P((struct ed_softc *, u_long *)); 82 83static void ed_get_packet __P((struct ed_softc *, char *, /* u_short */ int, int)); 84 85static __inline void ed_rint __P((struct ed_softc *)); 86static __inline void ed_xmit __P((struct ed_softc *)); 87static __inline char * ed_ring_copy __P((struct ed_softc *, char *, char *, 88 /* u_short */ int)); 89static void ed_hpp_set_physical_link __P((struct ed_softc *)); 90static void ed_hpp_readmem __P((struct ed_softc *, int, unsigned char *, 91 /* u_short */ int)); 92static u_short ed_hpp_write_mbufs __P((struct ed_softc *, struct mbuf *, 93 int)); 94 95static void ed_pio_readmem __P((struct ed_softc *, int, unsigned char *, 96 /* u_short */ int)); 97static void ed_pio_writemem __P((struct ed_softc *, char *, 98 /* u_short */ int, /* u_short */ int)); 99static u_short ed_pio_write_mbufs __P((struct ed_softc *, struct mbuf *, 100 int)); 101 102static void ed_setrcr __P((struct ed_softc *)); 103 104static u_long ds_crc __P((u_char *ep)); 105 106static u_short ed_get_Linksys __P((struct ed_softc *)); 107 108/* 109 * Interrupt conversion table for WD/SMC ASIC/83C584 110 */ 111static unsigned short ed_intr_val[] = { 112 9, 113 3, 114 5, 115 7, 116 10, 117 11, 118 15, 119 4 120}; 121 122/* 123 * Interrupt conversion table for 83C790 124 */ 125static unsigned short ed_790_intr_val[] = { 126 0, 127 9, 128 3, 129 5, 130 7, 131 10, 132 11, 133 15 134}; 135 136/* 137 * Interrupt conversion table for the HP PC LAN+ 138 */ 139 140static unsigned short ed_hpp_intr_val[] = { 141 0, /* 0 */ 142 0, /* 1 */ 143 0, /* 2 */ 144 3, /* 3 */ 145 4, /* 4 */ 146 5, /* 5 */ 147 6, /* 6 */ 148 7, /* 7 */ 149 0, /* 8 */ 150 9, /* 9 */ 151 10, /* 10 */ 152 11, /* 11 */ 153 12, /* 12 */ 154 0, /* 13 */ 155 0, /* 14 */ 156 15 /* 15 */ 157}; 158 159/* 160 * Generic probe routine for testing for the existance of a DS8390. 161 * Must be called after the NIC has just been reset. This routine 162 * works by looking at certain register values that are guaranteed 163 * to be initialized a certain way after power-up or reset. Seems 164 * not to currently work on the 83C690. 165 * 166 * Specifically: 167 * 168 * Register reset bits set bits 169 * Command Register (CR) TXP, STA RD2, STP 170 * Interrupt Status (ISR) RST 171 * Interrupt Mask (IMR) All bits 172 * Data Control (DCR) LAS 173 * Transmit Config. (TCR) LB1, LB0 174 * 175 * We only look at the CR and ISR registers, however, because looking at 176 * the others would require changing register pages (which would be 177 * intrusive if this isn't an 8390). 178 * 179 * Return 1 if 8390 was found, 0 if not. 180 */ 181 182int 183ed_probe_generic8390(sc) 184 struct ed_softc *sc; 185{ 186 if ((inb(sc->nic_addr + ED_P0_CR) & 187 (ED_CR_RD2 | ED_CR_TXP | ED_CR_STA | ED_CR_STP)) != 188 (ED_CR_RD2 | ED_CR_STP)) 189 return (0); 190 if ((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RST) != ED_ISR_RST) 191 return (0); 192 193 return (1); 194} 195 196/* 197 * Probe and vendor-specific initialization routine for SMC/WD80x3 boards 198 */ 199int 200ed_probe_WD80x3(dev) 201 device_t dev; 202{ 203 struct ed_softc *sc = device_get_softc(dev); 204 int error; 205 int i; 206 int flags = device_get_flags(dev); 207 u_int memsize, maddr; 208 u_char iptr, isa16bit, sum; 209 u_long conf_maddr, conf_msize, irq, junk; 210 211 error = ed_alloc_port(dev, 0, ED_WD_IO_PORTS); 212 if (error) 213 return (error); 214 215 sc->asic_addr = rman_get_start(sc->port_res); 216 sc->nic_addr = sc->asic_addr + ED_WD_NIC_OFFSET; 217 sc->is790 = 0; 218 219#ifdef TOSH_ETHER 220 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_POW); 221 DELAY(10000); 222#endif 223 224 /* 225 * Attempt to do a checksum over the station address PROM. If it 226 * fails, it's probably not a SMC/WD board. There is a problem with 227 * this, though: some clone WD boards don't pass the checksum test. 228 * Danpex boards for one. 229 */ 230 for (sum = 0, i = 0; i < 8; ++i) 231 sum += inb(sc->asic_addr + ED_WD_PROM + i); 232 233 if (sum != ED_WD_ROM_CHECKSUM_TOTAL) { 234 235 /* 236 * Checksum is invalid. This often happens with cheap WD8003E 237 * clones. In this case, the checksum byte (the eighth byte) 238 * seems to always be zero. 239 */ 240 if (inb(sc->asic_addr + ED_WD_CARD_ID) != ED_TYPE_WD8003E || 241 inb(sc->asic_addr + ED_WD_PROM + 7) != 0) 242 return (ENXIO); 243 } 244 /* reset card to force it into a known state. */ 245#ifdef TOSH_ETHER 246 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_RST | ED_WD_MSR_POW); 247#else 248 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_RST); 249#endif 250 DELAY(100); 251 outb(sc->asic_addr + ED_WD_MSR, inb(sc->asic_addr + ED_WD_MSR) & ~ED_WD_MSR_RST); 252 /* wait in the case this card is reading its EEROM */ 253 DELAY(5000); 254 255 sc->vendor = ED_VENDOR_WD_SMC; 256 sc->type = inb(sc->asic_addr + ED_WD_CARD_ID); 257 258 /* 259 * Set initial values for width/size. 260 */ 261 memsize = 8192; 262 isa16bit = 0; 263 switch (sc->type) { 264 case ED_TYPE_WD8003S: 265 sc->type_str = "WD8003S"; 266 break; 267 case ED_TYPE_WD8003E: 268 sc->type_str = "WD8003E"; 269 break; 270 case ED_TYPE_WD8003EB: 271 sc->type_str = "WD8003EB"; 272 break; 273 case ED_TYPE_WD8003W: 274 sc->type_str = "WD8003W"; 275 break; 276 case ED_TYPE_WD8013EBT: 277 sc->type_str = "WD8013EBT"; 278 memsize = 16384; 279 isa16bit = 1; 280 break; 281 case ED_TYPE_WD8013W: 282 sc->type_str = "WD8013W"; 283 memsize = 16384; 284 isa16bit = 1; 285 break; 286 case ED_TYPE_WD8013EP: /* also WD8003EP */ 287 if (inb(sc->asic_addr + ED_WD_ICR) 288 & ED_WD_ICR_16BIT) { 289 isa16bit = 1; 290 memsize = 16384; 291 sc->type_str = "WD8013EP"; 292 } else { 293 sc->type_str = "WD8003EP"; 294 } 295 break; 296 case ED_TYPE_WD8013WC: 297 sc->type_str = "WD8013WC"; 298 memsize = 16384; 299 isa16bit = 1; 300 break; 301 case ED_TYPE_WD8013EBP: 302 sc->type_str = "WD8013EBP"; 303 memsize = 16384; 304 isa16bit = 1; 305 break; 306 case ED_TYPE_WD8013EPC: 307 sc->type_str = "WD8013EPC"; 308 memsize = 16384; 309 isa16bit = 1; 310 break; 311 case ED_TYPE_SMC8216C: /* 8216 has 16K shared mem -- 8416 has 8K */ 312 case ED_TYPE_SMC8216T: 313 if (sc->type == ED_TYPE_SMC8216C) { 314 sc->type_str = "SMC8216/SMC8216C"; 315 } else { 316 sc->type_str = "SMC8216T"; 317 } 318 319 outb(sc->asic_addr + ED_WD790_HWR, 320 inb(sc->asic_addr + ED_WD790_HWR) | ED_WD790_HWR_SWH); 321 switch (inb(sc->asic_addr + ED_WD790_RAR) & ED_WD790_RAR_SZ64) { 322 case ED_WD790_RAR_SZ64: 323 memsize = 65536; 324 break; 325 case ED_WD790_RAR_SZ32: 326 memsize = 32768; 327 break; 328 case ED_WD790_RAR_SZ16: 329 memsize = 16384; 330 break; 331 case ED_WD790_RAR_SZ8: 332 /* 8216 has 16K shared mem -- 8416 has 8K */ 333 if (sc->type == ED_TYPE_SMC8216C) { 334 sc->type_str = "SMC8416C/SMC8416BT"; 335 } else { 336 sc->type_str = "SMC8416T"; 337 } 338 memsize = 8192; 339 break; 340 } 341 outb(sc->asic_addr + ED_WD790_HWR, 342 inb(sc->asic_addr + ED_WD790_HWR) & ~ED_WD790_HWR_SWH); 343 344 isa16bit = 1; 345 sc->is790 = 1; 346 break; 347#ifdef TOSH_ETHER 348 case ED_TYPE_TOSHIBA1: 349 sc->type_str = "Toshiba1"; 350 memsize = 32768; 351 isa16bit = 1; 352 break; 353 case ED_TYPE_TOSHIBA4: 354 sc->type_str = "Toshiba4"; 355 memsize = 32768; 356 isa16bit = 1; 357 break; 358#endif 359 default: 360 sc->type_str = ""; 361 break; 362 } 363 364 /* 365 * Make some adjustments to initial values depending on what is found 366 * in the ICR. 367 */ 368 if (isa16bit && (sc->type != ED_TYPE_WD8013EBT) 369#ifdef TOSH_ETHER 370 && (sc->type != ED_TYPE_TOSHIBA1) && (sc->type != ED_TYPE_TOSHIBA4) 371#endif 372 && ((inb(sc->asic_addr + ED_WD_ICR) & ED_WD_ICR_16BIT) == 0)) { 373 isa16bit = 0; 374 memsize = 8192; 375 } 376 377 error = bus_get_resource(dev, SYS_RES_MEMORY, 0, 378 &conf_maddr, &conf_msize); 379 if (error) 380 return (error); 381 382#if ED_DEBUG 383 printf("type = %x type_str=%s isa16bit=%d memsize=%d id_msize=%d\n", 384 sc->type, sc->type_str, isa16bit, memsize, conf_msize); 385 for (i = 0; i < 8; i++) 386 printf("%x -> %x\n", i, inb(sc->asic_addr + i)); 387#endif 388 389 /* 390 * Allow the user to override the autoconfiguration 391 */ 392 if (conf_msize > 1) 393 memsize = conf_msize; 394 395 maddr = conf_maddr; 396 if (maddr < 0xa0000 || maddr + memsize > 0x1000000) { 397 device_printf(dev, "Invalid ISA memory address range configured: 0x%x - 0x%x\n", 398 maddr, maddr + memsize); 399 return (ENXIO); 400 } 401 402 /* 403 * (note that if the user specifies both of the following flags that 404 * '8bit' mode intentionally has precedence) 405 */ 406 if (flags & ED_FLAGS_FORCE_16BIT_MODE) 407 isa16bit = 1; 408 if (flags & ED_FLAGS_FORCE_8BIT_MODE) 409 isa16bit = 0; 410 411 /* 412 * If possible, get the assigned interrupt number from the card and 413 * use it. 414 */ 415 if ((sc->type & ED_WD_SOFTCONFIG) && (!sc->is790)) { 416 417 /* 418 * Assemble together the encoded interrupt number. 419 */ 420 iptr = (inb(sc->asic_addr + ED_WD_ICR) & ED_WD_ICR_IR2) | 421 ((inb(sc->asic_addr + ED_WD_IRR) & 422 (ED_WD_IRR_IR0 | ED_WD_IRR_IR1)) >> 5); 423 424 /* 425 * If no interrupt specified (or "?"), use what the board tells us. 426 */ 427 error = bus_get_resource(dev, SYS_RES_IRQ, 0, 428 &irq, &junk); 429 if (error) { 430 bus_set_resource(dev, SYS_RES_IRQ, 0, 431 ed_intr_val[iptr], 1); 432 } 433 434 /* 435 * Enable the interrupt. 436 */ 437 outb(sc->asic_addr + ED_WD_IRR, 438 inb(sc->asic_addr + ED_WD_IRR) | ED_WD_IRR_IEN); 439 } 440 if (sc->is790) { 441 outb(sc->asic_addr + ED_WD790_HWR, 442 inb(sc->asic_addr + ED_WD790_HWR) | ED_WD790_HWR_SWH); 443 iptr = (((inb(sc->asic_addr + ED_WD790_GCR) & ED_WD790_GCR_IR2) >> 4) | 444 (inb(sc->asic_addr + ED_WD790_GCR) & 445 (ED_WD790_GCR_IR1 | ED_WD790_GCR_IR0)) >> 2); 446 outb(sc->asic_addr + ED_WD790_HWR, 447 inb(sc->asic_addr + ED_WD790_HWR) & ~ED_WD790_HWR_SWH); 448 449 /* 450 * If no interrupt specified (or "?"), use what the board tells us. 451 */ 452 error = bus_get_resource(dev, SYS_RES_IRQ, 0, 453 &irq, &junk); 454 if (error) { 455 bus_set_resource(dev, SYS_RES_IRQ, 0, 456 ed_790_intr_val[iptr], 1); 457 } 458 459 /* 460 * Enable interrupts. 461 */ 462 outb(sc->asic_addr + ED_WD790_ICR, 463 inb(sc->asic_addr + ED_WD790_ICR) | ED_WD790_ICR_EIL); 464 } 465 error = bus_get_resource(dev, SYS_RES_IRQ, 0, 466 &irq, &junk); 467 if (error) { 468 device_printf(dev, "%s cards don't support auto-detected/assigned interrupts.\n", 469 sc->type_str); 470 return (ENXIO); 471 } 472 sc->isa16bit = isa16bit; 473 sc->mem_shared = 1; 474 475 error = ed_alloc_memory(dev, 0, memsize); 476 if (error) { 477 printf("*** ed_alloc_memory() failed! (%d)\n", error); 478 return (error); 479 } 480 sc->mem_start = (caddr_t) rman_get_virtual(sc->mem_res); 481 482 /* 483 * allocate one xmit buffer if < 16k, two buffers otherwise 484 */ 485 if ((memsize < 16384) || 486 (flags & ED_FLAGS_NO_MULTI_BUFFERING)) { 487 sc->txb_cnt = 1; 488 } else { 489 sc->txb_cnt = 2; 490 } 491 sc->tx_page_start = ED_WD_PAGE_OFFSET; 492 sc->rec_page_start = ED_WD_PAGE_OFFSET + ED_TXBUF_SIZE * sc->txb_cnt; 493 sc->rec_page_stop = ED_WD_PAGE_OFFSET + memsize / ED_PAGE_SIZE; 494 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * sc->rec_page_start); 495 sc->mem_size = memsize; 496 sc->mem_end = sc->mem_start + memsize; 497 498 /* 499 * Get station address from on-board ROM 500 */ 501 for (i = 0; i < ETHER_ADDR_LEN; ++i) 502 sc->arpcom.ac_enaddr[i] = inb(sc->asic_addr + ED_WD_PROM + i); 503 504 /* 505 * Set upper address bits and 8/16 bit access to shared memory. 506 */ 507 if (isa16bit) { 508 if (sc->is790) { 509 sc->wd_laar_proto = inb(sc->asic_addr + ED_WD_LAAR); 510 } else { 511 sc->wd_laar_proto = ED_WD_LAAR_L16EN | 512 ((kvtop(sc->mem_start) >> 19) & ED_WD_LAAR_ADDRHI); 513 } 514 /* 515 * Enable 16bit access 516 */ 517 outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto | 518 ED_WD_LAAR_M16EN); 519 } else { 520 if (((sc->type & ED_WD_SOFTCONFIG) || 521#ifdef TOSH_ETHER 522 (sc->type == ED_TYPE_TOSHIBA1) || (sc->type == ED_TYPE_TOSHIBA4) || 523#endif 524 (sc->type == ED_TYPE_WD8013EBT)) && (!sc->is790)) { 525 sc->wd_laar_proto = (kvtop(sc->mem_start) >> 19) & 526 ED_WD_LAAR_ADDRHI; 527 outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto); 528 } 529 } 530 531 /* 532 * Set address and enable interface shared memory. 533 */ 534 if (!sc->is790) { 535#ifdef TOSH_ETHER 536 outb(sc->asic_addr + ED_WD_MSR + 1, ((kvtop(sc->mem_start) >> 8) & 0xe0) | 4); 537 outb(sc->asic_addr + ED_WD_MSR + 2, ((kvtop(sc->mem_start) >> 16) & 0x0f)); 538 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_MENB | ED_WD_MSR_POW); 539 540#else 541 outb(sc->asic_addr + ED_WD_MSR, ((kvtop(sc->mem_start) >> 13) & 542 ED_WD_MSR_ADDR) | ED_WD_MSR_MENB); 543#endif 544 sc->cr_proto = ED_CR_RD2; 545 } else { 546 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_MENB); 547 outb(sc->asic_addr + ED_WD790_HWR, (inb(sc->asic_addr + ED_WD790_HWR) | ED_WD790_HWR_SWH)); 548 outb(sc->asic_addr + ED_WD790_RAR, ((kvtop(sc->mem_start) >> 13) & 0x0f) | 549 ((kvtop(sc->mem_start) >> 11) & 0x40) | 550 (inb(sc->asic_addr + ED_WD790_RAR) & 0xb0)); 551 outb(sc->asic_addr + ED_WD790_HWR, (inb(sc->asic_addr + ED_WD790_HWR) & ~ED_WD790_HWR_SWH)); 552 sc->cr_proto = 0; 553 } 554 555#if 0 556 printf("starting memory performance test at 0x%x, size %d...\n", 557 sc->mem_start, memsize*16384); 558 for (i = 0; i < 16384; i++) 559 bzero(sc->mem_start, memsize); 560 printf("***DONE***\n"); 561#endif 562 563 /* 564 * Now zero memory and verify that it is clear 565 */ 566 bzero(sc->mem_start, memsize); 567 568 for (i = 0; i < memsize; ++i) { 569 if (sc->mem_start[i]) { 570 device_printf(dev, "failed to clear shared memory at %lx - check configuration\n", 571 kvtop(sc->mem_start + i)); 572 573 /* 574 * Disable 16 bit access to shared memory 575 */ 576 if (isa16bit) { 577 if (sc->is790) { 578 outb(sc->asic_addr + ED_WD_MSR, 0x00); 579 } 580 outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto & 581 ~ED_WD_LAAR_M16EN); 582 } 583 return (ENXIO); 584 } 585 } 586 587 /* 588 * Disable 16bit access to shared memory - we leave it 589 * disabled so that 1) machines reboot properly when the board 590 * is set 16 bit mode and there are conflicting 8bit 591 * devices/ROMS in the same 128k address space as this boards 592 * shared memory. and 2) so that other 8 bit devices with 593 * shared memory can be used in this 128k region, too. 594 */ 595 if (isa16bit) { 596 if (sc->is790) { 597 outb(sc->asic_addr + ED_WD_MSR, 0x00); 598 } 599 outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto & 600 ~ED_WD_LAAR_M16EN); 601 } 602 return (0); 603} 604 605/* 606 * Probe and vendor-specific initialization routine for 3Com 3c503 boards 607 */ 608int 609ed_probe_3Com(dev) 610 device_t dev; 611{ 612 struct ed_softc *sc = device_get_softc(dev); 613 int error; 614 int i; 615 int flags = device_get_flags(dev); 616 u_int memsize; 617 u_char isa16bit; 618 u_long conf_maddr, conf_msize, irq, junk; 619 620 error = ed_alloc_port(dev, 0, ED_3COM_IO_PORTS); 621 if (error) 622 return (error); 623 624 sc->asic_addr = rman_get_start(sc->port_res) + ED_3COM_ASIC_OFFSET; 625 sc->nic_addr = rman_get_start(sc->port_res) + ED_3COM_NIC_OFFSET; 626 627 /* 628 * Verify that the kernel configured I/O address matches the board 629 * configured address 630 */ 631 switch (inb(sc->asic_addr + ED_3COM_BCFR)) { 632 case ED_3COM_BCFR_300: 633 if (rman_get_start(sc->port_res) != 0x300) 634 return (ENXIO); 635 break; 636 case ED_3COM_BCFR_310: 637 if (rman_get_start(sc->port_res) != 0x310) 638 return (ENXIO); 639 break; 640 case ED_3COM_BCFR_330: 641 if (rman_get_start(sc->port_res) != 0x330) 642 return (ENXIO); 643 break; 644 case ED_3COM_BCFR_350: 645 if (rman_get_start(sc->port_res) != 0x350) 646 return (ENXIO); 647 break; 648 case ED_3COM_BCFR_250: 649 if (rman_get_start(sc->port_res) != 0x250) 650 return (ENXIO); 651 break; 652 case ED_3COM_BCFR_280: 653 if (rman_get_start(sc->port_res) != 0x280) 654 return (ENXIO); 655 break; 656 case ED_3COM_BCFR_2A0: 657 if (rman_get_start(sc->port_res) != 0x2a0) 658 return (ENXIO); 659 break; 660 case ED_3COM_BCFR_2E0: 661 if (rman_get_start(sc->port_res) != 0x2e0) 662 return (ENXIO); 663 break; 664 default: 665 return (ENXIO); 666 } 667 668 error = bus_get_resource(dev, SYS_RES_MEMORY, 0, 669 &conf_maddr, &conf_msize); 670 if (error) 671 return (error); 672 673 /* 674 * Verify that the kernel shared memory address matches the board 675 * configured address. 676 */ 677 switch (inb(sc->asic_addr + ED_3COM_PCFR)) { 678 case ED_3COM_PCFR_DC000: 679 if (conf_maddr != 0xdc000) 680 return (ENXIO); 681 break; 682 case ED_3COM_PCFR_D8000: 683 if (conf_maddr != 0xd8000) 684 return (ENXIO); 685 break; 686 case ED_3COM_PCFR_CC000: 687 if (conf_maddr != 0xcc000) 688 return (ENXIO); 689 break; 690 case ED_3COM_PCFR_C8000: 691 if (conf_maddr != 0xc8000) 692 return (ENXIO); 693 break; 694 default: 695 return (ENXIO); 696 } 697 698 699 /* 700 * Reset NIC and ASIC. Enable on-board transceiver throughout reset 701 * sequence because it'll lock up if the cable isn't connected if we 702 * don't. 703 */ 704 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_RST | ED_3COM_CR_XSEL); 705 706 /* 707 * Wait for a while, then un-reset it 708 */ 709 DELAY(50); 710 711 /* 712 * The 3Com ASIC defaults to rather strange settings for the CR after 713 * a reset - it's important to set it again after the following outb 714 * (this is done when we map the PROM below). 715 */ 716 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL); 717 718 /* 719 * Wait a bit for the NIC to recover from the reset 720 */ 721 DELAY(5000); 722 723 sc->vendor = ED_VENDOR_3COM; 724 sc->type_str = "3c503"; 725 sc->mem_shared = 1; 726 sc->cr_proto = ED_CR_RD2; 727 728 /* 729 * Hmmm...a 16bit 3Com board has 16k of memory, but only an 8k window 730 * to it. 731 */ 732 memsize = 8192; 733 734 /* 735 * Get station address from on-board ROM 736 */ 737 738 /* 739 * First, map ethernet address PROM over the top of where the NIC 740 * registers normally appear. 741 */ 742 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_EALO | ED_3COM_CR_XSEL); 743 744 for (i = 0; i < ETHER_ADDR_LEN; ++i) 745 sc->arpcom.ac_enaddr[i] = inb(sc->nic_addr + i); 746 747 /* 748 * Unmap PROM - select NIC registers. The proper setting of the 749 * tranceiver is set in ed_init so that the attach code is given a 750 * chance to set the default based on a compile-time config option 751 */ 752 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL); 753 754 /* 755 * Determine if this is an 8bit or 16bit board 756 */ 757 758 /* 759 * select page 0 registers 760 */ 761 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STP); 762 763 /* 764 * Attempt to clear WTS bit. If it doesn't clear, then this is a 16bit 765 * board. 766 */ 767 outb(sc->nic_addr + ED_P0_DCR, 0); 768 769 /* 770 * select page 2 registers 771 */ 772 outb(sc->nic_addr + ED_P0_CR, ED_CR_PAGE_2 | ED_CR_RD2 | ED_CR_STP); 773 774 /* 775 * The 3c503 forces the WTS bit to a one if this is a 16bit board 776 */ 777 if (inb(sc->nic_addr + ED_P2_DCR) & ED_DCR_WTS) 778 isa16bit = 1; 779 else 780 isa16bit = 0; 781 782 /* 783 * select page 0 registers 784 */ 785 outb(sc->nic_addr + ED_P2_CR, ED_CR_RD2 | ED_CR_STP); 786 787 error = ed_alloc_memory(dev, 0, memsize); 788 if (error) 789 return (error); 790 791 sc->mem_start = (caddr_t) rman_get_virtual(sc->mem_res); 792 sc->mem_size = memsize; 793 sc->mem_end = sc->mem_start + memsize; 794 795 /* 796 * We have an entire 8k window to put the transmit buffers on the 797 * 16bit boards. But since the 16bit 3c503's shared memory is only 798 * fast enough to overlap the loading of one full-size packet, trying 799 * to load more than 2 buffers can actually leave the transmitter idle 800 * during the load. So 2 seems the best value. (Although a mix of 801 * variable-sized packets might change this assumption. Nonetheless, 802 * we optimize for linear transfers of same-size packets.) 803 */ 804 if (isa16bit) { 805 if (flags & ED_FLAGS_NO_MULTI_BUFFERING) 806 sc->txb_cnt = 1; 807 else 808 sc->txb_cnt = 2; 809 810 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_16BIT; 811 sc->rec_page_start = ED_3COM_RX_PAGE_OFFSET_16BIT; 812 sc->rec_page_stop = memsize / ED_PAGE_SIZE + 813 ED_3COM_RX_PAGE_OFFSET_16BIT; 814 sc->mem_ring = sc->mem_start; 815 } else { 816 sc->txb_cnt = 1; 817 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_8BIT; 818 sc->rec_page_start = ED_TXBUF_SIZE + ED_3COM_TX_PAGE_OFFSET_8BIT; 819 sc->rec_page_stop = memsize / ED_PAGE_SIZE + 820 ED_3COM_TX_PAGE_OFFSET_8BIT; 821 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * ED_TXBUF_SIZE); 822 } 823 824 sc->isa16bit = isa16bit; 825 826 /* 827 * Initialize GA page start/stop registers. Probably only needed if 828 * doing DMA, but what the hell. 829 */ 830 outb(sc->asic_addr + ED_3COM_PSTR, sc->rec_page_start); 831 outb(sc->asic_addr + ED_3COM_PSPR, sc->rec_page_stop); 832 833 /* 834 * Set IRQ. 3c503 only allows a choice of irq 2-5. 835 */ 836 error = bus_get_resource(dev, SYS_RES_IRQ, 0, 837 &irq, &junk); 838 if (error) 839 return (error); 840 841 switch (irq) { 842 case 2: 843 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ2); 844 break; 845 case 3: 846 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ3); 847 break; 848 case 4: 849 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ4); 850 break; 851 case 5: 852 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ5); 853 break; 854 default: 855 device_printf(dev, "Invalid irq configuration (%ld) must be 3-5,9 for 3c503\n", 856 irq); 857 return (ENXIO); 858 } 859 860 /* 861 * Initialize GA configuration register. Set bank and enable shared 862 * mem. 863 */ 864 outb(sc->asic_addr + ED_3COM_GACFR, ED_3COM_GACFR_RSEL | 865 ED_3COM_GACFR_MBS0); 866 867 /* 868 * Initialize "Vector Pointer" registers. These gawd-awful things are 869 * compared to 20 bits of the address on ISA, and if they match, the 870 * shared memory is disabled. We set them to 0xffff0...allegedly the 871 * reset vector. 872 */ 873 outb(sc->asic_addr + ED_3COM_VPTR2, 0xff); 874 outb(sc->asic_addr + ED_3COM_VPTR1, 0xff); 875 outb(sc->asic_addr + ED_3COM_VPTR0, 0x00); 876 877 /* 878 * Zero memory and verify that it is clear 879 */ 880 bzero(sc->mem_start, memsize); 881 882 for (i = 0; i < memsize; ++i) 883 if (sc->mem_start[i]) { 884 device_printf(dev, "failed to clear shared memory at %lx - check configuration\n", 885 kvtop(sc->mem_start + i)); 886 return (ENXIO); 887 } 888 return (0); 889} 890 891static u_short 892ed_get_Linksys(sc) 893 struct ed_softc *sc; 894{ 895 u_char LinksysOUI[] = {0x00, 0xe0, 0x98}; 896 u_char sum; 897 int i; 898 899 for (sum = 0, i = 0x14; i < 0x1c; i++) 900 sum += inb(sc->nic_addr +i); 901 if (sum != 0xff) 902 return (0); 903 for (i = 0; i < ETHER_ADDR_LEN; i++) { 904 sc->arpcom.ac_enaddr[i] = inb(sc->nic_addr + 0x14 + i); 905 } 906 for (i = 0; i < sizeof(LinksysOUI); i++) { 907 if ( sc->arpcom.ac_enaddr[i] != LinksysOUI[i] ) 908 return (0); 909 } 910 return (1); 911} 912 913/* 914 * Probe and vendor-specific initialization routine for NE1000/2000 boards 915 */ 916int 917ed_probe_Novell_generic(dev, port_rid, flags) 918 device_t dev; 919 int port_rid; 920 int flags; 921{ 922 struct ed_softc *sc = device_get_softc(dev); 923 u_int memsize, n; 924 u_char romdata[16], tmp; 925 static char test_pattern[32] = "THIS is A memory TEST pattern"; 926 char test_buffer[32]; 927 int linksys = 0; 928 int error; 929 930 error = ed_alloc_port(dev, port_rid, ED_NOVELL_IO_PORTS); 931 if (error) 932 return (error); 933 934 sc->asic_addr = rman_get_start(sc->port_res) + ED_NOVELL_ASIC_OFFSET; 935 sc->nic_addr = rman_get_start(sc->port_res) + ED_NOVELL_NIC_OFFSET; 936 937 /* XXX - do Novell-specific probe here */ 938 939 /* Reset the board */ 940#ifdef GWETHER 941 outb(sc->asic_addr + ED_NOVELL_RESET, 0); 942 DELAY(200); 943#endif /* GWETHER */ 944 tmp = inb(sc->asic_addr + ED_NOVELL_RESET); 945 946 /* 947 * I don't know if this is necessary; probably cruft leftover from 948 * Clarkson packet driver code. Doesn't do a thing on the boards I've 949 * tested. -DG [note that a outb(0x84, 0) seems to work here, and is 950 * non-invasive...but some boards don't seem to reset and I don't have 951 * complete documentation on what the 'right' thing to do is...so we 952 * do the invasive thing for now. Yuck.] 953 */ 954 outb(sc->asic_addr + ED_NOVELL_RESET, tmp); 955 DELAY(5000); 956 957 /* 958 * This is needed because some NE clones apparently don't reset the 959 * NIC properly (or the NIC chip doesn't reset fully on power-up) XXX 960 * - this makes the probe invasive! ...Done against my better 961 * judgement. -DLG 962 */ 963 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STP); 964 965 DELAY(5000); 966 967 /* Make sure that we really have an 8390 based board */ 968 if (!ed_probe_generic8390(sc)) 969 return (ENXIO); 970 971 sc->vendor = ED_VENDOR_NOVELL; 972 sc->mem_shared = 0; 973 sc->cr_proto = ED_CR_RD2; 974 975 /* 976 * Test the ability to read and write to the NIC memory. This has the 977 * side affect of determining if this is an NE1000 or an NE2000. 978 */ 979 980 /* 981 * This prevents packets from being stored in the NIC memory when the 982 * readmem routine turns on the start bit in the CR. 983 */ 984 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_MON); 985 986 /* Temporarily initialize DCR for byte operations */ 987 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS); 988 989 outb(sc->nic_addr + ED_P0_PSTART, 8192 / ED_PAGE_SIZE); 990 outb(sc->nic_addr + ED_P0_PSTOP, 16384 / ED_PAGE_SIZE); 991 992 sc->isa16bit = 0; 993 994 /* 995 * Write a test pattern in byte mode. If this fails, then there 996 * probably isn't any memory at 8k - which likely means that the board 997 * is an NE2000. 998 */ 999 ed_pio_writemem(sc, test_pattern, 8192, sizeof(test_pattern)); 1000 ed_pio_readmem(sc, 8192, test_buffer, sizeof(test_pattern)); 1001 1002 linksys = ed_get_Linksys(sc); 1003 if (linksys) { 1004 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_WTS | ED_DCR_FT1 | ED_DCR_LS); 1005 sc->isa16bit = 1; 1006 sc->type = ED_TYPE_NE2000; 1007 sc->type_str = "Linksys"; 1008 } else if (bcmp(test_pattern, test_buffer, sizeof(test_pattern))) { 1009 /* not an NE1000 - try NE2000 */ 1010 1011 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_WTS | ED_DCR_FT1 | ED_DCR_LS); 1012 outb(sc->nic_addr + ED_P0_PSTART, 16384 / ED_PAGE_SIZE); 1013 outb(sc->nic_addr + ED_P0_PSTOP, 32768 / ED_PAGE_SIZE); 1014 1015 sc->isa16bit = 1; 1016 1017 /* 1018 * Write a test pattern in word mode. If this also fails, then 1019 * we don't know what this board is. 1020 */ 1021 ed_pio_writemem(sc, test_pattern, 16384, sizeof(test_pattern)); 1022 ed_pio_readmem(sc, 16384, test_buffer, sizeof(test_pattern)); 1023 1024 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern))) 1025 return (ENXIO); /* not an NE2000 either */ 1026 1027 sc->type = ED_TYPE_NE2000; 1028 sc->type_str = "NE2000"; 1029 } else { 1030 sc->type = ED_TYPE_NE1000; 1031 sc->type_str = "NE1000"; 1032 } 1033 1034 /* 8k of memory plus an additional 8k if 16bit */ 1035 memsize = 8192 + sc->isa16bit * 8192; 1036 1037#if 0 /* probably not useful - NE boards only come two ways */ 1038 /* allow kernel config file overrides */ 1039 if (isa_dev->id_msize) 1040 memsize = isa_dev->id_msize; 1041#endif 1042 1043 sc->mem_size = memsize; 1044 1045 /* NIC memory doesn't start at zero on an NE board */ 1046 /* The start address is tied to the bus width */ 1047 sc->mem_start = (char *) 8192 + sc->isa16bit * 8192; 1048 sc->mem_end = sc->mem_start + memsize; 1049 sc->tx_page_start = memsize / ED_PAGE_SIZE; 1050 1051#ifdef GWETHER 1052 { 1053 int x, i, mstart = 0, msize = 0; 1054 char pbuf0[ED_PAGE_SIZE], pbuf[ED_PAGE_SIZE], tbuf[ED_PAGE_SIZE]; 1055 1056 for (i = 0; i < ED_PAGE_SIZE; i++) 1057 pbuf0[i] = 0; 1058 1059 /* Clear all the memory. */ 1060 for (x = 1; x < 256; x++) 1061 ed_pio_writemem(sc, pbuf0, x * 256, ED_PAGE_SIZE); 1062 1063 /* Search for the start of RAM. */ 1064 for (x = 1; x < 256; x++) { 1065 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE); 1066 if (bcmp(pbuf0, tbuf, ED_PAGE_SIZE) == 0) { 1067 for (i = 0; i < ED_PAGE_SIZE; i++) 1068 pbuf[i] = 255 - x; 1069 ed_pio_writemem(sc, pbuf, x * 256, ED_PAGE_SIZE); 1070 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE); 1071 if (bcmp(pbuf, tbuf, ED_PAGE_SIZE) == 0) { 1072 mstart = x * ED_PAGE_SIZE; 1073 msize = ED_PAGE_SIZE; 1074 break; 1075 } 1076 } 1077 } 1078 1079 if (mstart == 0) { 1080 device_printf(dev, "Cannot find start of RAM.\n"); 1081 return (ENXIO); 1082 } 1083 /* Search for the start of RAM. */ 1084 for (x = (mstart / ED_PAGE_SIZE) + 1; x < 256; x++) { 1085 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE); 1086 if (bcmp(pbuf0, tbuf, ED_PAGE_SIZE) == 0) { 1087 for (i = 0; i < ED_PAGE_SIZE; i++) 1088 pbuf[i] = 255 - x; 1089 ed_pio_writemem(sc, pbuf, x * 256, ED_PAGE_SIZE); 1090 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE); 1091 if (bcmp(pbuf, tbuf, ED_PAGE_SIZE) == 0) 1092 msize += ED_PAGE_SIZE; 1093 else { 1094 break; 1095 } 1096 } else { 1097 break; 1098 } 1099 } 1100 1101 if (msize == 0) { 1102 device_printf(dev, "Cannot find any RAM, start : %d, x = %d.\n", mstart, x); 1103 return (ENXIO); 1104 } 1105 device_printf(dev, "RAM start at %d, size : %d.\n", mstart, msize); 1106 1107 sc->mem_size = msize; 1108 sc->mem_start = (char *) mstart; 1109 sc->mem_end = (char *) (msize + mstart); 1110 sc->tx_page_start = mstart / ED_PAGE_SIZE; 1111 } 1112#endif /* GWETHER */ 1113 1114 /* 1115 * Use one xmit buffer if < 16k, two buffers otherwise (if not told 1116 * otherwise). 1117 */ 1118 if ((memsize < 16384) || (flags & ED_FLAGS_NO_MULTI_BUFFERING)) 1119 sc->txb_cnt = 1; 1120 else 1121 sc->txb_cnt = 2; 1122 1123 sc->rec_page_start = sc->tx_page_start + sc->txb_cnt * ED_TXBUF_SIZE; 1124 sc->rec_page_stop = sc->tx_page_start + memsize / ED_PAGE_SIZE; 1125 1126 sc->mem_ring = sc->mem_start + sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE; 1127 1128 if (!linksys) { 1129 ed_pio_readmem(sc, 0, romdata, 16); 1130 for (n = 0; n < ETHER_ADDR_LEN; n++) 1131 sc->arpcom.ac_enaddr[n] = romdata[n * (sc->isa16bit + 1)]; 1132 } 1133 1134#ifdef GWETHER 1135 if (sc->arpcom.ac_enaddr[2] == 0x86) { 1136 sc->type_str = "Gateway AT"; 1137 } 1138#endif /* GWETHER */ 1139 1140 /* clear any pending interrupts that might have occurred above */ 1141 outb(sc->nic_addr + ED_P0_ISR, 0xff); 1142 1143 return (0); 1144} 1145 1146int 1147ed_probe_Novell(dev) 1148 device_t dev; 1149{ 1150 return ed_probe_Novell_generic(dev, 0, device_get_flags(dev)); 1151} 1152 1153#define ED_HPP_TEST_SIZE 16 1154 1155/* 1156 * Probe and vendor specific initialization for the HP PC Lan+ Cards. 1157 * (HP Part nos: 27247B and 27252A). 1158 * 1159 * The card has an asic wrapper around a DS8390 core. The asic handles 1160 * host accesses and offers both standard register IO and memory mapped 1161 * IO. Memory mapped I/O allows better performance at the expense of greater 1162 * chance of an incompatibility with existing ISA cards. 1163 * 1164 * The card has a few caveats: it isn't tolerant of byte wide accesses, only 1165 * short (16 bit) or word (32 bit) accesses are allowed. Some card revisions 1166 * don't allow 32 bit accesses; these are indicated by a bit in the software 1167 * ID register (see if_edreg.h). 1168 * 1169 * Other caveats are: we should read the MAC address only when the card 1170 * is inactive. 1171 * 1172 * For more information; please consult the CRYNWR packet driver. 1173 * 1174 * The AUI port is turned on using the "link2" option on the ifconfig 1175 * command line. 1176 */ 1177int 1178ed_probe_HP_pclanp(dev) 1179 device_t dev; 1180{ 1181 struct ed_softc *sc = device_get_softc(dev); 1182 int error; 1183 int n; /* temp var */ 1184 int memsize; /* mem on board */ 1185 u_char checksum; /* checksum of board address */ 1186 u_char irq; /* board configured IRQ */ 1187 char test_pattern[ED_HPP_TEST_SIZE]; /* read/write areas for */ 1188 char test_buffer[ED_HPP_TEST_SIZE]; /* probing card */ 1189 u_long conf_maddr, conf_msize, conf_irq, junk; 1190 1191 error = ed_alloc_port(dev, 0, ED_HPP_IO_PORTS); 1192 if (error) 1193 return (error); 1194 1195 /* Fill in basic information */ 1196 sc->asic_addr = rman_get_start(sc->port_res) + ED_HPP_ASIC_OFFSET; 1197 sc->nic_addr = rman_get_start(sc->port_res) + ED_HPP_NIC_OFFSET; 1198 sc->is790 = 0; 1199 sc->isa16bit = 0; /* the 8390 core needs to be in byte mode */ 1200 1201 /* 1202 * Look for the HP PCLAN+ signature: "0x50,0x48,0x00,0x53" 1203 */ 1204 1205 if ((inb(sc->asic_addr + ED_HPP_ID) != 0x50) || 1206 (inb(sc->asic_addr + ED_HPP_ID + 1) != 0x48) || 1207 ((inb(sc->asic_addr + ED_HPP_ID + 2) & 0xF0) != 0) || 1208 (inb(sc->asic_addr + ED_HPP_ID + 3) != 0x53)) 1209 return ENXIO; 1210 1211 /* 1212 * Read the MAC address and verify checksum on the address. 1213 */ 1214 1215 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_MAC); 1216 for (n = 0, checksum = 0; n < ETHER_ADDR_LEN; n++) 1217 checksum += (sc->arpcom.ac_enaddr[n] = 1218 inb(sc->asic_addr + ED_HPP_MAC_ADDR + n)); 1219 1220 checksum += inb(sc->asic_addr + ED_HPP_MAC_ADDR + ETHER_ADDR_LEN); 1221 1222 if (checksum != 0xFF) 1223 return ENXIO; 1224 1225 /* 1226 * Verify that the software model number is 0. 1227 */ 1228 1229 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_ID); 1230 if (((sc->hpp_id = inw(sc->asic_addr + ED_HPP_PAGE_4)) & 1231 ED_HPP_ID_SOFT_MODEL_MASK) != 0x0000) 1232 return ENXIO; 1233 1234 /* 1235 * Read in and save the current options configured on card. 1236 */ 1237 1238 sc->hpp_options = inw(sc->asic_addr + ED_HPP_OPTION); 1239 1240 sc->hpp_options |= (ED_HPP_OPTION_NIC_RESET | 1241 ED_HPP_OPTION_CHIP_RESET | 1242 ED_HPP_OPTION_ENABLE_IRQ); 1243 1244 /* 1245 * Reset the chip. This requires writing to the option register 1246 * so take care to preserve the other bits. 1247 */ 1248 1249 outw(sc->asic_addr + ED_HPP_OPTION, 1250 (sc->hpp_options & ~(ED_HPP_OPTION_NIC_RESET | 1251 ED_HPP_OPTION_CHIP_RESET))); 1252 1253 DELAY(5000); /* wait for chip reset to complete */ 1254 1255 outw(sc->asic_addr + ED_HPP_OPTION, 1256 (sc->hpp_options | (ED_HPP_OPTION_NIC_RESET | 1257 ED_HPP_OPTION_CHIP_RESET | 1258 ED_HPP_OPTION_ENABLE_IRQ))); 1259 1260 DELAY(5000); 1261 1262 if (!(inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RST)) 1263 return ENXIO; /* reset did not complete */ 1264 1265 /* 1266 * Read out configuration information. 1267 */ 1268 1269 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_HW); 1270 1271 irq = inb(sc->asic_addr + ED_HPP_HW_IRQ); 1272 1273 /* 1274 * Check for impossible IRQ. 1275 */ 1276 1277 if (irq >= (sizeof(ed_hpp_intr_val) / sizeof(ed_hpp_intr_val[0]))) 1278 return ENXIO; 1279 1280 /* 1281 * If the kernel IRQ was specified with a '?' use the cards idea 1282 * of the IRQ. If the kernel IRQ was explicitly specified, it 1283 * should match that of the hardware. 1284 */ 1285 error = bus_get_resource(dev, SYS_RES_IRQ, 0, 1286 &conf_irq, &junk); 1287 if (error) { 1288 bus_set_resource(dev, SYS_RES_IRQ, 0, 1289 ed_hpp_intr_val[irq], 1); 1290 } else { 1291 if (conf_irq != ed_hpp_intr_val[irq]) 1292 return (ENXIO); 1293 } 1294 1295 /* 1296 * Fill in softconfig info. 1297 */ 1298 1299 sc->vendor = ED_VENDOR_HP; 1300 sc->type = ED_TYPE_HP_PCLANPLUS; 1301 sc->type_str = "HP-PCLAN+"; 1302 1303 sc->mem_shared = 0; /* we DON'T have dual ported RAM */ 1304 sc->mem_start = 0; /* we use offsets inside the card RAM */ 1305 1306 sc->hpp_mem_start = NULL;/* no memory mapped I/O by default */ 1307 1308 /* 1309 * The board has 32KB of memory. Is there a way to determine 1310 * this programmatically? 1311 */ 1312 1313 memsize = 32768; 1314 1315 /* 1316 * Check if memory mapping of the I/O registers possible. 1317 */ 1318 1319 if (sc->hpp_options & ED_HPP_OPTION_MEM_ENABLE) 1320 { 1321 u_long mem_addr; 1322 1323 /* 1324 * determine the memory address from the board. 1325 */ 1326 1327 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_HW); 1328 mem_addr = (inw(sc->asic_addr + ED_HPP_HW_MEM_MAP) << 8); 1329 1330 /* 1331 * Check that the kernel specified start of memory and 1332 * hardware's idea of it match. 1333 */ 1334 error = bus_get_resource(dev, SYS_RES_MEMORY, 0, 1335 &conf_maddr, &conf_msize); 1336 if (error) 1337 return (error); 1338 1339 if (mem_addr != conf_maddr) 1340 return ENXIO; 1341 1342 error = ed_alloc_memory(dev, 0, memsize); 1343 if (error) 1344 return (error); 1345 1346 sc->hpp_mem_start = rman_get_virtual(sc->mem_res); 1347 } 1348 1349 /* 1350 * Fill in the rest of the soft config structure. 1351 */ 1352 1353 /* 1354 * The transmit page index. 1355 */ 1356 1357 sc->tx_page_start = ED_HPP_TX_PAGE_OFFSET; 1358 1359 if (device_get_flags(dev) & ED_FLAGS_NO_MULTI_BUFFERING) 1360 sc->txb_cnt = 1; 1361 else 1362 sc->txb_cnt = 2; 1363 1364 /* 1365 * Memory description 1366 */ 1367 1368 sc->mem_size = memsize; 1369 sc->mem_ring = sc->mem_start + 1370 (sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE); 1371 sc->mem_end = sc->mem_start + sc->mem_size; 1372 1373 /* 1374 * Receive area starts after the transmit area and 1375 * continues till the end of memory. 1376 */ 1377 1378 sc->rec_page_start = sc->tx_page_start + 1379 (sc->txb_cnt * ED_TXBUF_SIZE); 1380 sc->rec_page_stop = (sc->mem_size / ED_PAGE_SIZE); 1381 1382 1383 sc->cr_proto = 0; /* value works */ 1384 1385 /* 1386 * Set the wrap registers for string I/O reads. 1387 */ 1388 1389 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_HW); 1390 outw(sc->asic_addr + ED_HPP_HW_WRAP, 1391 ((sc->rec_page_start / ED_PAGE_SIZE) | 1392 (((sc->rec_page_stop / ED_PAGE_SIZE) - 1) << 8))); 1393 1394 /* 1395 * Reset the register page to normal operation. 1396 */ 1397 1398 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_PERF); 1399 1400 /* 1401 * Verify that we can read/write from adapter memory. 1402 * Create test pattern. 1403 */ 1404 1405 for (n = 0; n < ED_HPP_TEST_SIZE; n++) 1406 { 1407 test_pattern[n] = (n*n) ^ ~n; 1408 } 1409 1410#undef ED_HPP_TEST_SIZE 1411 1412 /* 1413 * Check that the memory is accessible thru the I/O ports. 1414 * Write out the contents of "test_pattern", read back 1415 * into "test_buffer" and compare the two for any 1416 * mismatch. 1417 */ 1418 1419 for (n = 0; n < (32768 / ED_PAGE_SIZE); n ++) { 1420 1421 ed_pio_writemem(sc, test_pattern, (n * ED_PAGE_SIZE), 1422 sizeof(test_pattern)); 1423 ed_pio_readmem(sc, (n * ED_PAGE_SIZE), 1424 test_buffer, sizeof(test_pattern)); 1425 1426 if (bcmp(test_pattern, test_buffer, 1427 sizeof(test_pattern))) 1428 return ENXIO; 1429 } 1430 1431 return (ED_HPP_IO_PORTS); 1432 1433} 1434 1435/* 1436 * HP PC Lan+ : Set the physical link to use AUI or TP/TL. 1437 */ 1438 1439void 1440ed_hpp_set_physical_link(struct ed_softc *sc) 1441{ 1442 struct ifnet *ifp = &sc->arpcom.ac_if; 1443 int lan_page; 1444 1445 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_LAN); 1446 lan_page = inw(sc->asic_addr + ED_HPP_PAGE_0); 1447 1448 if (ifp->if_flags & IFF_ALTPHYS) { 1449 1450 /* 1451 * Use the AUI port. 1452 */ 1453 1454 lan_page |= ED_HPP_LAN_AUI; 1455 1456 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_LAN); 1457 outw(sc->asic_addr + ED_HPP_PAGE_0, lan_page); 1458 1459 1460 } else { 1461 1462 /* 1463 * Use the ThinLan interface 1464 */ 1465 1466 lan_page &= ~ED_HPP_LAN_AUI; 1467 1468 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_LAN); 1469 outw(sc->asic_addr + ED_HPP_PAGE_0, lan_page); 1470 1471 } 1472 1473 /* 1474 * Wait for the lan card to re-initialize itself 1475 */ 1476 1477 DELAY(150000); /* wait 150 ms */ 1478 1479 /* 1480 * Restore normal pages. 1481 */ 1482 1483 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_PERF); 1484 1485} 1486 1487/* 1488 * Allocate a port resource with the given resource id. 1489 */ 1490int 1491ed_alloc_port(dev, rid, size) 1492 device_t dev; 1493 int rid; 1494 int size; 1495{ 1496 struct ed_softc *sc = device_get_softc(dev); 1497 struct resource *res; 1498 1499 res = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 1500 0ul, ~0ul, size, RF_ACTIVE); 1501 if (res) { 1502 sc->port_rid = rid; 1503 sc->port_res = res; 1504 sc->port_used = 1; 1505 return (0); 1506 } else { 1507 return (ENOENT); 1508 } 1509} 1510 1511/* 1512 * Allocate a memory resource with the given resource id. 1513 */ 1514int 1515ed_alloc_memory(dev, rid, size) 1516 device_t dev; 1517 int rid; 1518 int size; 1519{ 1520 struct ed_softc *sc = device_get_softc(dev); 1521 struct resource *res; 1522 1523 res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 1524 0ul, ~0ul, size, RF_ACTIVE); 1525 if (res) { 1526 sc->mem_rid = rid; 1527 sc->mem_res = res; 1528 sc->mem_used = 1; 1529 return (0); 1530 } else { 1531 return (ENOENT); 1532 } 1533} 1534 1535/* 1536 * Allocate an irq resource with the given resource id. 1537 */ 1538int 1539ed_alloc_irq(dev, rid, flags) 1540 device_t dev; 1541 int rid; 1542 int flags; 1543{ 1544 struct ed_softc *sc = device_get_softc(dev); 1545 struct resource *res; 1546 1547 res = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 1548 0ul, ~0ul, 1, (RF_ACTIVE | flags)); 1549 if (res) { 1550 sc->irq_rid = rid; 1551 sc->irq_res = res; 1552 return (0); 1553 } else { 1554 return (ENOENT); 1555 } 1556} 1557 1558/* 1559 * Release all resources 1560 */ 1561void 1562ed_release_resources(dev) 1563 device_t dev; 1564{ 1565 struct ed_softc *sc = device_get_softc(dev); 1566 1567 if (sc->port_res) { 1568 bus_release_resource(dev, SYS_RES_IOPORT, 1569 sc->port_rid, sc->port_res); 1570 sc->port_res = 0; 1571 } 1572 if (sc->mem_res) { 1573 bus_release_resource(dev, SYS_RES_MEMORY, 1574 sc->mem_rid, sc->mem_res); 1575 sc->mem_res = 0; 1576 } 1577 if (sc->irq_res) { 1578 bus_release_resource(dev, SYS_RES_IRQ, 1579 sc->irq_rid, sc->irq_res); 1580 sc->irq_res = 0; 1581 } 1582} 1583 1584/* 1585 * Install interface into kernel networking data structures 1586 */ 1587int 1588ed_attach(sc, unit, flags) 1589 struct ed_softc *sc; 1590 int unit; 1591 int flags; 1592{ 1593 struct ifnet *ifp = &sc->arpcom.ac_if; 1594 1595 /* 1596 * Set interface to stopped condition (reset) 1597 */ 1598 ed_stop(sc); 1599 1600 if (!ifp->if_name) { 1601 /* 1602 * Initialize ifnet structure 1603 */ 1604 ifp->if_softc = sc; 1605 ifp->if_unit = unit; 1606 ifp->if_name = "ed"; 1607 ifp->if_output = ether_output; 1608 ifp->if_start = ed_start; 1609 ifp->if_ioctl = ed_ioctl; 1610 ifp->if_watchdog = ed_watchdog; 1611 ifp->if_init = ed_init; 1612 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 1613 ifp->if_linkmib = &sc->mibdata; 1614 ifp->if_linkmiblen = sizeof sc->mibdata; 1615 /* 1616 * XXX - should do a better job. 1617 */ 1618 if (sc->is790) 1619 sc->mibdata.dot3StatsEtherChipSet = 1620 DOT3CHIPSET(dot3VendorWesternDigital, 1621 dot3ChipSetWesternDigital83C790); 1622 else 1623 sc->mibdata.dot3StatsEtherChipSet = 1624 DOT3CHIPSET(dot3VendorNational, 1625 dot3ChipSetNational8390); 1626 sc->mibdata.dot3Compliance = DOT3COMPLIANCE_COLLS; 1627 1628 /* 1629 * Set default state for ALTPHYS flag (used to disable the 1630 * tranceiver for AUI operation), based on compile-time 1631 * config option. 1632 */ 1633 if (flags & ED_FLAGS_DISABLE_TRANCEIVER) 1634 ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX | 1635 IFF_MULTICAST | IFF_ALTPHYS); 1636 else 1637 ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX | 1638 IFF_MULTICAST); 1639 1640 /* 1641 * Attach the interface 1642 */ 1643 if_attach(ifp); 1644 ether_ifattach(ifp); 1645 } 1646 /* device attach does transition from UNCONFIGURED to IDLE state */ 1647 1648 /* 1649 * Print additional info when attached 1650 */ 1651 printf("%s%d: address %6D, ", ifp->if_name, ifp->if_unit, 1652 sc->arpcom.ac_enaddr, ":"); 1653 1654 if (sc->type_str && (*sc->type_str != 0)) 1655 printf("type %s ", sc->type_str); 1656 else 1657 printf("type unknown (0x%x) ", sc->type); 1658 1659 if (sc->vendor == ED_VENDOR_HP) 1660 printf("(%s %s IO)", (sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS) ? 1661 "16-bit" : "32-bit", 1662 sc->hpp_mem_start ? "memory mapped" : "regular"); 1663 else 1664 printf("%s ", sc->isa16bit ? "(16 bit)" : "(8 bit)"); 1665 1666 printf("%s\n", (((sc->vendor == ED_VENDOR_3COM) || 1667 (sc->vendor == ED_VENDOR_HP)) && 1668 (ifp->if_flags & IFF_ALTPHYS)) ? " tranceiver disabled" : ""); 1669 1670 /* 1671 * If BPF is in the kernel, call the attach for it 1672 */ 1673 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header)); 1674 return (0); 1675} 1676 1677/* 1678 * Reset interface. 1679 */ 1680static void 1681ed_reset(ifp) 1682 struct ifnet *ifp; 1683{ 1684 struct ed_softc *sc = ifp->if_softc; 1685 int s; 1686 1687 if (sc->gone) 1688 return; 1689 s = splimp(); 1690 1691 /* 1692 * Stop interface and re-initialize. 1693 */ 1694 ed_stop(sc); 1695 ed_init(sc); 1696 1697 (void) splx(s); 1698} 1699 1700/* 1701 * Take interface offline. 1702 */ 1703static void 1704ed_stop(sc) 1705 struct ed_softc *sc; 1706{ 1707 int n = 5000; 1708 1709 if (sc->gone) 1710 return; 1711 /* 1712 * Stop everything on the interface, and select page 0 registers. 1713 */ 1714 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP); 1715 1716 /* 1717 * Wait for interface to enter stopped state, but limit # of checks to 1718 * 'n' (about 5ms). It shouldn't even take 5us on modern DS8390's, but 1719 * just in case it's an old one. 1720 */ 1721 while (((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RST) == 0) && --n); 1722} 1723 1724/* 1725 * Device timeout/watchdog routine. Entered if the device neglects to 1726 * generate an interrupt after a transmit has been started on it. 1727 */ 1728static void 1729ed_watchdog(ifp) 1730 struct ifnet *ifp; 1731{ 1732 struct ed_softc *sc = ifp->if_softc; 1733 1734 if (sc->gone) 1735 return; 1736 log(LOG_ERR, "ed%d: device timeout\n", ifp->if_unit); 1737 ifp->if_oerrors++; 1738 1739 ed_reset(ifp); 1740} 1741 1742/* 1743 * Initialize device. 1744 */ 1745static void 1746ed_init(xsc) 1747 void *xsc; 1748{ 1749 struct ed_softc *sc = xsc; 1750 struct ifnet *ifp = &sc->arpcom.ac_if; 1751 int i, s; 1752 1753 if (sc->gone) 1754 return; 1755 1756 /* address not known */ 1757 if (TAILQ_EMPTY(&ifp->if_addrhead)) /* unlikely? XXX */ 1758 return; 1759 1760 /* 1761 * Initialize the NIC in the exact order outlined in the NS manual. 1762 * This init procedure is "mandatory"...don't change what or when 1763 * things happen. 1764 */ 1765 s = splimp(); 1766 1767 /* reset transmitter flags */ 1768 sc->xmit_busy = 0; 1769 ifp->if_timer = 0; 1770 1771 sc->txb_inuse = 0; 1772 sc->txb_new = 0; 1773 sc->txb_next_tx = 0; 1774 1775 /* This variable is used below - don't move this assignment */ 1776 sc->next_packet = sc->rec_page_start + 1; 1777 1778 /* 1779 * Set interface for page 0, Remote DMA complete, Stopped 1780 */ 1781 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP); 1782 1783 if (sc->isa16bit) { 1784 1785 /* 1786 * Set FIFO threshold to 8, No auto-init Remote DMA, byte 1787 * order=80x86, word-wide DMA xfers, 1788 */ 1789 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1 | ED_DCR_WTS | ED_DCR_LS); 1790 } else { 1791 1792 /* 1793 * Same as above, but byte-wide DMA xfers 1794 */ 1795 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS); 1796 } 1797 1798 /* 1799 * Clear Remote Byte Count Registers 1800 */ 1801 outb(sc->nic_addr + ED_P0_RBCR0, 0); 1802 outb(sc->nic_addr + ED_P0_RBCR1, 0); 1803 1804 /* 1805 * For the moment, don't store incoming packets in memory. 1806 */ 1807 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_MON); 1808 1809 /* 1810 * Place NIC in internal loopback mode 1811 */ 1812 outb(sc->nic_addr + ED_P0_TCR, ED_TCR_LB0); 1813 1814 /* 1815 * Initialize transmit/receive (ring-buffer) Page Start 1816 */ 1817 outb(sc->nic_addr + ED_P0_TPSR, sc->tx_page_start); 1818 outb(sc->nic_addr + ED_P0_PSTART, sc->rec_page_start); 1819 /* Set lower bits of byte addressable framing to 0 */ 1820 if (sc->is790) 1821 outb(sc->nic_addr + 0x09, 0); 1822 1823 /* 1824 * Initialize Receiver (ring-buffer) Page Stop and Boundry 1825 */ 1826 outb(sc->nic_addr + ED_P0_PSTOP, sc->rec_page_stop); 1827 outb(sc->nic_addr + ED_P0_BNRY, sc->rec_page_start); 1828 1829 /* 1830 * Clear all interrupts. A '1' in each bit position clears the 1831 * corresponding flag. 1832 */ 1833 outb(sc->nic_addr + ED_P0_ISR, 0xff); 1834 1835 /* 1836 * Enable the following interrupts: receive/transmit complete, 1837 * receive/transmit error, and Receiver OverWrite. 1838 * 1839 * Counter overflow and Remote DMA complete are *not* enabled. 1840 */ 1841 outb(sc->nic_addr + ED_P0_IMR, 1842 ED_IMR_PRXE | ED_IMR_PTXE | ED_IMR_RXEE | ED_IMR_TXEE | ED_IMR_OVWE); 1843 1844 /* 1845 * Program Command Register for page 1 1846 */ 1847 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP); 1848 1849 /* 1850 * Copy out our station address 1851 */ 1852 for (i = 0; i < ETHER_ADDR_LEN; ++i) 1853 outb(sc->nic_addr + ED_P1_PAR(i), sc->arpcom.ac_enaddr[i]); 1854 1855 /* 1856 * Set Current Page pointer to next_packet (initialized above) 1857 */ 1858 outb(sc->nic_addr + ED_P1_CURR, sc->next_packet); 1859 1860 /* 1861 * Program Receiver Configuration Register and multicast filter. CR is 1862 * set to page 0 on return. 1863 */ 1864 ed_setrcr(sc); 1865 1866 /* 1867 * Take interface out of loopback 1868 */ 1869 outb(sc->nic_addr + ED_P0_TCR, 0); 1870 1871 /* 1872 * If this is a 3Com board, the tranceiver must be software enabled 1873 * (there is no settable hardware default). 1874 */ 1875 if (sc->vendor == ED_VENDOR_3COM) { 1876 if (ifp->if_flags & IFF_ALTPHYS) { 1877 outb(sc->asic_addr + ED_3COM_CR, 0); 1878 } else { 1879 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL); 1880 } 1881 } 1882 1883 /* 1884 * Set 'running' flag, and clear output active flag. 1885 */ 1886 ifp->if_flags |= IFF_RUNNING; 1887 ifp->if_flags &= ~IFF_OACTIVE; 1888 1889 /* 1890 * ...and attempt to start output 1891 */ 1892 ed_start(ifp); 1893 1894 (void) splx(s); 1895} 1896 1897/* 1898 * This routine actually starts the transmission on the interface 1899 */ 1900static __inline void 1901ed_xmit(sc) 1902 struct ed_softc *sc; 1903{ 1904 struct ifnet *ifp = (struct ifnet *)sc; 1905 unsigned short len; 1906 1907 if (sc->gone) 1908 return; 1909 len = sc->txb_len[sc->txb_next_tx]; 1910 1911 /* 1912 * Set NIC for page 0 register access 1913 */ 1914 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA); 1915 1916 /* 1917 * Set TX buffer start page 1918 */ 1919 outb(sc->nic_addr + ED_P0_TPSR, sc->tx_page_start + 1920 sc->txb_next_tx * ED_TXBUF_SIZE); 1921 1922 /* 1923 * Set TX length 1924 */ 1925 outb(sc->nic_addr + ED_P0_TBCR0, len); 1926 outb(sc->nic_addr + ED_P0_TBCR1, len >> 8); 1927 1928 /* 1929 * Set page 0, Remote DMA complete, Transmit Packet, and *Start* 1930 */ 1931 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_TXP | ED_CR_STA); 1932 sc->xmit_busy = 1; 1933 1934 /* 1935 * Point to next transmit buffer slot and wrap if necessary. 1936 */ 1937 sc->txb_next_tx++; 1938 if (sc->txb_next_tx == sc->txb_cnt) 1939 sc->txb_next_tx = 0; 1940 1941 /* 1942 * Set a timer just in case we never hear from the board again 1943 */ 1944 ifp->if_timer = 2; 1945} 1946 1947/* 1948 * Start output on interface. 1949 * We make two assumptions here: 1950 * 1) that the current priority is set to splimp _before_ this code 1951 * is called *and* is returned to the appropriate priority after 1952 * return 1953 * 2) that the IFF_OACTIVE flag is checked before this code is called 1954 * (i.e. that the output part of the interface is idle) 1955 */ 1956static void 1957ed_start(ifp) 1958 struct ifnet *ifp; 1959{ 1960 struct ed_softc *sc = ifp->if_softc; 1961 struct mbuf *m0, *m; 1962 caddr_t buffer; 1963 int len; 1964 1965 if (sc->gone) { 1966 printf("ed_start(%p) GONE\n",ifp); 1967 return; 1968 } 1969outloop: 1970 1971 /* 1972 * First, see if there are buffered packets and an idle transmitter - 1973 * should never happen at this point. 1974 */ 1975 if (sc->txb_inuse && (sc->xmit_busy == 0)) { 1976 printf("ed: packets buffered, but transmitter idle\n"); 1977 ed_xmit(sc); 1978 } 1979 1980 /* 1981 * See if there is room to put another packet in the buffer. 1982 */ 1983 if (sc->txb_inuse == sc->txb_cnt) { 1984 1985 /* 1986 * No room. Indicate this to the outside world and exit. 1987 */ 1988 ifp->if_flags |= IFF_OACTIVE; 1989 return; 1990 } 1991 IF_DEQUEUE(&ifp->if_snd, m); 1992 if (m == 0) { 1993 1994 /* 1995 * We are using the !OACTIVE flag to indicate to the outside 1996 * world that we can accept an additional packet rather than 1997 * that the transmitter is _actually_ active. Indeed, the 1998 * transmitter may be active, but if we haven't filled all the 1999 * buffers with data then we still want to accept more. 2000 */ 2001 ifp->if_flags &= ~IFF_OACTIVE; 2002 return; 2003 } 2004 2005 /* 2006 * Copy the mbuf chain into the transmit buffer 2007 */ 2008 2009 m0 = m; 2010 2011 /* txb_new points to next open buffer slot */ 2012 buffer = sc->mem_start + (sc->txb_new * ED_TXBUF_SIZE * ED_PAGE_SIZE); 2013 2014 if (sc->mem_shared) { 2015 2016 /* 2017 * Special case setup for 16 bit boards... 2018 */ 2019 if (sc->isa16bit) { 2020 switch (sc->vendor) { 2021 2022 /* 2023 * For 16bit 3Com boards (which have 16k of 2024 * memory), we have the xmit buffers in a 2025 * different page of memory ('page 0') - so 2026 * change pages. 2027 */ 2028 case ED_VENDOR_3COM: 2029 outb(sc->asic_addr + ED_3COM_GACFR, 2030 ED_3COM_GACFR_RSEL); 2031 break; 2032 2033 /* 2034 * Enable 16bit access to shared memory on 2035 * WD/SMC boards. 2036 */ 2037 case ED_VENDOR_WD_SMC:{ 2038 outb(sc->asic_addr + ED_WD_LAAR, 2039 sc->wd_laar_proto | ED_WD_LAAR_M16EN); 2040 if (sc->is790) { 2041 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_MENB); 2042 } 2043 break; 2044 } 2045 } 2046 } 2047 for (len = 0; m != 0; m = m->m_next) { 2048 bcopy(mtod(m, caddr_t), buffer, m->m_len); 2049 buffer += m->m_len; 2050 len += m->m_len; 2051 } 2052 2053 /* 2054 * Restore previous shared memory access 2055 */ 2056 if (sc->isa16bit) { 2057 switch (sc->vendor) { 2058 case ED_VENDOR_3COM: 2059 outb(sc->asic_addr + ED_3COM_GACFR, 2060 ED_3COM_GACFR_RSEL | ED_3COM_GACFR_MBS0); 2061 break; 2062 case ED_VENDOR_WD_SMC:{ 2063 if (sc->is790) { 2064 outb(sc->asic_addr + ED_WD_MSR, 0x00); 2065 } 2066 outb(sc->asic_addr + ED_WD_LAAR, 2067 sc->wd_laar_proto & ~ED_WD_LAAR_M16EN); 2068 break; 2069 } 2070 } 2071 } 2072 } else { 2073 len = ed_pio_write_mbufs(sc, m, (int)buffer); 2074 if (len == 0) 2075 goto outloop; 2076 } 2077 2078 sc->txb_len[sc->txb_new] = max(len, (ETHER_MIN_LEN-ETHER_CRC_LEN)); 2079 2080 sc->txb_inuse++; 2081 2082 /* 2083 * Point to next buffer slot and wrap if necessary. 2084 */ 2085 sc->txb_new++; 2086 if (sc->txb_new == sc->txb_cnt) 2087 sc->txb_new = 0; 2088 2089 if (sc->xmit_busy == 0) 2090 ed_xmit(sc); 2091 2092 /* 2093 * Tap off here if there is a bpf listener. 2094 */ 2095 if (ifp->if_bpf) { 2096 bpf_mtap(ifp, m0); 2097 } 2098 2099 m_freem(m0); 2100 2101 /* 2102 * Loop back to the top to possibly buffer more packets 2103 */ 2104 goto outloop; 2105} 2106 2107/* 2108 * Ethernet interface receiver interrupt. 2109 */ 2110static __inline void 2111ed_rint(sc) 2112 struct ed_softc *sc; 2113{ 2114 struct ifnet *ifp = &sc->arpcom.ac_if; 2115 u_char boundry; 2116 u_short len; 2117 struct ed_ring packet_hdr; 2118 char *packet_ptr; 2119 2120 if (sc->gone) 2121 return; 2122 2123 /* 2124 * Set NIC to page 1 registers to get 'current' pointer 2125 */ 2126 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA); 2127 2128 /* 2129 * 'sc->next_packet' is the logical beginning of the ring-buffer - 2130 * i.e. it points to where new data has been buffered. The 'CURR' 2131 * (current) register points to the logical end of the ring-buffer - 2132 * i.e. it points to where additional new data will be added. We loop 2133 * here until the logical beginning equals the logical end (or in 2134 * other words, until the ring-buffer is empty). 2135 */ 2136 while (sc->next_packet != inb(sc->nic_addr + ED_P1_CURR)) { 2137 2138 /* get pointer to this buffer's header structure */ 2139 packet_ptr = sc->mem_ring + 2140 (sc->next_packet - sc->rec_page_start) * ED_PAGE_SIZE; 2141 2142 /* 2143 * The byte count includes a 4 byte header that was added by 2144 * the NIC. 2145 */ 2146 if (sc->mem_shared) 2147 packet_hdr = *(struct ed_ring *) packet_ptr; 2148 else 2149 ed_pio_readmem(sc, (int)packet_ptr, (char *) &packet_hdr, 2150 sizeof(packet_hdr)); 2151 len = packet_hdr.count; 2152 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring)) || 2153 len < (ETHER_MIN_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring))) { 2154 /* 2155 * Length is a wild value. There's a good chance that 2156 * this was caused by the NIC being old and buggy. 2157 * The bug is that the length low byte is duplicated in 2158 * the high byte. Try to recalculate the length based on 2159 * the pointer to the next packet. 2160 */ 2161 /* 2162 * NOTE: sc->next_packet is pointing at the current packet. 2163 */ 2164 len &= ED_PAGE_SIZE - 1; /* preserve offset into page */ 2165 if (packet_hdr.next_packet >= sc->next_packet) { 2166 len += (packet_hdr.next_packet - sc->next_packet) * ED_PAGE_SIZE; 2167 } else { 2168 len += ((packet_hdr.next_packet - sc->rec_page_start) + 2169 (sc->rec_page_stop - sc->next_packet)) * ED_PAGE_SIZE; 2170 } 2171 /* 2172 * because buffers are aligned on 256-byte boundary, 2173 * the length computed above is off by 256 in almost 2174 * all cases. Fix it... 2175 */ 2176 if (len & 0xff) 2177 len -= 256 ; 2178 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN 2179 + sizeof(struct ed_ring))) 2180 sc->mibdata.dot3StatsFrameTooLongs++; 2181 } 2182 /* 2183 * Be fairly liberal about what we allow as a "reasonable" length 2184 * so that a [crufty] packet will make it to BPF (and can thus 2185 * be analyzed). Note that all that is really important is that 2186 * we have a length that will fit into one mbuf cluster or less; 2187 * the upper layer protocols can then figure out the length from 2188 * their own length field(s). 2189 */ 2190 if ((len > sizeof(struct ed_ring)) && 2191 (len <= MCLBYTES) && 2192 (packet_hdr.next_packet >= sc->rec_page_start) && 2193 (packet_hdr.next_packet < sc->rec_page_stop)) { 2194 /* 2195 * Go get packet. 2196 */ 2197 ed_get_packet(sc, packet_ptr + sizeof(struct ed_ring), 2198 len - sizeof(struct ed_ring), packet_hdr.rsr & ED_RSR_PHY); 2199 ifp->if_ipackets++; 2200 } else { 2201 /* 2202 * Really BAD. The ring pointers are corrupted. 2203 */ 2204 log(LOG_ERR, 2205 "ed%d: NIC memory corrupt - invalid packet length %d\n", 2206 ifp->if_unit, len); 2207 ifp->if_ierrors++; 2208 ed_reset(ifp); 2209 return; 2210 } 2211 2212 /* 2213 * Update next packet pointer 2214 */ 2215 sc->next_packet = packet_hdr.next_packet; 2216 2217 /* 2218 * Update NIC boundry pointer - being careful to keep it one 2219 * buffer behind. (as recommended by NS databook) 2220 */ 2221 boundry = sc->next_packet - 1; 2222 if (boundry < sc->rec_page_start) 2223 boundry = sc->rec_page_stop - 1; 2224 2225 /* 2226 * Set NIC to page 0 registers to update boundry register 2227 */ 2228 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA); 2229 2230 outb(sc->nic_addr + ED_P0_BNRY, boundry); 2231 2232 /* 2233 * Set NIC to page 1 registers before looping to top (prepare 2234 * to get 'CURR' current pointer) 2235 */ 2236 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA); 2237 } 2238} 2239 2240/* 2241 * Ethernet interface interrupt processor 2242 */ 2243void 2244edintr(arg) 2245 void *arg; 2246{ 2247 struct ed_softc *sc = (struct ed_softc*) arg; 2248 struct ifnet *ifp = (struct ifnet *)sc; 2249 u_char isr; 2250 2251 if (sc->gone) 2252 return; 2253 /* 2254 * Set NIC to page 0 registers 2255 */ 2256 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA); 2257 2258 /* 2259 * loop until there are no more new interrupts 2260 */ 2261 while ((isr = inb(sc->nic_addr + ED_P0_ISR)) != 0) { 2262 2263 /* 2264 * reset all the bits that we are 'acknowledging' by writing a 2265 * '1' to each bit position that was set (writing a '1' 2266 * *clears* the bit) 2267 */ 2268 outb(sc->nic_addr + ED_P0_ISR, isr); 2269 2270 /* 2271 * Handle transmitter interrupts. Handle these first because 2272 * the receiver will reset the board under some conditions. 2273 */ 2274 if (isr & (ED_ISR_PTX | ED_ISR_TXE)) { 2275 u_char collisions = inb(sc->nic_addr + ED_P0_NCR) & 0x0f; 2276 2277 /* 2278 * Check for transmit error. If a TX completed with an 2279 * error, we end up throwing the packet away. Really 2280 * the only error that is possible is excessive 2281 * collisions, and in this case it is best to allow 2282 * the automatic mechanisms of TCP to backoff the 2283 * flow. Of course, with UDP we're screwed, but this 2284 * is expected when a network is heavily loaded. 2285 */ 2286 (void) inb(sc->nic_addr + ED_P0_TSR); 2287 if (isr & ED_ISR_TXE) { 2288 u_char tsr; 2289 2290 /* 2291 * Excessive collisions (16) 2292 */ 2293 tsr = inb(sc->nic_addr + ED_P0_TSR); 2294 if ((tsr & ED_TSR_ABT) 2295 && (collisions == 0)) { 2296 2297 /* 2298 * When collisions total 16, the 2299 * P0_NCR will indicate 0, and the 2300 * TSR_ABT is set. 2301 */ 2302 collisions = 16; 2303 sc->mibdata.dot3StatsExcessiveCollisions++; 2304 sc->mibdata.dot3StatsCollFrequencies[15]++; 2305 } 2306 if (tsr & ED_TSR_OWC) 2307 sc->mibdata.dot3StatsLateCollisions++; 2308 if (tsr & ED_TSR_CDH) 2309 sc->mibdata.dot3StatsSQETestErrors++; 2310 if (tsr & ED_TSR_CRS) 2311 sc->mibdata.dot3StatsCarrierSenseErrors++; 2312 if (tsr & ED_TSR_FU) 2313 sc->mibdata.dot3StatsInternalMacTransmitErrors++; 2314 2315 /* 2316 * update output errors counter 2317 */ 2318 ifp->if_oerrors++; 2319 } else { 2320 2321 /* 2322 * Update total number of successfully 2323 * transmitted packets. 2324 */ 2325 ifp->if_opackets++; 2326 } 2327 2328 /* 2329 * reset tx busy and output active flags 2330 */ 2331 sc->xmit_busy = 0; 2332 ifp->if_flags &= ~IFF_OACTIVE; 2333 2334 /* 2335 * clear watchdog timer 2336 */ 2337 ifp->if_timer = 0; 2338 2339 /* 2340 * Add in total number of collisions on last 2341 * transmission. 2342 */ 2343 ifp->if_collisions += collisions; 2344 switch(collisions) { 2345 case 0: 2346 case 16: 2347 break; 2348 case 1: 2349 sc->mibdata.dot3StatsSingleCollisionFrames++; 2350 sc->mibdata.dot3StatsCollFrequencies[0]++; 2351 break; 2352 default: 2353 sc->mibdata.dot3StatsMultipleCollisionFrames++; 2354 sc->mibdata. 2355 dot3StatsCollFrequencies[collisions-1] 2356 ++; 2357 break; 2358 } 2359 2360 /* 2361 * Decrement buffer in-use count if not zero (can only 2362 * be zero if a transmitter interrupt occured while 2363 * not actually transmitting). If data is ready to 2364 * transmit, start it transmitting, otherwise defer 2365 * until after handling receiver 2366 */ 2367 if (sc->txb_inuse && --sc->txb_inuse) 2368 ed_xmit(sc); 2369 } 2370 2371 /* 2372 * Handle receiver interrupts 2373 */ 2374 if (isr & (ED_ISR_PRX | ED_ISR_RXE | ED_ISR_OVW)) { 2375 2376 /* 2377 * Overwrite warning. In order to make sure that a 2378 * lockup of the local DMA hasn't occurred, we reset 2379 * and re-init the NIC. The NSC manual suggests only a 2380 * partial reset/re-init is necessary - but some chips 2381 * seem to want more. The DMA lockup has been seen 2382 * only with early rev chips - Methinks this bug was 2383 * fixed in later revs. -DG 2384 */ 2385 if (isr & ED_ISR_OVW) { 2386 ifp->if_ierrors++; 2387#ifdef DIAGNOSTIC 2388 log(LOG_WARNING, 2389 "ed%d: warning - receiver ring buffer overrun\n", 2390 ifp->if_unit); 2391#endif 2392 2393 /* 2394 * Stop/reset/re-init NIC 2395 */ 2396 ed_reset(ifp); 2397 } else { 2398 2399 /* 2400 * Receiver Error. One or more of: CRC error, 2401 * frame alignment error FIFO overrun, or 2402 * missed packet. 2403 */ 2404 if (isr & ED_ISR_RXE) { 2405 u_char rsr; 2406 rsr = inb(sc->nic_addr + ED_P0_RSR); 2407 if (rsr & ED_RSR_CRC) 2408 sc->mibdata.dot3StatsFCSErrors++; 2409 if (rsr & ED_RSR_FAE) 2410 sc->mibdata.dot3StatsAlignmentErrors++; 2411 if (rsr & ED_RSR_FO) 2412 sc->mibdata.dot3StatsInternalMacReceiveErrors++; 2413 ifp->if_ierrors++; 2414#ifdef ED_DEBUG 2415 printf("ed%d: receive error %x\n", ifp->if_unit, 2416 inb(sc->nic_addr + ED_P0_RSR)); 2417#endif 2418 } 2419 2420 /* 2421 * Go get the packet(s) XXX - Doing this on an 2422 * error is dubious because there shouldn't be 2423 * any data to get (we've configured the 2424 * interface to not accept packets with 2425 * errors). 2426 */ 2427 2428 /* 2429 * Enable 16bit access to shared memory first 2430 * on WD/SMC boards. 2431 */ 2432 if (sc->isa16bit && 2433 (sc->vendor == ED_VENDOR_WD_SMC)) { 2434 2435 outb(sc->asic_addr + ED_WD_LAAR, 2436 sc->wd_laar_proto | ED_WD_LAAR_M16EN); 2437 if (sc->is790) { 2438 outb(sc->asic_addr + ED_WD_MSR, 2439 ED_WD_MSR_MENB); 2440 } 2441 } 2442 ed_rint(sc); 2443 2444 /* disable 16bit access */ 2445 if (sc->isa16bit && 2446 (sc->vendor == ED_VENDOR_WD_SMC)) { 2447 2448 if (sc->is790) { 2449 outb(sc->asic_addr + ED_WD_MSR, 0x00); 2450 } 2451 outb(sc->asic_addr + ED_WD_LAAR, 2452 sc->wd_laar_proto & ~ED_WD_LAAR_M16EN); 2453 } 2454 } 2455 } 2456 2457 /* 2458 * If it looks like the transmitter can take more data, 2459 * attempt to start output on the interface. This is done 2460 * after handling the receiver to give the receiver priority. 2461 */ 2462 if ((ifp->if_flags & IFF_OACTIVE) == 0) 2463 ed_start(ifp); 2464 2465 /* 2466 * return NIC CR to standard state: page 0, remote DMA 2467 * complete, start (toggling the TXP bit off, even if was just 2468 * set in the transmit routine, is *okay* - it is 'edge' 2469 * triggered from low to high) 2470 */ 2471 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA); 2472 2473 /* 2474 * If the Network Talley Counters overflow, read them to reset 2475 * them. It appears that old 8390's won't clear the ISR flag 2476 * otherwise - resulting in an infinite loop. 2477 */ 2478 if (isr & ED_ISR_CNT) { 2479 (void) inb(sc->nic_addr + ED_P0_CNTR0); 2480 (void) inb(sc->nic_addr + ED_P0_CNTR1); 2481 (void) inb(sc->nic_addr + ED_P0_CNTR2); 2482 } 2483 } 2484} 2485 2486/* 2487 * Process an ioctl request. This code needs some work - it looks 2488 * pretty ugly. 2489 */ 2490static int 2491ed_ioctl(ifp, command, data) 2492 register struct ifnet *ifp; 2493 u_long command; 2494 caddr_t data; 2495{ 2496 struct ed_softc *sc = ifp->if_softc; 2497 int s, error = 0; 2498 2499 if (sc->gone) { 2500 ifp->if_flags &= ~IFF_RUNNING; 2501 return ENXIO; 2502 } 2503 s = splimp(); 2504 2505 switch (command) { 2506 2507 case SIOCSIFADDR: 2508 case SIOCGIFADDR: 2509 case SIOCSIFMTU: 2510 error = ether_ioctl(ifp, command, data); 2511 break; 2512 2513 case SIOCSIFFLAGS: 2514 2515 /* 2516 * If the interface is marked up and stopped, then start it. 2517 * If it is marked down and running, then stop it. 2518 */ 2519 if (ifp->if_flags & IFF_UP) { 2520 if ((ifp->if_flags & IFF_RUNNING) == 0) 2521 ed_init(sc); 2522 } else { 2523 if (ifp->if_flags & IFF_RUNNING) { 2524 ed_stop(sc); 2525 ifp->if_flags &= ~IFF_RUNNING; 2526 } 2527 } 2528 2529 /* 2530 * Promiscuous flag may have changed, so reprogram the RCR. 2531 */ 2532 ed_setrcr(sc); 2533 2534 /* 2535 * An unfortunate hack to provide the (required) software 2536 * control of the tranceiver for 3Com boards. The ALTPHYS flag 2537 * disables the tranceiver if set. 2538 */ 2539 if (sc->vendor == ED_VENDOR_3COM) { 2540 if (ifp->if_flags & IFF_ALTPHYS) { 2541 outb(sc->asic_addr + ED_3COM_CR, 0); 2542 } else { 2543 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL); 2544 } 2545 } else if (sc->vendor == ED_VENDOR_HP) 2546 ed_hpp_set_physical_link(sc); 2547 break; 2548 2549 case SIOCADDMULTI: 2550 case SIOCDELMULTI: 2551 /* 2552 * Multicast list has changed; set the hardware filter 2553 * accordingly. 2554 */ 2555 ed_setrcr(sc); 2556 error = 0; 2557 break; 2558 2559 default: 2560 error = EINVAL; 2561 } 2562 (void) splx(s); 2563 return (error); 2564} 2565 2566/* 2567 * Given a source and destination address, copy 'amount' of a packet from 2568 * the ring buffer into a linear destination buffer. Takes into account 2569 * ring-wrap. 2570 */ 2571static __inline char * 2572ed_ring_copy(sc, src, dst, amount) 2573 struct ed_softc *sc; 2574 char *src; 2575 char *dst; 2576 u_short amount; 2577{ 2578 u_short tmp_amount; 2579 2580 /* does copy wrap to lower addr in ring buffer? */ 2581 if (src + amount > sc->mem_end) { 2582 tmp_amount = sc->mem_end - src; 2583 2584 /* copy amount up to end of NIC memory */ 2585 if (sc->mem_shared) 2586 bcopy(src, dst, tmp_amount); 2587 else 2588 ed_pio_readmem(sc, (int)src, dst, tmp_amount); 2589 2590 amount -= tmp_amount; 2591 src = sc->mem_ring; 2592 dst += tmp_amount; 2593 } 2594 if (sc->mem_shared) 2595 bcopy(src, dst, amount); 2596 else 2597 ed_pio_readmem(sc, (int)src, dst, amount); 2598 2599 return (src + amount); 2600} 2601 2602/* 2603 * Retreive packet from shared memory and send to the next level up via 2604 * ether_input(). If there is a BPF listener, give a copy to BPF, too. 2605 */ 2606static void 2607ed_get_packet(sc, buf, len, multicast) 2608 struct ed_softc *sc; 2609 char *buf; 2610 u_short len; 2611 int multicast; 2612{ 2613 struct ether_header *eh; 2614 struct mbuf *m; 2615 2616 /* Allocate a header mbuf */ 2617 MGETHDR(m, M_DONTWAIT, MT_DATA); 2618 if (m == NULL) 2619 return; 2620 m->m_pkthdr.rcvif = &sc->arpcom.ac_if; 2621 m->m_pkthdr.len = m->m_len = len; 2622 2623 /* 2624 * We always put the received packet in a single buffer - 2625 * either with just an mbuf header or in a cluster attached 2626 * to the header. The +2 is to compensate for the alignment 2627 * fixup below. 2628 */ 2629 if ((len + 2) > MHLEN) { 2630 /* Attach an mbuf cluster */ 2631 MCLGET(m, M_DONTWAIT); 2632 2633 /* Insist on getting a cluster */ 2634 if ((m->m_flags & M_EXT) == 0) { 2635 m_freem(m); 2636 return; 2637 } 2638 } 2639 2640 /* 2641 * The +2 is to longword align the start of the real packet. 2642 * This is important for NFS. 2643 */ 2644 m->m_data += 2; 2645 eh = mtod(m, struct ether_header *); 2646 2647#ifdef BRIDGE 2648 /* 2649 * Get link layer header, invoke brige_in, then 2650 * depending on the outcome of the test fetch the rest of the 2651 * packet and either pass up or call bdg_forward. 2652 */ 2653 if (do_bridge) { 2654 struct ifnet *ifp ; 2655 int need_more = 1 ; /* in case not bpf */ 2656 2657 if (sc->arpcom.ac_if.if_bpf) { 2658 need_more = 0 ; 2659 ed_ring_copy(sc, buf, (char *)eh, len); 2660 bpf_mtap(&sc->arpcom.ac_if, m); 2661 } else 2662 ed_ring_copy(sc, buf, (char *)eh, 14); 2663 ifp = bridge_in(m); 2664 if (ifp == BDG_DROP) { 2665 m_freem(m); 2666 return ; 2667 } 2668 /* else fetch rest of pkt and continue */ 2669 if (need_more && len > 14) 2670 ed_ring_copy(sc, buf+14, (char *)(eh+1), len - 14); 2671 if (ifp != BDG_LOCAL ) 2672 bdg_forward(&m, ifp); /* not local, need forwarding */ 2673 if (ifp == BDG_LOCAL || ifp == BDG_BCAST || ifp == BDG_MCAST) 2674 goto getit ; 2675 /* not local and not multicast, just drop it */ 2676 if (m) 2677 m_freem(m); 2678 return ; 2679 } 2680#endif 2681 /* 2682 * Get packet, including link layer address, from interface. 2683 */ 2684 ed_ring_copy(sc, buf, (char *)eh, len); 2685 2686 /* 2687 * Check if there's a BPF listener on this interface. If so, hand off 2688 * the raw packet to bpf. 2689 */ 2690 if (sc->arpcom.ac_if.if_bpf) 2691 bpf_mtap(&sc->arpcom.ac_if, m); 2692 /* 2693 * If we are in promiscuous mode, we have to check whether 2694 * this packet is really for us. 2695 */ 2696 if ((sc->arpcom.ac_if.if_flags & IFF_PROMISC) && 2697 bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr, 2698 sizeof(eh->ether_dhost)) != 0 && multicast == 0) { 2699 m_freem(m); 2700 return; 2701 } 2702 2703#ifdef BRIDGE 2704getit: 2705#endif 2706 /* 2707 * Remove link layer address. 2708 */ 2709 m->m_pkthdr.len = m->m_len = len - sizeof(struct ether_header); 2710 m->m_data += sizeof(struct ether_header); 2711 2712 ether_input(&sc->arpcom.ac_if, eh, m); 2713 return; 2714} 2715 2716/* 2717 * Supporting routines 2718 */ 2719 2720/* 2721 * Given a NIC memory source address and a host memory destination 2722 * address, copy 'amount' from NIC to host using Programmed I/O. 2723 * The 'amount' is rounded up to a word - okay as long as mbufs 2724 * are word sized. 2725 * This routine is currently Novell-specific. 2726 */ 2727static void 2728ed_pio_readmem(sc, src, dst, amount) 2729 struct ed_softc *sc; 2730 int src; 2731 unsigned char *dst; 2732 unsigned short amount; 2733{ 2734 /* HP cards need special handling */ 2735 if (sc->vendor == ED_VENDOR_HP && sc->type == ED_TYPE_HP_PCLANPLUS) { 2736 ed_hpp_readmem(sc, src, dst, amount); 2737 return; 2738 } 2739 2740 /* Regular Novell cards */ 2741 /* select page 0 registers */ 2742 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STA); 2743 2744 /* round up to a word */ 2745 if (amount & 1) 2746 ++amount; 2747 2748 /* set up DMA byte count */ 2749 outb(sc->nic_addr + ED_P0_RBCR0, amount); 2750 outb(sc->nic_addr + ED_P0_RBCR1, amount >> 8); 2751 2752 /* set up source address in NIC mem */ 2753 outb(sc->nic_addr + ED_P0_RSAR0, src); 2754 outb(sc->nic_addr + ED_P0_RSAR1, src >> 8); 2755 2756 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD0 | ED_CR_STA); 2757 2758 if (sc->isa16bit) { 2759 insw(sc->asic_addr + ED_NOVELL_DATA, dst, amount / 2); 2760 } else 2761 insb(sc->asic_addr + ED_NOVELL_DATA, dst, amount); 2762 2763} 2764 2765/* 2766 * Stripped down routine for writing a linear buffer to NIC memory. 2767 * Only used in the probe routine to test the memory. 'len' must 2768 * be even. 2769 */ 2770static void 2771ed_pio_writemem(sc, src, dst, len) 2772 struct ed_softc *sc; 2773 char *src; 2774 unsigned short dst; 2775 unsigned short len; 2776{ 2777 int maxwait = 200; /* about 240us */ 2778 2779 if (sc->vendor == ED_VENDOR_NOVELL) { 2780 2781 /* select page 0 registers */ 2782 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STA); 2783 2784 /* reset remote DMA complete flag */ 2785 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC); 2786 2787 /* set up DMA byte count */ 2788 outb(sc->nic_addr + ED_P0_RBCR0, len); 2789 outb(sc->nic_addr + ED_P0_RBCR1, len >> 8); 2790 2791 /* set up destination address in NIC mem */ 2792 outb(sc->nic_addr + ED_P0_RSAR0, dst); 2793 outb(sc->nic_addr + ED_P0_RSAR1, dst >> 8); 2794 2795 /* set remote DMA write */ 2796 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD1 | ED_CR_STA); 2797 2798 if (sc->isa16bit) 2799 outsw(sc->asic_addr + ED_NOVELL_DATA, src, len / 2); 2800 else 2801 outsb(sc->asic_addr + ED_NOVELL_DATA, src, len); 2802 2803 /* 2804 * Wait for remote DMA complete. This is necessary because on the 2805 * transmit side, data is handled internally by the NIC in bursts and 2806 * we can't start another remote DMA until this one completes. Not 2807 * waiting causes really bad things to happen - like the NIC 2808 * irrecoverably jamming the ISA bus. 2809 */ 2810 while (((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait); 2811 2812 } else if ((sc->vendor == ED_VENDOR_HP) && 2813 (sc->type == ED_TYPE_HP_PCLANPLUS)) { 2814 2815 /* HP PCLAN+ */ 2816 2817 /* reset remote DMA complete flag */ 2818 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC); 2819 2820 /* program the write address in RAM */ 2821 outw(sc->asic_addr + ED_HPP_PAGE_0, dst); 2822 2823 if (sc->hpp_mem_start) { 2824 u_short *s = (u_short *) src; 2825 volatile u_short *d = (u_short *) sc->hpp_mem_start; 2826 u_short *const fence = s + (len >> 1); 2827 2828 /* 2829 * Enable memory mapped access. 2830 */ 2831 2832 outw(sc->asic_addr + ED_HPP_OPTION, 2833 sc->hpp_options & 2834 ~(ED_HPP_OPTION_MEM_DISABLE | 2835 ED_HPP_OPTION_BOOT_ROM_ENB)); 2836 2837 /* 2838 * Copy to NIC memory. 2839 */ 2840 2841 while (s < fence) 2842 *d = *s++; 2843 2844 /* 2845 * Restore Boot ROM access. 2846 */ 2847 2848 outw(sc->asic_addr + ED_HPP_OPTION, 2849 sc->hpp_options); 2850 2851 } else { 2852 /* write data using I/O writes */ 2853 outsw(sc->asic_addr + ED_HPP_PAGE_4, src, len / 2); 2854 } 2855 2856 } 2857} 2858 2859/* 2860 * Write an mbuf chain to the destination NIC memory address using 2861 * programmed I/O. 2862 */ 2863static u_short 2864ed_pio_write_mbufs(sc, m, dst) 2865 struct ed_softc *sc; 2866 struct mbuf *m; 2867 int dst; 2868{ 2869 struct ifnet *ifp = (struct ifnet *)sc; 2870 unsigned short total_len, dma_len; 2871 struct mbuf *mp; 2872 int maxwait = 200; /* about 240us */ 2873 2874 /* HP PC Lan+ cards need special handling */ 2875 if ((sc->vendor == ED_VENDOR_HP) && 2876 (sc->type == ED_TYPE_HP_PCLANPLUS)) { 2877 return ed_hpp_write_mbufs(sc, m, dst); 2878 } 2879 2880 /* First, count up the total number of bytes to copy */ 2881 for (total_len = 0, mp = m; mp; mp = mp->m_next) 2882 total_len += mp->m_len; 2883 2884 dma_len = total_len; 2885 if (sc->isa16bit && (dma_len & 1)) 2886 dma_len++; 2887 2888 /* select page 0 registers */ 2889 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STA); 2890 2891 /* reset remote DMA complete flag */ 2892 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC); 2893 2894 /* set up DMA byte count */ 2895 outb(sc->nic_addr + ED_P0_RBCR0, dma_len); 2896 outb(sc->nic_addr + ED_P0_RBCR1, dma_len >> 8); 2897 2898 /* set up destination address in NIC mem */ 2899 outb(sc->nic_addr + ED_P0_RSAR0, dst); 2900 outb(sc->nic_addr + ED_P0_RSAR1, dst >> 8); 2901 2902 /* set remote DMA write */ 2903 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD1 | ED_CR_STA); 2904 2905 /* 2906 * Transfer the mbuf chain to the NIC memory. 2907 * 16-bit cards require that data be transferred as words, and only words. 2908 * So that case requires some extra code to patch over odd-length mbufs. 2909 */ 2910 2911 if (!sc->isa16bit) { 2912 /* NE1000s are easy */ 2913 while (m) { 2914 if (m->m_len) { 2915 outsb(sc->asic_addr + ED_NOVELL_DATA, 2916 m->m_data, m->m_len); 2917 } 2918 m = m->m_next; 2919 } 2920 } else { 2921 /* NE2000s are a pain */ 2922 unsigned char *data; 2923 int len, wantbyte; 2924 unsigned char savebyte[2]; 2925 2926 wantbyte = 0; 2927 2928 while (m) { 2929 len = m->m_len; 2930 if (len) { 2931 data = mtod(m, caddr_t); 2932 /* finish the last word */ 2933 if (wantbyte) { 2934 savebyte[1] = *data; 2935 outw(sc->asic_addr + ED_NOVELL_DATA, *(u_short *)savebyte); 2936 data++; 2937 len--; 2938 wantbyte = 0; 2939 } 2940 /* output contiguous words */ 2941 if (len > 1) { 2942 outsw(sc->asic_addr + ED_NOVELL_DATA, 2943 data, len >> 1); 2944 data += len & ~1; 2945 len &= 1; 2946 } 2947 /* save last byte, if necessary */ 2948 if (len == 1) { 2949 savebyte[0] = *data; 2950 wantbyte = 1; 2951 } 2952 } 2953 m = m->m_next; 2954 } 2955 /* spit last byte */ 2956 if (wantbyte) { 2957 outw(sc->asic_addr + ED_NOVELL_DATA, *(u_short *)savebyte); 2958 } 2959 } 2960 2961 /* 2962 * Wait for remote DMA complete. This is necessary because on the 2963 * transmit side, data is handled internally by the NIC in bursts and 2964 * we can't start another remote DMA until this one completes. Not 2965 * waiting causes really bad things to happen - like the NIC 2966 * irrecoverably jamming the ISA bus. 2967 */ 2968 while (((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait); 2969 2970 if (!maxwait) { 2971 log(LOG_WARNING, "ed%d: remote transmit DMA failed to complete\n", 2972 ifp->if_unit); 2973 ed_reset(ifp); 2974 return(0); 2975 } 2976 return (total_len); 2977} 2978 2979/* 2980 * Support routines to handle the HP PC Lan+ card. 2981 */ 2982 2983/* 2984 * HP PC Lan+: Read from NIC memory, using either PIO or memory mapped 2985 * IO. 2986 */ 2987 2988static void 2989ed_hpp_readmem(sc, src, dst, amount) 2990 struct ed_softc *sc; 2991 unsigned short src; 2992 unsigned char *dst; 2993 unsigned short amount; 2994{ 2995 2996 int use_32bit_access = !(sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS); 2997 2998 2999 /* Program the source address in RAM */ 3000 outw(sc->asic_addr + ED_HPP_PAGE_2, src); 3001 3002 /* 3003 * The HP PC Lan+ card supports word reads as well as 3004 * a memory mapped i/o port that is aliased to every 3005 * even address on the board. 3006 */ 3007 3008 if (sc->hpp_mem_start) { 3009 3010 /* Enable memory mapped access. */ 3011 outw(sc->asic_addr + ED_HPP_OPTION, 3012 sc->hpp_options & 3013 ~(ED_HPP_OPTION_MEM_DISABLE | 3014 ED_HPP_OPTION_BOOT_ROM_ENB)); 3015 3016 if (use_32bit_access && (amount > 3)) { 3017 u_long *dl = (u_long *) dst; 3018 volatile u_long *const sl = 3019 (u_long *) sc->hpp_mem_start; 3020 u_long *const fence = dl + (amount >> 2); 3021 3022 /* Copy out NIC data. We could probably write this 3023 as a `movsl'. The currently generated code is lousy. 3024 */ 3025 3026 while (dl < fence) 3027 *dl++ = *sl; 3028 3029 dst += (amount & ~3); 3030 amount &= 3; 3031 3032 } 3033 3034 /* Finish off any words left, as a series of short reads */ 3035 if (amount > 1) { 3036 u_short *d = (u_short *) dst; 3037 volatile u_short *const s = 3038 (u_short *) sc->hpp_mem_start; 3039 u_short *const fence = d + (amount >> 1); 3040 3041 /* Copy out NIC data. */ 3042 3043 while (d < fence) 3044 *d++ = *s; 3045 3046 dst += (amount & ~1); 3047 amount &= 1; 3048 } 3049 3050 /* 3051 * read in a byte; however we need to always read 16 bits 3052 * at a time or the hardware gets into a funny state 3053 */ 3054 3055 if (amount == 1) { 3056 /* need to read in a short and copy LSB */ 3057 volatile u_short *const s = 3058 (volatile u_short *) sc->hpp_mem_start; 3059 3060 *dst = (*s) & 0xFF; 3061 } 3062 3063 /* Restore Boot ROM access. */ 3064 3065 outw(sc->asic_addr + ED_HPP_OPTION, 3066 sc->hpp_options); 3067 3068 3069 } else { 3070 /* Read in data using the I/O port */ 3071 if (use_32bit_access && (amount > 3)) { 3072 insl(sc->asic_addr + ED_HPP_PAGE_4, dst, amount >> 2); 3073 dst += (amount & ~3); 3074 amount &= 3; 3075 } 3076 if (amount > 1) { 3077 insw(sc->asic_addr + ED_HPP_PAGE_4, dst, amount >> 1); 3078 dst += (amount & ~1); 3079 amount &= 1; 3080 } 3081 if (amount == 1) { /* read in a short and keep the LSB */ 3082 *dst = inw(sc->asic_addr + ED_HPP_PAGE_4) & 0xFF; 3083 } 3084 } 3085} 3086 3087/* 3088 * Write to HP PC Lan+ NIC memory. Access to the NIC can be by using 3089 * outsw() or via the memory mapped interface to the same register. 3090 * Writes have to be in word units; byte accesses won't work and may cause 3091 * the NIC to behave wierdly. Long word accesses are permitted if the ASIC 3092 * allows it. 3093 */ 3094 3095static u_short 3096ed_hpp_write_mbufs(struct ed_softc *sc, struct mbuf *m, int dst) 3097{ 3098 int len, wantbyte; 3099 unsigned short total_len; 3100 unsigned char savebyte[2]; 3101 volatile u_short * const d = 3102 (volatile u_short *) sc->hpp_mem_start; 3103 int use_32bit_accesses = !(sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS); 3104 3105 /* select page 0 registers */ 3106 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA); 3107 3108 /* reset remote DMA complete flag */ 3109 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC); 3110 3111 /* program the write address in RAM */ 3112 outw(sc->asic_addr + ED_HPP_PAGE_0, dst); 3113 3114 if (sc->hpp_mem_start) /* enable memory mapped I/O */ 3115 outw(sc->asic_addr + ED_HPP_OPTION, sc->hpp_options & 3116 ~(ED_HPP_OPTION_MEM_DISABLE | 3117 ED_HPP_OPTION_BOOT_ROM_ENB)); 3118 3119 wantbyte = 0; 3120 total_len = 0; 3121 3122 if (sc->hpp_mem_start) { /* Memory mapped I/O port */ 3123 while (m) { 3124 total_len += (len = m->m_len); 3125 if (len) { 3126 caddr_t data = mtod(m, caddr_t); 3127 /* finish the last word of the previous mbuf */ 3128 if (wantbyte) { 3129 savebyte[1] = *data; 3130 *d = *((ushort *) savebyte); 3131 data++; len--; wantbyte = 0; 3132 } 3133 /* output contiguous words */ 3134 if ((len > 3) && (use_32bit_accesses)) { 3135 volatile u_long *const dl = 3136 (volatile u_long *) d; 3137 u_long *sl = (u_long *) data; 3138 u_long *fence = sl + (len >> 2); 3139 3140 while (sl < fence) 3141 *dl = *sl++; 3142 3143 data += (len & ~3); 3144 len &= 3; 3145 } 3146 /* finish off remain 16 bit writes */ 3147 if (len > 1) { 3148 u_short *s = (u_short *) data; 3149 u_short *fence = s + (len >> 1); 3150 3151 while (s < fence) 3152 *d = *s++; 3153 3154 data += (len & ~1); 3155 len &= 1; 3156 } 3157 /* save last byte if needed */ 3158 if ((wantbyte = (len == 1)) != 0) 3159 savebyte[0] = *data; 3160 } 3161 m = m->m_next; /* to next mbuf */ 3162 } 3163 if (wantbyte) /* write last byte */ 3164 *d = *((u_short *) savebyte); 3165 } else { 3166 /* use programmed I/O */ 3167 while (m) { 3168 total_len += (len = m->m_len); 3169 if (len) { 3170 caddr_t data = mtod(m, caddr_t); 3171 /* finish the last word of the previous mbuf */ 3172 if (wantbyte) { 3173 savebyte[1] = *data; 3174 outw(sc->asic_addr + ED_HPP_PAGE_4, 3175 *((u_short *)savebyte)); 3176 data++; 3177 len--; 3178 wantbyte = 0; 3179 } 3180 /* output contiguous words */ 3181 if ((len > 3) && use_32bit_accesses) { 3182 outsl(sc->asic_addr + ED_HPP_PAGE_4, 3183 data, len >> 2); 3184 data += (len & ~3); 3185 len &= 3; 3186 } 3187 /* finish off remaining 16 bit accesses */ 3188 if (len > 1) { 3189 outsw(sc->asic_addr + ED_HPP_PAGE_4, 3190 data, len >> 1); 3191 data += (len & ~1); 3192 len &= 1; 3193 } 3194 if ((wantbyte = (len == 1)) != 0) 3195 savebyte[0] = *data; 3196 3197 } /* if len != 0 */ 3198 m = m->m_next; 3199 } 3200 if (wantbyte) /* spit last byte */ 3201 outw(sc->asic_addr + ED_HPP_PAGE_4, 3202 *(u_short *)savebyte); 3203 3204 } 3205 3206 if (sc->hpp_mem_start) /* turn off memory mapped i/o */ 3207 outw(sc->asic_addr + ED_HPP_OPTION, 3208 sc->hpp_options); 3209 3210 return (total_len); 3211} 3212 3213static void 3214ed_setrcr(sc) 3215 struct ed_softc *sc; 3216{ 3217 struct ifnet *ifp = (struct ifnet *)sc; 3218 int i; 3219 3220 /* set page 1 registers */ 3221 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP); 3222 3223 if (ifp->if_flags & IFF_PROMISC) { 3224 3225 /* 3226 * Reconfigure the multicast filter. 3227 */ 3228 for (i = 0; i < 8; i++) 3229 outb(sc->nic_addr + ED_P1_MAR(i), 0xff); 3230 3231 /* 3232 * And turn on promiscuous mode. Also enable reception of 3233 * runts and packets with CRC & alignment errors. 3234 */ 3235 /* Set page 0 registers */ 3236 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP); 3237 3238 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_PRO | ED_RCR_AM | 3239 ED_RCR_AB | ED_RCR_AR | ED_RCR_SEP); 3240 } else { 3241 /* set up multicast addresses and filter modes */ 3242 if (ifp->if_flags & IFF_MULTICAST) { 3243 u_long mcaf[2]; 3244 3245 if (ifp->if_flags & IFF_ALLMULTI) { 3246 mcaf[0] = 0xffffffff; 3247 mcaf[1] = 0xffffffff; 3248 } else 3249 ds_getmcaf(sc, mcaf); 3250 3251 /* 3252 * Set multicast filter on chip. 3253 */ 3254 for (i = 0; i < 8; i++) 3255 outb(sc->nic_addr + ED_P1_MAR(i), ((u_char *) mcaf)[i]); 3256 3257 /* Set page 0 registers */ 3258 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP); 3259 3260 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_AM | ED_RCR_AB); 3261 } else { 3262 3263 /* 3264 * Initialize multicast address hashing registers to 3265 * not accept multicasts. 3266 */ 3267 for (i = 0; i < 8; ++i) 3268 outb(sc->nic_addr + ED_P1_MAR(i), 0x00); 3269 3270 /* Set page 0 registers */ 3271 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP); 3272 3273 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_AB); 3274 } 3275 } 3276 3277 /* 3278 * Start interface. 3279 */ 3280 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA); 3281} 3282 3283/* 3284 * Compute crc for ethernet address 3285 */ 3286static u_long 3287ds_crc(ep) 3288 u_char *ep; 3289{ 3290#define POLYNOMIAL 0x04c11db6 3291 register u_long crc = 0xffffffffL; 3292 register int carry, i, j; 3293 register u_char b; 3294 3295 for (i = 6; --i >= 0;) { 3296 b = *ep++; 3297 for (j = 8; --j >= 0;) { 3298 carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01); 3299 crc <<= 1; 3300 b >>= 1; 3301 if (carry) 3302 crc = ((crc ^ POLYNOMIAL) | carry); 3303 } 3304 } 3305 return crc; 3306#undef POLYNOMIAL 3307} 3308 3309/* 3310 * Compute the multicast address filter from the 3311 * list of multicast addresses we need to listen to. 3312 */ 3313static void 3314ds_getmcaf(sc, mcaf) 3315 struct ed_softc *sc; 3316 u_long *mcaf; 3317{ 3318 register u_int index; 3319 register u_char *af = (u_char *) mcaf; 3320 struct ifmultiaddr *ifma; 3321 3322 mcaf[0] = 0; 3323 mcaf[1] = 0; 3324 3325 for (ifma = sc->arpcom.ac_if.if_multiaddrs.lh_first; ifma; 3326 ifma = ifma->ifma_link.le_next) { 3327 if (ifma->ifma_addr->sa_family != AF_LINK) 3328 continue; 3329 index = ds_crc(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)) 3330 >> 26; 3331 af[index >> 3] |= 1 << (index & 7); 3332 } 3333} 3334