if_ed.c revision 52473
1/* 2 * Copyright (c) 1995, David Greenman 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD: head/sys/dev/ed/if_ed.c 52473 1999-10-25 02:55:14Z imp $ 28 */ 29 30/* 31 * Device driver for National Semiconductor DS8390/WD83C690 based ethernet 32 * adapters. By David Greenman, 29-April-1993 33 * 34 * Currently supports the Western Digital/SMC 8003 and 8013 series, 35 * the SMC Elite Ultra (8216), the 3Com 3c503, the NE1000 and NE2000, 36 * and a variety of similar clones. 37 * 38 */ 39 40#include <sys/param.h> 41#include <sys/systm.h> 42#include <sys/kernel.h> 43#include <sys/sockio.h> 44#include <sys/malloc.h> 45#include <sys/mbuf.h> 46#include <sys/socket.h> 47#include <sys/syslog.h> 48 49#include <sys/module.h> 50#include <sys/bus.h> 51 52#include <machine/bus.h> 53#include <sys/rman.h> 54#include <machine/resource.h> 55 56#include <net/ethernet.h> 57#include <net/if.h> 58#include <net/if_arp.h> 59#include <net/if_dl.h> 60#include <net/if_mib.h> 61 62#include <net/bpf.h> 63#include "opt_bdg.h" 64#ifdef BRIDGE 65#include <net/bridge.h> 66#endif 67 68#include <machine/clock.h> 69#include <machine/md_var.h> 70 71#include <dev/ed/if_edreg.h> 72#include <dev/ed/if_edvar.h> 73 74static void ed_init __P((void *)); 75static int ed_ioctl __P((struct ifnet *, u_long, caddr_t)); 76static void ed_start __P((struct ifnet *)); 77static void ed_reset __P((struct ifnet *)); 78static void ed_watchdog __P((struct ifnet *)); 79static void ed_stop __P((struct ed_softc *)); 80 81static void ds_getmcaf __P((struct ed_softc *, u_long *)); 82 83static void ed_get_packet __P((struct ed_softc *, char *, /* u_short */ int, int)); 84 85static __inline void ed_rint __P((struct ed_softc *)); 86static __inline void ed_xmit __P((struct ed_softc *)); 87static __inline char * ed_ring_copy __P((struct ed_softc *, char *, char *, 88 /* u_short */ int)); 89static void ed_hpp_set_physical_link __P((struct ed_softc *)); 90static void ed_hpp_readmem __P((struct ed_softc *, int, unsigned char *, 91 /* u_short */ int)); 92static u_short ed_hpp_write_mbufs __P((struct ed_softc *, struct mbuf *, 93 int)); 94 95static void ed_pio_readmem __P((struct ed_softc *, int, unsigned char *, 96 /* u_short */ int)); 97static void ed_pio_writemem __P((struct ed_softc *, char *, 98 /* u_short */ int, /* u_short */ int)); 99static u_short ed_pio_write_mbufs __P((struct ed_softc *, struct mbuf *, 100 int)); 101 102static void ed_setrcr __P((struct ed_softc *)); 103 104static u_long ds_crc __P((u_char *ep)); 105 106/* 107 * Interrupt conversion table for WD/SMC ASIC/83C584 108 */ 109static unsigned short ed_intr_val[] = { 110 9, 111 3, 112 5, 113 7, 114 10, 115 11, 116 15, 117 4 118}; 119 120/* 121 * Interrupt conversion table for 83C790 122 */ 123static unsigned short ed_790_intr_val[] = { 124 0, 125 9, 126 3, 127 5, 128 7, 129 10, 130 11, 131 15 132}; 133 134/* 135 * Interrupt conversion table for the HP PC LAN+ 136 */ 137 138static unsigned short ed_hpp_intr_val[] = { 139 0, /* 0 */ 140 0, /* 1 */ 141 0, /* 2 */ 142 3, /* 3 */ 143 4, /* 4 */ 144 5, /* 5 */ 145 6, /* 6 */ 146 7, /* 7 */ 147 0, /* 8 */ 148 9, /* 9 */ 149 10, /* 10 */ 150 11, /* 11 */ 151 12, /* 12 */ 152 0, /* 13 */ 153 0, /* 14 */ 154 15 /* 15 */ 155}; 156 157/* 158 * Generic probe routine for testing for the existance of a DS8390. 159 * Must be called after the NIC has just been reset. This routine 160 * works by looking at certain register values that are guaranteed 161 * to be initialized a certain way after power-up or reset. Seems 162 * not to currently work on the 83C690. 163 * 164 * Specifically: 165 * 166 * Register reset bits set bits 167 * Command Register (CR) TXP, STA RD2, STP 168 * Interrupt Status (ISR) RST 169 * Interrupt Mask (IMR) All bits 170 * Data Control (DCR) LAS 171 * Transmit Config. (TCR) LB1, LB0 172 * 173 * We only look at the CR and ISR registers, however, because looking at 174 * the others would require changing register pages (which would be 175 * intrusive if this isn't an 8390). 176 * 177 * Return 1 if 8390 was found, 0 if not. 178 */ 179 180int 181ed_probe_generic8390(sc) 182 struct ed_softc *sc; 183{ 184 if ((inb(sc->nic_addr + ED_P0_CR) & 185 (ED_CR_RD2 | ED_CR_TXP | ED_CR_STA | ED_CR_STP)) != 186 (ED_CR_RD2 | ED_CR_STP)) 187 return (0); 188 if ((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RST) != ED_ISR_RST) 189 return (0); 190 191 return (1); 192} 193 194/* 195 * Probe and vendor-specific initialization routine for SMC/WD80x3 boards 196 */ 197int 198ed_probe_WD80x3(dev) 199 device_t dev; 200{ 201 struct ed_softc *sc = device_get_softc(dev); 202 int error; 203 int i; 204 int flags = device_get_flags(dev); 205 u_int memsize, maddr; 206 u_char iptr, isa16bit, sum; 207 u_long conf_maddr, conf_msize, irq, junk; 208 209 error = ed_alloc_port(dev, 0, ED_WD_IO_PORTS); 210 if (error) 211 return (error); 212 213 sc->asic_addr = rman_get_start(sc->port_res); 214 sc->nic_addr = sc->asic_addr + ED_WD_NIC_OFFSET; 215 sc->is790 = 0; 216 217#ifdef TOSH_ETHER 218 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_POW); 219 DELAY(10000); 220#endif 221 222 /* 223 * Attempt to do a checksum over the station address PROM. If it 224 * fails, it's probably not a SMC/WD board. There is a problem with 225 * this, though: some clone WD boards don't pass the checksum test. 226 * Danpex boards for one. 227 */ 228 for (sum = 0, i = 0; i < 8; ++i) 229 sum += inb(sc->asic_addr + ED_WD_PROM + i); 230 231 if (sum != ED_WD_ROM_CHECKSUM_TOTAL) { 232 233 /* 234 * Checksum is invalid. This often happens with cheap WD8003E 235 * clones. In this case, the checksum byte (the eighth byte) 236 * seems to always be zero. 237 */ 238 if (inb(sc->asic_addr + ED_WD_CARD_ID) != ED_TYPE_WD8003E || 239 inb(sc->asic_addr + ED_WD_PROM + 7) != 0) 240 return (ENXIO); 241 } 242 /* reset card to force it into a known state. */ 243#ifdef TOSH_ETHER 244 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_RST | ED_WD_MSR_POW); 245#else 246 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_RST); 247#endif 248 DELAY(100); 249 outb(sc->asic_addr + ED_WD_MSR, inb(sc->asic_addr + ED_WD_MSR) & ~ED_WD_MSR_RST); 250 /* wait in the case this card is reading its EEROM */ 251 DELAY(5000); 252 253 sc->vendor = ED_VENDOR_WD_SMC; 254 sc->type = inb(sc->asic_addr + ED_WD_CARD_ID); 255 256 /* 257 * Set initial values for width/size. 258 */ 259 memsize = 8192; 260 isa16bit = 0; 261 switch (sc->type) { 262 case ED_TYPE_WD8003S: 263 sc->type_str = "WD8003S"; 264 break; 265 case ED_TYPE_WD8003E: 266 sc->type_str = "WD8003E"; 267 break; 268 case ED_TYPE_WD8003EB: 269 sc->type_str = "WD8003EB"; 270 break; 271 case ED_TYPE_WD8003W: 272 sc->type_str = "WD8003W"; 273 break; 274 case ED_TYPE_WD8013EBT: 275 sc->type_str = "WD8013EBT"; 276 memsize = 16384; 277 isa16bit = 1; 278 break; 279 case ED_TYPE_WD8013W: 280 sc->type_str = "WD8013W"; 281 memsize = 16384; 282 isa16bit = 1; 283 break; 284 case ED_TYPE_WD8013EP: /* also WD8003EP */ 285 if (inb(sc->asic_addr + ED_WD_ICR) 286 & ED_WD_ICR_16BIT) { 287 isa16bit = 1; 288 memsize = 16384; 289 sc->type_str = "WD8013EP"; 290 } else { 291 sc->type_str = "WD8003EP"; 292 } 293 break; 294 case ED_TYPE_WD8013WC: 295 sc->type_str = "WD8013WC"; 296 memsize = 16384; 297 isa16bit = 1; 298 break; 299 case ED_TYPE_WD8013EBP: 300 sc->type_str = "WD8013EBP"; 301 memsize = 16384; 302 isa16bit = 1; 303 break; 304 case ED_TYPE_WD8013EPC: 305 sc->type_str = "WD8013EPC"; 306 memsize = 16384; 307 isa16bit = 1; 308 break; 309 case ED_TYPE_SMC8216C: /* 8216 has 16K shared mem -- 8416 has 8K */ 310 case ED_TYPE_SMC8216T: 311 if (sc->type == ED_TYPE_SMC8216C) { 312 sc->type_str = "SMC8216/SMC8216C"; 313 } else { 314 sc->type_str = "SMC8216T"; 315 } 316 317 outb(sc->asic_addr + ED_WD790_HWR, 318 inb(sc->asic_addr + ED_WD790_HWR) | ED_WD790_HWR_SWH); 319 switch (inb(sc->asic_addr + ED_WD790_RAR) & ED_WD790_RAR_SZ64) { 320 case ED_WD790_RAR_SZ64: 321 memsize = 65536; 322 break; 323 case ED_WD790_RAR_SZ32: 324 memsize = 32768; 325 break; 326 case ED_WD790_RAR_SZ16: 327 memsize = 16384; 328 break; 329 case ED_WD790_RAR_SZ8: 330 /* 8216 has 16K shared mem -- 8416 has 8K */ 331 if (sc->type == ED_TYPE_SMC8216C) { 332 sc->type_str = "SMC8416C/SMC8416BT"; 333 } else { 334 sc->type_str = "SMC8416T"; 335 } 336 memsize = 8192; 337 break; 338 } 339 outb(sc->asic_addr + ED_WD790_HWR, 340 inb(sc->asic_addr + ED_WD790_HWR) & ~ED_WD790_HWR_SWH); 341 342 isa16bit = 1; 343 sc->is790 = 1; 344 break; 345#ifdef TOSH_ETHER 346 case ED_TYPE_TOSHIBA1: 347 sc->type_str = "Toshiba1"; 348 memsize = 32768; 349 isa16bit = 1; 350 break; 351 case ED_TYPE_TOSHIBA4: 352 sc->type_str = "Toshiba4"; 353 memsize = 32768; 354 isa16bit = 1; 355 break; 356#endif 357 default: 358 sc->type_str = ""; 359 break; 360 } 361 362 /* 363 * Make some adjustments to initial values depending on what is found 364 * in the ICR. 365 */ 366 if (isa16bit && (sc->type != ED_TYPE_WD8013EBT) 367#ifdef TOSH_ETHER 368 && (sc->type != ED_TYPE_TOSHIBA1) && (sc->type != ED_TYPE_TOSHIBA4) 369#endif 370 && ((inb(sc->asic_addr + ED_WD_ICR) & ED_WD_ICR_16BIT) == 0)) { 371 isa16bit = 0; 372 memsize = 8192; 373 } 374 375 error = bus_get_resource(dev, SYS_RES_MEMORY, 0, 376 &conf_maddr, &conf_msize); 377 if (error) 378 return (error); 379 380#if ED_DEBUG 381 printf("type = %x type_str=%s isa16bit=%d memsize=%d id_msize=%d\n", 382 sc->type, sc->type_str, isa16bit, memsize, conf_msize); 383 for (i = 0; i < 8; i++) 384 printf("%x -> %x\n", i, inb(sc->asic_addr + i)); 385#endif 386 387 /* 388 * Allow the user to override the autoconfiguration 389 */ 390 if (conf_msize > 1) 391 memsize = conf_msize; 392 393 maddr = conf_maddr; 394 if (maddr < 0xa0000 || maddr + memsize > 0x1000000) { 395 device_printf(dev, "Invalid ISA memory address range configured: 0x%x - 0x%x\n", 396 maddr, maddr + memsize); 397 return (ENXIO); 398 } 399 400 /* 401 * (note that if the user specifies both of the following flags that 402 * '8bit' mode intentionally has precedence) 403 */ 404 if (flags & ED_FLAGS_FORCE_16BIT_MODE) 405 isa16bit = 1; 406 if (flags & ED_FLAGS_FORCE_8BIT_MODE) 407 isa16bit = 0; 408 409 /* 410 * If possible, get the assigned interrupt number from the card and 411 * use it. 412 */ 413 if ((sc->type & ED_WD_SOFTCONFIG) && (!sc->is790)) { 414 415 /* 416 * Assemble together the encoded interrupt number. 417 */ 418 iptr = (inb(sc->asic_addr + ED_WD_ICR) & ED_WD_ICR_IR2) | 419 ((inb(sc->asic_addr + ED_WD_IRR) & 420 (ED_WD_IRR_IR0 | ED_WD_IRR_IR1)) >> 5); 421 422 /* 423 * If no interrupt specified (or "?"), use what the board tells us. 424 */ 425 error = bus_get_resource(dev, SYS_RES_IRQ, 0, 426 &irq, &junk); 427 if (error) { 428 bus_set_resource(dev, SYS_RES_IRQ, 0, 429 ed_intr_val[iptr], 1); 430 } 431 432 /* 433 * Enable the interrupt. 434 */ 435 outb(sc->asic_addr + ED_WD_IRR, 436 inb(sc->asic_addr + ED_WD_IRR) | ED_WD_IRR_IEN); 437 } 438 if (sc->is790) { 439 outb(sc->asic_addr + ED_WD790_HWR, 440 inb(sc->asic_addr + ED_WD790_HWR) | ED_WD790_HWR_SWH); 441 iptr = (((inb(sc->asic_addr + ED_WD790_GCR) & ED_WD790_GCR_IR2) >> 4) | 442 (inb(sc->asic_addr + ED_WD790_GCR) & 443 (ED_WD790_GCR_IR1 | ED_WD790_GCR_IR0)) >> 2); 444 outb(sc->asic_addr + ED_WD790_HWR, 445 inb(sc->asic_addr + ED_WD790_HWR) & ~ED_WD790_HWR_SWH); 446 447 /* 448 * If no interrupt specified (or "?"), use what the board tells us. 449 */ 450 error = bus_get_resource(dev, SYS_RES_IRQ, 0, 451 &irq, &junk); 452 if (error) { 453 bus_set_resource(dev, SYS_RES_IRQ, 0, 454 ed_790_intr_val[iptr], 1); 455 } 456 457 /* 458 * Enable interrupts. 459 */ 460 outb(sc->asic_addr + ED_WD790_ICR, 461 inb(sc->asic_addr + ED_WD790_ICR) | ED_WD790_ICR_EIL); 462 } 463 error = bus_get_resource(dev, SYS_RES_IRQ, 0, 464 &irq, &junk); 465 if (error) { 466 device_printf(dev, "%s cards don't support auto-detected/assigned interrupts.\n", 467 sc->type_str); 468 return (ENXIO); 469 } 470 sc->isa16bit = isa16bit; 471 sc->mem_shared = 1; 472 473 error = ed_alloc_memory(dev, 0, memsize); 474 if (error) { 475 printf("*** ed_alloc_memory() failed! (%d)\n", error); 476 return (error); 477 } 478 sc->mem_start = (caddr_t) rman_get_virtual(sc->mem_res); 479 480 /* 481 * allocate one xmit buffer if < 16k, two buffers otherwise 482 */ 483 if ((memsize < 16384) || 484 (flags & ED_FLAGS_NO_MULTI_BUFFERING)) { 485 sc->txb_cnt = 1; 486 } else { 487 sc->txb_cnt = 2; 488 } 489 sc->tx_page_start = ED_WD_PAGE_OFFSET; 490 sc->rec_page_start = ED_WD_PAGE_OFFSET + ED_TXBUF_SIZE * sc->txb_cnt; 491 sc->rec_page_stop = ED_WD_PAGE_OFFSET + memsize / ED_PAGE_SIZE; 492 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * sc->rec_page_start); 493 sc->mem_size = memsize; 494 sc->mem_end = sc->mem_start + memsize; 495 496 /* 497 * Get station address from on-board ROM 498 */ 499 for (i = 0; i < ETHER_ADDR_LEN; ++i) 500 sc->arpcom.ac_enaddr[i] = inb(sc->asic_addr + ED_WD_PROM + i); 501 502 /* 503 * Set upper address bits and 8/16 bit access to shared memory. 504 */ 505 if (isa16bit) { 506 if (sc->is790) { 507 sc->wd_laar_proto = inb(sc->asic_addr + ED_WD_LAAR); 508 } else { 509 sc->wd_laar_proto = ED_WD_LAAR_L16EN | 510 ((kvtop(sc->mem_start) >> 19) & ED_WD_LAAR_ADDRHI); 511 } 512 /* 513 * Enable 16bit access 514 */ 515 outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto | 516 ED_WD_LAAR_M16EN); 517 } else { 518 if (((sc->type & ED_WD_SOFTCONFIG) || 519#ifdef TOSH_ETHER 520 (sc->type == ED_TYPE_TOSHIBA1) || (sc->type == ED_TYPE_TOSHIBA4) || 521#endif 522 (sc->type == ED_TYPE_WD8013EBT)) && (!sc->is790)) { 523 sc->wd_laar_proto = (kvtop(sc->mem_start) >> 19) & 524 ED_WD_LAAR_ADDRHI; 525 outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto); 526 } 527 } 528 529 /* 530 * Set address and enable interface shared memory. 531 */ 532 if (!sc->is790) { 533#ifdef TOSH_ETHER 534 outb(sc->asic_addr + ED_WD_MSR + 1, ((kvtop(sc->mem_start) >> 8) & 0xe0) | 4); 535 outb(sc->asic_addr + ED_WD_MSR + 2, ((kvtop(sc->mem_start) >> 16) & 0x0f)); 536 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_MENB | ED_WD_MSR_POW); 537 538#else 539 outb(sc->asic_addr + ED_WD_MSR, ((kvtop(sc->mem_start) >> 13) & 540 ED_WD_MSR_ADDR) | ED_WD_MSR_MENB); 541#endif 542 sc->cr_proto = ED_CR_RD2; 543 } else { 544 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_MENB); 545 outb(sc->asic_addr + ED_WD790_HWR, (inb(sc->asic_addr + ED_WD790_HWR) | ED_WD790_HWR_SWH)); 546 outb(sc->asic_addr + ED_WD790_RAR, ((kvtop(sc->mem_start) >> 13) & 0x0f) | 547 ((kvtop(sc->mem_start) >> 11) & 0x40) | 548 (inb(sc->asic_addr + ED_WD790_RAR) & 0xb0)); 549 outb(sc->asic_addr + ED_WD790_HWR, (inb(sc->asic_addr + ED_WD790_HWR) & ~ED_WD790_HWR_SWH)); 550 sc->cr_proto = 0; 551 } 552 553#if 0 554 printf("starting memory performance test at 0x%x, size %d...\n", 555 sc->mem_start, memsize*16384); 556 for (i = 0; i < 16384; i++) 557 bzero(sc->mem_start, memsize); 558 printf("***DONE***\n"); 559#endif 560 561 /* 562 * Now zero memory and verify that it is clear 563 */ 564 bzero(sc->mem_start, memsize); 565 566 for (i = 0; i < memsize; ++i) { 567 if (sc->mem_start[i]) { 568 device_printf(dev, "failed to clear shared memory at %lx - check configuration\n", 569 kvtop(sc->mem_start + i)); 570 571 /* 572 * Disable 16 bit access to shared memory 573 */ 574 if (isa16bit) { 575 if (sc->is790) { 576 outb(sc->asic_addr + ED_WD_MSR, 0x00); 577 } 578 outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto & 579 ~ED_WD_LAAR_M16EN); 580 } 581 return (ENXIO); 582 } 583 } 584 585 /* 586 * Disable 16bit access to shared memory - we leave it 587 * disabled so that 1) machines reboot properly when the board 588 * is set 16 bit mode and there are conflicting 8bit 589 * devices/ROMS in the same 128k address space as this boards 590 * shared memory. and 2) so that other 8 bit devices with 591 * shared memory can be used in this 128k region, too. 592 */ 593 if (isa16bit) { 594 if (sc->is790) { 595 outb(sc->asic_addr + ED_WD_MSR, 0x00); 596 } 597 outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto & 598 ~ED_WD_LAAR_M16EN); 599 } 600 return (0); 601} 602 603/* 604 * Probe and vendor-specific initialization routine for 3Com 3c503 boards 605 */ 606int 607ed_probe_3Com(dev) 608 device_t dev; 609{ 610 struct ed_softc *sc = device_get_softc(dev); 611 int error; 612 int i; 613 int flags = device_get_flags(dev); 614 u_int memsize; 615 u_char isa16bit; 616 u_long conf_maddr, conf_msize, irq, junk; 617 618 error = ed_alloc_port(dev, 0, ED_3COM_IO_PORTS); 619 if (error) 620 return (error); 621 622 sc->asic_addr = rman_get_start(sc->port_res) + ED_3COM_ASIC_OFFSET; 623 sc->nic_addr = rman_get_start(sc->port_res) + ED_3COM_NIC_OFFSET; 624 625 /* 626 * Verify that the kernel configured I/O address matches the board 627 * configured address 628 */ 629 switch (inb(sc->asic_addr + ED_3COM_BCFR)) { 630 case ED_3COM_BCFR_300: 631 if (rman_get_start(sc->port_res) != 0x300) 632 return (ENXIO); 633 break; 634 case ED_3COM_BCFR_310: 635 if (rman_get_start(sc->port_res) != 0x310) 636 return (ENXIO); 637 break; 638 case ED_3COM_BCFR_330: 639 if (rman_get_start(sc->port_res) != 0x330) 640 return (ENXIO); 641 break; 642 case ED_3COM_BCFR_350: 643 if (rman_get_start(sc->port_res) != 0x350) 644 return (ENXIO); 645 break; 646 case ED_3COM_BCFR_250: 647 if (rman_get_start(sc->port_res) != 0x250) 648 return (ENXIO); 649 break; 650 case ED_3COM_BCFR_280: 651 if (rman_get_start(sc->port_res) != 0x280) 652 return (ENXIO); 653 break; 654 case ED_3COM_BCFR_2A0: 655 if (rman_get_start(sc->port_res) != 0x2a0) 656 return (ENXIO); 657 break; 658 case ED_3COM_BCFR_2E0: 659 if (rman_get_start(sc->port_res) != 0x2e0) 660 return (ENXIO); 661 break; 662 default: 663 return (ENXIO); 664 } 665 666 error = bus_get_resource(dev, SYS_RES_MEMORY, 0, 667 &conf_maddr, &conf_msize); 668 if (error) 669 return (error); 670 671 /* 672 * Verify that the kernel shared memory address matches the board 673 * configured address. 674 */ 675 switch (inb(sc->asic_addr + ED_3COM_PCFR)) { 676 case ED_3COM_PCFR_DC000: 677 if (conf_maddr != 0xdc000) 678 return (ENXIO); 679 break; 680 case ED_3COM_PCFR_D8000: 681 if (conf_maddr != 0xd8000) 682 return (ENXIO); 683 break; 684 case ED_3COM_PCFR_CC000: 685 if (conf_maddr != 0xcc000) 686 return (ENXIO); 687 break; 688 case ED_3COM_PCFR_C8000: 689 if (conf_maddr != 0xc8000) 690 return (ENXIO); 691 break; 692 default: 693 return (ENXIO); 694 } 695 696 697 /* 698 * Reset NIC and ASIC. Enable on-board transceiver throughout reset 699 * sequence because it'll lock up if the cable isn't connected if we 700 * don't. 701 */ 702 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_RST | ED_3COM_CR_XSEL); 703 704 /* 705 * Wait for a while, then un-reset it 706 */ 707 DELAY(50); 708 709 /* 710 * The 3Com ASIC defaults to rather strange settings for the CR after 711 * a reset - it's important to set it again after the following outb 712 * (this is done when we map the PROM below). 713 */ 714 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL); 715 716 /* 717 * Wait a bit for the NIC to recover from the reset 718 */ 719 DELAY(5000); 720 721 sc->vendor = ED_VENDOR_3COM; 722 sc->type_str = "3c503"; 723 sc->mem_shared = 1; 724 sc->cr_proto = ED_CR_RD2; 725 726 /* 727 * Hmmm...a 16bit 3Com board has 16k of memory, but only an 8k window 728 * to it. 729 */ 730 memsize = 8192; 731 732 /* 733 * Get station address from on-board ROM 734 */ 735 736 /* 737 * First, map ethernet address PROM over the top of where the NIC 738 * registers normally appear. 739 */ 740 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_EALO | ED_3COM_CR_XSEL); 741 742 for (i = 0; i < ETHER_ADDR_LEN; ++i) 743 sc->arpcom.ac_enaddr[i] = inb(sc->nic_addr + i); 744 745 /* 746 * Unmap PROM - select NIC registers. The proper setting of the 747 * tranceiver is set in ed_init so that the attach code is given a 748 * chance to set the default based on a compile-time config option 749 */ 750 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL); 751 752 /* 753 * Determine if this is an 8bit or 16bit board 754 */ 755 756 /* 757 * select page 0 registers 758 */ 759 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STP); 760 761 /* 762 * Attempt to clear WTS bit. If it doesn't clear, then this is a 16bit 763 * board. 764 */ 765 outb(sc->nic_addr + ED_P0_DCR, 0); 766 767 /* 768 * select page 2 registers 769 */ 770 outb(sc->nic_addr + ED_P0_CR, ED_CR_PAGE_2 | ED_CR_RD2 | ED_CR_STP); 771 772 /* 773 * The 3c503 forces the WTS bit to a one if this is a 16bit board 774 */ 775 if (inb(sc->nic_addr + ED_P2_DCR) & ED_DCR_WTS) 776 isa16bit = 1; 777 else 778 isa16bit = 0; 779 780 /* 781 * select page 0 registers 782 */ 783 outb(sc->nic_addr + ED_P2_CR, ED_CR_RD2 | ED_CR_STP); 784 785 error = ed_alloc_memory(dev, 0, memsize); 786 if (error) 787 return (error); 788 789 sc->mem_start = (caddr_t) rman_get_virtual(sc->mem_res); 790 sc->mem_size = memsize; 791 sc->mem_end = sc->mem_start + memsize; 792 793 /* 794 * We have an entire 8k window to put the transmit buffers on the 795 * 16bit boards. But since the 16bit 3c503's shared memory is only 796 * fast enough to overlap the loading of one full-size packet, trying 797 * to load more than 2 buffers can actually leave the transmitter idle 798 * during the load. So 2 seems the best value. (Although a mix of 799 * variable-sized packets might change this assumption. Nonetheless, 800 * we optimize for linear transfers of same-size packets.) 801 */ 802 if (isa16bit) { 803 if (flags & ED_FLAGS_NO_MULTI_BUFFERING) 804 sc->txb_cnt = 1; 805 else 806 sc->txb_cnt = 2; 807 808 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_16BIT; 809 sc->rec_page_start = ED_3COM_RX_PAGE_OFFSET_16BIT; 810 sc->rec_page_stop = memsize / ED_PAGE_SIZE + 811 ED_3COM_RX_PAGE_OFFSET_16BIT; 812 sc->mem_ring = sc->mem_start; 813 } else { 814 sc->txb_cnt = 1; 815 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_8BIT; 816 sc->rec_page_start = ED_TXBUF_SIZE + ED_3COM_TX_PAGE_OFFSET_8BIT; 817 sc->rec_page_stop = memsize / ED_PAGE_SIZE + 818 ED_3COM_TX_PAGE_OFFSET_8BIT; 819 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * ED_TXBUF_SIZE); 820 } 821 822 sc->isa16bit = isa16bit; 823 824 /* 825 * Initialize GA page start/stop registers. Probably only needed if 826 * doing DMA, but what the hell. 827 */ 828 outb(sc->asic_addr + ED_3COM_PSTR, sc->rec_page_start); 829 outb(sc->asic_addr + ED_3COM_PSPR, sc->rec_page_stop); 830 831 /* 832 * Set IRQ. 3c503 only allows a choice of irq 2-5. 833 */ 834 error = bus_get_resource(dev, SYS_RES_IRQ, 0, 835 &irq, &junk); 836 if (error) 837 return (error); 838 839 switch (irq) { 840 case 2: 841 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ2); 842 break; 843 case 3: 844 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ3); 845 break; 846 case 4: 847 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ4); 848 break; 849 case 5: 850 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ5); 851 break; 852 default: 853 device_printf(dev, "Invalid irq configuration (%ld) must be 3-5,9 for 3c503\n", 854 irq); 855 return (ENXIO); 856 } 857 858 /* 859 * Initialize GA configuration register. Set bank and enable shared 860 * mem. 861 */ 862 outb(sc->asic_addr + ED_3COM_GACFR, ED_3COM_GACFR_RSEL | 863 ED_3COM_GACFR_MBS0); 864 865 /* 866 * Initialize "Vector Pointer" registers. These gawd-awful things are 867 * compared to 20 bits of the address on ISA, and if they match, the 868 * shared memory is disabled. We set them to 0xffff0...allegedly the 869 * reset vector. 870 */ 871 outb(sc->asic_addr + ED_3COM_VPTR2, 0xff); 872 outb(sc->asic_addr + ED_3COM_VPTR1, 0xff); 873 outb(sc->asic_addr + ED_3COM_VPTR0, 0x00); 874 875 /* 876 * Zero memory and verify that it is clear 877 */ 878 bzero(sc->mem_start, memsize); 879 880 for (i = 0; i < memsize; ++i) 881 if (sc->mem_start[i]) { 882 device_printf(dev, "failed to clear shared memory at %lx - check configuration\n", 883 kvtop(sc->mem_start + i)); 884 return (ENXIO); 885 } 886 return (0); 887} 888 889/* 890 * Probe and vendor-specific initialization routine for NE1000/2000 boards 891 */ 892int 893ed_probe_Novell_generic(dev, port_rid, flags) 894 device_t dev; 895 int port_rid; 896 int flags; 897{ 898 struct ed_softc *sc = device_get_softc(dev); 899 u_int memsize, n; 900 u_char romdata[16], tmp; 901 static char test_pattern[32] = "THIS is A memory TEST pattern"; 902 char test_buffer[32]; 903 int error; 904 905 error = ed_alloc_port(dev, port_rid, ED_NOVELL_IO_PORTS); 906 if (error) 907 return (error); 908 909 sc->asic_addr = rman_get_start(sc->port_res) + ED_NOVELL_ASIC_OFFSET; 910 sc->nic_addr = rman_get_start(sc->port_res) + ED_NOVELL_NIC_OFFSET; 911 912 /* XXX - do Novell-specific probe here */ 913 914 /* Reset the board */ 915#ifdef GWETHER 916 outb(sc->asic_addr + ED_NOVELL_RESET, 0); 917 DELAY(200); 918#endif /* GWETHER */ 919 tmp = inb(sc->asic_addr + ED_NOVELL_RESET); 920 921 /* 922 * I don't know if this is necessary; probably cruft leftover from 923 * Clarkson packet driver code. Doesn't do a thing on the boards I've 924 * tested. -DG [note that a outb(0x84, 0) seems to work here, and is 925 * non-invasive...but some boards don't seem to reset and I don't have 926 * complete documentation on what the 'right' thing to do is...so we 927 * do the invasive thing for now. Yuck.] 928 */ 929 outb(sc->asic_addr + ED_NOVELL_RESET, tmp); 930 DELAY(5000); 931 932 /* 933 * This is needed because some NE clones apparently don't reset the 934 * NIC properly (or the NIC chip doesn't reset fully on power-up) XXX 935 * - this makes the probe invasive! ...Done against my better 936 * judgement. -DLG 937 */ 938 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STP); 939 940 DELAY(5000); 941 942 /* Make sure that we really have an 8390 based board */ 943 if (!ed_probe_generic8390(sc)) 944 return (ENXIO); 945 946 sc->vendor = ED_VENDOR_NOVELL; 947 sc->mem_shared = 0; 948 sc->cr_proto = ED_CR_RD2; 949 950 /* 951 * Test the ability to read and write to the NIC memory. This has the 952 * side affect of determining if this is an NE1000 or an NE2000. 953 */ 954 955 /* 956 * This prevents packets from being stored in the NIC memory when the 957 * readmem routine turns on the start bit in the CR. 958 */ 959 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_MON); 960 961 /* Temporarily initialize DCR for byte operations */ 962 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS); 963 964 outb(sc->nic_addr + ED_P0_PSTART, 8192 / ED_PAGE_SIZE); 965 outb(sc->nic_addr + ED_P0_PSTOP, 16384 / ED_PAGE_SIZE); 966 967 sc->isa16bit = 0; 968 969 /* 970 * Write a test pattern in byte mode. If this fails, then there 971 * probably isn't any memory at 8k - which likely means that the board 972 * is an NE2000. 973 */ 974 ed_pio_writemem(sc, test_pattern, 8192, sizeof(test_pattern)); 975 ed_pio_readmem(sc, 8192, test_buffer, sizeof(test_pattern)); 976 977 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern))) { 978 /* not an NE1000 - try NE2000 */ 979 980 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_WTS | ED_DCR_FT1 | ED_DCR_LS); 981 outb(sc->nic_addr + ED_P0_PSTART, 16384 / ED_PAGE_SIZE); 982 outb(sc->nic_addr + ED_P0_PSTOP, 32768 / ED_PAGE_SIZE); 983 984 sc->isa16bit = 1; 985 986 /* 987 * Write a test pattern in word mode. If this also fails, then 988 * we don't know what this board is. 989 */ 990 ed_pio_writemem(sc, test_pattern, 16384, sizeof(test_pattern)); 991 ed_pio_readmem(sc, 16384, test_buffer, sizeof(test_pattern)); 992 993 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern))) 994 return (ENXIO); /* not an NE2000 either */ 995 996 sc->type = ED_TYPE_NE2000; 997 sc->type_str = "NE2000"; 998 } else { 999 sc->type = ED_TYPE_NE1000; 1000 sc->type_str = "NE1000"; 1001 } 1002 1003 /* 8k of memory plus an additional 8k if 16bit */ 1004 memsize = 8192 + sc->isa16bit * 8192; 1005 1006#if 0 /* probably not useful - NE boards only come two ways */ 1007 /* allow kernel config file overrides */ 1008 if (isa_dev->id_msize) 1009 memsize = isa_dev->id_msize; 1010#endif 1011 1012 sc->mem_size = memsize; 1013 1014 /* NIC memory doesn't start at zero on an NE board */ 1015 /* The start address is tied to the bus width */ 1016 sc->mem_start = (char *) 8192 + sc->isa16bit * 8192; 1017 sc->mem_end = sc->mem_start + memsize; 1018 sc->tx_page_start = memsize / ED_PAGE_SIZE; 1019 1020#ifdef GWETHER 1021 { 1022 int x, i, mstart = 0, msize = 0; 1023 char pbuf0[ED_PAGE_SIZE], pbuf[ED_PAGE_SIZE], tbuf[ED_PAGE_SIZE]; 1024 1025 for (i = 0; i < ED_PAGE_SIZE; i++) 1026 pbuf0[i] = 0; 1027 1028 /* Clear all the memory. */ 1029 for (x = 1; x < 256; x++) 1030 ed_pio_writemem(sc, pbuf0, x * 256, ED_PAGE_SIZE); 1031 1032 /* Search for the start of RAM. */ 1033 for (x = 1; x < 256; x++) { 1034 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE); 1035 if (bcmp(pbuf0, tbuf, ED_PAGE_SIZE) == 0) { 1036 for (i = 0; i < ED_PAGE_SIZE; i++) 1037 pbuf[i] = 255 - x; 1038 ed_pio_writemem(sc, pbuf, x * 256, ED_PAGE_SIZE); 1039 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE); 1040 if (bcmp(pbuf, tbuf, ED_PAGE_SIZE) == 0) { 1041 mstart = x * ED_PAGE_SIZE; 1042 msize = ED_PAGE_SIZE; 1043 break; 1044 } 1045 } 1046 } 1047 1048 if (mstart == 0) { 1049 device_printf(dev, "Cannot find start of RAM.\n"); 1050 return (ENXIO); 1051 } 1052 /* Search for the start of RAM. */ 1053 for (x = (mstart / ED_PAGE_SIZE) + 1; x < 256; x++) { 1054 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE); 1055 if (bcmp(pbuf0, tbuf, ED_PAGE_SIZE) == 0) { 1056 for (i = 0; i < ED_PAGE_SIZE; i++) 1057 pbuf[i] = 255 - x; 1058 ed_pio_writemem(sc, pbuf, x * 256, ED_PAGE_SIZE); 1059 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE); 1060 if (bcmp(pbuf, tbuf, ED_PAGE_SIZE) == 0) 1061 msize += ED_PAGE_SIZE; 1062 else { 1063 break; 1064 } 1065 } else { 1066 break; 1067 } 1068 } 1069 1070 if (msize == 0) { 1071 device_printf(dev, "Cannot find any RAM, start : %d, x = %d.\n", mstart, x); 1072 return (ENXIO); 1073 } 1074 device_printf(dev, "RAM start at %d, size : %d.\n", mstart, msize); 1075 1076 sc->mem_size = msize; 1077 sc->mem_start = (char *) mstart; 1078 sc->mem_end = (char *) (msize + mstart); 1079 sc->tx_page_start = mstart / ED_PAGE_SIZE; 1080 } 1081#endif /* GWETHER */ 1082 1083 /* 1084 * Use one xmit buffer if < 16k, two buffers otherwise (if not told 1085 * otherwise). 1086 */ 1087 if ((memsize < 16384) || (flags & ED_FLAGS_NO_MULTI_BUFFERING)) 1088 sc->txb_cnt = 1; 1089 else 1090 sc->txb_cnt = 2; 1091 1092 sc->rec_page_start = sc->tx_page_start + sc->txb_cnt * ED_TXBUF_SIZE; 1093 sc->rec_page_stop = sc->tx_page_start + memsize / ED_PAGE_SIZE; 1094 1095 sc->mem_ring = sc->mem_start + sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE; 1096 1097 ed_pio_readmem(sc, 0, romdata, 16); 1098 for (n = 0; n < ETHER_ADDR_LEN; n++) 1099 sc->arpcom.ac_enaddr[n] = romdata[n * (sc->isa16bit + 1)]; 1100 1101#ifdef GWETHER 1102 if (sc->arpcom.ac_enaddr[2] == 0x86) { 1103 sc->type_str = "Gateway AT"; 1104 } 1105#endif /* GWETHER */ 1106 1107 /* clear any pending interrupts that might have occurred above */ 1108 outb(sc->nic_addr + ED_P0_ISR, 0xff); 1109 1110 return (0); 1111} 1112 1113int 1114ed_probe_Novell(dev) 1115 device_t dev; 1116{ 1117 return ed_probe_Novell_generic(dev, 0, device_get_flags(dev)); 1118} 1119 1120#define ED_HPP_TEST_SIZE 16 1121 1122/* 1123 * Probe and vendor specific initialization for the HP PC Lan+ Cards. 1124 * (HP Part nos: 27247B and 27252A). 1125 * 1126 * The card has an asic wrapper around a DS8390 core. The asic handles 1127 * host accesses and offers both standard register IO and memory mapped 1128 * IO. Memory mapped I/O allows better performance at the expense of greater 1129 * chance of an incompatibility with existing ISA cards. 1130 * 1131 * The card has a few caveats: it isn't tolerant of byte wide accesses, only 1132 * short (16 bit) or word (32 bit) accesses are allowed. Some card revisions 1133 * don't allow 32 bit accesses; these are indicated by a bit in the software 1134 * ID register (see if_edreg.h). 1135 * 1136 * Other caveats are: we should read the MAC address only when the card 1137 * is inactive. 1138 * 1139 * For more information; please consult the CRYNWR packet driver. 1140 * 1141 * The AUI port is turned on using the "link2" option on the ifconfig 1142 * command line. 1143 */ 1144int 1145ed_probe_HP_pclanp(dev) 1146 device_t dev; 1147{ 1148 struct ed_softc *sc = device_get_softc(dev); 1149 int error; 1150 int n; /* temp var */ 1151 int memsize; /* mem on board */ 1152 u_char checksum; /* checksum of board address */ 1153 u_char irq; /* board configured IRQ */ 1154 char test_pattern[ED_HPP_TEST_SIZE]; /* read/write areas for */ 1155 char test_buffer[ED_HPP_TEST_SIZE]; /* probing card */ 1156 u_long conf_maddr, conf_msize, conf_irq, junk; 1157 1158 error = ed_alloc_port(dev, 0, ED_HPP_IO_PORTS); 1159 if (error) 1160 return (error); 1161 1162 /* Fill in basic information */ 1163 sc->asic_addr = rman_get_start(sc->port_res) + ED_HPP_ASIC_OFFSET; 1164 sc->nic_addr = rman_get_start(sc->port_res) + ED_HPP_NIC_OFFSET; 1165 sc->is790 = 0; 1166 sc->isa16bit = 0; /* the 8390 core needs to be in byte mode */ 1167 1168 /* 1169 * Look for the HP PCLAN+ signature: "0x50,0x48,0x00,0x53" 1170 */ 1171 1172 if ((inb(sc->asic_addr + ED_HPP_ID) != 0x50) || 1173 (inb(sc->asic_addr + ED_HPP_ID + 1) != 0x48) || 1174 ((inb(sc->asic_addr + ED_HPP_ID + 2) & 0xF0) != 0) || 1175 (inb(sc->asic_addr + ED_HPP_ID + 3) != 0x53)) 1176 return ENXIO; 1177 1178 /* 1179 * Read the MAC address and verify checksum on the address. 1180 */ 1181 1182 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_MAC); 1183 for (n = 0, checksum = 0; n < ETHER_ADDR_LEN; n++) 1184 checksum += (sc->arpcom.ac_enaddr[n] = 1185 inb(sc->asic_addr + ED_HPP_MAC_ADDR + n)); 1186 1187 checksum += inb(sc->asic_addr + ED_HPP_MAC_ADDR + ETHER_ADDR_LEN); 1188 1189 if (checksum != 0xFF) 1190 return ENXIO; 1191 1192 /* 1193 * Verify that the software model number is 0. 1194 */ 1195 1196 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_ID); 1197 if (((sc->hpp_id = inw(sc->asic_addr + ED_HPP_PAGE_4)) & 1198 ED_HPP_ID_SOFT_MODEL_MASK) != 0x0000) 1199 return ENXIO; 1200 1201 /* 1202 * Read in and save the current options configured on card. 1203 */ 1204 1205 sc->hpp_options = inw(sc->asic_addr + ED_HPP_OPTION); 1206 1207 sc->hpp_options |= (ED_HPP_OPTION_NIC_RESET | 1208 ED_HPP_OPTION_CHIP_RESET | 1209 ED_HPP_OPTION_ENABLE_IRQ); 1210 1211 /* 1212 * Reset the chip. This requires writing to the option register 1213 * so take care to preserve the other bits. 1214 */ 1215 1216 outw(sc->asic_addr + ED_HPP_OPTION, 1217 (sc->hpp_options & ~(ED_HPP_OPTION_NIC_RESET | 1218 ED_HPP_OPTION_CHIP_RESET))); 1219 1220 DELAY(5000); /* wait for chip reset to complete */ 1221 1222 outw(sc->asic_addr + ED_HPP_OPTION, 1223 (sc->hpp_options | (ED_HPP_OPTION_NIC_RESET | 1224 ED_HPP_OPTION_CHIP_RESET | 1225 ED_HPP_OPTION_ENABLE_IRQ))); 1226 1227 DELAY(5000); 1228 1229 if (!(inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RST)) 1230 return ENXIO; /* reset did not complete */ 1231 1232 /* 1233 * Read out configuration information. 1234 */ 1235 1236 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_HW); 1237 1238 irq = inb(sc->asic_addr + ED_HPP_HW_IRQ); 1239 1240 /* 1241 * Check for impossible IRQ. 1242 */ 1243 1244 if (irq >= (sizeof(ed_hpp_intr_val) / sizeof(ed_hpp_intr_val[0]))) 1245 return ENXIO; 1246 1247 /* 1248 * If the kernel IRQ was specified with a '?' use the cards idea 1249 * of the IRQ. If the kernel IRQ was explicitly specified, it 1250 * should match that of the hardware. 1251 */ 1252 error = bus_get_resource(dev, SYS_RES_IRQ, 0, 1253 &conf_irq, &junk); 1254 if (error) { 1255 bus_set_resource(dev, SYS_RES_IRQ, 0, 1256 ed_hpp_intr_val[irq], 1); 1257 } else { 1258 if (conf_irq != ed_hpp_intr_val[irq]) 1259 return (ENXIO); 1260 } 1261 1262 /* 1263 * Fill in softconfig info. 1264 */ 1265 1266 sc->vendor = ED_VENDOR_HP; 1267 sc->type = ED_TYPE_HP_PCLANPLUS; 1268 sc->type_str = "HP-PCLAN+"; 1269 1270 sc->mem_shared = 0; /* we DON'T have dual ported RAM */ 1271 sc->mem_start = 0; /* we use offsets inside the card RAM */ 1272 1273 sc->hpp_mem_start = NULL;/* no memory mapped I/O by default */ 1274 1275 /* 1276 * The board has 32KB of memory. Is there a way to determine 1277 * this programmatically? 1278 */ 1279 1280 memsize = 32768; 1281 1282 /* 1283 * Check if memory mapping of the I/O registers possible. 1284 */ 1285 1286 if (sc->hpp_options & ED_HPP_OPTION_MEM_ENABLE) 1287 { 1288 u_long mem_addr; 1289 1290 /* 1291 * determine the memory address from the board. 1292 */ 1293 1294 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_HW); 1295 mem_addr = (inw(sc->asic_addr + ED_HPP_HW_MEM_MAP) << 8); 1296 1297 /* 1298 * Check that the kernel specified start of memory and 1299 * hardware's idea of it match. 1300 */ 1301 error = bus_get_resource(dev, SYS_RES_MEMORY, 0, 1302 &conf_maddr, &conf_msize); 1303 if (error) 1304 return (error); 1305 1306 if (mem_addr != conf_maddr) 1307 return ENXIO; 1308 1309 error = ed_alloc_memory(dev, 0, memsize); 1310 if (error) 1311 return (error); 1312 1313 sc->hpp_mem_start = rman_get_virtual(sc->mem_res); 1314 } 1315 1316 /* 1317 * Fill in the rest of the soft config structure. 1318 */ 1319 1320 /* 1321 * The transmit page index. 1322 */ 1323 1324 sc->tx_page_start = ED_HPP_TX_PAGE_OFFSET; 1325 1326 if (device_get_flags(dev) & ED_FLAGS_NO_MULTI_BUFFERING) 1327 sc->txb_cnt = 1; 1328 else 1329 sc->txb_cnt = 2; 1330 1331 /* 1332 * Memory description 1333 */ 1334 1335 sc->mem_size = memsize; 1336 sc->mem_ring = sc->mem_start + 1337 (sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE); 1338 sc->mem_end = sc->mem_start + sc->mem_size; 1339 1340 /* 1341 * Receive area starts after the transmit area and 1342 * continues till the end of memory. 1343 */ 1344 1345 sc->rec_page_start = sc->tx_page_start + 1346 (sc->txb_cnt * ED_TXBUF_SIZE); 1347 sc->rec_page_stop = (sc->mem_size / ED_PAGE_SIZE); 1348 1349 1350 sc->cr_proto = 0; /* value works */ 1351 1352 /* 1353 * Set the wrap registers for string I/O reads. 1354 */ 1355 1356 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_HW); 1357 outw(sc->asic_addr + ED_HPP_HW_WRAP, 1358 ((sc->rec_page_start / ED_PAGE_SIZE) | 1359 (((sc->rec_page_stop / ED_PAGE_SIZE) - 1) << 8))); 1360 1361 /* 1362 * Reset the register page to normal operation. 1363 */ 1364 1365 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_PERF); 1366 1367 /* 1368 * Verify that we can read/write from adapter memory. 1369 * Create test pattern. 1370 */ 1371 1372 for (n = 0; n < ED_HPP_TEST_SIZE; n++) 1373 { 1374 test_pattern[n] = (n*n) ^ ~n; 1375 } 1376 1377#undef ED_HPP_TEST_SIZE 1378 1379 /* 1380 * Check that the memory is accessible thru the I/O ports. 1381 * Write out the contents of "test_pattern", read back 1382 * into "test_buffer" and compare the two for any 1383 * mismatch. 1384 */ 1385 1386 for (n = 0; n < (32768 / ED_PAGE_SIZE); n ++) { 1387 1388 ed_pio_writemem(sc, test_pattern, (n * ED_PAGE_SIZE), 1389 sizeof(test_pattern)); 1390 ed_pio_readmem(sc, (n * ED_PAGE_SIZE), 1391 test_buffer, sizeof(test_pattern)); 1392 1393 if (bcmp(test_pattern, test_buffer, 1394 sizeof(test_pattern))) 1395 return ENXIO; 1396 } 1397 1398 return (ED_HPP_IO_PORTS); 1399 1400} 1401 1402/* 1403 * HP PC Lan+ : Set the physical link to use AUI or TP/TL. 1404 */ 1405 1406void 1407ed_hpp_set_physical_link(struct ed_softc *sc) 1408{ 1409 struct ifnet *ifp = &sc->arpcom.ac_if; 1410 int lan_page; 1411 1412 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_LAN); 1413 lan_page = inw(sc->asic_addr + ED_HPP_PAGE_0); 1414 1415 if (ifp->if_flags & IFF_ALTPHYS) { 1416 1417 /* 1418 * Use the AUI port. 1419 */ 1420 1421 lan_page |= ED_HPP_LAN_AUI; 1422 1423 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_LAN); 1424 outw(sc->asic_addr + ED_HPP_PAGE_0, lan_page); 1425 1426 1427 } else { 1428 1429 /* 1430 * Use the ThinLan interface 1431 */ 1432 1433 lan_page &= ~ED_HPP_LAN_AUI; 1434 1435 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_LAN); 1436 outw(sc->asic_addr + ED_HPP_PAGE_0, lan_page); 1437 1438 } 1439 1440 /* 1441 * Wait for the lan card to re-initialize itself 1442 */ 1443 1444 DELAY(150000); /* wait 150 ms */ 1445 1446 /* 1447 * Restore normal pages. 1448 */ 1449 1450 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_PERF); 1451 1452} 1453 1454/* 1455 * Allocate a port resource with the given resource id. 1456 */ 1457int 1458ed_alloc_port(dev, rid, size) 1459 device_t dev; 1460 int rid; 1461 int size; 1462{ 1463 struct ed_softc *sc = device_get_softc(dev); 1464 struct resource *res; 1465 1466 res = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 1467 0ul, ~0ul, size, RF_ACTIVE); 1468 if (res) { 1469 sc->port_rid = rid; 1470 sc->port_res = res; 1471 sc->port_used = 1; 1472 return (0); 1473 } else { 1474 return (ENOENT); 1475 } 1476} 1477 1478/* 1479 * Allocate a memory resource with the given resource id. 1480 */ 1481int 1482ed_alloc_memory(dev, rid, size) 1483 device_t dev; 1484 int rid; 1485 int size; 1486{ 1487 struct ed_softc *sc = device_get_softc(dev); 1488 struct resource *res; 1489 1490 res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 1491 0ul, ~0ul, size, RF_ACTIVE); 1492 if (res) { 1493 sc->mem_rid = rid; 1494 sc->mem_res = res; 1495 sc->mem_used = 1; 1496 return (0); 1497 } else { 1498 return (ENOENT); 1499 } 1500} 1501 1502/* 1503 * Allocate an irq resource with the given resource id. 1504 */ 1505int 1506ed_alloc_irq(dev, rid, flags) 1507 device_t dev; 1508 int rid; 1509 int flags; 1510{ 1511 struct ed_softc *sc = device_get_softc(dev); 1512 struct resource *res; 1513 1514 res = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 1515 0ul, ~0ul, 1, (RF_ACTIVE | flags)); 1516 if (res) { 1517 sc->irq_rid = rid; 1518 sc->irq_res = res; 1519 return (0); 1520 } else { 1521 return (ENOENT); 1522 } 1523} 1524 1525/* 1526 * Release all resources 1527 */ 1528void 1529ed_release_resources(dev) 1530 device_t dev; 1531{ 1532 struct ed_softc *sc = device_get_softc(dev); 1533 1534 if (sc->port_res) { 1535 bus_release_resource(dev, SYS_RES_IOPORT, 1536 sc->port_rid, sc->port_res); 1537 sc->port_res = 0; 1538 } 1539 if (sc->mem_res) { 1540 bus_release_resource(dev, SYS_RES_MEMORY, 1541 sc->mem_rid, sc->mem_res); 1542 sc->mem_res = 0; 1543 } 1544 if (sc->irq_res) { 1545 bus_release_resource(dev, SYS_RES_IRQ, 1546 sc->irq_rid, sc->irq_res); 1547 sc->irq_res = 0; 1548 } 1549} 1550 1551/* 1552 * Install interface into kernel networking data structures 1553 */ 1554int 1555ed_attach(sc, unit, flags) 1556 struct ed_softc *sc; 1557 int unit; 1558 int flags; 1559{ 1560 struct ifnet *ifp = &sc->arpcom.ac_if; 1561 1562 /* 1563 * Set interface to stopped condition (reset) 1564 */ 1565 ed_stop(sc); 1566 1567 if (!ifp->if_name) { 1568 /* 1569 * Initialize ifnet structure 1570 */ 1571 ifp->if_softc = sc; 1572 ifp->if_unit = unit; 1573 ifp->if_name = "ed"; 1574 ifp->if_output = ether_output; 1575 ifp->if_start = ed_start; 1576 ifp->if_ioctl = ed_ioctl; 1577 ifp->if_watchdog = ed_watchdog; 1578 ifp->if_init = ed_init; 1579 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 1580 ifp->if_linkmib = &sc->mibdata; 1581 ifp->if_linkmiblen = sizeof sc->mibdata; 1582 /* 1583 * XXX - should do a better job. 1584 */ 1585 if (sc->is790) 1586 sc->mibdata.dot3StatsEtherChipSet = 1587 DOT3CHIPSET(dot3VendorWesternDigital, 1588 dot3ChipSetWesternDigital83C790); 1589 else 1590 sc->mibdata.dot3StatsEtherChipSet = 1591 DOT3CHIPSET(dot3VendorNational, 1592 dot3ChipSetNational8390); 1593 sc->mibdata.dot3Compliance = DOT3COMPLIANCE_COLLS; 1594 1595 /* 1596 * Set default state for ALTPHYS flag (used to disable the 1597 * tranceiver for AUI operation), based on compile-time 1598 * config option. 1599 */ 1600 if (flags & ED_FLAGS_DISABLE_TRANCEIVER) 1601 ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX | 1602 IFF_MULTICAST | IFF_ALTPHYS); 1603 else 1604 ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX | 1605 IFF_MULTICAST); 1606 1607 /* 1608 * Attach the interface 1609 */ 1610 if_attach(ifp); 1611 ether_ifattach(ifp); 1612 } 1613 /* device attach does transition from UNCONFIGURED to IDLE state */ 1614 1615 /* 1616 * Print additional info when attached 1617 */ 1618 printf("%s%d: address %6D, ", ifp->if_name, ifp->if_unit, 1619 sc->arpcom.ac_enaddr, ":"); 1620 1621 if (sc->type_str && (*sc->type_str != 0)) 1622 printf("type %s ", sc->type_str); 1623 else 1624 printf("type unknown (0x%x) ", sc->type); 1625 1626 if (sc->vendor == ED_VENDOR_HP) 1627 printf("(%s %s IO)", (sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS) ? 1628 "16-bit" : "32-bit", 1629 sc->hpp_mem_start ? "memory mapped" : "regular"); 1630 else 1631 printf("%s ", sc->isa16bit ? "(16 bit)" : "(8 bit)"); 1632 1633 printf("%s\n", (((sc->vendor == ED_VENDOR_3COM) || 1634 (sc->vendor == ED_VENDOR_HP)) && 1635 (ifp->if_flags & IFF_ALTPHYS)) ? " tranceiver disabled" : ""); 1636 1637 /* 1638 * If BPF is in the kernel, call the attach for it 1639 */ 1640 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header)); 1641 return (0); 1642} 1643 1644/* 1645 * Reset interface. 1646 */ 1647static void 1648ed_reset(ifp) 1649 struct ifnet *ifp; 1650{ 1651 struct ed_softc *sc = ifp->if_softc; 1652 int s; 1653 1654 if (sc->gone) 1655 return; 1656 s = splimp(); 1657 1658 /* 1659 * Stop interface and re-initialize. 1660 */ 1661 ed_stop(sc); 1662 ed_init(sc); 1663 1664 (void) splx(s); 1665} 1666 1667/* 1668 * Take interface offline. 1669 */ 1670static void 1671ed_stop(sc) 1672 struct ed_softc *sc; 1673{ 1674 int n = 5000; 1675 1676 if (sc->gone) 1677 return; 1678 /* 1679 * Stop everything on the interface, and select page 0 registers. 1680 */ 1681 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP); 1682 1683 /* 1684 * Wait for interface to enter stopped state, but limit # of checks to 1685 * 'n' (about 5ms). It shouldn't even take 5us on modern DS8390's, but 1686 * just in case it's an old one. 1687 */ 1688 while (((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RST) == 0) && --n); 1689} 1690 1691/* 1692 * Device timeout/watchdog routine. Entered if the device neglects to 1693 * generate an interrupt after a transmit has been started on it. 1694 */ 1695static void 1696ed_watchdog(ifp) 1697 struct ifnet *ifp; 1698{ 1699 struct ed_softc *sc = ifp->if_softc; 1700 1701 if (sc->gone) 1702 return; 1703 log(LOG_ERR, "ed%d: device timeout\n", ifp->if_unit); 1704 ifp->if_oerrors++; 1705 1706 ed_reset(ifp); 1707} 1708 1709/* 1710 * Initialize device. 1711 */ 1712static void 1713ed_init(xsc) 1714 void *xsc; 1715{ 1716 struct ed_softc *sc = xsc; 1717 struct ifnet *ifp = &sc->arpcom.ac_if; 1718 int i, s; 1719 1720 if (sc->gone) 1721 return; 1722 1723 /* address not known */ 1724 if (TAILQ_EMPTY(&ifp->if_addrhead)) /* unlikely? XXX */ 1725 return; 1726 1727 /* 1728 * Initialize the NIC in the exact order outlined in the NS manual. 1729 * This init procedure is "mandatory"...don't change what or when 1730 * things happen. 1731 */ 1732 s = splimp(); 1733 1734 /* reset transmitter flags */ 1735 sc->xmit_busy = 0; 1736 ifp->if_timer = 0; 1737 1738 sc->txb_inuse = 0; 1739 sc->txb_new = 0; 1740 sc->txb_next_tx = 0; 1741 1742 /* This variable is used below - don't move this assignment */ 1743 sc->next_packet = sc->rec_page_start + 1; 1744 1745 /* 1746 * Set interface for page 0, Remote DMA complete, Stopped 1747 */ 1748 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP); 1749 1750 if (sc->isa16bit) { 1751 1752 /* 1753 * Set FIFO threshold to 8, No auto-init Remote DMA, byte 1754 * order=80x86, word-wide DMA xfers, 1755 */ 1756 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1 | ED_DCR_WTS | ED_DCR_LS); 1757 } else { 1758 1759 /* 1760 * Same as above, but byte-wide DMA xfers 1761 */ 1762 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS); 1763 } 1764 1765 /* 1766 * Clear Remote Byte Count Registers 1767 */ 1768 outb(sc->nic_addr + ED_P0_RBCR0, 0); 1769 outb(sc->nic_addr + ED_P0_RBCR1, 0); 1770 1771 /* 1772 * For the moment, don't store incoming packets in memory. 1773 */ 1774 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_MON); 1775 1776 /* 1777 * Place NIC in internal loopback mode 1778 */ 1779 outb(sc->nic_addr + ED_P0_TCR, ED_TCR_LB0); 1780 1781 /* 1782 * Initialize transmit/receive (ring-buffer) Page Start 1783 */ 1784 outb(sc->nic_addr + ED_P0_TPSR, sc->tx_page_start); 1785 outb(sc->nic_addr + ED_P0_PSTART, sc->rec_page_start); 1786 /* Set lower bits of byte addressable framing to 0 */ 1787 if (sc->is790) 1788 outb(sc->nic_addr + 0x09, 0); 1789 1790 /* 1791 * Initialize Receiver (ring-buffer) Page Stop and Boundry 1792 */ 1793 outb(sc->nic_addr + ED_P0_PSTOP, sc->rec_page_stop); 1794 outb(sc->nic_addr + ED_P0_BNRY, sc->rec_page_start); 1795 1796 /* 1797 * Clear all interrupts. A '1' in each bit position clears the 1798 * corresponding flag. 1799 */ 1800 outb(sc->nic_addr + ED_P0_ISR, 0xff); 1801 1802 /* 1803 * Enable the following interrupts: receive/transmit complete, 1804 * receive/transmit error, and Receiver OverWrite. 1805 * 1806 * Counter overflow and Remote DMA complete are *not* enabled. 1807 */ 1808 outb(sc->nic_addr + ED_P0_IMR, 1809 ED_IMR_PRXE | ED_IMR_PTXE | ED_IMR_RXEE | ED_IMR_TXEE | ED_IMR_OVWE); 1810 1811 /* 1812 * Program Command Register for page 1 1813 */ 1814 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP); 1815 1816 /* 1817 * Copy out our station address 1818 */ 1819 for (i = 0; i < ETHER_ADDR_LEN; ++i) 1820 outb(sc->nic_addr + ED_P1_PAR(i), sc->arpcom.ac_enaddr[i]); 1821 1822 /* 1823 * Set Current Page pointer to next_packet (initialized above) 1824 */ 1825 outb(sc->nic_addr + ED_P1_CURR, sc->next_packet); 1826 1827 /* 1828 * Program Receiver Configuration Register and multicast filter. CR is 1829 * set to page 0 on return. 1830 */ 1831 ed_setrcr(sc); 1832 1833 /* 1834 * Take interface out of loopback 1835 */ 1836 outb(sc->nic_addr + ED_P0_TCR, 0); 1837 1838 /* 1839 * If this is a 3Com board, the tranceiver must be software enabled 1840 * (there is no settable hardware default). 1841 */ 1842 if (sc->vendor == ED_VENDOR_3COM) { 1843 if (ifp->if_flags & IFF_ALTPHYS) { 1844 outb(sc->asic_addr + ED_3COM_CR, 0); 1845 } else { 1846 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL); 1847 } 1848 } 1849 1850 /* 1851 * Set 'running' flag, and clear output active flag. 1852 */ 1853 ifp->if_flags |= IFF_RUNNING; 1854 ifp->if_flags &= ~IFF_OACTIVE; 1855 1856 /* 1857 * ...and attempt to start output 1858 */ 1859 ed_start(ifp); 1860 1861 (void) splx(s); 1862} 1863 1864/* 1865 * This routine actually starts the transmission on the interface 1866 */ 1867static __inline void 1868ed_xmit(sc) 1869 struct ed_softc *sc; 1870{ 1871 struct ifnet *ifp = (struct ifnet *)sc; 1872 unsigned short len; 1873 1874 if (sc->gone) 1875 return; 1876 len = sc->txb_len[sc->txb_next_tx]; 1877 1878 /* 1879 * Set NIC for page 0 register access 1880 */ 1881 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA); 1882 1883 /* 1884 * Set TX buffer start page 1885 */ 1886 outb(sc->nic_addr + ED_P0_TPSR, sc->tx_page_start + 1887 sc->txb_next_tx * ED_TXBUF_SIZE); 1888 1889 /* 1890 * Set TX length 1891 */ 1892 outb(sc->nic_addr + ED_P0_TBCR0, len); 1893 outb(sc->nic_addr + ED_P0_TBCR1, len >> 8); 1894 1895 /* 1896 * Set page 0, Remote DMA complete, Transmit Packet, and *Start* 1897 */ 1898 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_TXP | ED_CR_STA); 1899 sc->xmit_busy = 1; 1900 1901 /* 1902 * Point to next transmit buffer slot and wrap if necessary. 1903 */ 1904 sc->txb_next_tx++; 1905 if (sc->txb_next_tx == sc->txb_cnt) 1906 sc->txb_next_tx = 0; 1907 1908 /* 1909 * Set a timer just in case we never hear from the board again 1910 */ 1911 ifp->if_timer = 2; 1912} 1913 1914/* 1915 * Start output on interface. 1916 * We make two assumptions here: 1917 * 1) that the current priority is set to splimp _before_ this code 1918 * is called *and* is returned to the appropriate priority after 1919 * return 1920 * 2) that the IFF_OACTIVE flag is checked before this code is called 1921 * (i.e. that the output part of the interface is idle) 1922 */ 1923static void 1924ed_start(ifp) 1925 struct ifnet *ifp; 1926{ 1927 struct ed_softc *sc = ifp->if_softc; 1928 struct mbuf *m0, *m; 1929 caddr_t buffer; 1930 int len; 1931 1932 if (sc->gone) { 1933 printf("ed_start(%p) GONE\n",ifp); 1934 return; 1935 } 1936outloop: 1937 1938 /* 1939 * First, see if there are buffered packets and an idle transmitter - 1940 * should never happen at this point. 1941 */ 1942 if (sc->txb_inuse && (sc->xmit_busy == 0)) { 1943 printf("ed: packets buffered, but transmitter idle\n"); 1944 ed_xmit(sc); 1945 } 1946 1947 /* 1948 * See if there is room to put another packet in the buffer. 1949 */ 1950 if (sc->txb_inuse == sc->txb_cnt) { 1951 1952 /* 1953 * No room. Indicate this to the outside world and exit. 1954 */ 1955 ifp->if_flags |= IFF_OACTIVE; 1956 return; 1957 } 1958 IF_DEQUEUE(&ifp->if_snd, m); 1959 if (m == 0) { 1960 1961 /* 1962 * We are using the !OACTIVE flag to indicate to the outside 1963 * world that we can accept an additional packet rather than 1964 * that the transmitter is _actually_ active. Indeed, the 1965 * transmitter may be active, but if we haven't filled all the 1966 * buffers with data then we still want to accept more. 1967 */ 1968 ifp->if_flags &= ~IFF_OACTIVE; 1969 return; 1970 } 1971 1972 /* 1973 * Copy the mbuf chain into the transmit buffer 1974 */ 1975 1976 m0 = m; 1977 1978 /* txb_new points to next open buffer slot */ 1979 buffer = sc->mem_start + (sc->txb_new * ED_TXBUF_SIZE * ED_PAGE_SIZE); 1980 1981 if (sc->mem_shared) { 1982 1983 /* 1984 * Special case setup for 16 bit boards... 1985 */ 1986 if (sc->isa16bit) { 1987 switch (sc->vendor) { 1988 1989 /* 1990 * For 16bit 3Com boards (which have 16k of 1991 * memory), we have the xmit buffers in a 1992 * different page of memory ('page 0') - so 1993 * change pages. 1994 */ 1995 case ED_VENDOR_3COM: 1996 outb(sc->asic_addr + ED_3COM_GACFR, 1997 ED_3COM_GACFR_RSEL); 1998 break; 1999 2000 /* 2001 * Enable 16bit access to shared memory on 2002 * WD/SMC boards. 2003 */ 2004 case ED_VENDOR_WD_SMC:{ 2005 outb(sc->asic_addr + ED_WD_LAAR, 2006 sc->wd_laar_proto | ED_WD_LAAR_M16EN); 2007 if (sc->is790) { 2008 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_MENB); 2009 } 2010 break; 2011 } 2012 } 2013 } 2014 for (len = 0; m != 0; m = m->m_next) { 2015 bcopy(mtod(m, caddr_t), buffer, m->m_len); 2016 buffer += m->m_len; 2017 len += m->m_len; 2018 } 2019 2020 /* 2021 * Restore previous shared memory access 2022 */ 2023 if (sc->isa16bit) { 2024 switch (sc->vendor) { 2025 case ED_VENDOR_3COM: 2026 outb(sc->asic_addr + ED_3COM_GACFR, 2027 ED_3COM_GACFR_RSEL | ED_3COM_GACFR_MBS0); 2028 break; 2029 case ED_VENDOR_WD_SMC:{ 2030 if (sc->is790) { 2031 outb(sc->asic_addr + ED_WD_MSR, 0x00); 2032 } 2033 outb(sc->asic_addr + ED_WD_LAAR, 2034 sc->wd_laar_proto & ~ED_WD_LAAR_M16EN); 2035 break; 2036 } 2037 } 2038 } 2039 } else { 2040 len = ed_pio_write_mbufs(sc, m, (int)buffer); 2041 if (len == 0) 2042 goto outloop; 2043 } 2044 2045 sc->txb_len[sc->txb_new] = max(len, (ETHER_MIN_LEN-ETHER_CRC_LEN)); 2046 2047 sc->txb_inuse++; 2048 2049 /* 2050 * Point to next buffer slot and wrap if necessary. 2051 */ 2052 sc->txb_new++; 2053 if (sc->txb_new == sc->txb_cnt) 2054 sc->txb_new = 0; 2055 2056 if (sc->xmit_busy == 0) 2057 ed_xmit(sc); 2058 2059 /* 2060 * Tap off here if there is a bpf listener. 2061 */ 2062 if (ifp->if_bpf) { 2063 bpf_mtap(ifp, m0); 2064 } 2065 2066 m_freem(m0); 2067 2068 /* 2069 * Loop back to the top to possibly buffer more packets 2070 */ 2071 goto outloop; 2072} 2073 2074/* 2075 * Ethernet interface receiver interrupt. 2076 */ 2077static __inline void 2078ed_rint(sc) 2079 struct ed_softc *sc; 2080{ 2081 struct ifnet *ifp = &sc->arpcom.ac_if; 2082 u_char boundry; 2083 u_short len; 2084 struct ed_ring packet_hdr; 2085 char *packet_ptr; 2086 2087 if (sc->gone) 2088 return; 2089 2090 /* 2091 * Set NIC to page 1 registers to get 'current' pointer 2092 */ 2093 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA); 2094 2095 /* 2096 * 'sc->next_packet' is the logical beginning of the ring-buffer - 2097 * i.e. it points to where new data has been buffered. The 'CURR' 2098 * (current) register points to the logical end of the ring-buffer - 2099 * i.e. it points to where additional new data will be added. We loop 2100 * here until the logical beginning equals the logical end (or in 2101 * other words, until the ring-buffer is empty). 2102 */ 2103 while (sc->next_packet != inb(sc->nic_addr + ED_P1_CURR)) { 2104 2105 /* get pointer to this buffer's header structure */ 2106 packet_ptr = sc->mem_ring + 2107 (sc->next_packet - sc->rec_page_start) * ED_PAGE_SIZE; 2108 2109 /* 2110 * The byte count includes a 4 byte header that was added by 2111 * the NIC. 2112 */ 2113 if (sc->mem_shared) 2114 packet_hdr = *(struct ed_ring *) packet_ptr; 2115 else 2116 ed_pio_readmem(sc, (int)packet_ptr, (char *) &packet_hdr, 2117 sizeof(packet_hdr)); 2118 len = packet_hdr.count; 2119 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring)) || 2120 len < (ETHER_MIN_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring))) { 2121 /* 2122 * Length is a wild value. There's a good chance that 2123 * this was caused by the NIC being old and buggy. 2124 * The bug is that the length low byte is duplicated in 2125 * the high byte. Try to recalculate the length based on 2126 * the pointer to the next packet. 2127 */ 2128 /* 2129 * NOTE: sc->next_packet is pointing at the current packet. 2130 */ 2131 len &= ED_PAGE_SIZE - 1; /* preserve offset into page */ 2132 if (packet_hdr.next_packet >= sc->next_packet) { 2133 len += (packet_hdr.next_packet - sc->next_packet) * ED_PAGE_SIZE; 2134 } else { 2135 len += ((packet_hdr.next_packet - sc->rec_page_start) + 2136 (sc->rec_page_stop - sc->next_packet)) * ED_PAGE_SIZE; 2137 } 2138 /* 2139 * because buffers are aligned on 256-byte boundary, 2140 * the length computed above is off by 256 in almost 2141 * all cases. Fix it... 2142 */ 2143 if (len & 0xff) 2144 len -= 256 ; 2145 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN 2146 + sizeof(struct ed_ring))) 2147 sc->mibdata.dot3StatsFrameTooLongs++; 2148 } 2149 /* 2150 * Be fairly liberal about what we allow as a "reasonable" length 2151 * so that a [crufty] packet will make it to BPF (and can thus 2152 * be analyzed). Note that all that is really important is that 2153 * we have a length that will fit into one mbuf cluster or less; 2154 * the upper layer protocols can then figure out the length from 2155 * their own length field(s). 2156 */ 2157 if ((len > sizeof(struct ed_ring)) && 2158 (len <= MCLBYTES) && 2159 (packet_hdr.next_packet >= sc->rec_page_start) && 2160 (packet_hdr.next_packet < sc->rec_page_stop)) { 2161 /* 2162 * Go get packet. 2163 */ 2164 ed_get_packet(sc, packet_ptr + sizeof(struct ed_ring), 2165 len - sizeof(struct ed_ring), packet_hdr.rsr & ED_RSR_PHY); 2166 ifp->if_ipackets++; 2167 } else { 2168 /* 2169 * Really BAD. The ring pointers are corrupted. 2170 */ 2171 log(LOG_ERR, 2172 "ed%d: NIC memory corrupt - invalid packet length %d\n", 2173 ifp->if_unit, len); 2174 ifp->if_ierrors++; 2175 ed_reset(ifp); 2176 return; 2177 } 2178 2179 /* 2180 * Update next packet pointer 2181 */ 2182 sc->next_packet = packet_hdr.next_packet; 2183 2184 /* 2185 * Update NIC boundry pointer - being careful to keep it one 2186 * buffer behind. (as recommended by NS databook) 2187 */ 2188 boundry = sc->next_packet - 1; 2189 if (boundry < sc->rec_page_start) 2190 boundry = sc->rec_page_stop - 1; 2191 2192 /* 2193 * Set NIC to page 0 registers to update boundry register 2194 */ 2195 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA); 2196 2197 outb(sc->nic_addr + ED_P0_BNRY, boundry); 2198 2199 /* 2200 * Set NIC to page 1 registers before looping to top (prepare 2201 * to get 'CURR' current pointer) 2202 */ 2203 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA); 2204 } 2205} 2206 2207/* 2208 * Ethernet interface interrupt processor 2209 */ 2210void 2211edintr(arg) 2212 void *arg; 2213{ 2214 struct ed_softc *sc = (struct ed_softc*) arg; 2215 struct ifnet *ifp = (struct ifnet *)sc; 2216 u_char isr; 2217 2218 if (sc->gone) 2219 return; 2220 /* 2221 * Set NIC to page 0 registers 2222 */ 2223 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA); 2224 2225 /* 2226 * loop until there are no more new interrupts 2227 */ 2228 while ((isr = inb(sc->nic_addr + ED_P0_ISR)) != 0) { 2229 2230 /* 2231 * reset all the bits that we are 'acknowledging' by writing a 2232 * '1' to each bit position that was set (writing a '1' 2233 * *clears* the bit) 2234 */ 2235 outb(sc->nic_addr + ED_P0_ISR, isr); 2236 2237 /* 2238 * Handle transmitter interrupts. Handle these first because 2239 * the receiver will reset the board under some conditions. 2240 */ 2241 if (isr & (ED_ISR_PTX | ED_ISR_TXE)) { 2242 u_char collisions = inb(sc->nic_addr + ED_P0_NCR) & 0x0f; 2243 2244 /* 2245 * Check for transmit error. If a TX completed with an 2246 * error, we end up throwing the packet away. Really 2247 * the only error that is possible is excessive 2248 * collisions, and in this case it is best to allow 2249 * the automatic mechanisms of TCP to backoff the 2250 * flow. Of course, with UDP we're screwed, but this 2251 * is expected when a network is heavily loaded. 2252 */ 2253 (void) inb(sc->nic_addr + ED_P0_TSR); 2254 if (isr & ED_ISR_TXE) { 2255 u_char tsr; 2256 2257 /* 2258 * Excessive collisions (16) 2259 */ 2260 tsr = inb(sc->nic_addr + ED_P0_TSR); 2261 if ((tsr & ED_TSR_ABT) 2262 && (collisions == 0)) { 2263 2264 /* 2265 * When collisions total 16, the 2266 * P0_NCR will indicate 0, and the 2267 * TSR_ABT is set. 2268 */ 2269 collisions = 16; 2270 sc->mibdata.dot3StatsExcessiveCollisions++; 2271 sc->mibdata.dot3StatsCollFrequencies[15]++; 2272 } 2273 if (tsr & ED_TSR_OWC) 2274 sc->mibdata.dot3StatsLateCollisions++; 2275 if (tsr & ED_TSR_CDH) 2276 sc->mibdata.dot3StatsSQETestErrors++; 2277 if (tsr & ED_TSR_CRS) 2278 sc->mibdata.dot3StatsCarrierSenseErrors++; 2279 if (tsr & ED_TSR_FU) 2280 sc->mibdata.dot3StatsInternalMacTransmitErrors++; 2281 2282 /* 2283 * update output errors counter 2284 */ 2285 ifp->if_oerrors++; 2286 } else { 2287 2288 /* 2289 * Update total number of successfully 2290 * transmitted packets. 2291 */ 2292 ifp->if_opackets++; 2293 } 2294 2295 /* 2296 * reset tx busy and output active flags 2297 */ 2298 sc->xmit_busy = 0; 2299 ifp->if_flags &= ~IFF_OACTIVE; 2300 2301 /* 2302 * clear watchdog timer 2303 */ 2304 ifp->if_timer = 0; 2305 2306 /* 2307 * Add in total number of collisions on last 2308 * transmission. 2309 */ 2310 ifp->if_collisions += collisions; 2311 switch(collisions) { 2312 case 0: 2313 case 16: 2314 break; 2315 case 1: 2316 sc->mibdata.dot3StatsSingleCollisionFrames++; 2317 sc->mibdata.dot3StatsCollFrequencies[0]++; 2318 break; 2319 default: 2320 sc->mibdata.dot3StatsMultipleCollisionFrames++; 2321 sc->mibdata. 2322 dot3StatsCollFrequencies[collisions-1] 2323 ++; 2324 break; 2325 } 2326 2327 /* 2328 * Decrement buffer in-use count if not zero (can only 2329 * be zero if a transmitter interrupt occured while 2330 * not actually transmitting). If data is ready to 2331 * transmit, start it transmitting, otherwise defer 2332 * until after handling receiver 2333 */ 2334 if (sc->txb_inuse && --sc->txb_inuse) 2335 ed_xmit(sc); 2336 } 2337 2338 /* 2339 * Handle receiver interrupts 2340 */ 2341 if (isr & (ED_ISR_PRX | ED_ISR_RXE | ED_ISR_OVW)) { 2342 2343 /* 2344 * Overwrite warning. In order to make sure that a 2345 * lockup of the local DMA hasn't occurred, we reset 2346 * and re-init the NIC. The NSC manual suggests only a 2347 * partial reset/re-init is necessary - but some chips 2348 * seem to want more. The DMA lockup has been seen 2349 * only with early rev chips - Methinks this bug was 2350 * fixed in later revs. -DG 2351 */ 2352 if (isr & ED_ISR_OVW) { 2353 ifp->if_ierrors++; 2354#ifdef DIAGNOSTIC 2355 log(LOG_WARNING, 2356 "ed%d: warning - receiver ring buffer overrun\n", 2357 ifp->if_unit); 2358#endif 2359 2360 /* 2361 * Stop/reset/re-init NIC 2362 */ 2363 ed_reset(ifp); 2364 } else { 2365 2366 /* 2367 * Receiver Error. One or more of: CRC error, 2368 * frame alignment error FIFO overrun, or 2369 * missed packet. 2370 */ 2371 if (isr & ED_ISR_RXE) { 2372 u_char rsr; 2373 rsr = inb(sc->nic_addr + ED_P0_RSR); 2374 if (rsr & ED_RSR_CRC) 2375 sc->mibdata.dot3StatsFCSErrors++; 2376 if (rsr & ED_RSR_FAE) 2377 sc->mibdata.dot3StatsAlignmentErrors++; 2378 if (rsr & ED_RSR_FO) 2379 sc->mibdata.dot3StatsInternalMacReceiveErrors++; 2380 ifp->if_ierrors++; 2381#ifdef ED_DEBUG 2382 printf("ed%d: receive error %x\n", ifp->if_unit, 2383 inb(sc->nic_addr + ED_P0_RSR)); 2384#endif 2385 } 2386 2387 /* 2388 * Go get the packet(s) XXX - Doing this on an 2389 * error is dubious because there shouldn't be 2390 * any data to get (we've configured the 2391 * interface to not accept packets with 2392 * errors). 2393 */ 2394 2395 /* 2396 * Enable 16bit access to shared memory first 2397 * on WD/SMC boards. 2398 */ 2399 if (sc->isa16bit && 2400 (sc->vendor == ED_VENDOR_WD_SMC)) { 2401 2402 outb(sc->asic_addr + ED_WD_LAAR, 2403 sc->wd_laar_proto | ED_WD_LAAR_M16EN); 2404 if (sc->is790) { 2405 outb(sc->asic_addr + ED_WD_MSR, 2406 ED_WD_MSR_MENB); 2407 } 2408 } 2409 ed_rint(sc); 2410 2411 /* disable 16bit access */ 2412 if (sc->isa16bit && 2413 (sc->vendor == ED_VENDOR_WD_SMC)) { 2414 2415 if (sc->is790) { 2416 outb(sc->asic_addr + ED_WD_MSR, 0x00); 2417 } 2418 outb(sc->asic_addr + ED_WD_LAAR, 2419 sc->wd_laar_proto & ~ED_WD_LAAR_M16EN); 2420 } 2421 } 2422 } 2423 2424 /* 2425 * If it looks like the transmitter can take more data, 2426 * attempt to start output on the interface. This is done 2427 * after handling the receiver to give the receiver priority. 2428 */ 2429 if ((ifp->if_flags & IFF_OACTIVE) == 0) 2430 ed_start(ifp); 2431 2432 /* 2433 * return NIC CR to standard state: page 0, remote DMA 2434 * complete, start (toggling the TXP bit off, even if was just 2435 * set in the transmit routine, is *okay* - it is 'edge' 2436 * triggered from low to high) 2437 */ 2438 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA); 2439 2440 /* 2441 * If the Network Talley Counters overflow, read them to reset 2442 * them. It appears that old 8390's won't clear the ISR flag 2443 * otherwise - resulting in an infinite loop. 2444 */ 2445 if (isr & ED_ISR_CNT) { 2446 (void) inb(sc->nic_addr + ED_P0_CNTR0); 2447 (void) inb(sc->nic_addr + ED_P0_CNTR1); 2448 (void) inb(sc->nic_addr + ED_P0_CNTR2); 2449 } 2450 } 2451} 2452 2453/* 2454 * Process an ioctl request. This code needs some work - it looks 2455 * pretty ugly. 2456 */ 2457static int 2458ed_ioctl(ifp, command, data) 2459 register struct ifnet *ifp; 2460 u_long command; 2461 caddr_t data; 2462{ 2463 struct ed_softc *sc = ifp->if_softc; 2464 int s, error = 0; 2465 2466 if (sc->gone) { 2467 ifp->if_flags &= ~IFF_RUNNING; 2468 return ENXIO; 2469 } 2470 s = splimp(); 2471 2472 switch (command) { 2473 2474 case SIOCSIFADDR: 2475 case SIOCGIFADDR: 2476 case SIOCSIFMTU: 2477 error = ether_ioctl(ifp, command, data); 2478 break; 2479 2480 case SIOCSIFFLAGS: 2481 2482 /* 2483 * If the interface is marked up and stopped, then start it. 2484 * If it is marked down and running, then stop it. 2485 */ 2486 if (ifp->if_flags & IFF_UP) { 2487 if ((ifp->if_flags & IFF_RUNNING) == 0) 2488 ed_init(sc); 2489 } else { 2490 if (ifp->if_flags & IFF_RUNNING) { 2491 ed_stop(sc); 2492 ifp->if_flags &= ~IFF_RUNNING; 2493 } 2494 } 2495 2496 /* 2497 * Promiscuous flag may have changed, so reprogram the RCR. 2498 */ 2499 ed_setrcr(sc); 2500 2501 /* 2502 * An unfortunate hack to provide the (required) software 2503 * control of the tranceiver for 3Com boards. The ALTPHYS flag 2504 * disables the tranceiver if set. 2505 */ 2506 if (sc->vendor == ED_VENDOR_3COM) { 2507 if (ifp->if_flags & IFF_ALTPHYS) { 2508 outb(sc->asic_addr + ED_3COM_CR, 0); 2509 } else { 2510 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL); 2511 } 2512 } else if (sc->vendor == ED_VENDOR_HP) 2513 ed_hpp_set_physical_link(sc); 2514 break; 2515 2516 case SIOCADDMULTI: 2517 case SIOCDELMULTI: 2518 /* 2519 * Multicast list has changed; set the hardware filter 2520 * accordingly. 2521 */ 2522 ed_setrcr(sc); 2523 error = 0; 2524 break; 2525 2526 default: 2527 error = EINVAL; 2528 } 2529 (void) splx(s); 2530 return (error); 2531} 2532 2533/* 2534 * Given a source and destination address, copy 'amount' of a packet from 2535 * the ring buffer into a linear destination buffer. Takes into account 2536 * ring-wrap. 2537 */ 2538static __inline char * 2539ed_ring_copy(sc, src, dst, amount) 2540 struct ed_softc *sc; 2541 char *src; 2542 char *dst; 2543 u_short amount; 2544{ 2545 u_short tmp_amount; 2546 2547 /* does copy wrap to lower addr in ring buffer? */ 2548 if (src + amount > sc->mem_end) { 2549 tmp_amount = sc->mem_end - src; 2550 2551 /* copy amount up to end of NIC memory */ 2552 if (sc->mem_shared) 2553 bcopy(src, dst, tmp_amount); 2554 else 2555 ed_pio_readmem(sc, (int)src, dst, tmp_amount); 2556 2557 amount -= tmp_amount; 2558 src = sc->mem_ring; 2559 dst += tmp_amount; 2560 } 2561 if (sc->mem_shared) 2562 bcopy(src, dst, amount); 2563 else 2564 ed_pio_readmem(sc, (int)src, dst, amount); 2565 2566 return (src + amount); 2567} 2568 2569/* 2570 * Retreive packet from shared memory and send to the next level up via 2571 * ether_input(). If there is a BPF listener, give a copy to BPF, too. 2572 */ 2573static void 2574ed_get_packet(sc, buf, len, multicast) 2575 struct ed_softc *sc; 2576 char *buf; 2577 u_short len; 2578 int multicast; 2579{ 2580 struct ether_header *eh; 2581 struct mbuf *m; 2582 2583 /* Allocate a header mbuf */ 2584 MGETHDR(m, M_DONTWAIT, MT_DATA); 2585 if (m == NULL) 2586 return; 2587 m->m_pkthdr.rcvif = &sc->arpcom.ac_if; 2588 m->m_pkthdr.len = m->m_len = len; 2589 2590 /* 2591 * We always put the received packet in a single buffer - 2592 * either with just an mbuf header or in a cluster attached 2593 * to the header. The +2 is to compensate for the alignment 2594 * fixup below. 2595 */ 2596 if ((len + 2) > MHLEN) { 2597 /* Attach an mbuf cluster */ 2598 MCLGET(m, M_DONTWAIT); 2599 2600 /* Insist on getting a cluster */ 2601 if ((m->m_flags & M_EXT) == 0) { 2602 m_freem(m); 2603 return; 2604 } 2605 } 2606 2607 /* 2608 * The +2 is to longword align the start of the real packet. 2609 * This is important for NFS. 2610 */ 2611 m->m_data += 2; 2612 eh = mtod(m, struct ether_header *); 2613 2614#ifdef BRIDGE 2615 /* 2616 * Get link layer header, invoke brige_in, then 2617 * depending on the outcome of the test fetch the rest of the 2618 * packet and either pass up or call bdg_forward. 2619 */ 2620 if (do_bridge) { 2621 struct ifnet *ifp ; 2622 int need_more = 1 ; /* in case not bpf */ 2623 2624 if (sc->arpcom.ac_if.if_bpf) { 2625 need_more = 0 ; 2626 ed_ring_copy(sc, buf, (char *)eh, len); 2627 bpf_mtap(&sc->arpcom.ac_if, m); 2628 } else 2629 ed_ring_copy(sc, buf, (char *)eh, 14); 2630 ifp = bridge_in(m); 2631 if (ifp == BDG_DROP) { 2632 m_freem(m); 2633 return ; 2634 } 2635 /* else fetch rest of pkt and continue */ 2636 if (need_more && len > 14) 2637 ed_ring_copy(sc, buf+14, (char *)(eh+1), len - 14); 2638 if (ifp != BDG_LOCAL ) 2639 bdg_forward(&m, ifp); /* not local, need forwarding */ 2640 if (ifp == BDG_LOCAL || ifp == BDG_BCAST || ifp == BDG_MCAST) 2641 goto getit ; 2642 /* not local and not multicast, just drop it */ 2643 if (m) 2644 m_freem(m); 2645 return ; 2646 } 2647#endif 2648 /* 2649 * Get packet, including link layer address, from interface. 2650 */ 2651 ed_ring_copy(sc, buf, (char *)eh, len); 2652 2653 /* 2654 * Check if there's a BPF listener on this interface. If so, hand off 2655 * the raw packet to bpf. 2656 */ 2657 if (sc->arpcom.ac_if.if_bpf) 2658 bpf_mtap(&sc->arpcom.ac_if, m); 2659 /* 2660 * If we are in promiscuous mode, we have to check whether 2661 * this packet is really for us. 2662 */ 2663 if ((sc->arpcom.ac_if.if_flags & IFF_PROMISC) && 2664 bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr, 2665 sizeof(eh->ether_dhost)) != 0 && multicast == 0) { 2666 m_freem(m); 2667 return; 2668 } 2669 2670#ifdef BRIDGE 2671getit: 2672#endif 2673 /* 2674 * Remove link layer address. 2675 */ 2676 m->m_pkthdr.len = m->m_len = len - sizeof(struct ether_header); 2677 m->m_data += sizeof(struct ether_header); 2678 2679 ether_input(&sc->arpcom.ac_if, eh, m); 2680 return; 2681} 2682 2683/* 2684 * Supporting routines 2685 */ 2686 2687/* 2688 * Given a NIC memory source address and a host memory destination 2689 * address, copy 'amount' from NIC to host using Programmed I/O. 2690 * The 'amount' is rounded up to a word - okay as long as mbufs 2691 * are word sized. 2692 * This routine is currently Novell-specific. 2693 */ 2694static void 2695ed_pio_readmem(sc, src, dst, amount) 2696 struct ed_softc *sc; 2697 int src; 2698 unsigned char *dst; 2699 unsigned short amount; 2700{ 2701 /* HP cards need special handling */ 2702 if (sc->vendor == ED_VENDOR_HP && sc->type == ED_TYPE_HP_PCLANPLUS) { 2703 ed_hpp_readmem(sc, src, dst, amount); 2704 return; 2705 } 2706 2707 /* Regular Novell cards */ 2708 /* select page 0 registers */ 2709 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STA); 2710 2711 /* round up to a word */ 2712 if (amount & 1) 2713 ++amount; 2714 2715 /* set up DMA byte count */ 2716 outb(sc->nic_addr + ED_P0_RBCR0, amount); 2717 outb(sc->nic_addr + ED_P0_RBCR1, amount >> 8); 2718 2719 /* set up source address in NIC mem */ 2720 outb(sc->nic_addr + ED_P0_RSAR0, src); 2721 outb(sc->nic_addr + ED_P0_RSAR1, src >> 8); 2722 2723 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD0 | ED_CR_STA); 2724 2725 if (sc->isa16bit) { 2726 insw(sc->asic_addr + ED_NOVELL_DATA, dst, amount / 2); 2727 } else 2728 insb(sc->asic_addr + ED_NOVELL_DATA, dst, amount); 2729 2730} 2731 2732/* 2733 * Stripped down routine for writing a linear buffer to NIC memory. 2734 * Only used in the probe routine to test the memory. 'len' must 2735 * be even. 2736 */ 2737static void 2738ed_pio_writemem(sc, src, dst, len) 2739 struct ed_softc *sc; 2740 char *src; 2741 unsigned short dst; 2742 unsigned short len; 2743{ 2744 int maxwait = 200; /* about 240us */ 2745 2746 if (sc->vendor == ED_VENDOR_NOVELL) { 2747 2748 /* select page 0 registers */ 2749 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STA); 2750 2751 /* reset remote DMA complete flag */ 2752 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC); 2753 2754 /* set up DMA byte count */ 2755 outb(sc->nic_addr + ED_P0_RBCR0, len); 2756 outb(sc->nic_addr + ED_P0_RBCR1, len >> 8); 2757 2758 /* set up destination address in NIC mem */ 2759 outb(sc->nic_addr + ED_P0_RSAR0, dst); 2760 outb(sc->nic_addr + ED_P0_RSAR1, dst >> 8); 2761 2762 /* set remote DMA write */ 2763 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD1 | ED_CR_STA); 2764 2765 if (sc->isa16bit) 2766 outsw(sc->asic_addr + ED_NOVELL_DATA, src, len / 2); 2767 else 2768 outsb(sc->asic_addr + ED_NOVELL_DATA, src, len); 2769 2770 /* 2771 * Wait for remote DMA complete. This is necessary because on the 2772 * transmit side, data is handled internally by the NIC in bursts and 2773 * we can't start another remote DMA until this one completes. Not 2774 * waiting causes really bad things to happen - like the NIC 2775 * irrecoverably jamming the ISA bus. 2776 */ 2777 while (((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait); 2778 2779 } else if ((sc->vendor == ED_VENDOR_HP) && 2780 (sc->type == ED_TYPE_HP_PCLANPLUS)) { 2781 2782 /* HP PCLAN+ */ 2783 2784 /* reset remote DMA complete flag */ 2785 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC); 2786 2787 /* program the write address in RAM */ 2788 outw(sc->asic_addr + ED_HPP_PAGE_0, dst); 2789 2790 if (sc->hpp_mem_start) { 2791 u_short *s = (u_short *) src; 2792 volatile u_short *d = (u_short *) sc->hpp_mem_start; 2793 u_short *const fence = s + (len >> 1); 2794 2795 /* 2796 * Enable memory mapped access. 2797 */ 2798 2799 outw(sc->asic_addr + ED_HPP_OPTION, 2800 sc->hpp_options & 2801 ~(ED_HPP_OPTION_MEM_DISABLE | 2802 ED_HPP_OPTION_BOOT_ROM_ENB)); 2803 2804 /* 2805 * Copy to NIC memory. 2806 */ 2807 2808 while (s < fence) 2809 *d = *s++; 2810 2811 /* 2812 * Restore Boot ROM access. 2813 */ 2814 2815 outw(sc->asic_addr + ED_HPP_OPTION, 2816 sc->hpp_options); 2817 2818 } else { 2819 /* write data using I/O writes */ 2820 outsw(sc->asic_addr + ED_HPP_PAGE_4, src, len / 2); 2821 } 2822 2823 } 2824} 2825 2826/* 2827 * Write an mbuf chain to the destination NIC memory address using 2828 * programmed I/O. 2829 */ 2830static u_short 2831ed_pio_write_mbufs(sc, m, dst) 2832 struct ed_softc *sc; 2833 struct mbuf *m; 2834 int dst; 2835{ 2836 struct ifnet *ifp = (struct ifnet *)sc; 2837 unsigned short total_len, dma_len; 2838 struct mbuf *mp; 2839 int maxwait = 200; /* about 240us */ 2840 2841 /* HP PC Lan+ cards need special handling */ 2842 if ((sc->vendor == ED_VENDOR_HP) && 2843 (sc->type == ED_TYPE_HP_PCLANPLUS)) { 2844 return ed_hpp_write_mbufs(sc, m, dst); 2845 } 2846 2847 /* First, count up the total number of bytes to copy */ 2848 for (total_len = 0, mp = m; mp; mp = mp->m_next) 2849 total_len += mp->m_len; 2850 2851 dma_len = total_len; 2852 if (sc->isa16bit && (dma_len & 1)) 2853 dma_len++; 2854 2855 /* select page 0 registers */ 2856 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STA); 2857 2858 /* reset remote DMA complete flag */ 2859 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC); 2860 2861 /* set up DMA byte count */ 2862 outb(sc->nic_addr + ED_P0_RBCR0, dma_len); 2863 outb(sc->nic_addr + ED_P0_RBCR1, dma_len >> 8); 2864 2865 /* set up destination address in NIC mem */ 2866 outb(sc->nic_addr + ED_P0_RSAR0, dst); 2867 outb(sc->nic_addr + ED_P0_RSAR1, dst >> 8); 2868 2869 /* set remote DMA write */ 2870 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD1 | ED_CR_STA); 2871 2872 /* 2873 * Transfer the mbuf chain to the NIC memory. 2874 * 16-bit cards require that data be transferred as words, and only words. 2875 * So that case requires some extra code to patch over odd-length mbufs. 2876 */ 2877 2878 if (!sc->isa16bit) { 2879 /* NE1000s are easy */ 2880 while (m) { 2881 if (m->m_len) { 2882 outsb(sc->asic_addr + ED_NOVELL_DATA, 2883 m->m_data, m->m_len); 2884 } 2885 m = m->m_next; 2886 } 2887 } else { 2888 /* NE2000s are a pain */ 2889 unsigned char *data; 2890 int len, wantbyte; 2891 unsigned char savebyte[2]; 2892 2893 wantbyte = 0; 2894 2895 while (m) { 2896 len = m->m_len; 2897 if (len) { 2898 data = mtod(m, caddr_t); 2899 /* finish the last word */ 2900 if (wantbyte) { 2901 savebyte[1] = *data; 2902 outw(sc->asic_addr + ED_NOVELL_DATA, *(u_short *)savebyte); 2903 data++; 2904 len--; 2905 wantbyte = 0; 2906 } 2907 /* output contiguous words */ 2908 if (len > 1) { 2909 outsw(sc->asic_addr + ED_NOVELL_DATA, 2910 data, len >> 1); 2911 data += len & ~1; 2912 len &= 1; 2913 } 2914 /* save last byte, if necessary */ 2915 if (len == 1) { 2916 savebyte[0] = *data; 2917 wantbyte = 1; 2918 } 2919 } 2920 m = m->m_next; 2921 } 2922 /* spit last byte */ 2923 if (wantbyte) { 2924 outw(sc->asic_addr + ED_NOVELL_DATA, *(u_short *)savebyte); 2925 } 2926 } 2927 2928 /* 2929 * Wait for remote DMA complete. This is necessary because on the 2930 * transmit side, data is handled internally by the NIC in bursts and 2931 * we can't start another remote DMA until this one completes. Not 2932 * waiting causes really bad things to happen - like the NIC 2933 * irrecoverably jamming the ISA bus. 2934 */ 2935 while (((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait); 2936 2937 if (!maxwait) { 2938 log(LOG_WARNING, "ed%d: remote transmit DMA failed to complete\n", 2939 ifp->if_unit); 2940 ed_reset(ifp); 2941 return(0); 2942 } 2943 return (total_len); 2944} 2945 2946/* 2947 * Support routines to handle the HP PC Lan+ card. 2948 */ 2949 2950/* 2951 * HP PC Lan+: Read from NIC memory, using either PIO or memory mapped 2952 * IO. 2953 */ 2954 2955static void 2956ed_hpp_readmem(sc, src, dst, amount) 2957 struct ed_softc *sc; 2958 unsigned short src; 2959 unsigned char *dst; 2960 unsigned short amount; 2961{ 2962 2963 int use_32bit_access = !(sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS); 2964 2965 2966 /* Program the source address in RAM */ 2967 outw(sc->asic_addr + ED_HPP_PAGE_2, src); 2968 2969 /* 2970 * The HP PC Lan+ card supports word reads as well as 2971 * a memory mapped i/o port that is aliased to every 2972 * even address on the board. 2973 */ 2974 2975 if (sc->hpp_mem_start) { 2976 2977 /* Enable memory mapped access. */ 2978 outw(sc->asic_addr + ED_HPP_OPTION, 2979 sc->hpp_options & 2980 ~(ED_HPP_OPTION_MEM_DISABLE | 2981 ED_HPP_OPTION_BOOT_ROM_ENB)); 2982 2983 if (use_32bit_access && (amount > 3)) { 2984 u_long *dl = (u_long *) dst; 2985 volatile u_long *const sl = 2986 (u_long *) sc->hpp_mem_start; 2987 u_long *const fence = dl + (amount >> 2); 2988 2989 /* Copy out NIC data. We could probably write this 2990 as a `movsl'. The currently generated code is lousy. 2991 */ 2992 2993 while (dl < fence) 2994 *dl++ = *sl; 2995 2996 dst += (amount & ~3); 2997 amount &= 3; 2998 2999 } 3000 3001 /* Finish off any words left, as a series of short reads */ 3002 if (amount > 1) { 3003 u_short *d = (u_short *) dst; 3004 volatile u_short *const s = 3005 (u_short *) sc->hpp_mem_start; 3006 u_short *const fence = d + (amount >> 1); 3007 3008 /* Copy out NIC data. */ 3009 3010 while (d < fence) 3011 *d++ = *s; 3012 3013 dst += (amount & ~1); 3014 amount &= 1; 3015 } 3016 3017 /* 3018 * read in a byte; however we need to always read 16 bits 3019 * at a time or the hardware gets into a funny state 3020 */ 3021 3022 if (amount == 1) { 3023 /* need to read in a short and copy LSB */ 3024 volatile u_short *const s = 3025 (volatile u_short *) sc->hpp_mem_start; 3026 3027 *dst = (*s) & 0xFF; 3028 } 3029 3030 /* Restore Boot ROM access. */ 3031 3032 outw(sc->asic_addr + ED_HPP_OPTION, 3033 sc->hpp_options); 3034 3035 3036 } else { 3037 /* Read in data using the I/O port */ 3038 if (use_32bit_access && (amount > 3)) { 3039 insl(sc->asic_addr + ED_HPP_PAGE_4, dst, amount >> 2); 3040 dst += (amount & ~3); 3041 amount &= 3; 3042 } 3043 if (amount > 1) { 3044 insw(sc->asic_addr + ED_HPP_PAGE_4, dst, amount >> 1); 3045 dst += (amount & ~1); 3046 amount &= 1; 3047 } 3048 if (amount == 1) { /* read in a short and keep the LSB */ 3049 *dst = inw(sc->asic_addr + ED_HPP_PAGE_4) & 0xFF; 3050 } 3051 } 3052} 3053 3054/* 3055 * Write to HP PC Lan+ NIC memory. Access to the NIC can be by using 3056 * outsw() or via the memory mapped interface to the same register. 3057 * Writes have to be in word units; byte accesses won't work and may cause 3058 * the NIC to behave wierdly. Long word accesses are permitted if the ASIC 3059 * allows it. 3060 */ 3061 3062static u_short 3063ed_hpp_write_mbufs(struct ed_softc *sc, struct mbuf *m, int dst) 3064{ 3065 int len, wantbyte; 3066 unsigned short total_len; 3067 unsigned char savebyte[2]; 3068 volatile u_short * const d = 3069 (volatile u_short *) sc->hpp_mem_start; 3070 int use_32bit_accesses = !(sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS); 3071 3072 /* select page 0 registers */ 3073 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA); 3074 3075 /* reset remote DMA complete flag */ 3076 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC); 3077 3078 /* program the write address in RAM */ 3079 outw(sc->asic_addr + ED_HPP_PAGE_0, dst); 3080 3081 if (sc->hpp_mem_start) /* enable memory mapped I/O */ 3082 outw(sc->asic_addr + ED_HPP_OPTION, sc->hpp_options & 3083 ~(ED_HPP_OPTION_MEM_DISABLE | 3084 ED_HPP_OPTION_BOOT_ROM_ENB)); 3085 3086 wantbyte = 0; 3087 total_len = 0; 3088 3089 if (sc->hpp_mem_start) { /* Memory mapped I/O port */ 3090 while (m) { 3091 total_len += (len = m->m_len); 3092 if (len) { 3093 caddr_t data = mtod(m, caddr_t); 3094 /* finish the last word of the previous mbuf */ 3095 if (wantbyte) { 3096 savebyte[1] = *data; 3097 *d = *((ushort *) savebyte); 3098 data++; len--; wantbyte = 0; 3099 } 3100 /* output contiguous words */ 3101 if ((len > 3) && (use_32bit_accesses)) { 3102 volatile u_long *const dl = 3103 (volatile u_long *) d; 3104 u_long *sl = (u_long *) data; 3105 u_long *fence = sl + (len >> 2); 3106 3107 while (sl < fence) 3108 *dl = *sl++; 3109 3110 data += (len & ~3); 3111 len &= 3; 3112 } 3113 /* finish off remain 16 bit writes */ 3114 if (len > 1) { 3115 u_short *s = (u_short *) data; 3116 u_short *fence = s + (len >> 1); 3117 3118 while (s < fence) 3119 *d = *s++; 3120 3121 data += (len & ~1); 3122 len &= 1; 3123 } 3124 /* save last byte if needed */ 3125 if ((wantbyte = (len == 1)) != 0) 3126 savebyte[0] = *data; 3127 } 3128 m = m->m_next; /* to next mbuf */ 3129 } 3130 if (wantbyte) /* write last byte */ 3131 *d = *((u_short *) savebyte); 3132 } else { 3133 /* use programmed I/O */ 3134 while (m) { 3135 total_len += (len = m->m_len); 3136 if (len) { 3137 caddr_t data = mtod(m, caddr_t); 3138 /* finish the last word of the previous mbuf */ 3139 if (wantbyte) { 3140 savebyte[1] = *data; 3141 outw(sc->asic_addr + ED_HPP_PAGE_4, 3142 *((u_short *)savebyte)); 3143 data++; 3144 len--; 3145 wantbyte = 0; 3146 } 3147 /* output contiguous words */ 3148 if ((len > 3) && use_32bit_accesses) { 3149 outsl(sc->asic_addr + ED_HPP_PAGE_4, 3150 data, len >> 2); 3151 data += (len & ~3); 3152 len &= 3; 3153 } 3154 /* finish off remaining 16 bit accesses */ 3155 if (len > 1) { 3156 outsw(sc->asic_addr + ED_HPP_PAGE_4, 3157 data, len >> 1); 3158 data += (len & ~1); 3159 len &= 1; 3160 } 3161 if ((wantbyte = (len == 1)) != 0) 3162 savebyte[0] = *data; 3163 3164 } /* if len != 0 */ 3165 m = m->m_next; 3166 } 3167 if (wantbyte) /* spit last byte */ 3168 outw(sc->asic_addr + ED_HPP_PAGE_4, 3169 *(u_short *)savebyte); 3170 3171 } 3172 3173 if (sc->hpp_mem_start) /* turn off memory mapped i/o */ 3174 outw(sc->asic_addr + ED_HPP_OPTION, 3175 sc->hpp_options); 3176 3177 return (total_len); 3178} 3179 3180static void 3181ed_setrcr(sc) 3182 struct ed_softc *sc; 3183{ 3184 struct ifnet *ifp = (struct ifnet *)sc; 3185 int i; 3186 3187 /* set page 1 registers */ 3188 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP); 3189 3190 if (ifp->if_flags & IFF_PROMISC) { 3191 3192 /* 3193 * Reconfigure the multicast filter. 3194 */ 3195 for (i = 0; i < 8; i++) 3196 outb(sc->nic_addr + ED_P1_MAR(i), 0xff); 3197 3198 /* 3199 * And turn on promiscuous mode. Also enable reception of 3200 * runts and packets with CRC & alignment errors. 3201 */ 3202 /* Set page 0 registers */ 3203 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP); 3204 3205 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_PRO | ED_RCR_AM | 3206 ED_RCR_AB | ED_RCR_AR | ED_RCR_SEP); 3207 } else { 3208 /* set up multicast addresses and filter modes */ 3209 if (ifp->if_flags & IFF_MULTICAST) { 3210 u_long mcaf[2]; 3211 3212 if (ifp->if_flags & IFF_ALLMULTI) { 3213 mcaf[0] = 0xffffffff; 3214 mcaf[1] = 0xffffffff; 3215 } else 3216 ds_getmcaf(sc, mcaf); 3217 3218 /* 3219 * Set multicast filter on chip. 3220 */ 3221 for (i = 0; i < 8; i++) 3222 outb(sc->nic_addr + ED_P1_MAR(i), ((u_char *) mcaf)[i]); 3223 3224 /* Set page 0 registers */ 3225 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP); 3226 3227 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_AM | ED_RCR_AB); 3228 } else { 3229 3230 /* 3231 * Initialize multicast address hashing registers to 3232 * not accept multicasts. 3233 */ 3234 for (i = 0; i < 8; ++i) 3235 outb(sc->nic_addr + ED_P1_MAR(i), 0x00); 3236 3237 /* Set page 0 registers */ 3238 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP); 3239 3240 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_AB); 3241 } 3242 } 3243 3244 /* 3245 * Start interface. 3246 */ 3247 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA); 3248} 3249 3250/* 3251 * Compute crc for ethernet address 3252 */ 3253static u_long 3254ds_crc(ep) 3255 u_char *ep; 3256{ 3257#define POLYNOMIAL 0x04c11db6 3258 register u_long crc = 0xffffffffL; 3259 register int carry, i, j; 3260 register u_char b; 3261 3262 for (i = 6; --i >= 0;) { 3263 b = *ep++; 3264 for (j = 8; --j >= 0;) { 3265 carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01); 3266 crc <<= 1; 3267 b >>= 1; 3268 if (carry) 3269 crc = ((crc ^ POLYNOMIAL) | carry); 3270 } 3271 } 3272 return crc; 3273#undef POLYNOMIAL 3274} 3275 3276/* 3277 * Compute the multicast address filter from the 3278 * list of multicast addresses we need to listen to. 3279 */ 3280static void 3281ds_getmcaf(sc, mcaf) 3282 struct ed_softc *sc; 3283 u_long *mcaf; 3284{ 3285 register u_int index; 3286 register u_char *af = (u_char *) mcaf; 3287 struct ifmultiaddr *ifma; 3288 3289 mcaf[0] = 0; 3290 mcaf[1] = 0; 3291 3292 for (ifma = sc->arpcom.ac_if.if_multiaddrs.lh_first; ifma; 3293 ifma = ifma->ifma_link.le_next) { 3294 if (ifma->ifma_addr->sa_family != AF_LINK) 3295 continue; 3296 index = ds_crc(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)) 3297 >> 26; 3298 af[index >> 3] |= 1 << (index & 7); 3299 } 3300} 3301