if_ed.c revision 50
1/* 2 * Device driver for National Semiconductor DS8390 based ethernet 3 * adapters. By David Greenman, 29-April-1993 4 * 5 * Copyright (C) 1993, David Greenman. This software may be used, modified, 6 * copied, distributed, and sold, in both source and binary form provided 7 * that the above copyright and these terms are retained. Under no 8 * circumstances is the author responsible for the proper functioning 9 * of this software, nor does the author assume any responsibility 10 * for damages incurred with its use. 11 * 12 * Currently supports the Western Digital/SMC 8003 and 8013 series 13 * and the 3Com 3c503 14 */ 15 16/* 17 * Modification history 18 * 19 * $Log: if_ed.c,v $ 20 * Revision 1.11 93/06/27 03:07:01 davidg 21 * fixed bugs in the 3Com part of the probe routine that were uncovered by 22 * the previous fix. 23 * 24 * Revision 1.10 93/06/25 19:23:19 davidg 25 * fixed bug that caused erroneous 'Invalid irq configuration' message when 26 * no board is present (during autoconfiguration). 27 * 28 * Revision 1.9 93/06/23 03:48:14 davidg 29 * fixed minor typo introduced when cleaning up probe routine 30 * 31 * Revision 1.8 93/06/23 03:37:19 davidg 32 * cleaned up/added some comments. Also improved readability of a part of 33 * the probe routine. 34 * 35 * Revision 1.7 93/06/22 04:45:01 davidg 36 * (no additional changes) Second beta release 37 * 38 * Revision 1.6 93/06/22 04:40:35 davidg 39 * minor definition fix to ed_reset() 40 * 41 * Revision 1.5 93/06/22 04:37:39 davidg 42 * fixed some comments 43 * 44 * Revision 1.4 93/06/22 04:34:34 davidg 45 * added support to use the LLC0 'link-level control' flag 46 * to disable the tranceiver for AUI operation on 3Com boards. 47 * The default for this flag can be set in the kernel config 48 * file - 'flags 0x01' sets the flag (disables the tranceiver). 49 * 50 * Revision 1.3 93/06/17 03:57:28 davidg 51 * fixed some printf's 52 * 53 * Revision 1.2 93/06/17 03:26:49 davidg 54 * fixed 3c503 code to determine 8/16bit board 55 * changed attach printf to work with Interim-0.1.5 and NetBSD 56 * 57 * Revision 1.1 93/06/14 22:21:24 davidg 58 * Beta release of device driver for SMC/WD80x3 and 3C503 ethernet boards. 59 * 60 * 61 */ 62 63#include "ed.h" 64#if NED > 0 65#include "bpfilter.h" 66 67#include "param.h" 68#include "errno.h" 69#include "ioctl.h" 70#include "mbuf.h" 71#include "socket.h" 72#include "syslog.h" 73 74#include "net/if.h" 75#include "net/if_dl.h" 76#include "net/if_types.h" 77#include "net/netisr.h" 78 79#ifdef INET 80#include "netinet/in.h" 81#include "netinet/in_systm.h" 82#include "netinet/in_var.h" 83#include "netinet/ip.h" 84#include "netinet/if_ether.h" 85#endif 86 87#ifdef NS 88#include "netns/ns.h" 89#include "netns/ns_if.h" 90#endif 91 92#if NBPFILTER > 0 93#include "net/bpf.h" 94#include "net/bpfdesc.h" 95#endif 96 97#include "i386/isa/isa.h" 98#include "i386/isa/isa_device.h" 99#include "i386/isa/icu.h" 100#include "i386/isa/if_edreg.h" 101 102#include "i386/include/pio.h" 103 104 105/* 106 * ed_softc: per line info and status 107 */ 108struct ed_softc { 109 struct arpcom arpcom; /* ethernet common */ 110 111 char *type_str; /* pointer to type string */ 112 u_char vendor; /* interface vendor */ 113 u_char type; /* interface type code */ 114 115 u_short vector; /* interrupt vector */ 116 u_short asic_addr; /* ASIC I/O bus address */ 117 u_short nic_addr; /* NIC (DS8390) I/O bus address */ 118 119 caddr_t smem_start; /* shared memory start address */ 120 caddr_t smem_end; /* shared memory end address */ 121 u_long smem_size; /* total shared memory size */ 122 caddr_t smem_ring; /* start of RX ring-buffer (in smem) */ 123 124 caddr_t bpf; /* BPF "magic cookie" */ 125 126 u_char memwidth; /* width of access to card mem 8 or 16 */ 127 u_char xmit_busy; /* transmitter is busy */ 128 u_char txb_cnt; /* Number of transmit buffers */ 129 u_char txb_next; /* Pointer to next buffer ready to xmit */ 130 u_short txb_next_len; /* next xmit buffer length */ 131 u_char data_buffered; /* data has been buffered in interface memory */ 132 u_char tx_page_start; /* first page of TX buffer area */ 133 134 u_char rec_page_start; /* first page of RX ring-buffer */ 135 u_char rec_page_stop; /* last page of RX ring-buffer */ 136 u_char next_packet; /* pointer to next unread RX packet */ 137} ed_softc[NED]; 138 139int ed_attach(), ed_init(), edintr(), ed_ioctl(), ed_probe(), 140 ed_start(), ed_reset(), ed_watchdog(); 141 142static void ed_stop(); 143 144static inline void ed_rint(); 145static inline void ed_xmit(); 146static inline char *ed_ring_copy(); 147 148extern int ether_output(); 149 150struct isa_driver eddriver = { 151 ed_probe, 152 ed_attach, 153 "ed" 154}; 155/* 156 * Interrupt conversion table for WD/SMC ASIC 157 * (IRQ* are defined in icu.h) 158 */ 159static unsigned short ed_intr_mask[] = { 160 IRQ9, 161 IRQ3, 162 IRQ5, 163 IRQ7, 164 IRQ10, 165 IRQ11, 166 IRQ15, 167 IRQ4 168}; 169 170#define ETHER_MIN_LEN 64 171#define ETHER_MAX_LEN 1518 172#define ETHER_ADDR_LEN 6 173#define ETHER_HDR_SIZE 14 174 175/* 176 * Determine if the device is present 177 * 178 * on entry: 179 * a pointer to an isa_device struct 180 * on exit: 181 * NULL if device not found 182 * or # of i/o addresses used (if found) 183 */ 184int 185ed_probe(isa_dev) 186 struct isa_device *isa_dev; 187{ 188 struct ed_softc *sc = &ed_softc[isa_dev->id_unit]; 189 int i, x; 190 u_int memsize; 191 u_char iptr, memwidth, sum, tmp; 192 193 /* 194 * Setup initial i/o address for ASIC and NIC 195 */ 196 sc->asic_addr = isa_dev->id_iobase; 197 sc->vector = isa_dev->id_irq; 198 sc->smem_start = (caddr_t)isa_dev->id_maddr; 199 200 /* 201 * Attempt to do a checksum over the station address PROM. 202 * This is mapped differently on the WD80x3 and 3C503, so if 203 * it fails, it might be a 3C503. There is a problem with 204 * this, though: some clone WD boards don't pass the 205 * checksum test. Danpex boards for one. We need to do 206 * additional checking for this case. 207 */ 208 for (sum = 0, i = 0; i < 8; ++i) { 209 sum += inb(sc->asic_addr + ED_WD_PROM + i); 210 } 211 212 if (sum == ED_WD_ROM_CHECKSUM_TOTAL) { 213 goto type_WD80x3; 214 } else { 215 /* 216 * Do additional checking to make sure its a 3Com and 217 * not a broken WD clone 218 */ 219 goto type_3Com; 220 } 221 222type_WD80x3: 223 /* 224 * Looks like a WD/SMC board 225 */ 226 227 sc->vendor = ED_VENDOR_WD_SMC; 228 sc->type = inb(sc->asic_addr + ED_WD_CARD_ID); 229 230 sc->nic_addr = sc->asic_addr + ED_WD_NIC_OFFSET; 231 232 /* reset card to force it into a known state. */ 233 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_RST); 234 DELAY(100); 235 outb(sc->asic_addr + ED_WD_MSR, inb(sc->asic_addr + ED_WD_MSR) & ~ED_WD_MSR_RST); 236 /* wait in the case this card is reading it's EEROM */ 237 DELAY(5000); 238 239 /* 240 * Set initial values for width/size. 241 */ 242 switch (sc->type) { 243 case ED_TYPE_WD8003S: 244 sc->type_str = "WD8003S"; 245 memsize = 8192; 246 memwidth = 8; 247 break; 248 case ED_TYPE_WD8003E: 249 sc->type_str = "WD8003E"; 250 memsize = 8192; 251 memwidth = 8; 252 break; 253 case ED_TYPE_WD8013EBT: 254 sc->type_str = "WD8013EBT"; 255 memsize = 16384; 256 memwidth = 16; 257 break; 258 case ED_TYPE_WD8013EB: /* also WD8003EP */ 259 if (inb(sc->asic_addr + ED_WD_ICR) 260 & ED_WD_ICR_16BIT) { 261 memwidth = 16; 262 memsize = 16384; 263 sc->type_str = "WD8013EB"; 264 } else { 265 sc->type_str = "WD8003EP"; 266 memsize = 8192; 267 memwidth = 8; 268 } 269 break; 270 case ED_TYPE_WD8013EBP: 271 sc->type_str = "WD8013EBP"; 272 memsize = 16384; 273 memwidth = 16; 274 break; 275 case ED_TYPE_WD8013EPC: 276 sc->type_str = "WD8013EPC"; 277 memsize = 16384; 278 memwidth = 16; 279 break; 280 default: 281 sc->type_str = "unknown"; 282 memsize = 8192; 283 memwidth = 8; 284 break; 285 } 286 /* 287 * Make some adjustments to initial values depending on what is 288 * found in the ICR. 289 */ 290 if ((memwidth==16) 291 && ((inb(sc->asic_addr + ED_WD_ICR) & ED_WD_ICR_16BIT) == 0)) { 292 memwidth = 8; 293 memsize = 8192; 294 } 295 if (inb(sc->asic_addr + ED_WD_ICR) & ED_WD_ICR_MSZ) { 296 memsize = 32768; 297 } 298 299#if ED_DEBUG 300 printf("type=%s width=%d memsize=%d\n",sc->type_str,memwidth,memsize); 301 for (i=0; i<8; i++) 302 printf("%x -> %x\n", i, inb(sc->asic_addr + i)); 303#endif 304 /* 305 * Check 83C584 interrupt configuration register if this board has one 306 * XXX - we could also check the IO address register. But why 307 * bother...if we get past this, it *has* to be correct. 308 */ 309 if (sc->type & ED_WD_SOFTCONFIG) { 310 /* 311 * Assemble together the encoded interrupt number. 312 */ 313 iptr = (inb(isa_dev->id_iobase + ED_WD_ICR) & ED_WD_ICR_IR2) | 314 ((inb(isa_dev->id_iobase + ED_WD_IRR) & 315 (ED_WD_IRR_IR0 | ED_WD_IRR_IR1)) >> 5); 316 /* 317 * Translate it using translation table, and check for correctness. 318 */ 319 if (ed_intr_mask[iptr] != isa_dev->id_irq) { 320 printf("ed%d: kernel configured irq doesn't match board configured irq\n", 321 isa_dev->id_unit); 322 return(0); 323 } 324 /* 325 * Enable the interrupt. 326 */ 327 outb(isa_dev->id_iobase + ED_WD_IRR, 328 inb(isa_dev->id_iobase + ED_WD_IRR) | ED_WD_IRR_IEN); 329 } 330 331 sc->memwidth = memwidth; 332 /* 333 * allocate one xmit buffer if < 16k, two buffers otherwise 334 */ 335 if (memsize < 16384) { 336 sc->smem_ring = sc->smem_start + (ED_PAGE_SIZE * ED_TXBUF_SIZE); 337 sc->txb_cnt = 1; 338 sc->rec_page_start = ED_TXBUF_SIZE; 339 } else { 340 sc->smem_ring = sc->smem_start + (ED_PAGE_SIZE * ED_TXBUF_SIZE * 2); 341 sc->txb_cnt = 2; 342 sc->rec_page_start = ED_TXBUF_SIZE * 2; 343 } 344 sc->smem_size = memsize; 345 sc->smem_end = sc->smem_start + memsize; 346 sc->rec_page_stop = memsize / ED_PAGE_SIZE; 347 sc->tx_page_start = ED_WD_PAGE_OFFSET; 348 349 /* 350 * Get station address from on-board ROM 351 */ 352 for (i = 0; i < ETHER_ADDR_LEN; ++i) 353 sc->arpcom.ac_enaddr[i] = inb(sc->asic_addr + ED_WD_PROM + i); 354 355 /* 356 * Set address and enable interface shared memory. 357 */ 358 outb(sc->asic_addr + ED_WD_MSR, ((kvtop(sc->smem_start) >> 13) & 359 ED_WD_MSR_ADDR) | ED_WD_MSR_MENB); 360 361 /* 362 * Set upper address bits and 8/16 bit access to shared memory 363 */ 364 if (sc->type & ED_WD_SOFTCONFIG) { 365 if (memwidth == 8) { 366 outb(sc->asic_addr + ED_WD_LAAR, 367 ((kvtop(sc->smem_start) >> 19) & ED_WD_LAAR_ADDRHI)); 368 } else { 369 outb(sc->asic_addr + ED_WD_LAAR, 370 ED_WD_LAAR_L16EN | ED_WD_LAAR_M16EN | 371 ((kvtop(sc->smem_start) >> 19) & ED_WD_LAAR_ADDRHI)); 372 } 373 } 374 375 /* 376 * Now zero memory and verify that it is clear 377 */ 378 bzero(sc->smem_start, memsize); 379 380 for (i = 0; i < memsize; ++i) 381 if (sc->smem_start[i]) { 382 printf("ed%d: failed to clear shared memory at %x - check configuration\n", 383 isa_dev->id_unit, sc->smem_start + i); 384 385 /* 386 * Disable 16 bit access to shared memory 387 */ 388 if (memwidth == 16) 389 outb(sc->asic_addr + ED_WD_LAAR, 390 inb(sc->asic_addr + ED_WD_LAAR) 391 & ~ED_WD_LAAR_M16EN); 392 393 return(0); 394 } 395 396 /* 397 * Disable 16bit access to shared memory - we leave it disabled so 398 * that 1) machines reboot properly when the board is set 399 * 16 bit mode and there are conflicting 8bit devices/ROMS 400 * in the same 128k address space as this boards shared 401 * memory. and 2) so that other 8 bit devices with shared 402 * memory can be used in this 128k region, too. 403 */ 404 if (memwidth == 16) 405 outb(sc->asic_addr + ED_WD_LAAR, inb(sc->asic_addr + ED_WD_LAAR) 406 & ~ED_WD_LAAR_M16EN); 407 408 isa_dev->id_msize = memsize; 409 return (ED_WD_IO_PORTS); 410 411type_3Com: 412 /* 413 * Looks like a 3Com board 414 */ 415 416 sc->vendor = ED_VENDOR_3COM; 417 sc->asic_addr = isa_dev->id_iobase + ED_3COM_ASIC_OFFSET; 418 sc->nic_addr = isa_dev->id_iobase + ED_3COM_NIC_OFFSET; 419 420 sc->type_str = "3c503"; 421 422 memsize = 8192; 423 424 /* 425 * Verify that the kernel configured I/O address matches the board 426 * configured address 427 */ 428 switch (inb(sc->asic_addr + ED_3COM_BCFR)) { 429 case ED_3COM_BCFR_300: 430 if (isa_dev->id_iobase != 0x300) 431 return(0); 432 break; 433 case ED_3COM_BCFR_310: 434 if (isa_dev->id_iobase != 0x310) 435 return(0); 436 break; 437 case ED_3COM_BCFR_330: 438 if (isa_dev->id_iobase != 0x330) 439 return(0); 440 break; 441 case ED_3COM_BCFR_350: 442 if (isa_dev->id_iobase != 0x350) 443 return(0); 444 break; 445 case ED_3COM_BCFR_250: 446 if (isa_dev->id_iobase != 0x250) 447 return(0); 448 break; 449 case ED_3COM_BCFR_280: 450 if (isa_dev->id_iobase != 0x280) 451 return(0); 452 break; 453 case ED_3COM_BCFR_2A0: 454 if (isa_dev->id_iobase != 0x2a0) 455 return(0); 456 break; 457 case ED_3COM_BCFR_2E0: 458 if (isa_dev->id_iobase != 0x2e0) 459 return(0); 460 break; 461 default: 462 return(0); 463 } 464 465 /* 466 * Verify that the kernel shared memory address matches the 467 * board configured address. 468 */ 469 switch (inb(sc->asic_addr + ED_3COM_PCFR)) { 470 case ED_3COM_PCFR_DC000: 471 if (kvtop(isa_dev->id_maddr) != 0xdc000) 472 return(0); 473 break; 474 case ED_3COM_PCFR_D8000: 475 if (kvtop(isa_dev->id_maddr) != 0xd8000) 476 return(0); 477 break; 478 case ED_3COM_PCFR_CC000: 479 if (kvtop(isa_dev->id_maddr) != 0xcc000) 480 return(0); 481 break; 482 case ED_3COM_PCFR_C8000: 483 if (kvtop(isa_dev->id_maddr) != 0xc8000) 484 return(0); 485 break; 486 default: 487 return(0); 488 } 489 490 /* 491 * Reset NIC and ASIC 492 */ 493 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_RST); 494 /* 495 * Wait for a while, then un-reset it 496 */ 497 DELAY(5000); 498 outb(sc->asic_addr + ED_3COM_CR, 0); 499 500 /* 501 * Wait a bit for the NIC to recover from the reset 502 */ 503 DELAY(5000); 504 505 /* 506 * The 3Com ASIC defaults to rather strange settings for the CR after 507 * a reset - it's important to set it so that the NIC I/O 508 * registers are mapped. The above setting of it to '0' only 509 * resets the reset condition - the CR is *not* set to zeros. 510 */ 511 outb(sc->asic_addr + ED_3COM_CR, 0); 512 513 /* 514 * Determine if this is an 8bit or 16bit board 515 */ 516 517 /* 518 * select page 0 registers 519 */ 520 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_STP); 521 522 /* 523 * Attempt to clear WTS bit. If it doesn't clear, then this is a 524 * 16bit board. 525 */ 526 outb(sc->nic_addr + ED_P0_DCR, 0); 527 528 /* 529 * select page 2 registers 530 */ 531 outb(sc->nic_addr + ED_P0_CR, ED_CR_PAGE_2|ED_CR_RD2|ED_CR_STP); 532 533 /* 534 * The 3c503 forces the WTS bit to a one if this is a 16bit board 535 */ 536 if (inb(sc->nic_addr + ED_P2_DCR) & ED_DCR_WTS) 537 memwidth = 16; 538 else 539 memwidth = 8; 540 541 /* 542 * select page 0 registers 543 */ 544 outb(sc->nic_addr + ED_P2_CR, ED_CR_RD2|ED_CR_STP); 545 546 sc->txb_cnt = 1; 547 548 sc->tx_page_start = ED_3COM_PAGE_OFFSET; 549 sc->rec_page_start = ED_TXBUF_SIZE + ED_3COM_PAGE_OFFSET; 550 sc->rec_page_stop = memsize / ED_PAGE_SIZE + ED_3COM_PAGE_OFFSET; 551 552 sc->smem_size = memsize; 553 sc->smem_end = sc->smem_start + memsize; 554 sc->smem_ring = sc->smem_start + (ED_PAGE_SIZE * ED_TXBUF_SIZE); 555 556 sc->memwidth = memwidth; 557 558 /* 559 * Initialize GA page start/stop registers. Probably only needed 560 * if doing DMA, but what the hell. 561 */ 562 outb(sc->asic_addr + ED_3COM_PSTR, sc->rec_page_start); 563 outb(sc->asic_addr + ED_3COM_PSPR, sc->rec_page_stop); 564 565 /* 566 * Set IRQ. 3c503 only allows a choice of irq 2-5. 567 */ 568 switch (isa_dev->id_irq) { 569 case IRQ2: 570 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ2); 571 break; 572 case IRQ3: 573 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ3); 574 break; 575 case IRQ4: 576 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ4); 577 break; 578 case IRQ5: 579 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ5); 580 break; 581 default: 582 printf("ed%d: Invalid irq configuration\n", isa_dev->id_unit); 583 return(0); 584 } 585 586 /* 587 * Initialize GA configuration register. Set bank and enable smem. 588 */ 589 outb(sc->asic_addr + ED_3COM_GACFR, ED_3COM_GACFR_RSEL | 590 ED_3COM_GACFR_MBS0); 591 592 /* 593 * Initialize "Vector Pointer" registers. These gawd-awful things 594 * are compared to 20 bits of the address on ISA, and if they 595 * match, the shared memory is disabled. We set them to 596 * 0xffff0...allegedly the reset vector. 597 */ 598 outb(sc->asic_addr + ED_3COM_VPTR2, 0xff); 599 outb(sc->asic_addr + ED_3COM_VPTR1, 0xff); 600 outb(sc->asic_addr + ED_3COM_VPTR0, 0x00); 601 602 /* 603 * Get station address from on-board ROM 604 */ 605 /* 606 * First, map ethernet address PROM over the top of where the NIC 607 * registers normally appear. 608 */ 609 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_EALO); 610 611 for (i = 0; i < ETHER_ADDR_LEN; ++i) 612 sc->arpcom.ac_enaddr[i] = inb(sc->nic_addr + i); 613 614 /* 615 * Unmap PROM - select NIC registers. Tranceiver remains disabled at 616 * this point. It's enabled in ed_init so that the attach code 617 * is given a chance to set the default based on a compile-time 618 * config option 619 */ 620 outb(sc->asic_addr + ED_3COM_CR, 0); 621 622#if 0 623printf("Starting write\n"); 624for (i = 0; i < 8192; ++i) 625 bzerow(sc->smem_start, 8192); 626printf("Done.\n"); 627#endif 628#if 0 629{ char test_buf[1024]; 630printf("starting write\n"); 631 for (i = 0; i < 8*8192; ++i) 632 bcopy(test_buf, sc->smem_start, 1024); 633printf("starting read\n"); 634 for (i = 0; i < 8*8192; ++i) 635 bcopy(sc->smem_start, test_buf, 1024); 636printf("done.\n"); 637} 638#endif 639 640 /* 641 * Zero memory and verify that it is clear 642 */ 643 bzero(sc->smem_start, memsize); 644 645 for (i = 0; i < memsize; ++i) 646 if (sc->smem_start[i]) { 647 printf("ed%d: failed to clear shared memory at %x - check configuration\n", 648 isa_dev->id_unit, sc->smem_start + i); 649 return(0); 650 } 651 652 isa_dev->id_msize = memsize; 653 return(ED_3COM_IO_PORTS); 654} 655 656/* 657 * Install interface into kernel networking data structures 658 */ 659int 660ed_attach(isa_dev) 661 struct isa_device *isa_dev; 662{ 663 struct ed_softc *sc = &ed_softc[isa_dev->id_unit]; 664 struct ifnet *ifp = &sc->arpcom.ac_if; 665 struct ifaddr *ifa; 666 struct sockaddr_dl *sdl; 667 668 /* 669 * Set interface to stopped condition (reset) 670 */ 671 ed_stop(isa_dev->id_unit); 672 673 /* 674 * Initialize ifnet structure 675 */ 676 ifp->if_unit = isa_dev->id_unit; 677 ifp->if_name = "ed" ; 678 ifp->if_mtu = ETHERMTU; 679 ifp->if_init = ed_init; 680 ifp->if_output = ether_output; 681 ifp->if_start = ed_start; 682 ifp->if_ioctl = ed_ioctl; 683 ifp->if_reset = ed_reset; 684 ifp->if_watchdog = ed_watchdog; 685 686 /* 687 * Set default state for LLC0 flag (used to disable the tranceiver 688 * for AUI operation), based on compile-time config option. 689 */ 690 if (isa_dev->id_flags & ED_FLAGS_DISABLE_TRANCEIVER) 691 ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS 692 | IFF_LLC0); 693 else 694 ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS); 695 696 /* 697 * Attach the interface 698 */ 699 if_attach(ifp); 700 701#if NBPFILTER > 0 702 bpfattach(&sc->bpf, ifp, DLT_EN10MB, sizeof(struct ether_header)); 703#endif 704 705 /* 706 * Search down the ifa address list looking for the AF_LINK type entry 707 */ 708 ifa = ifp->if_addrlist; 709 while ((ifa != 0) && (ifa->ifa_addr != 0) && 710 (ifa->ifa_addr->sa_family != AF_LINK)) 711 ifa = ifa->ifa_next; 712 /* 713 * If we find an AF_LINK type entry we fill in the hardware address. 714 * This is useful for netstat(1) to keep track of which interface 715 * is which. 716 */ 717 if ((ifa != 0) && (ifa->ifa_addr != 0)) { 718 /* 719 * Fill in the link-level address for this interface 720 */ 721 sdl = (struct sockaddr_dl *)ifa->ifa_addr; 722 sdl->sdl_type = IFT_ETHER; 723 sdl->sdl_alen = ETHER_ADDR_LEN; 724 sdl->sdl_slen = 0; 725 bcopy(sc->arpcom.ac_enaddr, LLADDR(sdl), ETHER_ADDR_LEN); 726 } 727 728 /* 729 * Print additional info when attached 730 */ 731 printf("ed%d: address %s, type %s (%dbit) %s\n", isa_dev->id_unit, 732 ether_sprintf(sc->arpcom.ac_enaddr), sc->type_str, 733 sc->memwidth, ((sc->vendor == ED_VENDOR_3COM) && 734 (ifp->if_flags & IFF_LLC0)) ? "tranceiver disabled" : ""); 735} 736 737/* 738 * Reset interface. 739 */ 740int 741ed_reset(unit) 742 int unit; 743{ 744 int s; 745 746 s = splnet(); 747 748 /* 749 * Stop interface and re-initialize. 750 */ 751 ed_stop(unit); 752 ed_init(unit); 753 754 s = splx(s); 755} 756 757/* 758 * Take interface offline. 759 */ 760void 761ed_stop(unit) 762 int unit; 763{ 764 struct ed_softc *sc = &ed_softc[unit]; 765 int n = 5000; 766 767 /* 768 * Stop everything on the interface, and select page 0 registers. 769 */ 770 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_STP); 771 772 /* 773 * Wait for interface to enter stopped state, but limit # of checks 774 * to 'n' (about 5ms). It shouldn't even take 5us on modern 775 * DS8390's, but just in case it's an old one. 776 */ 777 while ((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RST) == 0) { 778 if (--n == 0) 779 break; 780 } 781} 782 783/* 784 * Device timeout/watchdog routine. Entered if the device neglects to 785 * generate an interrupt after a transmit has been started on it. 786 */ 787int 788ed_watchdog(unit) 789 int unit; 790{ 791 log(LOG_ERR, "ed%d: device timeout\n", unit); 792 793 ed_reset(unit); 794} 795 796/* 797 * Initialize device. 798 */ 799ed_init(unit) 800 int unit; 801{ 802 struct ed_softc *sc = &ed_softc[unit]; 803 struct ifnet *ifp = &sc->arpcom.ac_if; 804 int i, s; 805 u_char command; 806 807 808 /* address not known */ 809 if (ifp->if_addrlist == (struct ifaddr *)0) return; 810 811 /* 812 * Initialize the NIC in the exact order outlined in the NS manual. 813 * This init procedure is "mandatory"...don't change what or when 814 * things happen. 815 */ 816 s = splnet(); 817 818 /* reset transmitter flags */ 819 sc->data_buffered = 0; 820 sc->xmit_busy = 0; 821 sc->arpcom.ac_if.if_timer = 0; 822 823 sc->txb_next = 0; 824 825 /* This variable is used below - don't move this assignment */ 826 sc->next_packet = sc->rec_page_start + 1; 827 828 /* 829 * Set interface for page 0, Remote DMA complete, Stopped 830 */ 831 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_STP); 832 833 if (sc->memwidth == 16) { 834 /* 835 * Set FIFO threshold to 8, No auto-init Remote DMA, 836 * byte order=80x86, word-wide DMA xfers 837 */ 838 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1|ED_DCR_WTS); 839 } else { 840 /* 841 * Same as above, but byte-wide DMA xfers 842 */ 843 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1); 844 } 845 846 /* 847 * Clear Remote Byte Count Registers 848 */ 849 outb(sc->nic_addr + ED_P0_RBCR0, 0); 850 outb(sc->nic_addr + ED_P0_RBCR1, 0); 851 852 /* 853 * Enable reception of broadcast packets 854 */ 855 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_AB); 856 857 /* 858 * Place NIC in internal loopback mode 859 */ 860 outb(sc->nic_addr + ED_P0_TCR, ED_TCR_LB0); 861 862 /* 863 * Initialize transmit/receive (ring-buffer) Page Start 864 */ 865 outb(sc->nic_addr + ED_P0_TPSR, sc->tx_page_start); 866 outb(sc->nic_addr + ED_P0_PSTART, sc->rec_page_start); 867 868 /* 869 * Initialize Receiver (ring-buffer) Page Stop and Boundry 870 */ 871 outb(sc->nic_addr + ED_P0_PSTOP, sc->rec_page_stop); 872 outb(sc->nic_addr + ED_P0_BNRY, sc->rec_page_start); 873 874 /* 875 * Clear all interrupts. A '1' in each bit position clears the 876 * corresponding flag. 877 */ 878 outb(sc->nic_addr + ED_P0_ISR, 0xff); 879 880 /* 881 * Enable the following interrupts: receive/transmit complete, 882 * receive/transmit error, and Receiver OverWrite. 883 * 884 * Counter overflow and Remote DMA complete are *not* enabled. 885 */ 886 outb(sc->nic_addr + ED_P0_IMR, 887 ED_IMR_PRXE|ED_IMR_PTXE|ED_IMR_RXEE|ED_IMR_TXEE|ED_IMR_OVWE); 888 889 /* 890 * Program Command Register for page 1 891 */ 892 outb(sc->nic_addr + ED_P0_CR, ED_CR_PAGE_1|ED_CR_RD2|ED_CR_STP); 893 894 /* 895 * Copy out our station address 896 */ 897 for (i = 0; i < ETHER_ADDR_LEN; ++i) 898 outb(sc->nic_addr + ED_P1_PAR0 + i, sc->arpcom.ac_enaddr[i]); 899 900#if NBPFILTER > 0 901 /* 902 * Initialize multicast address hashing registers to accept 903 * all multicasts (only used when in promiscuous mode) 904 */ 905 for (i = 0; i < 8; ++i) 906 outb(sc->nic_addr + ED_P1_MAR0 + i, 0xff); 907#endif 908 909 /* 910 * Set Current Page pointer to next_packet (initialized above) 911 */ 912 outb(sc->nic_addr + ED_P1_CURR, sc->next_packet); 913 914 /* 915 * Set Command Register for page 0, Remote DMA complete, 916 * and interface Start. 917 */ 918 outb(sc->nic_addr + ED_P1_CR, ED_CR_RD2|ED_CR_STA); 919 920 /* 921 * Take interface out of loopback 922 */ 923 outb(sc->nic_addr + ED_P0_TCR, 0); 924 925 /* 926 * If this is a 3Com board, the tranceiver must be software enabled 927 * (there is no settable hardware default). 928 */ 929 if ((sc->vendor == ED_VENDOR_3COM) && (ifp->if_flags & IFF_LLC0)) { 930 outb(sc->asic_addr + ED_3COM_CR, 0); 931 } else { 932 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL); 933 } 934 935 /* 936 * Set 'running' flag, and clear output active flag. 937 */ 938 ifp->if_flags |= IFF_RUNNING; 939 ifp->if_flags &= ~IFF_OACTIVE; 940 941 /* 942 * ...and attempt to start output 943 */ 944 ed_start(ifp); 945 946 (void) splx(s); 947} 948 949/* 950 * This routine actually starts the transmission on the interface 951 */ 952static inline void ed_xmit(ifp) 953 struct ifnet *ifp; 954{ 955 struct ed_softc *sc = &ed_softc[ifp->if_unit]; 956 u_short len = sc->txb_next_len; 957 958 /* 959 * Set NIC for page 0 register access 960 */ 961 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_STA); 962 963 /* 964 * Set TX buffer start page 965 */ 966 outb(sc->nic_addr + ED_P0_TPSR, sc->tx_page_start + 967 sc->txb_next * ED_TXBUF_SIZE); 968 969 /* 970 * Set TX length 971 */ 972 outb(sc->nic_addr + ED_P0_TBCR0, len & 0xff); 973 outb(sc->nic_addr + ED_P0_TBCR1, len >> 8); 974 975 /* 976 * Set page 0, Remote DMA complete, Transmit Packet, and *Start* 977 */ 978 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_TXP|ED_CR_STA); 979 980 sc->xmit_busy = 1; 981 sc->data_buffered = 0; 982 983 /* 984 * Switch buffers if we are doing double-buffered transmits 985 */ 986 if ((sc->txb_next == 0) && (sc->txb_cnt > 1)) 987 sc->txb_next = 1; 988 else 989 sc->txb_next = 0; 990 991 /* 992 * Set a timer just in case we never hear from the board again 993 */ 994 ifp->if_timer = 2; 995} 996 997/* 998 * Start output on interface. 999 * We make two assumptions here: 1000 * 1) that the current priority is set to splnet _before_ this code 1001 * is called *and* is returned to the appropriate priority after 1002 * return 1003 * 2) that the IFF_OACTIVE flag is checked before this code is called 1004 * (i.e. that the output part of the interface is idle) 1005 */ 1006int 1007ed_start(ifp) 1008 struct ifnet *ifp; 1009{ 1010 struct ed_softc *sc = &ed_softc[ifp->if_unit]; 1011 struct mbuf *m0, *m; 1012 caddr_t buffer; 1013 int len; 1014 u_char laar_tmp; 1015 1016outloop: 1017 /* 1018 * See if there is room to send more data (i.e. one or both of the 1019 * buffers is empty). 1020 */ 1021 if (sc->data_buffered) 1022 if (sc->xmit_busy) { 1023 /* 1024 * No room. Indicate this to the outside world 1025 * and exit. 1026 */ 1027 ifp->if_flags |= IFF_OACTIVE; 1028 return; 1029 } else { 1030 /* 1031 * Data is buffered, but we're not transmitting, so 1032 * start the xmit on the buffered data. 1033 * Note that ed_xmit() resets the data_buffered flag 1034 * before returning. 1035 */ 1036 ed_xmit(ifp); 1037 } 1038 1039 IF_DEQUEUE(&sc->arpcom.ac_if.if_snd, m); 1040 if (m == 0) { 1041 /* 1042 * The following isn't pretty; we are using the !OACTIVE flag to 1043 * indicate to the outside world that we can accept an additional 1044 * packet rather than that the transmitter is _actually_ 1045 * active. Indeed, the transmitter may be active, but if we haven't 1046 * filled the secondary buffer with data then we still want to 1047 * accept more. 1048 * Note that it isn't necessary to test the data_buffered flag - 1049 * we wouldn't have tried to de-queue the packet in the first place 1050 * if it was set. 1051 */ 1052 ifp->if_flags &= ~IFF_OACTIVE; 1053 return; 1054 } 1055 1056 /* 1057 * Copy the mbuf chain into the transmit buffer 1058 */ 1059 /* 1060 * Enable 16bit access to shared memory on WD/SMC boards 1061 */ 1062 if (sc->memwidth == 16) 1063 if (sc->vendor == ED_VENDOR_WD_SMC) { 1064 laar_tmp = inb(sc->asic_addr + ED_WD_LAAR); 1065 outb(sc->asic_addr + ED_WD_LAAR, laar_tmp | ED_WD_LAAR_M16EN); 1066 } 1067 1068 buffer = sc->smem_start + (sc->txb_next * ED_TXBUF_SIZE * ED_PAGE_SIZE); 1069 len = 0; 1070 for (m0 = m; m != 0; m = m->m_next) { 1071 bcopy(mtod(m, caddr_t), buffer, m->m_len); 1072 buffer += m->m_len; 1073 len += m->m_len; 1074 } 1075 1076 /* 1077 * Restore previous shared mem access type 1078 */ 1079 if (sc->memwidth == 16) 1080 if (sc->vendor == ED_VENDOR_WD_SMC) { 1081 outb(sc->asic_addr + ED_WD_LAAR, laar_tmp); 1082 } 1083 1084 sc->txb_next_len = MAX(len, ETHER_MIN_LEN); 1085 1086 if (sc->txb_cnt > 1) 1087 /* 1088 * only set 'buffered' flag if doing multiple buffers 1089 */ 1090 sc->data_buffered = 1; 1091 1092 if (sc->xmit_busy == 0) 1093 ed_xmit(ifp); 1094 /* 1095 * If there is BPF support in the configuration, tap off here. 1096 * The following has support for converting trailer packets 1097 * back to normal. 1098 */ 1099#if NBPFILTER > 0 1100 if (sc->bpf) { 1101 u_short etype; 1102 int off, datasize, resid; 1103 struct ether_header *eh; 1104 struct trailer_header { 1105 u_short ether_type; 1106 u_short ether_residual; 1107 } trailer_header; 1108 char ether_packet[ETHER_MAX_LEN]; 1109 char *ep; 1110 1111 ep = ether_packet; 1112 1113 /* 1114 * We handle trailers below: 1115 * Copy ether header first, then residual data, 1116 * then data. Put all this in a temporary buffer 1117 * 'ether_packet' and send off to bpf. Since the 1118 * system has generated this packet, we assume 1119 * that all of the offsets in the packet are 1120 * correct; if they're not, the system will almost 1121 * certainly crash in m_copydata. 1122 * We make no assumptions about how the data is 1123 * arranged in the mbuf chain (i.e. how much 1124 * data is in each mbuf, if mbuf clusters are 1125 * used, etc.), which is why we use m_copydata 1126 * to get the ether header rather than assume 1127 * that this is located in the first mbuf. 1128 */ 1129 /* copy ether header */ 1130 m_copydata(m0, 0, sizeof(struct ether_header), ep); 1131 eh = (struct ether_header *) ep; 1132 ep += sizeof(struct ether_header); 1133 etype = ntohs(eh->ether_type); 1134 if (etype >= ETHERTYPE_TRAIL && 1135 etype < ETHERTYPE_TRAIL+ETHERTYPE_NTRAILER) { 1136 datasize = ((etype - ETHERTYPE_TRAIL) << 9); 1137 off = datasize + sizeof(struct ether_header); 1138 1139 /* copy trailer_header into a data structure */ 1140 m_copydata(m0, off, sizeof(struct trailer_header), 1141 &trailer_header.ether_type); 1142 1143 /* copy residual data */ 1144 m_copydata(m0, off+sizeof(struct trailer_header), 1145 resid = ntohs(trailer_header.ether_residual) - 1146 sizeof(struct trailer_header), ep); 1147 ep += resid; 1148 1149 /* copy data */ 1150 m_copydata(m0, sizeof(struct ether_header), 1151 datasize, ep); 1152 ep += datasize; 1153 1154 /* restore original ether packet type */ 1155 eh->ether_type = trailer_header.ether_type; 1156 1157 bpf_tap(sc->bpf, ether_packet, ep - ether_packet); 1158 } else 1159 bpf_mtap(sc->bpf, m0); 1160 } 1161#endif 1162 1163 m_freem(m0); 1164 1165 /* 1166 * If we are doing double-buffering, a buffer might be free to 1167 * fill with another packet, so loop back to the top. 1168 */ 1169 if (sc->txb_cnt > 1) 1170 goto outloop; 1171 else { 1172 ifp->if_flags |= IFF_OACTIVE; 1173 return; 1174 } 1175} 1176 1177/* 1178 * Ethernet interface receiver interrupt. 1179 */ 1180static inline void /* only called from one place, so may as well integrate */ 1181ed_rint(unit) 1182 int unit; 1183{ 1184 register struct ed_softc *sc = &ed_softc[unit]; 1185 u_char boundry, current; 1186 u_short len; 1187 struct ed_ring *packet_ptr; 1188 1189 /* 1190 * Set NIC to page 1 registers to get 'current' pointer 1191 */ 1192 outb(sc->nic_addr + ED_P0_CR, ED_CR_PAGE_1|ED_CR_RD2|ED_CR_STA); 1193 1194 /* 1195 * 'sc->next_packet' is the logical beginning of the ring-buffer - i.e. 1196 * it points to where new data has been buffered. The 'CURR' 1197 * (current) register points to the logical end of the ring-buffer 1198 * - i.e. it points to where additional new data will be added. 1199 * We loop here until the logical beginning equals the logical 1200 * end (or in other words, until the ring-buffer is empty). 1201 */ 1202 while (sc->next_packet != inb(sc->nic_addr + ED_P1_CURR)) { 1203 1204 /* get pointer to this buffer header structure */ 1205 packet_ptr = (struct ed_ring *)(sc->smem_ring + 1206 (sc->next_packet - sc->rec_page_start) * ED_PAGE_SIZE); 1207 1208 /* 1209 * The byte count includes the FCS - Frame Check Sequence (a 1210 * 32 bit CRC). 1211 */ 1212 len = packet_ptr->count; 1213 if ((len >= ETHER_MIN_LEN) && (len <= ETHER_MAX_LEN)) { 1214 /* 1215 * Go get packet. len - 4 removes CRC from length. 1216 * (packet_ptr + 1) points to data just after the packet ring 1217 * header (+4 bytes) 1218 */ 1219 ed_get_packet(sc, (caddr_t)(packet_ptr + 1), len - 4); 1220 ++sc->arpcom.ac_if.if_ipackets; 1221 } else { 1222 /* 1223 * Really BAD...probably indicates that the ring pointers 1224 * are corrupted. Also seen on early rev chips under 1225 * high load - the byte order of the length gets switched. 1226 */ 1227 log(LOG_ERR, 1228 "ed%d: shared memory corrupt - invalid packet length %d\n", 1229 unit, len); 1230 ed_reset(unit); 1231 return; 1232 } 1233 1234 /* 1235 * Update next packet pointer 1236 */ 1237 sc->next_packet = packet_ptr->next_packet; 1238 1239 /* 1240 * Update NIC boundry pointer - being careful to keep it 1241 * one buffer behind. (as recommended by NS databook) 1242 */ 1243 boundry = sc->next_packet - 1; 1244 if (boundry < sc->rec_page_start) 1245 boundry = sc->rec_page_stop - 1; 1246 1247 /* 1248 * Set NIC to page 0 registers to update boundry register 1249 */ 1250 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_STA); 1251 1252 outb(sc->nic_addr + ED_P0_BNRY, boundry); 1253 1254 /* 1255 * Set NIC to page 1 registers before looping to top (prepare to 1256 * get 'CURR' current pointer) 1257 */ 1258 outb(sc->nic_addr + ED_P0_CR, ED_CR_PAGE_1|ED_CR_RD2|ED_CR_STA); 1259 } 1260} 1261 1262/* 1263 * Ethernet interface interrupt processor 1264 */ 1265int 1266edintr(unit) 1267 int unit; 1268{ 1269 struct ed_softc *sc = &ed_softc[unit]; 1270 u_char isr; 1271 1272 /* 1273 * Set NIC to page 0 registers 1274 */ 1275 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_STA); 1276 1277 /* 1278 * loop until there are no more new interrupts 1279 */ 1280 while (isr = inb(sc->nic_addr + ED_P0_ISR)) { 1281 1282 /* 1283 * reset all the bits that we are 'acknowleging' 1284 * by writing a '1' to each bit position that was set 1285 * (writing a '1' *clears* the bit) 1286 */ 1287 outb(sc->nic_addr + ED_P0_ISR, isr); 1288 1289 /* 1290 * Transmit error. If a TX completed with an error, we end up 1291 * throwing the packet away. Really the only error that is 1292 * possible is excessive collisions, and in this case it is 1293 * best to allow the automatic mechanisms of TCP to backoff 1294 * the flow. Of course, with UDP we're screwed, but this is 1295 * expected when a network is heavily loaded. 1296 */ 1297 if (isr & ED_ISR_TXE) { 1298 u_char tsr = inb(sc->nic_addr + ED_P0_TSR); 1299 u_char ncr = inb(sc->nic_addr + ED_P0_NCR); 1300 1301 /* 1302 * Excessive collisions (16) 1303 */ 1304 if ((tsr & ED_TSR_ABT) && (ncr == 0)) { 1305 /* 1306 * When collisions total 16, the P0_NCR will 1307 * indicate 0, and the TSR_ABT is set. 1308 */ 1309 sc->arpcom.ac_if.if_collisions += 16; 1310 } else 1311 sc->arpcom.ac_if.if_collisions += ncr; 1312 1313 /* 1314 * update output errors counter 1315 */ 1316 ++sc->arpcom.ac_if.if_oerrors; 1317 1318 /* 1319 * reset tx busy and output active flags 1320 */ 1321 sc->xmit_busy = 0; 1322 sc->arpcom.ac_if.if_flags &= ~IFF_OACTIVE; 1323 1324 /* 1325 * clear watchdog timer 1326 */ 1327 sc->arpcom.ac_if.if_timer = 0; 1328 } 1329 1330 1331 /* 1332 * Receiver Error. One or more of: CRC error, frame alignment error 1333 * FIFO overrun, or missed packet. 1334 */ 1335 if (isr & ED_ISR_RXE) { 1336 ++sc->arpcom.ac_if.if_ierrors; 1337#ifdef ED_DEBUG 1338 printf("ed%d: receive error %x\n", unit, 1339 inb(sc->nic_addr + ED_P0_RSR)); 1340#endif 1341 } 1342 1343 /* 1344 * Overwrite warning. In order to make sure that a lockup 1345 * of the local DMA hasn't occurred, we reset and 1346 * re-init the NIC. The NSC manual suggests only a 1347 * partial reset/re-init is necessary - but some 1348 * chips seem to want more. The DMA lockup has been 1349 * seen only with early rev chips - Methinks this 1350 * bug was fixed in later revs. -DG 1351 */ 1352 if (isr & ED_ISR_OVW) { 1353 ++sc->arpcom.ac_if.if_ierrors; 1354 log(LOG_WARNING, 1355 "ed%d: warning - receiver ring buffer overrun\n", 1356 unit); 1357 /* 1358 * Stop/reset/re-init NIC 1359 */ 1360 ed_reset(unit); 1361 } 1362 1363 /* 1364 * Transmission completed normally. 1365 */ 1366 if (isr & ED_ISR_PTX) { 1367 1368 /* 1369 * reset tx busy and output active flags 1370 */ 1371 sc->xmit_busy = 0; 1372 sc->arpcom.ac_if.if_flags &= ~IFF_OACTIVE; 1373 1374 /* 1375 * clear watchdog timer 1376 */ 1377 sc->arpcom.ac_if.if_timer = 0; 1378 1379 /* 1380 * Update total number of successfully transmitted 1381 * packets. 1382 */ 1383 ++sc->arpcom.ac_if.if_opackets; 1384 1385 /* 1386 * Add in total number of collisions on last 1387 * transmission. 1388 */ 1389 sc->arpcom.ac_if.if_collisions += inb(sc->nic_addr + 1390 ED_P0_TBCR0); 1391 } 1392 1393 /* 1394 * Receive Completion. Go and get the packet. 1395 * XXX - Doing this on an error is dubious because there 1396 * shouldn't be any data to get (we've configured the 1397 * interface to not accept packets with errors). 1398 */ 1399 if (isr & (ED_ISR_PRX|ED_ISR_RXE)) { 1400 /* 1401 * Enable access to shared memory on WD/SMC boards 1402 */ 1403 if (sc->memwidth == 16) 1404 if (sc->vendor == ED_VENDOR_WD_SMC) { 1405 outb(sc->asic_addr + ED_WD_LAAR, 1406 inb(sc->asic_addr + ED_WD_LAAR) 1407 | ED_WD_LAAR_M16EN); 1408 } 1409 1410 ed_rint (unit); 1411 1412 /* 1413 * Disable access to shared memory 1414 */ 1415 if (sc->memwidth == 16) 1416 if (sc->vendor == ED_VENDOR_WD_SMC) { 1417 outb(sc->asic_addr + ED_WD_LAAR, 1418 inb(sc->asic_addr + ED_WD_LAAR) 1419 & ~ED_WD_LAAR_M16EN); 1420 } 1421 } 1422 1423 /* 1424 * If it looks like the transmitter can take more data, 1425 * attempt to start output on the interface. If data is 1426 * already buffered and ready to go, send it first. 1427 */ 1428 if ((sc->arpcom.ac_if.if_flags & IFF_OACTIVE) == 0) { 1429 if (sc->data_buffered) 1430 ed_xmit(&sc->arpcom.ac_if); 1431 ed_start(&sc->arpcom.ac_if); 1432 } 1433 1434 /* 1435 * return NIC CR to standard state before looping back 1436 * to top: page 0, remote DMA complete, start 1437 * (toggling the TXP bit off, even if was just set in the 1438 * transmit routine, is *okay* - it is 'edge' triggered 1439 * from low to high) 1440 */ 1441 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_STA); 1442 } 1443} 1444 1445/* 1446 * Process an ioctl request. This code needs some work - it looks 1447 * pretty ugly. 1448 */ 1449int 1450ed_ioctl(ifp, command, data) 1451 register struct ifnet *ifp; 1452 int command; 1453 caddr_t data; 1454{ 1455 register struct ifaddr *ifa = (struct ifaddr *)data; 1456 struct ed_softc *sc = &ed_softc[ifp->if_unit]; 1457 struct ifreq *ifr = (struct ifreq *)data; 1458 int s, error = 0; 1459 1460 s = splnet(); 1461 1462 switch (command) { 1463 1464 case SIOCSIFADDR: 1465 ifp->if_flags |= IFF_UP; 1466 1467 switch (ifa->ifa_addr->sa_family) { 1468#ifdef INET 1469 case AF_INET: 1470 ed_init(ifp->if_unit); /* before arpwhohas */ 1471 /* 1472 * See if another station has *our* IP address. 1473 * i.e.: There is an address conflict! If a 1474 * conflict exists, a message is sent to the 1475 * console. 1476 */ 1477 ((struct arpcom *)ifp)->ac_ipaddr = 1478 IA_SIN(ifa)->sin_addr; 1479 arpwhohas((struct arpcom *)ifp, &IA_SIN(ifa)->sin_addr); 1480 break; 1481#endif 1482#ifdef NS 1483 /* 1484 * XXX - This code is probably wrong 1485 */ 1486 case AF_NS: 1487 { 1488 register struct ns_addr *ina = &(IA_SNS(ifa)->sns_addr); 1489 1490 if (ns_nullhost(*ina)) 1491 ina->x_host = 1492 *(union ns_host *)(sc->arpcom.ac_enaddr); 1493 else { 1494 /* 1495 * 1496 */ 1497 bcopy((caddr_t)ina->x_host.c_host, 1498 (caddr_t)sc->arpcom.ac_enaddr, 1499 sizeof(sc->arpcom.ac_enaddr)); 1500 } 1501 /* 1502 * Set new address 1503 */ 1504 ed_init(ifp->if_unit); 1505 break; 1506 } 1507#endif 1508 default: 1509 ed_init(ifp->if_unit); 1510 break; 1511 } 1512 break; 1513 1514 case SIOCSIFFLAGS: 1515 /* 1516 * If interface is marked down and it is running, then stop it 1517 */ 1518 if (((ifp->if_flags & IFF_UP) == 0) && 1519 (ifp->if_flags & IFF_RUNNING)) { 1520 ed_stop(ifp->if_unit); 1521 ifp->if_flags &= ~IFF_RUNNING; 1522 } else { 1523 /* 1524 * If interface is marked up and it is stopped, then start it 1525 */ 1526 if ((ifp->if_flags & IFF_UP) && 1527 ((ifp->if_flags & IFF_RUNNING) == 0)) 1528 ed_init(ifp->if_unit); 1529 } 1530#if NBPFILTER > 0 1531 if (ifp->if_flags & IFF_PROMISC) { 1532 /* 1533 * Set promiscuous mode on interface. 1534 * XXX - for multicasts to work, we would need to 1535 * write 1's in all bits of multicast 1536 * hashing array. For now we assume that 1537 * this was done in ed_init(). 1538 */ 1539 outb(sc->nic_addr + ED_P0_RCR, 1540 ED_RCR_PRO|ED_RCR_AM|ED_RCR_AB); 1541 } else { 1542 /* 1543 * XXX - for multicasts to work, we would need to 1544 * rewrite the multicast hashing array with the 1545 * proper hash (would have been destroyed above). 1546 */ 1547 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_AB); 1548 } 1549#endif 1550 /* 1551 * An unfortunate hack to provide the (required) software control 1552 * of the tranceiver for 3Com boards. The LLC0 flag disables 1553 * the tranceiver if set. 1554 */ 1555 if ((sc->vendor == ED_VENDOR_3COM) && (ifp->if_flags & IFF_LLC0)) { 1556 outb(sc->asic_addr + ED_3COM_CR, 0); 1557 } else { 1558 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL); 1559 } 1560 1561 break; 1562 1563 default: 1564 error = EINVAL; 1565 } 1566 (void) splx(s); 1567 return (error); 1568} 1569 1570/* 1571 * Macro to calculate a new address within shared memory when given an offset 1572 * from an address, taking into account ring-wrap. 1573 */ 1574#define ringoffset(sc, start, off, type) \ 1575 ((type)( ((caddr_t)(start)+(off) >= (sc)->smem_end) ? \ 1576 (((caddr_t)(start)+(off))) - (sc)->smem_end \ 1577 + (sc)->smem_ring: \ 1578 ((caddr_t)(start)+(off)) )) 1579 1580/* 1581 * Retreive packet from shared memory and send to the next level up via 1582 * ether_input(). If there is a BPF listener, give a copy to BPF, too. 1583 */ 1584ed_get_packet(sc, buf, len) 1585 struct ed_softc *sc; 1586 char *buf; 1587 u_short len; 1588{ 1589 struct ether_header *eh; 1590 struct mbuf *m, *head, *ed_ring_to_mbuf(); 1591 u_short off; 1592 int resid; 1593 u_short etype; 1594 struct trailer_header { 1595 u_short trail_type; 1596 u_short trail_residual; 1597 } trailer_header; 1598 1599 /* Allocate a header mbuf */ 1600 MGETHDR(m, M_DONTWAIT, MT_DATA); 1601 if (m == 0) 1602 goto bad; 1603 m->m_pkthdr.rcvif = &sc->arpcom.ac_if; 1604 m->m_pkthdr.len = len; 1605 m->m_len = 0; 1606 head = m; 1607 1608 eh = (struct ether_header *)buf; 1609 1610 /* The following sillines is to make NFS happy */ 1611#define EROUND ((sizeof(struct ether_header) + 3) & ~3) 1612#define EOFF (EROUND - sizeof(struct ether_header)) 1613 1614 /* 1615 * The following assumes there is room for 1616 * the ether header in the header mbuf 1617 */ 1618 head->m_data += EOFF; 1619 bcopy(buf, mtod(head, caddr_t), sizeof(struct ether_header)); 1620 buf += sizeof(struct ether_header); 1621 head->m_len += sizeof(struct ether_header); 1622 len -= sizeof(struct ether_header); 1623 1624 etype = ntohs((u_short)eh->ether_type); 1625 1626 /* 1627 * Deal with trailer protocol: 1628 * If trailer protocol, calculate the datasize as 'off', 1629 * which is also the offset to the trailer header. 1630 * Set resid to the amount of packet data following the 1631 * trailer header. 1632 * Finally, copy residual data into mbuf chain. 1633 */ 1634 if (etype >= ETHERTYPE_TRAIL && 1635 etype < ETHERTYPE_TRAIL+ETHERTYPE_NTRAILER) { 1636 1637 off = (etype - ETHERTYPE_TRAIL) << 9; 1638 if ((off + sizeof(struct trailer_header)) > len) 1639 goto bad; /* insanity */ 1640 1641 eh->ether_type = *ringoffset(sc, buf, off, u_short *); 1642 resid = ntohs(*ringoffset(sc, buf, off+2, u_short *)); 1643 1644 if ((off + resid) > len) goto bad; /* insanity */ 1645 1646 resid -= sizeof(struct trailer_header); 1647 if (resid < 0) goto bad; /* insanity */ 1648 1649 m = ed_ring_to_mbuf(sc, ringoffset(sc, buf, off+4, char *), head, resid); 1650 if (m == 0) goto bad; 1651 1652 len = off; 1653 head->m_pkthdr.len -= 4; /* subtract trailer header */ 1654 } 1655 1656 /* 1657 * Pull packet off interface. Or if this was a trailer packet, 1658 * the data portion is appended. 1659 */ 1660 m = ed_ring_to_mbuf(sc, buf, m, len); 1661 if (m == 0) goto bad; 1662 1663#if NBPFILTER > 0 1664 /* 1665 * Check if there's a BPF listener on this interface. 1666 * If so, hand off the raw packet to bpf. 1667 */ 1668 if (sc->bpf) { 1669 bpf_mtap(sc->bpf, head); 1670 1671 /* 1672 * Note that the interface cannot be in promiscuous mode if 1673 * there are no BPF listeners. And if we are in promiscuous 1674 * mode, we have to check if this packet is really ours. 1675 * 1676 * XXX This test does not support multicasts. 1677 */ 1678 if ((sc->arpcom.ac_if.if_flags & IFF_PROMISC) && 1679 bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr, 1680 sizeof(eh->ether_dhost)) != 0 && 1681 bcmp(eh->ether_dhost, etherbroadcastaddr, 1682 sizeof(eh->ether_dhost)) != 0) { 1683 1684 m_freem(head); 1685 return; 1686 } 1687 } 1688#endif 1689 1690 /* 1691 * Fix up data start offset in mbuf to point past ether header 1692 */ 1693 m_adj(head, sizeof(struct ether_header)); 1694 1695 /* 1696 * silly ether_input routine needs 'type' in host byte order 1697 */ 1698 eh->ether_type = ntohs(eh->ether_type); 1699 1700 ether_input(&sc->arpcom.ac_if, eh, head); 1701 return; 1702 1703bad: if (head) 1704 m_freem(head); 1705 return; 1706} 1707 1708/* 1709 * Supporting routines 1710 */ 1711 1712/* 1713 * Given a source and destination address, copy 'amount' of a packet from 1714 * the ring buffer into a linear destination buffer. Takes into account 1715 * ring-wrap. 1716 */ 1717static inline char * 1718ed_ring_copy(sc,src,dst,amount) 1719 struct ed_softc *sc; 1720 char *src; 1721 char *dst; 1722 u_short amount; 1723{ 1724 u_short tmp_amount; 1725 1726 /* does copy wrap to lower addr in ring buffer? */ 1727 if (src + amount > sc->smem_end) { 1728 tmp_amount = sc->smem_end - src; 1729 bcopy(src,dst,tmp_amount); /* copy amount up to end of smem */ 1730 amount -= tmp_amount; 1731 src = sc->smem_ring; 1732 dst += tmp_amount; 1733 } 1734 1735 bcopy(src, dst, amount); 1736 1737 return(src + amount); 1738} 1739 1740/* 1741 * Copy data from receive buffer to end of mbuf chain 1742 * allocate additional mbufs as needed. return pointer 1743 * to last mbuf in chain. 1744 * sc = ed info (softc) 1745 * src = pointer in ed ring buffer 1746 * dst = pointer to last mbuf in mbuf chain to copy to 1747 * amount = amount of data to copy 1748 */ 1749struct mbuf * 1750ed_ring_to_mbuf(sc,src,dst,total_len) 1751 struct ed_softc *sc; 1752 char *src; 1753 struct mbuf *dst; 1754 u_short total_len; 1755{ 1756 register struct mbuf *m = dst; 1757 1758 while (total_len) { 1759 register u_short amount = min(total_len, M_TRAILINGSPACE(m)); 1760 1761 if (amount == 0) { /* no more data in this mbuf, alloc another */ 1762 /* 1763 * If there is enough data for an mbuf cluster, attempt 1764 * to allocate one of those, otherwise, a regular 1765 * mbuf will do. 1766 * Note that a regular mbuf is always required, even if 1767 * we get a cluster - getting a cluster does not 1768 * allocate any mbufs, and one is needed to assign 1769 * the cluster to. The mbuf that has a cluster 1770 * extension can not be used to contain data - only 1771 * the cluster can contain data. 1772 */ 1773 dst = m; 1774 MGET(m, M_DONTWAIT, MT_DATA); 1775 if (m == 0) 1776 return (0); 1777 1778 if (total_len >= MINCLSIZE) 1779 MCLGET(m, M_DONTWAIT); 1780 1781 m->m_len = 0; 1782 dst->m_next = m; 1783 amount = min(total_len, M_TRAILINGSPACE(m)); 1784 } 1785 1786 src = ed_ring_copy(sc, src, mtod(m, caddr_t) + m->m_len, amount); 1787 1788 m->m_len += amount; 1789 total_len -= amount; 1790 1791 } 1792 return (m); 1793} 1794#endif 1795 1796