if_ed.c revision 4558
1/* 2 * Device driver for National Semiconductor DS8390/WD83C690 based ethernet 3 * adapters. By David Greenman, 29-April-1993 4 * 5 * Copyright (C) 1993, David Greenman. This software may be used, modified, 6 * copied, distributed, and sold, in both source and binary form provided 7 * that the above copyright and these terms are retained. Under no 8 * circumstances is the author responsible for the proper functioning 9 * of this software, nor does the author assume any responsibility 10 * for damages incurred with its use. 11 * 12 * Currently supports the Western Digital/SMC 8003 and 8013 series, 13 * the SMC Elite Ultra (8216), the 3Com 3c503, the NE1000 and NE2000, 14 * and a variety of similar clones. 15 * 16 * $Id: if_ed.c,v 1.55 1994/11/13 07:17:46 davidg Exp $ 17 */ 18 19#include "ed.h" 20#include "bpfilter.h" 21 22#include <sys/param.h> 23#include <sys/systm.h> 24#include <sys/errno.h> 25#include <sys/ioctl.h> 26#include <sys/mbuf.h> 27#include <sys/socket.h> 28#include <sys/syslog.h> 29#include <sys/devconf.h> 30 31#include <net/if.h> 32#include <net/if_dl.h> 33#include <net/if_types.h> 34 35#ifdef INET 36#include <netinet/in.h> 37#include <netinet/in_systm.h> 38#include <netinet/in_var.h> 39#include <netinet/ip.h> 40#include <netinet/if_ether.h> 41#endif 42 43#ifdef NS 44#include <netns/ns.h> 45#include <netns/ns_if.h> 46#endif 47 48#if NBPFILTER > 0 49#include <net/bpf.h> 50#include <net/bpfdesc.h> 51#endif 52 53#include <i386/isa/isa.h> 54#include <i386/isa/isa_device.h> 55#include <i386/isa/icu.h> 56#include <i386/isa/if_edreg.h> 57 58/* For backwards compatibility */ 59#ifndef IFF_ALTPHYS 60#define IFF_ALTPHYS IFF_LINK0 61#endif 62 63/* 64 * ed_softc: per line info and status 65 */ 66struct ed_softc { 67 struct arpcom arpcom; /* ethernet common */ 68 69 char *type_str; /* pointer to type string */ 70 u_char vendor; /* interface vendor */ 71 u_char type; /* interface type code */ 72 73 u_short asic_addr; /* ASIC I/O bus address */ 74 u_short nic_addr; /* NIC (DS8390) I/O bus address */ 75 76/* 77 * The following 'proto' variable is part of a work-around for 8013EBT asics 78 * being write-only. It's sort of a prototype/shadow of the real thing. 79 */ 80 u_char wd_laar_proto; 81 u_char cr_proto; 82 u_char isa16bit; /* width of access to card 0=8 or 1=16 */ 83 int is790; /* set by the probe code if the card is 790 84 * based */ 85 86 caddr_t bpf; /* BPF "magic cookie" */ 87 caddr_t mem_start; /* NIC memory start address */ 88 caddr_t mem_end; /* NIC memory end address */ 89 u_long mem_size; /* total NIC memory size */ 90 caddr_t mem_ring; /* start of RX ring-buffer (in NIC mem) */ 91 92 u_char mem_shared; /* NIC memory is shared with host */ 93 u_char xmit_busy; /* transmitter is busy */ 94 u_char txb_cnt; /* number of transmit buffers */ 95 u_char txb_inuse; /* number of TX buffers currently in-use */ 96 97 u_char txb_new; /* pointer to where new buffer will be added */ 98 u_char txb_next_tx; /* pointer to next buffer ready to xmit */ 99 u_short txb_len[8]; /* buffered xmit buffer lengths */ 100 u_char tx_page_start; /* first page of TX buffer area */ 101 u_char rec_page_start; /* first page of RX ring-buffer */ 102 u_char rec_page_stop; /* last page of RX ring-buffer */ 103 u_char next_packet; /* pointer to next unread RX packet */ 104} ed_softc[NED]; 105 106int ed_attach(struct isa_device *); 107void ed_init(int); 108void edintr(int); 109int ed_ioctl(struct ifnet *, int, caddr_t); 110int ed_probe(struct isa_device *); 111void ed_start(struct ifnet *); 112void ed_reset(int); 113void ed_watchdog(int); 114int ed_probe_generic8390(struct ed_softc *); 115int ed_probe_WD80x3(struct isa_device *); 116int ed_probe_3Com(struct isa_device *); 117int ed_probe_Novell(struct isa_device *); 118 119void ds_getmcaf(); 120 121static void ed_get_packet(struct ed_softc *, char *, int /* u_short */ , int); 122static void ed_stop(int); 123 124static inline void ed_rint(); 125static inline void ed_xmit(); 126static inline char *ed_ring_copy(); 127 128void ed_pio_readmem(), ed_pio_writemem(); 129u_short ed_pio_write_mbufs(); 130 131void ed_setrcr(struct ifnet *, struct ed_softc *); 132 133struct isa_driver eddriver = { 134 ed_probe, 135 ed_attach, 136 "ed", 137 1 /* We are ultra sensitive */ 138}; 139 140/* 141 * Interrupt conversion table for WD/SMC ASIC 142 * (IRQ* are defined in icu.h) 143 */ 144static unsigned short ed_intr_mask[] = { 145 IRQ9, 146 IRQ3, 147 IRQ5, 148 IRQ7, 149 IRQ10, 150 IRQ11, 151 IRQ15, 152 IRQ4 153}; 154 155/* 156 * Interrupt conversion table for 585/790 Combo 157 */ 158static unsigned short ed_790_intr_mask[] = { 159 0, 160 IRQ9, 161 IRQ3, 162 IRQ5, 163 IRQ7, 164 IRQ10, 165 IRQ11, 166 IRQ15 167}; 168 169#define ETHER_MIN_LEN 64 170#define ETHER_MAX_LEN 1518 171#define ETHER_ADDR_LEN 6 172#define ETHER_HDR_SIZE 14 173 174static struct kern_devconf kdc_ed[NED] = { { 175 0, 0, 0, /* filled in by dev_attach */ 176 "ed", 0, { MDDT_ISA, 0, "net" }, 177 isa_generic_externalize, 0, 0, ISA_EXTERNALLEN, 178 &kdc_isa0, /* parent */ 179 0, /* parentdata */ 180 DC_BUSY, /* network interfaces are always ``open'' */ 181 "" /* description */ 182} }; 183 184static inline void 185ed_registerdev(struct isa_device *id, const char *descr) 186{ 187 if(id->id_unit) 188 kdc_ed[id->id_unit] = kdc_ed[0]; 189 kdc_ed[id->id_unit].kdc_unit = id->id_unit; 190 kdc_ed[id->id_unit].kdc_parentdata = id; 191 kdc_ed[id->id_unit].kdc_description = descr; 192 dev_attach(&kdc_ed[id->id_unit]); 193} 194 195/* 196 * Determine if the device is present 197 * 198 * on entry: 199 * a pointer to an isa_device struct 200 * on exit: 201 * NULL if device not found 202 * or # of i/o addresses used (if found) 203 */ 204int 205ed_probe(isa_dev) 206 struct isa_device *isa_dev; 207{ 208 int nports; 209 210 nports = ed_probe_WD80x3(isa_dev); 211 if (nports) 212 return (nports); 213 214 nports = ed_probe_3Com(isa_dev); 215 if (nports) 216 return (nports); 217 218 nports = ed_probe_Novell(isa_dev); 219 if (nports) 220 return (nports); 221 222 return (0); 223} 224 225/* 226 * Generic probe routine for testing for the existance of a DS8390. 227 * Must be called after the NIC has just been reset. This routine 228 * works by looking at certain register values that are gauranteed 229 * to be initialized a certain way after power-up or reset. Seems 230 * not to currently work on the 83C690. 231 * 232 * Specifically: 233 * 234 * Register reset bits set bits 235 * Command Register (CR) TXP, STA RD2, STP 236 * Interrupt Status (ISR) RST 237 * Interrupt Mask (IMR) All bits 238 * Data Control (DCR) LAS 239 * Transmit Config. (TCR) LB1, LB0 240 * 241 * We only look at the CR and ISR registers, however, because looking at 242 * the others would require changing register pages (which would be 243 * intrusive if this isn't an 8390). 244 * 245 * Return 1 if 8390 was found, 0 if not. 246 */ 247 248int 249ed_probe_generic8390(sc) 250 struct ed_softc *sc; 251{ 252 if ((inb(sc->nic_addr + ED_P0_CR) & 253 (ED_CR_RD2 | ED_CR_TXP | ED_CR_STA | ED_CR_STP)) != 254 (ED_CR_RD2 | ED_CR_STP)) 255 return (0); 256 if ((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RST) != ED_ISR_RST) 257 return (0); 258 259 return (1); 260} 261 262/* 263 * Probe and vendor-specific initialization routine for SMC/WD80x3 boards 264 */ 265int 266ed_probe_WD80x3(isa_dev) 267 struct isa_device *isa_dev; 268{ 269 struct ed_softc *sc = &ed_softc[isa_dev->id_unit]; 270 int i; 271 u_int memsize; 272 u_char iptr, isa16bit, sum; 273 274 sc->asic_addr = isa_dev->id_iobase; 275 sc->nic_addr = sc->asic_addr + ED_WD_NIC_OFFSET; 276 sc->is790 = 0; 277 278#ifdef TOSH_ETHER 279 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_POW); 280 DELAY(10000); 281#endif 282 283 /* 284 * Attempt to do a checksum over the station address PROM. If it 285 * fails, it's probably not a SMC/WD board. There is a problem with 286 * this, though: some clone WD boards don't pass the checksum test. 287 * Danpex boards for one. 288 */ 289 for (sum = 0, i = 0; i < 8; ++i) 290 sum += inb(sc->asic_addr + ED_WD_PROM + i); 291 292 if (sum != ED_WD_ROM_CHECKSUM_TOTAL) { 293 294 /* 295 * Checksum is invalid. This often happens with cheap WD8003E 296 * clones. In this case, the checksum byte (the eighth byte) 297 * seems to always be zero. 298 */ 299 if (inb(sc->asic_addr + ED_WD_CARD_ID) != ED_TYPE_WD8003E || 300 inb(sc->asic_addr + ED_WD_PROM + 7) != 0) 301 return (0); 302 } 303 /* reset card to force it into a known state. */ 304#ifdef TOSH_ETHER 305 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_RST | ED_WD_MSR_POW); 306#else 307 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_RST); 308#endif 309 DELAY(100); 310 outb(sc->asic_addr + ED_WD_MSR, inb(sc->asic_addr + ED_WD_MSR) & ~ED_WD_MSR_RST); 311 /* wait in the case this card is reading it's EEROM */ 312 DELAY(5000); 313 314 sc->vendor = ED_VENDOR_WD_SMC; 315 sc->type = inb(sc->asic_addr + ED_WD_CARD_ID); 316 317 /* 318 * Set initial values for width/size. 319 */ 320 memsize = 8192; 321 isa16bit = 0; 322 switch (sc->type) { 323 case ED_TYPE_WD8003S: 324 sc->type_str = "WD8003S"; 325 break; 326 case ED_TYPE_WD8003E: 327 sc->type_str = "WD8003E"; 328 break; 329 case ED_TYPE_WD8003EB: 330 sc->type_str = "WD8003EB"; 331 break; 332 case ED_TYPE_WD8003W: 333 sc->type_str = "WD8003W"; 334 break; 335 case ED_TYPE_WD8013EBT: 336 sc->type_str = "WD8013EBT"; 337 memsize = 16384; 338 isa16bit = 1; 339 break; 340 case ED_TYPE_WD8013W: 341 sc->type_str = "WD8013W"; 342 memsize = 16384; 343 isa16bit = 1; 344 break; 345 case ED_TYPE_WD8013EP: /* also WD8003EP */ 346 if (inb(sc->asic_addr + ED_WD_ICR) 347 & ED_WD_ICR_16BIT) { 348 isa16bit = 1; 349 memsize = 16384; 350 sc->type_str = "WD8013EP"; 351 } else { 352 sc->type_str = "WD8003EP"; 353 } 354 break; 355 case ED_TYPE_WD8013WC: 356 sc->type_str = "WD8013WC"; 357 memsize = 16384; 358 isa16bit = 1; 359 break; 360 case ED_TYPE_WD8013EBP: 361 sc->type_str = "WD8013EBP"; 362 memsize = 16384; 363 isa16bit = 1; 364 break; 365 case ED_TYPE_WD8013EPC: 366 sc->type_str = "WD8013EPC"; 367 memsize = 16384; 368 isa16bit = 1; 369 break; 370 case ED_TYPE_SMC8216C: 371 sc->type_str = "SMC8216/SMC8216C"; 372 memsize = 16384; 373 isa16bit = 1; 374 sc->is790 = 1; 375 break; 376 case ED_TYPE_SMC8216T: 377 sc->type_str = "SMC8216T"; 378 memsize = 16384; 379 isa16bit = 1; 380 sc->is790 = 1; 381 break; 382#ifdef TOSH_ETHER 383 case ED_TYPE_TOSHIBA1: 384 sc->type_str = "Toshiba1"; 385 memsize = 32768; 386 isa16bit = 1; 387 break; 388 case ED_TYPE_TOSHIBA4: 389 sc->type_str = "Toshiba4"; 390 memsize = 32768; 391 isa16bit = 1; 392 break; 393#endif 394 default: 395 sc->type_str = ""; 396 break; 397 } 398 399 /* 400 * Make some adjustments to initial values depending on what is found 401 * in the ICR. 402 */ 403 if (isa16bit && (sc->type != ED_TYPE_WD8013EBT) 404#ifdef TOSH_ETHER 405 && (sc->type != ED_TYPE_TOSHIBA1) && (sc->type != ED_TYPE_TOSHIBA4) 406#endif 407 && ((inb(sc->asic_addr + ED_WD_ICR) & ED_WD_ICR_16BIT) == 0)) { 408 isa16bit = 0; 409 memsize = 8192; 410 } 411#if ED_DEBUG 412 printf("type = %x type_str=%s isa16bit=%d memsize=%d id_msize=%d\n", 413 sc->type, sc->type_str, isa16bit, memsize, isa_dev->id_msize); 414 for (i = 0; i < 8; i++) 415 printf("%x -> %x\n", i, inb(sc->asic_addr + i)); 416#endif 417 418 /* 419 * Allow the user to override the autoconfiguration 420 */ 421 if (isa_dev->id_msize) 422 memsize = isa_dev->id_msize; 423 424 /* 425 * (note that if the user specifies both of the following flags that 426 * '8bit' mode intentionally has precedence) 427 */ 428 if (isa_dev->id_flags & ED_FLAGS_FORCE_16BIT_MODE) 429 isa16bit = 1; 430 if (isa_dev->id_flags & ED_FLAGS_FORCE_8BIT_MODE) 431 isa16bit = 0; 432 433 /* 434 * If possible, get the assigned interrupt number from the card and 435 * use it. 436 */ 437 if ((sc->type & ED_WD_SOFTCONFIG) && (!sc->is790)) { 438 439 /* 440 * Assemble together the encoded interrupt number. 441 */ 442 iptr = (inb(isa_dev->id_iobase + ED_WD_ICR) & ED_WD_ICR_IR2) | 443 ((inb(isa_dev->id_iobase + ED_WD_IRR) & 444 (ED_WD_IRR_IR0 | ED_WD_IRR_IR1)) >> 5); 445 446 /* 447 * Use what the board tells us. 448 */ 449 isa_dev->id_irq = ed_intr_mask[iptr]; 450 451 /* 452 * Enable the interrupt. 453 */ 454 outb(isa_dev->id_iobase + ED_WD_IRR, 455 inb(isa_dev->id_iobase + ED_WD_IRR) | ED_WD_IRR_IEN); 456 } 457 if (sc->is790) { 458 outb(isa_dev->id_iobase + ED_WD790_HWR, 459 inb(isa_dev->id_iobase + ED_WD790_HWR) | ED_WD790_HWR_SWH); 460 iptr = (((inb(isa_dev->id_iobase + ED_WD790_GCR) & ED_WD790_GCR_IR2) >> 4) | 461 (inb(isa_dev->id_iobase + ED_WD790_GCR) & 462 (ED_WD790_GCR_IR1 | ED_WD790_GCR_IR0)) >> 2); 463 outb(isa_dev->id_iobase + ED_WD790_HWR, 464 inb(isa_dev->id_iobase + ED_WD790_HWR) & ~ED_WD790_HWR_SWH); 465 466 /* 467 * Use what the board tells us. 468 */ 469 isa_dev->id_irq = ed_790_intr_mask[iptr]; 470 471 /* 472 * Enable interrupts. 473 */ 474 outb(isa_dev->id_iobase + ED_WD790_ICR, 475 inb(isa_dev->id_iobase + ED_WD790_ICR) | ED_WD790_ICR_EIL); 476 } 477 if (isa_dev->id_irq <= 0) { 478 printf("ed%d: %s cards don't support auto-detected/assigned interrupts.\n", 479 isa_dev->id_unit, sc->type_str); 480 return (0); 481 } 482 sc->isa16bit = isa16bit; 483 sc->mem_shared = 1; 484 isa_dev->id_msize = memsize; 485 sc->mem_start = (caddr_t) isa_dev->id_maddr; 486 487 /* 488 * allocate one xmit buffer if < 16k, two buffers otherwise 489 */ 490 if ((memsize < 16384) || (isa_dev->id_flags & ED_FLAGS_NO_MULTI_BUFFERING)) { 491 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * ED_TXBUF_SIZE); 492 sc->txb_cnt = 1; 493 sc->rec_page_start = ED_TXBUF_SIZE; 494 } else { 495 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * ED_TXBUF_SIZE * 2); 496 sc->txb_cnt = 2; 497 sc->rec_page_start = ED_TXBUF_SIZE * 2; 498 } 499 sc->mem_size = memsize; 500 sc->mem_end = sc->mem_start + memsize; 501 sc->rec_page_stop = memsize / ED_PAGE_SIZE; 502 sc->tx_page_start = ED_WD_PAGE_OFFSET; 503 504 /* 505 * Get station address from on-board ROM 506 */ 507 for (i = 0; i < ETHER_ADDR_LEN; ++i) 508 sc->arpcom.ac_enaddr[i] = inb(sc->asic_addr + ED_WD_PROM + i); 509 510 /* 511 * Set upper address bits and 8/16 bit access to shared memory 512 */ 513 if (isa16bit) { 514 if (sc->is790) { 515 sc->wd_laar_proto = inb(sc->asic_addr + ED_WD_LAAR); 516 outb(sc->asic_addr + ED_WD_LAAR, ED_WD_LAAR_M16EN); 517 } else { 518 outb(sc->asic_addr + ED_WD_LAAR, (sc->wd_laar_proto = 519 ED_WD_LAAR_L16EN | ED_WD_LAAR_M16EN | 520 ((kvtop(sc->mem_start) >> 19) & ED_WD_LAAR_ADDRHI))); 521 } 522 } else { 523 if (((sc->type & ED_WD_SOFTCONFIG) || 524#ifdef TOSH_ETHER 525 (sc->type == ED_TYPE_TOSHIBA1) || (sc->type == ED_TYPE_TOSHIBA4) || 526#endif 527 (sc->type == ED_TYPE_WD8013EBT)) && (!sc->is790)) { 528 outb(sc->asic_addr + ED_WD_LAAR, (sc->wd_laar_proto = 529 ((kvtop(sc->mem_start) >> 19) & ED_WD_LAAR_ADDRHI))); 530 } 531 } 532 533 /* 534 * Set address and enable interface shared memory. 535 */ 536 if (!sc->is790) { 537#ifdef TOSH_ETHER 538 outb(sc->asic_addr + ED_WD_MSR + 1, ((kvtop(sc->mem_start) >> 8) & 0xe0) | 4); 539 outb(sc->asic_addr + ED_WD_MSR + 2, ((kvtop(sc->mem_start) >> 16) & 0x0f)); 540 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_MENB | ED_WD_MSR_POW); 541 542#else 543 outb(sc->asic_addr + ED_WD_MSR, ((kvtop(sc->mem_start) >> 13) & 544 ED_WD_MSR_ADDR) | ED_WD_MSR_MENB); 545#endif 546 sc->cr_proto = ED_CR_RD2; 547 } else { 548 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_MENB); 549 outb(sc->asic_addr + 0x04, (inb(sc->asic_addr + 0x04) | 0x80)); 550 outb(sc->asic_addr + 0x0b, ((kvtop(sc->mem_start) >> 13) & 0x0f) | 551 ((kvtop(sc->mem_start) >> 11) & 0x40) | 552 (inb(sc->asic_addr + 0x0b) & 0xb0)); 553 outb(sc->asic_addr + 0x04, (inb(sc->asic_addr + 0x04) & ~0x80)); 554 sc->cr_proto = 0; 555 } 556 557#if 0 558 printf("starting memory performance test at 0x%x, size %d...\n", 559 sc->mem_start, memsize*16384); 560 for (i = 0; i < 16384; i++) 561 bzero(sc->mem_start, memsize); 562 printf("***DONE***\n"); 563#endif 564 565 /* 566 * Now zero memory and verify that it is clear 567 */ 568 bzero(sc->mem_start, memsize); 569 570 for (i = 0; i < memsize; ++i) { 571 if (sc->mem_start[i]) { 572 printf("ed%d: failed to clear shared memory at %lx - check configuration\n", 573 isa_dev->id_unit, kvtop(sc->mem_start + i)); 574 575 /* 576 * Disable 16 bit access to shared memory 577 */ 578 if (isa16bit) { 579 if (sc->is790) { 580 outb(sc->asic_addr + ED_WD_MSR, 0x00); 581 } 582 outb(sc->asic_addr + ED_WD_LAAR, (sc->wd_laar_proto &= 583 ~ED_WD_LAAR_M16EN)); 584 } 585 return (0); 586 } 587 } 588 589 /* 590 * Disable 16bit access to shared memory - we leave it 591 * disabled so that 1) machines reboot properly when the board 592 * is set 16 bit mode and there are conflicting 8bit 593 * devices/ROMS in the same 128k address space as this boards 594 * shared memory. and 2) so that other 8 bit devices with 595 * shared memory can be used in this 128k region, too. 596 */ 597 if (isa16bit) { 598 if (sc->is790) { 599 outb(sc->asic_addr + ED_WD_MSR, 0x00); 600 } 601 outb(sc->asic_addr + ED_WD_LAAR, (sc->wd_laar_proto &= 602 ~ED_WD_LAAR_M16EN)); 603 } 604 return (ED_WD_IO_PORTS); 605} 606 607/* 608 * Probe and vendor-specific initialization routine for 3Com 3c503 boards 609 */ 610int 611ed_probe_3Com(isa_dev) 612 struct isa_device *isa_dev; 613{ 614 struct ed_softc *sc = &ed_softc[isa_dev->id_unit]; 615 int i; 616 u_int memsize; 617 u_char isa16bit; 618 619 sc->asic_addr = isa_dev->id_iobase + ED_3COM_ASIC_OFFSET; 620 sc->nic_addr = isa_dev->id_iobase + ED_3COM_NIC_OFFSET; 621 622 /* 623 * Verify that the kernel configured I/O address matches the board 624 * configured address 625 */ 626 switch (inb(sc->asic_addr + ED_3COM_BCFR)) { 627 case ED_3COM_BCFR_300: 628 if (isa_dev->id_iobase != 0x300) 629 return (0); 630 break; 631 case ED_3COM_BCFR_310: 632 if (isa_dev->id_iobase != 0x310) 633 return (0); 634 break; 635 case ED_3COM_BCFR_330: 636 if (isa_dev->id_iobase != 0x330) 637 return (0); 638 break; 639 case ED_3COM_BCFR_350: 640 if (isa_dev->id_iobase != 0x350) 641 return (0); 642 break; 643 case ED_3COM_BCFR_250: 644 if (isa_dev->id_iobase != 0x250) 645 return (0); 646 break; 647 case ED_3COM_BCFR_280: 648 if (isa_dev->id_iobase != 0x280) 649 return (0); 650 break; 651 case ED_3COM_BCFR_2A0: 652 if (isa_dev->id_iobase != 0x2a0) 653 return (0); 654 break; 655 case ED_3COM_BCFR_2E0: 656 if (isa_dev->id_iobase != 0x2e0) 657 return (0); 658 break; 659 default: 660 return (0); 661 } 662 663 /* 664 * Verify that the kernel shared memory address matches the board 665 * configured address. 666 */ 667 switch (inb(sc->asic_addr + ED_3COM_PCFR)) { 668 case ED_3COM_PCFR_DC000: 669 if (kvtop(isa_dev->id_maddr) != 0xdc000) 670 return (0); 671 break; 672 case ED_3COM_PCFR_D8000: 673 if (kvtop(isa_dev->id_maddr) != 0xd8000) 674 return (0); 675 break; 676 case ED_3COM_PCFR_CC000: 677 if (kvtop(isa_dev->id_maddr) != 0xcc000) 678 return (0); 679 break; 680 case ED_3COM_PCFR_C8000: 681 if (kvtop(isa_dev->id_maddr) != 0xc8000) 682 return (0); 683 break; 684 default: 685 return (0); 686 } 687 688 689 /* 690 * Reset NIC and ASIC. Enable on-board transceiver throughout reset 691 * sequence because it'll lock up if the cable isn't connected if we 692 * don't. 693 */ 694 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_RST | ED_3COM_CR_XSEL); 695 696 /* 697 * Wait for a while, then un-reset it 698 */ 699 DELAY(50); 700 701 /* 702 * The 3Com ASIC defaults to rather strange settings for the CR after 703 * a reset - it's important to set it again after the following outb 704 * (this is done when we map the PROM below). 705 */ 706 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL); 707 708 /* 709 * Wait a bit for the NIC to recover from the reset 710 */ 711 DELAY(5000); 712 713 sc->vendor = ED_VENDOR_3COM; 714 sc->type_str = "3c503"; 715 sc->mem_shared = 1; 716 sc->cr_proto = ED_CR_RD2; 717 718 /* 719 * Hmmm...a 16bit 3Com board has 16k of memory, but only an 8k window 720 * to it. 721 */ 722 memsize = 8192; 723 724 /* 725 * Get station address from on-board ROM 726 */ 727 728 /* 729 * First, map ethernet address PROM over the top of where the NIC 730 * registers normally appear. 731 */ 732 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_EALO | ED_3COM_CR_XSEL); 733 734 for (i = 0; i < ETHER_ADDR_LEN; ++i) 735 sc->arpcom.ac_enaddr[i] = inb(sc->nic_addr + i); 736 737 /* 738 * Unmap PROM - select NIC registers. The proper setting of the 739 * tranceiver is set in ed_init so that the attach code is given a 740 * chance to set the default based on a compile-time config option 741 */ 742 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL); 743 744 /* 745 * Determine if this is an 8bit or 16bit board 746 */ 747 748 /* 749 * select page 0 registers 750 */ 751 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STP); 752 753 /* 754 * Attempt to clear WTS bit. If it doesn't clear, then this is a 16bit 755 * board. 756 */ 757 outb(sc->nic_addr + ED_P0_DCR, 0); 758 759 /* 760 * select page 2 registers 761 */ 762 outb(sc->nic_addr + ED_P0_CR, ED_CR_PAGE_2 | ED_CR_RD2 | ED_CR_STP); 763 764 /* 765 * The 3c503 forces the WTS bit to a one if this is a 16bit board 766 */ 767 if (inb(sc->nic_addr + ED_P2_DCR) & ED_DCR_WTS) 768 isa16bit = 1; 769 else 770 isa16bit = 0; 771 772 /* 773 * select page 0 registers 774 */ 775 outb(sc->nic_addr + ED_P2_CR, ED_CR_RD2 | ED_CR_STP); 776 777 sc->mem_start = (caddr_t) isa_dev->id_maddr; 778 sc->mem_size = memsize; 779 sc->mem_end = sc->mem_start + memsize; 780 781 /* 782 * We have an entire 8k window to put the transmit buffers on the 783 * 16bit boards. But since the 16bit 3c503's shared memory is only 784 * fast enough to overlap the loading of one full-size packet, trying 785 * to load more than 2 buffers can actually leave the transmitter idle 786 * during the load. So 2 seems the best value. (Although a mix of 787 * variable-sized packets might change this assumption. Nonetheless, 788 * we optimize for linear transfers of same-size packets.) 789 */ 790 if (isa16bit) { 791 if (isa_dev->id_flags & ED_FLAGS_NO_MULTI_BUFFERING) 792 sc->txb_cnt = 1; 793 else 794 sc->txb_cnt = 2; 795 796 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_16BIT; 797 sc->rec_page_start = ED_3COM_RX_PAGE_OFFSET_16BIT; 798 sc->rec_page_stop = memsize / ED_PAGE_SIZE + 799 ED_3COM_RX_PAGE_OFFSET_16BIT; 800 sc->mem_ring = sc->mem_start; 801 } else { 802 sc->txb_cnt = 1; 803 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_8BIT; 804 sc->rec_page_start = ED_TXBUF_SIZE + ED_3COM_TX_PAGE_OFFSET_8BIT; 805 sc->rec_page_stop = memsize / ED_PAGE_SIZE + 806 ED_3COM_TX_PAGE_OFFSET_8BIT; 807 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * ED_TXBUF_SIZE); 808 } 809 810 sc->isa16bit = isa16bit; 811 812 /* 813 * Initialize GA page start/stop registers. Probably only needed if 814 * doing DMA, but what the hell. 815 */ 816 outb(sc->asic_addr + ED_3COM_PSTR, sc->rec_page_start); 817 outb(sc->asic_addr + ED_3COM_PSPR, sc->rec_page_stop); 818 819 /* 820 * Set IRQ. 3c503 only allows a choice of irq 2-5. 821 */ 822 switch (isa_dev->id_irq) { 823 case IRQ2: 824 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ2); 825 break; 826 case IRQ3: 827 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ3); 828 break; 829 case IRQ4: 830 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ4); 831 break; 832 case IRQ5: 833 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ5); 834 break; 835 default: 836 printf("ed%d: Invalid irq configuration (%d) must be 2-5 for 3c503\n", 837 isa_dev->id_unit, ffs(isa_dev->id_irq) - 1); 838 return (0); 839 } 840 841 /* 842 * Initialize GA configuration register. Set bank and enable shared 843 * mem. 844 */ 845 outb(sc->asic_addr + ED_3COM_GACFR, ED_3COM_GACFR_RSEL | 846 ED_3COM_GACFR_MBS0); 847 848 /* 849 * Initialize "Vector Pointer" registers. These gawd-awful things are 850 * compared to 20 bits of the address on ISA, and if they match, the 851 * shared memory is disabled. We set them to 0xffff0...allegedly the 852 * reset vector. 853 */ 854 outb(sc->asic_addr + ED_3COM_VPTR2, 0xff); 855 outb(sc->asic_addr + ED_3COM_VPTR1, 0xff); 856 outb(sc->asic_addr + ED_3COM_VPTR0, 0x00); 857 858 /* 859 * Zero memory and verify that it is clear 860 */ 861 bzero(sc->mem_start, memsize); 862 863 for (i = 0; i < memsize; ++i) 864 if (sc->mem_start[i]) { 865 printf("ed%d: failed to clear shared memory at %lx - check configuration\n", 866 isa_dev->id_unit, kvtop(sc->mem_start + i)); 867 return (0); 868 } 869 isa_dev->id_msize = memsize; 870 return (ED_3COM_IO_PORTS); 871} 872 873/* 874 * Probe and vendor-specific initialization routine for NE1000/2000 boards 875 */ 876int 877ed_probe_Novell(isa_dev) 878 struct isa_device *isa_dev; 879{ 880 struct ed_softc *sc = &ed_softc[isa_dev->id_unit]; 881 u_int memsize, n; 882 u_char romdata[16], tmp; 883 static char test_pattern[32] = "THIS is A memory TEST pattern"; 884 char test_buffer[32]; 885 886 sc->asic_addr = isa_dev->id_iobase + ED_NOVELL_ASIC_OFFSET; 887 sc->nic_addr = isa_dev->id_iobase + ED_NOVELL_NIC_OFFSET; 888 889 /* XXX - do Novell-specific probe here */ 890 891 /* Reset the board */ 892#ifdef GWETHER 893 outb(sc->asic_addr + ED_NOVELL_RESET, 0); 894 DELAY(200); 895#endif /* GWETHER */ 896 tmp = inb(sc->asic_addr + ED_NOVELL_RESET); 897 898 /* 899 * I don't know if this is necessary; probably cruft leftover from 900 * Clarkson packet driver code. Doesn't do a thing on the boards I've 901 * tested. -DG [note that a outb(0x84, 0) seems to work here, and is 902 * non-invasive...but some boards don't seem to reset and I don't have 903 * complete documentation on what the 'right' thing to do is...so we 904 * do the invasive thing for now. Yuck.] 905 */ 906 outb(sc->asic_addr + ED_NOVELL_RESET, tmp); 907 DELAY(5000); 908 909 /* 910 * This is needed because some NE clones apparently don't reset the 911 * NIC properly (or the NIC chip doesn't reset fully on power-up) XXX 912 * - this makes the probe invasive! ...Done against my better 913 * judgement. -DLG 914 */ 915 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STP); 916 917 DELAY(5000); 918 919 /* Make sure that we really have an 8390 based board */ 920 if (!ed_probe_generic8390(sc)) 921 return (0); 922 923 sc->vendor = ED_VENDOR_NOVELL; 924 sc->mem_shared = 0; 925 sc->cr_proto = ED_CR_RD2; 926 isa_dev->id_maddr = 0; 927 928 /* 929 * Test the ability to read and write to the NIC memory. This has the 930 * side affect of determining if this is an NE1000 or an NE2000. 931 */ 932 933 /* 934 * This prevents packets from being stored in the NIC memory when the 935 * readmem routine turns on the start bit in the CR. 936 */ 937 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_MON); 938 939 /* Temporarily initialize DCR for byte operations */ 940 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS); 941 942 outb(sc->nic_addr + ED_P0_PSTART, 8192 / ED_PAGE_SIZE); 943 outb(sc->nic_addr + ED_P0_PSTOP, 16384 / ED_PAGE_SIZE); 944 945 sc->isa16bit = 0; 946 947 /* 948 * Write a test pattern in byte mode. If this fails, then there 949 * probably isn't any memory at 8k - which likely means that the board 950 * is an NE2000. 951 */ 952 ed_pio_writemem(sc, test_pattern, 8192, sizeof(test_pattern)); 953 ed_pio_readmem(sc, 8192, test_buffer, sizeof(test_pattern)); 954 955 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern))) { 956 /* not an NE1000 - try NE2000 */ 957 958 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_WTS | ED_DCR_FT1 | ED_DCR_LS); 959 outb(sc->nic_addr + ED_P0_PSTART, 16384 / ED_PAGE_SIZE); 960 outb(sc->nic_addr + ED_P0_PSTOP, 32768 / ED_PAGE_SIZE); 961 962 sc->isa16bit = 1; 963 964 /* 965 * Write a test pattern in word mode. If this also fails, then 966 * we don't know what this board is. 967 */ 968 ed_pio_writemem(sc, test_pattern, 16384, sizeof(test_pattern)); 969 ed_pio_readmem(sc, 16384, test_buffer, sizeof(test_pattern)); 970 971 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern))) 972 return (0); /* not an NE2000 either */ 973 974 sc->type = ED_TYPE_NE2000; 975 sc->type_str = "NE2000"; 976 } else { 977 sc->type = ED_TYPE_NE1000; 978 sc->type_str = "NE1000"; 979 } 980 981 /* 8k of memory plus an additional 8k if 16bit */ 982 memsize = 8192 + sc->isa16bit * 8192; 983 984#if 0 /* probably not useful - NE boards only come two ways */ 985 /* allow kernel config file overrides */ 986 if (isa_dev->id_msize) 987 memsize = isa_dev->id_msize; 988#endif 989 990 sc->mem_size = memsize; 991 992 /* NIC memory doesn't start at zero on an NE board */ 993 /* The start address is tied to the bus width */ 994 sc->mem_start = (char *) 8192 + sc->isa16bit * 8192; 995 sc->mem_end = sc->mem_start + memsize; 996 sc->tx_page_start = memsize / ED_PAGE_SIZE; 997 998#ifdef GWETHER 999 { 1000 int x, i, mstart = 0, msize = 0; 1001 char pbuf0[ED_PAGE_SIZE], pbuf[ED_PAGE_SIZE], tbuf[ED_PAGE_SIZE]; 1002 1003 for (i = 0; i < ED_PAGE_SIZE; i++) 1004 pbuf0[i] = 0; 1005 1006 /* Clear all the memory. */ 1007 for (x = 1; x < 256; x++) 1008 ed_pio_writemem(sc, pbuf0, x * 256, ED_PAGE_SIZE); 1009 1010 /* Search for the start of RAM. */ 1011 for (x = 1; x < 256; x++) { 1012 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE); 1013 if (memcmp(pbuf0, tbuf, ED_PAGE_SIZE) == 0) { 1014 for (i = 0; i < ED_PAGE_SIZE; i++) 1015 pbuf[i] = 255 - x; 1016 ed_pio_writemem(sc, pbuf, x * 256, ED_PAGE_SIZE); 1017 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE); 1018 if (memcmp(pbuf, tbuf, ED_PAGE_SIZE) == 0) { 1019 mstart = x * ED_PAGE_SIZE; 1020 msize = ED_PAGE_SIZE; 1021 break; 1022 } 1023 } 1024 } 1025 1026 if (mstart == 0) { 1027 printf("ed%d: Cannot find start of RAM.\n", isa_dev->id_unit); 1028 return 0; 1029 } 1030 /* Search for the start of RAM. */ 1031 for (x = (mstart / ED_PAGE_SIZE) + 1; x < 256; x++) { 1032 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE); 1033 if (memcmp(pbuf0, tbuf, ED_PAGE_SIZE) == 0) { 1034 for (i = 0; i < ED_PAGE_SIZE; i++) 1035 pbuf[i] = 255 - x; 1036 ed_pio_writemem(sc, pbuf, x * 256, ED_PAGE_SIZE); 1037 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE); 1038 if (memcmp(pbuf, tbuf, ED_PAGE_SIZE) == 0) 1039 msize += ED_PAGE_SIZE; 1040 else { 1041 break; 1042 } 1043 } else { 1044 break; 1045 } 1046 } 1047 1048 if (msize == 0) { 1049 printf("ed%d: Cannot find any RAM, start : %d, x = %d.\n", isa_dev->id_unit, mstart, x); 1050 return 0; 1051 } 1052 printf("ed%d: RAM start at %d, size : %d.\n", isa_dev->id_unit, mstart, msize); 1053 1054 sc->mem_size = msize; 1055 sc->mem_start = (char *) mstart; 1056 sc->mem_end = (char *) (msize + mstart); 1057 sc->tx_page_start = mstart / ED_PAGE_SIZE; 1058 } 1059#endif /* GWETHER */ 1060 1061 /* 1062 * Use one xmit buffer if < 16k, two buffers otherwise (if not told 1063 * otherwise). 1064 */ 1065 if ((memsize < 16384) || (isa_dev->id_flags & ED_FLAGS_NO_MULTI_BUFFERING)) 1066 sc->txb_cnt = 1; 1067 else 1068 sc->txb_cnt = 2; 1069 1070 sc->rec_page_start = sc->tx_page_start + sc->txb_cnt * ED_TXBUF_SIZE; 1071 sc->rec_page_stop = sc->tx_page_start + memsize / ED_PAGE_SIZE; 1072 1073 sc->mem_ring = sc->mem_start + sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE; 1074 1075 ed_pio_readmem(sc, 0, romdata, 16); 1076 for (n = 0; n < ETHER_ADDR_LEN; n++) 1077 sc->arpcom.ac_enaddr[n] = romdata[n * (sc->isa16bit + 1)]; 1078 1079#ifdef GWETHER 1080 if (sc->arpcom.ac_enaddr[2] == 0x86) 1081 sc->type_str = "Gateway AT"; 1082#endif /* GWETHER */ 1083 1084 /* clear any pending interrupts that might have occurred above */ 1085 outb(sc->nic_addr + ED_P0_ISR, 0xff); 1086 1087 return (ED_NOVELL_IO_PORTS); 1088} 1089 1090/* 1091 * Install interface into kernel networking data structures 1092 */ 1093int 1094ed_attach(isa_dev) 1095 struct isa_device *isa_dev; 1096{ 1097 struct ed_softc *sc = &ed_softc[isa_dev->id_unit]; 1098 struct ifnet *ifp = &sc->arpcom.ac_if; 1099 1100 /* 1101 * Set interface to stopped condition (reset) 1102 */ 1103 ed_stop(isa_dev->id_unit); 1104 1105 /* 1106 * Initialize ifnet structure 1107 */ 1108 ifp->if_unit = isa_dev->id_unit; 1109 ifp->if_name = "ed"; 1110 ifp->if_init = ed_init; 1111 ifp->if_output = ether_output; 1112 ifp->if_start = ed_start; 1113 ifp->if_ioctl = ed_ioctl; 1114 ifp->if_reset = ed_reset; 1115 ifp->if_watchdog = ed_watchdog; 1116 1117 /* 1118 * Set default state for ALTPHYS flag (used to disable the tranceiver 1119 * for AUI operation), based on compile-time config option. 1120 */ 1121 if (isa_dev->id_flags & ED_FLAGS_DISABLE_TRANCEIVER) 1122 ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | 1123 IFF_MULTICAST | IFF_ALTPHYS); 1124 else 1125 ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | 1126 IFF_MULTICAST); 1127 1128 /* 1129 * Attach the interface 1130 */ 1131 if_attach(ifp); 1132 ed_registerdev(isa_dev, sc->type_str ? sc->type_str : "Ethernet adapter"); 1133 1134 /* 1135 * Print additional info when attached 1136 */ 1137 printf("ed%d: address %s, ", isa_dev->id_unit, 1138 ether_sprintf(sc->arpcom.ac_enaddr)); 1139 1140 if (sc->type_str && (*sc->type_str != 0)) 1141 printf("type %s ", sc->type_str); 1142 else 1143 printf("type unknown (0x%x) ", sc->type); 1144 1145 printf("%s ", sc->isa16bit ? "(16 bit)" : "(8 bit)"); 1146 1147 printf("%s\n", ((sc->vendor == ED_VENDOR_3COM) && 1148 (ifp->if_flags & IFF_ALTPHYS)) ? " tranceiver disabled" : ""); 1149 1150 /* 1151 * If BPF is in the kernel, call the attach for it 1152 */ 1153#if NBPFILTER > 0 1154 bpfattach(&sc->bpf, ifp, DLT_EN10MB, sizeof(struct ether_header)); 1155#endif 1156 return 1; 1157} 1158 1159/* 1160 * Reset interface. 1161 */ 1162void 1163ed_reset(unit) 1164 int unit; 1165{ 1166 int s; 1167 1168 s = splimp(); 1169 1170 /* 1171 * Stop interface and re-initialize. 1172 */ 1173 ed_stop(unit); 1174 ed_init(unit); 1175 1176 (void) splx(s); 1177} 1178 1179/* 1180 * Take interface offline. 1181 */ 1182void 1183ed_stop(unit) 1184 int unit; 1185{ 1186 struct ed_softc *sc = &ed_softc[unit]; 1187 int n = 5000; 1188 1189 /* 1190 * Stop everything on the interface, and select page 0 registers. 1191 */ 1192 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP); 1193 1194 /* 1195 * Wait for interface to enter stopped state, but limit # of checks to 1196 * 'n' (about 5ms). It shouldn't even take 5us on modern DS8390's, but 1197 * just in case it's an old one. 1198 */ 1199 while (((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RST) == 0) && --n); 1200 1201} 1202 1203/* 1204 * Device timeout/watchdog routine. Entered if the device neglects to 1205 * generate an interrupt after a transmit has been started on it. 1206 */ 1207void 1208ed_watchdog(unit) 1209 int unit; 1210{ 1211 struct ed_softc *sc = &ed_softc[unit]; 1212 1213 log(LOG_ERR, "ed%d: device timeout\n", unit); 1214 ++sc->arpcom.ac_if.if_oerrors; 1215 1216 ed_reset(unit); 1217} 1218 1219/* 1220 * Initialize device. 1221 */ 1222void 1223ed_init(unit) 1224 int unit; 1225{ 1226 struct ed_softc *sc = &ed_softc[unit]; 1227 struct ifnet *ifp = &sc->arpcom.ac_if; 1228 int i, s; 1229 1230 1231 /* address not known */ 1232 if (ifp->if_addrlist == (struct ifaddr *) 0) 1233 return; 1234 1235 /* 1236 * Initialize the NIC in the exact order outlined in the NS manual. 1237 * This init procedure is "mandatory"...don't change what or when 1238 * things happen. 1239 */ 1240 s = splimp(); 1241 1242 /* reset transmitter flags */ 1243 sc->xmit_busy = 0; 1244 sc->arpcom.ac_if.if_timer = 0; 1245 1246 sc->txb_inuse = 0; 1247 sc->txb_new = 0; 1248 sc->txb_next_tx = 0; 1249 1250 /* This variable is used below - don't move this assignment */ 1251 sc->next_packet = sc->rec_page_start + 1; 1252 1253 /* 1254 * Set interface for page 0, Remote DMA complete, Stopped 1255 */ 1256 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP); 1257 1258 if (sc->isa16bit) { 1259 1260 /* 1261 * Set FIFO threshold to 8, No auto-init Remote DMA, byte 1262 * order=80x86, word-wide DMA xfers, 1263 */ 1264 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1 | ED_DCR_WTS | ED_DCR_LS); 1265 } else { 1266 1267 /* 1268 * Same as above, but byte-wide DMA xfers 1269 */ 1270 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS); 1271 } 1272 1273 /* 1274 * Clear Remote Byte Count Registers 1275 */ 1276 outb(sc->nic_addr + ED_P0_RBCR0, 0); 1277 outb(sc->nic_addr + ED_P0_RBCR1, 0); 1278 1279 /* 1280 * For the moment, don't store incoming packets in memory. 1281 */ 1282 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_MON); 1283 1284 /* 1285 * Place NIC in internal loopback mode 1286 */ 1287 outb(sc->nic_addr + ED_P0_TCR, ED_TCR_LB0); 1288 1289 /* 1290 * Initialize transmit/receive (ring-buffer) Page Start 1291 */ 1292 outb(sc->nic_addr + ED_P0_TPSR, sc->tx_page_start); 1293 outb(sc->nic_addr + ED_P0_PSTART, sc->rec_page_start); 1294 /* Set lower bits of byte addressable framing to 0 */ 1295 if (sc->is790) 1296 outb(sc->nic_addr + 0x09, 0); 1297 1298 /* 1299 * Initialize Receiver (ring-buffer) Page Stop and Boundry 1300 */ 1301 outb(sc->nic_addr + ED_P0_PSTOP, sc->rec_page_stop); 1302 outb(sc->nic_addr + ED_P0_BNRY, sc->rec_page_start); 1303 1304 /* 1305 * Clear all interrupts. A '1' in each bit position clears the 1306 * corresponding flag. 1307 */ 1308 outb(sc->nic_addr + ED_P0_ISR, 0xff); 1309 1310 /* 1311 * Enable the following interrupts: receive/transmit complete, 1312 * receive/transmit error, and Receiver OverWrite. 1313 * 1314 * Counter overflow and Remote DMA complete are *not* enabled. 1315 */ 1316 outb(sc->nic_addr + ED_P0_IMR, 1317 ED_IMR_PRXE | ED_IMR_PTXE | ED_IMR_RXEE | ED_IMR_TXEE | ED_IMR_OVWE); 1318 1319 /* 1320 * Program Command Register for page 1 1321 */ 1322 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP); 1323 1324 /* 1325 * Copy out our station address 1326 */ 1327 for (i = 0; i < ETHER_ADDR_LEN; ++i) 1328 outb(sc->nic_addr + ED_P1_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1329 1330 /* 1331 * Set Current Page pointer to next_packet (initialized above) 1332 */ 1333 outb(sc->nic_addr + ED_P1_CURR, sc->next_packet); 1334 1335 /* 1336 * Program Receiver Configuration Register and multicast filter. CR is 1337 * set to page 0 on return. 1338 */ 1339 ed_setrcr(ifp, sc); 1340 1341 /* 1342 * Take interface out of loopback 1343 */ 1344 outb(sc->nic_addr + ED_P0_TCR, 0); 1345 1346 /* 1347 * If this is a 3Com board, the tranceiver must be software enabled 1348 * (there is no settable hardware default). 1349 */ 1350 if (sc->vendor == ED_VENDOR_3COM) { 1351 if (ifp->if_flags & IFF_ALTPHYS) { 1352 outb(sc->asic_addr + ED_3COM_CR, 0); 1353 } else { 1354 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL); 1355 } 1356 } 1357 1358 /* 1359 * Set 'running' flag, and clear output active flag. 1360 */ 1361 ifp->if_flags |= IFF_RUNNING; 1362 ifp->if_flags &= ~IFF_OACTIVE; 1363 1364 /* 1365 * ...and attempt to start output 1366 */ 1367 ed_start(ifp); 1368 1369 (void) splx(s); 1370} 1371 1372/* 1373 * This routine actually starts the transmission on the interface 1374 */ 1375static inline void 1376ed_xmit(ifp) 1377 struct ifnet *ifp; 1378{ 1379 struct ed_softc *sc = &ed_softc[ifp->if_unit]; 1380 unsigned short len; 1381 1382 len = sc->txb_len[sc->txb_next_tx]; 1383 1384 /* 1385 * Set NIC for page 0 register access 1386 */ 1387 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA); 1388 1389 /* 1390 * Set TX buffer start page 1391 */ 1392 outb(sc->nic_addr + ED_P0_TPSR, sc->tx_page_start + 1393 sc->txb_next_tx * ED_TXBUF_SIZE); 1394 1395 /* 1396 * Set TX length 1397 */ 1398 outb(sc->nic_addr + ED_P0_TBCR0, len); 1399 outb(sc->nic_addr + ED_P0_TBCR1, len >> 8); 1400 1401 /* 1402 * Set page 0, Remote DMA complete, Transmit Packet, and *Start* 1403 */ 1404 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_TXP | ED_CR_STA); 1405 sc->xmit_busy = 1; 1406 1407 /* 1408 * Point to next transmit buffer slot and wrap if necessary. 1409 */ 1410 sc->txb_next_tx++; 1411 if (sc->txb_next_tx == sc->txb_cnt) 1412 sc->txb_next_tx = 0; 1413 1414 /* 1415 * Set a timer just in case we never hear from the board again 1416 */ 1417 ifp->if_timer = 2; 1418} 1419 1420/* 1421 * Start output on interface. 1422 * We make two assumptions here: 1423 * 1) that the current priority is set to splimp _before_ this code 1424 * is called *and* is returned to the appropriate priority after 1425 * return 1426 * 2) that the IFF_OACTIVE flag is checked before this code is called 1427 * (i.e. that the output part of the interface is idle) 1428 */ 1429void 1430ed_start(ifp) 1431 struct ifnet *ifp; 1432{ 1433 struct ed_softc *sc = &ed_softc[ifp->if_unit]; 1434 struct mbuf *m0, *m; 1435 caddr_t buffer; 1436 int len; 1437 1438outloop: 1439 1440 /* 1441 * First, see if there are buffered packets and an idle transmitter - 1442 * should never happen at this point. 1443 */ 1444 if (sc->txb_inuse && (sc->xmit_busy == 0)) { 1445 printf("ed: packets buffered, but transmitter idle\n"); 1446 ed_xmit(ifp); 1447 } 1448 1449 /* 1450 * See if there is room to put another packet in the buffer. 1451 */ 1452 if (sc->txb_inuse == sc->txb_cnt) { 1453 1454 /* 1455 * No room. Indicate this to the outside world and exit. 1456 */ 1457 ifp->if_flags |= IFF_OACTIVE; 1458 return; 1459 } 1460 IF_DEQUEUE(&sc->arpcom.ac_if.if_snd, m); 1461 if (m == 0) { 1462 1463 /* 1464 * We are using the !OACTIVE flag to indicate to the outside 1465 * world that we can accept an additional packet rather than 1466 * that the transmitter is _actually_ active. Indeed, the 1467 * transmitter may be active, but if we haven't filled all the 1468 * buffers with data then we still want to accept more. 1469 */ 1470 ifp->if_flags &= ~IFF_OACTIVE; 1471 return; 1472 } 1473 1474 /* 1475 * Copy the mbuf chain into the transmit buffer 1476 */ 1477 1478 m0 = m; 1479 1480 /* txb_new points to next open buffer slot */ 1481 buffer = sc->mem_start + (sc->txb_new * ED_TXBUF_SIZE * ED_PAGE_SIZE); 1482 1483 if (sc->mem_shared) { 1484 1485 /* 1486 * Special case setup for 16 bit boards... 1487 */ 1488 if (sc->isa16bit) { 1489 switch (sc->vendor) { 1490 1491 /* 1492 * For 16bit 3Com boards (which have 16k of 1493 * memory), we have the xmit buffers in a 1494 * different page of memory ('page 0') - so 1495 * change pages. 1496 */ 1497 case ED_VENDOR_3COM: 1498 outb(sc->asic_addr + ED_3COM_GACFR, 1499 ED_3COM_GACFR_RSEL); 1500 break; 1501 1502 /* 1503 * Enable 16bit access to shared memory on 1504 * WD/SMC boards. 1505 */ 1506 case ED_VENDOR_WD_SMC:{ 1507 outb(sc->asic_addr + ED_WD_LAAR, 1508 (sc->wd_laar_proto | ED_WD_LAAR_M16EN)); 1509 if (sc->is790) { 1510 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_MENB); 1511 } 1512 break; 1513 } 1514 } 1515 } 1516 for (len = 0; m != 0; m = m->m_next) { 1517 bcopy(mtod(m, caddr_t), buffer, m->m_len); 1518 buffer += m->m_len; 1519 len += m->m_len; 1520 } 1521 1522 /* 1523 * Restore previous shared memory access 1524 */ 1525 if (sc->isa16bit) { 1526 switch (sc->vendor) { 1527 case ED_VENDOR_3COM: 1528 outb(sc->asic_addr + ED_3COM_GACFR, 1529 ED_3COM_GACFR_RSEL | ED_3COM_GACFR_MBS0); 1530 break; 1531 case ED_VENDOR_WD_SMC:{ 1532 if (sc->is790) { 1533 outb(sc->asic_addr + ED_WD_MSR, 0x00); 1534 } 1535 outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto); 1536 break; 1537 } 1538 } 1539 } 1540 } else { 1541 len = ed_pio_write_mbufs(sc, m, buffer); 1542 } 1543 1544 sc->txb_len[sc->txb_new] = max(len, ETHER_MIN_LEN); 1545 1546 sc->txb_inuse++; 1547 1548 /* 1549 * Point to next buffer slot and wrap if necessary. 1550 */ 1551 sc->txb_new++; 1552 if (sc->txb_new == sc->txb_cnt) 1553 sc->txb_new = 0; 1554 1555 if (sc->xmit_busy == 0) 1556 ed_xmit(ifp); 1557 1558 /* 1559 * Tap off here if there is a bpf listener. 1560 */ 1561#if NBPFILTER > 0 1562 if (sc->bpf) { 1563 bpf_mtap(sc->bpf, m0); 1564 } 1565#endif 1566 1567 m_freem(m0); 1568 1569 /* 1570 * Loop back to the top to possibly buffer more packets 1571 */ 1572 goto outloop; 1573} 1574 1575/* 1576 * Ethernet interface receiver interrupt. 1577 */ 1578static inline void 1579ed_rint(unit) 1580 int unit; 1581{ 1582 register struct ed_softc *sc = &ed_softc[unit]; 1583 u_char boundry; 1584 u_short len; 1585 struct ed_ring packet_hdr; 1586 char *packet_ptr; 1587 1588 /* 1589 * Set NIC to page 1 registers to get 'current' pointer 1590 */ 1591 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA); 1592 1593 /* 1594 * 'sc->next_packet' is the logical beginning of the ring-buffer - 1595 * i.e. it points to where new data has been buffered. The 'CURR' 1596 * (current) register points to the logical end of the ring-buffer - 1597 * i.e. it points to where additional new data will be added. We loop 1598 * here until the logical beginning equals the logical end (or in 1599 * other words, until the ring-buffer is empty). 1600 */ 1601 while (sc->next_packet != inb(sc->nic_addr + ED_P1_CURR)) { 1602 1603 /* get pointer to this buffer's header structure */ 1604 packet_ptr = sc->mem_ring + 1605 (sc->next_packet - sc->rec_page_start) * ED_PAGE_SIZE; 1606 1607 /* 1608 * The byte count includes a 4 byte header that was added by 1609 * the NIC. 1610 */ 1611 if (sc->mem_shared) 1612 packet_hdr = *(struct ed_ring *) packet_ptr; 1613 else 1614 ed_pio_readmem(sc, packet_ptr, (char *) &packet_hdr, 1615 sizeof(packet_hdr)); 1616 len = packet_hdr.count; 1617 if (len > ETHER_MAX_LEN) { 1618 /* 1619 * Length is a wild value. There's a good chance that 1620 * this was caused by the NIC being old and buggy. 1621 * The bug is that the length low byte is duplicated in 1622 * the high byte. Try to recalculate the length based on 1623 * the pointer to the next packet. 1624 */ 1625 /* 1626 * NOTE: sc->next_packet is pointing at the current packet. 1627 */ 1628 len &= ED_PAGE_SIZE - 1; /* preserve offset into page */ 1629 if (packet_hdr.next_packet >= sc->next_packet) { 1630 len += (packet_hdr.next_packet - sc->next_packet) * ED_PAGE_SIZE; 1631 } else { 1632 len += ((packet_hdr.next_packet - sc->rec_page_start) + 1633 (sc->rec_page_stop - sc->next_packet)) * ED_PAGE_SIZE; 1634 } 1635 } 1636 /* 1637 * Be fairly liberal about what we allow as a "reasonable" length 1638 * so that a [crufty] packet will make it to BPF (and can thus 1639 * be analyzed). Note that all that is really important is that 1640 * we have a length that will fit into one mbuf cluster or less; 1641 * the upper layer protocols can then figure out the length from 1642 * their own length field(s). 1643 */ 1644 if ((len <= MCLBYTES) && 1645 (packet_hdr.next_packet >= sc->rec_page_start) && 1646 (packet_hdr.next_packet < sc->rec_page_stop)) { 1647 /* 1648 * Go get packet. 1649 */ 1650 ed_get_packet(sc, packet_ptr + sizeof(struct ed_ring), 1651 len - sizeof(struct ed_ring), packet_hdr.rsr & ED_RSR_PHY); 1652 ++sc->arpcom.ac_if.if_ipackets; 1653 } else { 1654 /* 1655 * Really BAD. The ring pointers are corrupted. 1656 */ 1657 log(LOG_ERR, 1658 "ed%d: NIC memory corrupt - invalid packet length %d\n", 1659 unit, len); 1660 ++sc->arpcom.ac_if.if_ierrors; 1661 ed_reset(unit); 1662 return; 1663 } 1664 1665 /* 1666 * Update next packet pointer 1667 */ 1668 sc->next_packet = packet_hdr.next_packet; 1669 1670 /* 1671 * Update NIC boundry pointer - being careful to keep it one 1672 * buffer behind. (as recommended by NS databook) 1673 */ 1674 boundry = sc->next_packet - 1; 1675 if (boundry < sc->rec_page_start) 1676 boundry = sc->rec_page_stop - 1; 1677 1678 /* 1679 * Set NIC to page 0 registers to update boundry register 1680 */ 1681 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA); 1682 1683 outb(sc->nic_addr + ED_P0_BNRY, boundry); 1684 1685 /* 1686 * Set NIC to page 1 registers before looping to top (prepare 1687 * to get 'CURR' current pointer) 1688 */ 1689 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA); 1690 } 1691} 1692 1693/* 1694 * Ethernet interface interrupt processor 1695 */ 1696void 1697edintr(unit) 1698 int unit; 1699{ 1700 struct ed_softc *sc = &ed_softc[unit]; 1701 u_char isr; 1702 1703 /* 1704 * Set NIC to page 0 registers 1705 */ 1706 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA); 1707 1708 /* 1709 * loop until there are no more new interrupts 1710 */ 1711 while ((isr = inb(sc->nic_addr + ED_P0_ISR)) != 0) { 1712 1713 /* 1714 * reset all the bits that we are 'acknowledging' by writing a 1715 * '1' to each bit position that was set (writing a '1' 1716 * *clears* the bit) 1717 */ 1718 outb(sc->nic_addr + ED_P0_ISR, isr); 1719 1720 /* 1721 * Handle transmitter interrupts. Handle these first because 1722 * the receiver will reset the board under some conditions. 1723 */ 1724 if (isr & (ED_ISR_PTX | ED_ISR_TXE)) { 1725 u_char collisions = inb(sc->nic_addr + ED_P0_NCR) & 0x0f; 1726 1727 /* 1728 * Check for transmit error. If a TX completed with an 1729 * error, we end up throwing the packet away. Really 1730 * the only error that is possible is excessive 1731 * collisions, and in this case it is best to allow 1732 * the automatic mechanisms of TCP to backoff the 1733 * flow. Of course, with UDP we're screwed, but this 1734 * is expected when a network is heavily loaded. 1735 */ 1736 (void) inb(sc->nic_addr + ED_P0_TSR); 1737 if (isr & ED_ISR_TXE) { 1738 1739 /* 1740 * Excessive collisions (16) 1741 */ 1742 if ((inb(sc->nic_addr + ED_P0_TSR) & ED_TSR_ABT) 1743 && (collisions == 0)) { 1744 1745 /* 1746 * When collisions total 16, the 1747 * P0_NCR will indicate 0, and the 1748 * TSR_ABT is set. 1749 */ 1750 collisions = 16; 1751 } 1752 1753 /* 1754 * update output errors counter 1755 */ 1756 ++sc->arpcom.ac_if.if_oerrors; 1757 } else { 1758 1759 /* 1760 * Update total number of successfully 1761 * transmitted packets. 1762 */ 1763 ++sc->arpcom.ac_if.if_opackets; 1764 } 1765 1766 /* 1767 * reset tx busy and output active flags 1768 */ 1769 sc->xmit_busy = 0; 1770 sc->arpcom.ac_if.if_flags &= ~IFF_OACTIVE; 1771 1772 /* 1773 * clear watchdog timer 1774 */ 1775 sc->arpcom.ac_if.if_timer = 0; 1776 1777 /* 1778 * Add in total number of collisions on last 1779 * transmission. 1780 */ 1781 sc->arpcom.ac_if.if_collisions += collisions; 1782 1783 /* 1784 * Decrement buffer in-use count if not zero (can only 1785 * be zero if a transmitter interrupt occured while 1786 * not actually transmitting). If data is ready to 1787 * transmit, start it transmitting, otherwise defer 1788 * until after handling receiver 1789 */ 1790 if (sc->txb_inuse && --sc->txb_inuse) 1791 ed_xmit(&sc->arpcom.ac_if); 1792 } 1793 1794 /* 1795 * Handle receiver interrupts 1796 */ 1797 if (isr & (ED_ISR_PRX | ED_ISR_RXE | ED_ISR_OVW)) { 1798 1799 /* 1800 * Overwrite warning. In order to make sure that a 1801 * lockup of the local DMA hasn't occurred, we reset 1802 * and re-init the NIC. The NSC manual suggests only a 1803 * partial reset/re-init is necessary - but some chips 1804 * seem to want more. The DMA lockup has been seen 1805 * only with early rev chips - Methinks this bug was 1806 * fixed in later revs. -DG 1807 */ 1808 if (isr & ED_ISR_OVW) { 1809 ++sc->arpcom.ac_if.if_ierrors; 1810#ifdef DIAGNOSTIC 1811 log(LOG_WARNING, 1812 "ed%d: warning - receiver ring buffer overrun\n", 1813 unit); 1814#endif 1815 1816 /* 1817 * Stop/reset/re-init NIC 1818 */ 1819 ed_reset(unit); 1820 } else { 1821 1822 /* 1823 * Receiver Error. One or more of: CRC error, 1824 * frame alignment error FIFO overrun, or 1825 * missed packet. 1826 */ 1827 if (isr & ED_ISR_RXE) { 1828 ++sc->arpcom.ac_if.if_ierrors; 1829#ifdef ED_DEBUG 1830 printf("ed%d: receive error %x\n", unit, 1831 inb(sc->nic_addr + ED_P0_RSR)); 1832#endif 1833 } 1834 1835 /* 1836 * Go get the packet(s) XXX - Doing this on an 1837 * error is dubious because there shouldn't be 1838 * any data to get (we've configured the 1839 * interface to not accept packets with 1840 * errors). 1841 */ 1842 1843 /* 1844 * Enable 16bit access to shared memory first 1845 * on WD/SMC boards. 1846 */ 1847 if (sc->isa16bit && 1848 (sc->vendor == ED_VENDOR_WD_SMC)) { 1849 1850 outb(sc->asic_addr + ED_WD_LAAR, 1851 (sc->wd_laar_proto |= 1852 ED_WD_LAAR_M16EN)); 1853 if (sc->is790) { 1854 outb(sc->asic_addr + ED_WD_MSR, 1855 ED_WD_MSR_MENB); 1856 } 1857 } 1858 ed_rint(unit); 1859 1860 /* disable 16bit access */ 1861 if (sc->isa16bit && 1862 (sc->vendor == ED_VENDOR_WD_SMC)) { 1863 1864 if (sc->is790) { 1865 outb(sc->asic_addr + ED_WD_MSR, 0x00); 1866 } 1867 outb(sc->asic_addr + ED_WD_LAAR, 1868 (sc->wd_laar_proto &= 1869 ~ED_WD_LAAR_M16EN)); 1870 } 1871 } 1872 } 1873 1874 /* 1875 * If it looks like the transmitter can take more data, 1876 * attempt to start output on the interface. This is done 1877 * after handling the receiver to give the receiver priority. 1878 */ 1879 if ((sc->arpcom.ac_if.if_flags & IFF_OACTIVE) == 0) 1880 ed_start(&sc->arpcom.ac_if); 1881 1882 /* 1883 * return NIC CR to standard state: page 0, remote DMA 1884 * complete, start (toggling the TXP bit off, even if was just 1885 * set in the transmit routine, is *okay* - it is 'edge' 1886 * triggered from low to high) 1887 */ 1888 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA); 1889 1890 /* 1891 * If the Network Talley Counters overflow, read them to reset 1892 * them. It appears that old 8390's won't clear the ISR flag 1893 * otherwise - resulting in an infinite loop. 1894 */ 1895 if (isr & ED_ISR_CNT) { 1896 (void) inb(sc->nic_addr + ED_P0_CNTR0); 1897 (void) inb(sc->nic_addr + ED_P0_CNTR1); 1898 (void) inb(sc->nic_addr + ED_P0_CNTR2); 1899 } 1900 } 1901} 1902 1903/* 1904 * Process an ioctl request. This code needs some work - it looks 1905 * pretty ugly. 1906 */ 1907int 1908ed_ioctl(ifp, command, data) 1909 register struct ifnet *ifp; 1910 int command; 1911 caddr_t data; 1912{ 1913 register struct ifaddr *ifa = (struct ifaddr *) data; 1914 struct ed_softc *sc = &ed_softc[ifp->if_unit]; 1915 struct ifreq *ifr = (struct ifreq *) data; 1916 int s, error = 0; 1917 1918 s = splimp(); 1919 1920 switch (command) { 1921 1922 case SIOCSIFADDR: 1923 ifp->if_flags |= IFF_UP; 1924 1925 switch (ifa->ifa_addr->sa_family) { 1926#ifdef INET 1927 case AF_INET: 1928 ed_init(ifp->if_unit); /* before arpwhohas */ 1929 1930 /* 1931 * See if another station has *our* IP address. i.e.: 1932 * There is an address conflict! If a conflict exists, 1933 * a message is sent to the console. 1934 */ 1935 ((struct arpcom *) ifp)->ac_ipaddr = IA_SIN(ifa)->sin_addr; 1936 arpwhohas((struct arpcom *) ifp, &IA_SIN(ifa)->sin_addr); 1937 break; 1938#endif 1939#ifdef NS 1940 1941 /* 1942 * XXX - This code is probably wrong 1943 */ 1944 case AF_NS: 1945 { 1946 register struct ns_addr *ina = &(IA_SNS(ifa)->sns_addr); 1947 1948 if (ns_nullhost(*ina)) 1949 ina->x_host = 1950 *(union ns_host *) (sc->arpcom.ac_enaddr); 1951 else { 1952 bcopy((caddr_t) ina->x_host.c_host, 1953 (caddr_t) sc->arpcom.ac_enaddr, 1954 sizeof(sc->arpcom.ac_enaddr)); 1955 } 1956 1957 /* 1958 * Set new address 1959 */ 1960 ed_init(ifp->if_unit); 1961 break; 1962 } 1963#endif 1964 default: 1965 ed_init(ifp->if_unit); 1966 break; 1967 } 1968 break; 1969 1970 case SIOCGIFADDR: 1971 { 1972 struct sockaddr *sa; 1973 1974 sa = (struct sockaddr *) & ifr->ifr_data; 1975 bcopy((caddr_t) sc->arpcom.ac_enaddr, 1976 (caddr_t) sa->sa_data, ETHER_ADDR_LEN); 1977 } 1978 break; 1979 1980 case SIOCSIFFLAGS: 1981 1982 /* 1983 * If interface is marked down and it is running, then stop it 1984 */ 1985 if (((ifp->if_flags & IFF_UP) == 0) && 1986 (ifp->if_flags & IFF_RUNNING)) { 1987 ed_stop(ifp->if_unit); 1988 ifp->if_flags &= ~IFF_RUNNING; 1989 } else { 1990 1991 /* 1992 * If interface is marked up and it is stopped, then 1993 * start it 1994 */ 1995 if ((ifp->if_flags & IFF_UP) && 1996 ((ifp->if_flags & IFF_RUNNING) == 0)) 1997 ed_init(ifp->if_unit); 1998 } 1999 2000#if NBPFILTER > 0 2001 2002 /* 2003 * Promiscuous flag may have changed, so reprogram the RCR. 2004 */ 2005 ed_setrcr(ifp, sc); 2006#endif 2007 2008 /* 2009 * An unfortunate hack to provide the (required) software 2010 * control of the tranceiver for 3Com boards. The ALTPHYS flag 2011 * disables the tranceiver if set. 2012 */ 2013 if (sc->vendor == ED_VENDOR_3COM) { 2014 if (ifp->if_flags & IFF_ALTPHYS) { 2015 outb(sc->asic_addr + ED_3COM_CR, 0); 2016 } else { 2017 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL); 2018 } 2019 } 2020 break; 2021 2022 case SIOCADDMULTI: 2023 case SIOCDELMULTI: 2024 /* 2025 * Update out multicast list. 2026 */ 2027 error = (command == SIOCADDMULTI) ? 2028 ether_addmulti(ifr, &sc->arpcom) : 2029 ether_delmulti(ifr, &sc->arpcom); 2030 2031 if (error == ENETRESET) { 2032 2033 /* 2034 * Multicast list has changed; set the hardware filter 2035 * accordingly. 2036 */ 2037 ed_setrcr(ifp, sc); 2038 error = 0; 2039 } 2040 break; 2041 2042 case SIOCSIFMTU: 2043 /* 2044 * Set the interface MTU. 2045 */ 2046 if (ifr->ifr_mtu > ETHERMTU) { 2047 error = EINVAL; 2048 } else { 2049 ifp->if_mtu = ifr->ifr_mtu; 2050 } 2051 break; 2052 2053 default: 2054 error = EINVAL; 2055 } 2056 (void) splx(s); 2057 return (error); 2058} 2059 2060/* 2061 * Macro to calculate a new address within shared memory when given an offset 2062 * from an address, taking into account ring-wrap. 2063 */ 2064#define ringoffset(sc, start, off, type) \ 2065 ((type)( ((caddr_t)(start)+(off) >= (sc)->mem_end) ? \ 2066 (((caddr_t)(start)+(off))) - (sc)->mem_end \ 2067 + (sc)->mem_ring: \ 2068 ((caddr_t)(start)+(off)) )) 2069 2070/* 2071 * Retreive packet from shared memory and send to the next level up via 2072 * ether_input(). If there is a BPF listener, give a copy to BPF, too. 2073 */ 2074static void 2075ed_get_packet(sc, buf, len, multicast) 2076 struct ed_softc *sc; 2077 char *buf; 2078 u_short len; 2079 int multicast; 2080{ 2081 struct ether_header *eh; 2082 struct mbuf *m, *ed_ring_to_mbuf(); 2083 2084 /* Allocate a header mbuf */ 2085 MGETHDR(m, M_DONTWAIT, MT_DATA); 2086 if (m == NULL) 2087 return; 2088 m->m_pkthdr.rcvif = &sc->arpcom.ac_if; 2089 m->m_pkthdr.len = len; 2090 m->m_len = 0; 2091 2092 /* The following sillines is to make NFS happy */ 2093#define EROUND ((sizeof(struct ether_header) + 3) & ~3) 2094#define EOFF (EROUND - sizeof(struct ether_header)) 2095 2096 /* 2097 * The following assumes there is room for the ether header in the 2098 * header mbuf 2099 */ 2100 m->m_data += EOFF; 2101 eh = mtod(m, struct ether_header *); 2102 2103 if (sc->mem_shared) 2104 bcopy(buf, mtod(m, caddr_t), sizeof(struct ether_header)); 2105 else 2106 ed_pio_readmem(sc, buf, mtod(m, caddr_t), 2107 sizeof(struct ether_header)); 2108 buf += sizeof(struct ether_header); 2109 m->m_len += sizeof(struct ether_header); 2110 len -= sizeof(struct ether_header); 2111 2112 /* 2113 * Pull packet off interface. Or if this was a trailer packet, the 2114 * data portion is appended. 2115 */ 2116 if (ed_ring_to_mbuf(sc, buf, m, len) == NULL) { 2117 m_freem(m); 2118 return; 2119 } 2120 2121#if NBPFILTER > 0 2122 2123 /* 2124 * Check if there's a BPF listener on this interface. If so, hand off 2125 * the raw packet to bpf. 2126 */ 2127 if (sc->bpf) { 2128 bpf_mtap(sc->bpf, m); 2129 2130 /* 2131 * Note that the interface cannot be in promiscuous mode if 2132 * there are no BPF listeners. And if we are in promiscuous 2133 * mode, we have to check if this packet is really ours. 2134 */ 2135 if ((sc->arpcom.ac_if.if_flags & IFF_PROMISC) && 2136 bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr, 2137 sizeof(eh->ether_dhost)) != 0 && multicast == 0) { 2138 m_freem(m); 2139 return; 2140 } 2141 } 2142#endif 2143 2144 /* 2145 * Fix up data start offset in mbuf to point past ether header 2146 */ 2147 m_adj(m, sizeof(struct ether_header)); 2148 2149 /* 2150 * silly ether_input routine needs 'type' in host byte order 2151 */ 2152 eh->ether_type = ntohs(eh->ether_type); 2153 2154 ether_input(&sc->arpcom.ac_if, eh, m); 2155 return; 2156} 2157 2158/* 2159 * Supporting routines 2160 */ 2161 2162/* 2163 * Given a NIC memory source address and a host memory destination 2164 * address, copy 'amount' from NIC to host using Programmed I/O. 2165 * The 'amount' is rounded up to a word - okay as long as mbufs 2166 * are word sized. 2167 * This routine is currently Novell-specific. 2168 */ 2169void 2170ed_pio_readmem(sc, src, dst, amount) 2171 struct ed_softc *sc; 2172 unsigned short src; 2173 unsigned char *dst; 2174 unsigned short amount; 2175{ 2176 unsigned short tmp_amount; 2177 2178 /* select page 0 registers */ 2179 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STA); 2180 2181 /* round up to a word */ 2182 tmp_amount = amount; 2183 if (amount & 1) 2184 ++amount; 2185 2186 /* set up DMA byte count */ 2187 outb(sc->nic_addr + ED_P0_RBCR0, amount); 2188 outb(sc->nic_addr + ED_P0_RBCR1, amount >> 8); 2189 2190 /* set up source address in NIC mem */ 2191 outb(sc->nic_addr + ED_P0_RSAR0, src); 2192 outb(sc->nic_addr + ED_P0_RSAR1, src >> 8); 2193 2194 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD0 | ED_CR_STA); 2195 2196 if (sc->isa16bit) { 2197 insw(sc->asic_addr + ED_NOVELL_DATA, dst, amount / 2); 2198 } else 2199 insb(sc->asic_addr + ED_NOVELL_DATA, dst, amount); 2200 2201} 2202 2203/* 2204 * Stripped down routine for writing a linear buffer to NIC memory. 2205 * Only used in the probe routine to test the memory. 'len' must 2206 * be even. 2207 */ 2208void 2209ed_pio_writemem(sc, src, dst, len) 2210 struct ed_softc *sc; 2211 char *src; 2212 unsigned short dst; 2213 unsigned short len; 2214{ 2215 int maxwait = 100; /* about 120us */ 2216 2217 /* select page 0 registers */ 2218 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STA); 2219 2220 /* reset remote DMA complete flag */ 2221 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC); 2222 2223 /* set up DMA byte count */ 2224 outb(sc->nic_addr + ED_P0_RBCR0, len); 2225 outb(sc->nic_addr + ED_P0_RBCR1, len >> 8); 2226 2227 /* set up destination address in NIC mem */ 2228 outb(sc->nic_addr + ED_P0_RSAR0, dst); 2229 outb(sc->nic_addr + ED_P0_RSAR1, dst >> 8); 2230 2231 /* set remote DMA write */ 2232 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD1 | ED_CR_STA); 2233 2234 if (sc->isa16bit) 2235 outsw(sc->asic_addr + ED_NOVELL_DATA, src, len / 2); 2236 else 2237 outsb(sc->asic_addr + ED_NOVELL_DATA, src, len); 2238 2239 /* 2240 * Wait for remote DMA complete. This is necessary because on the 2241 * transmit side, data is handled internally by the NIC in bursts and 2242 * we can't start another remote DMA until this one completes. Not 2243 * waiting causes really bad things to happen - like the NIC 2244 * irrecoverably jamming the ISA bus. 2245 */ 2246 while (((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait); 2247} 2248 2249/* 2250 * Write an mbuf chain to the destination NIC memory address using 2251 * programmed I/O. 2252 */ 2253u_short 2254ed_pio_write_mbufs(sc, m, dst) 2255 struct ed_softc *sc; 2256 struct mbuf *m; 2257 unsigned short dst; 2258{ 2259 unsigned short len; 2260 struct mbuf *mp; 2261 int maxwait = 100; /* about 120us */ 2262 2263 /* First, count up the total number of bytes to copy */ 2264 for (len = 0, mp = m; mp; mp = mp->m_next) 2265 len += mp->m_len; 2266 2267 /* select page 0 registers */ 2268 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STA); 2269 2270 /* reset remote DMA complete flag */ 2271 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC); 2272 2273 /* set up DMA byte count */ 2274 outb(sc->nic_addr + ED_P0_RBCR0, len); 2275 outb(sc->nic_addr + ED_P0_RBCR1, len >> 8); 2276 2277 /* set up destination address in NIC mem */ 2278 outb(sc->nic_addr + ED_P0_RSAR0, dst); 2279 outb(sc->nic_addr + ED_P0_RSAR1, dst >> 8); 2280 2281 /* set remote DMA write */ 2282 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD1 | ED_CR_STA); 2283 2284 /* 2285 * Transfer the mbuf chain to the NIC memory. 2286 * 16-bit cards require that data be transferred as words, and only words. 2287 * So that case requires some extra code to patch over odd-length mbufs. 2288 */ 2289 2290 if (!sc->isa16bit) { 2291 /* NE1000s are easy */ 2292 while (m) { 2293 if (m->m_len) { 2294 outsb(sc->asic_addr + ED_NOVELL_DATA, 2295 m->m_data, m->m_len); 2296 } 2297 m = m->m_next; 2298 } 2299 } else { 2300 /* NE2000s are a pain */ 2301 unsigned char *data; 2302 int len, wantbyte; 2303 unsigned char savebyte[2]; 2304 2305 wantbyte = 0; 2306 2307 while (m) { 2308 data = mtod(m, caddr_t); 2309 len = m->m_len; 2310 if (len) { 2311 /* finish the last word */ 2312 if (wantbyte) { 2313 savebyte[1] = *data; 2314 outw(sc->asic_addr + ED_NOVELL_DATA, 2315 *((unsigned short *) savebyte)); 2316 data++; 2317 len--; 2318 wantbyte = 0; 2319 } 2320 /* output contiguous words */ 2321 if (len > 1) { 2322 outsw(sc->asic_addr + ED_NOVELL_DATA, 2323 data, len >> 1); 2324 data += len & ~1; 2325 len &= 1; 2326 } 2327 /* save last byte, if necessary */ 2328 if (len == 1) { 2329 savebyte[0] = *data; 2330 wantbyte = 1; 2331 } 2332 } 2333 m = m->m_next; 2334 } 2335 /* spit last byte */ 2336 if (wantbyte) 2337 outw(sc->asic_addr + ED_NOVELL_DATA, 2338 *((unsigned short *) savebyte)); 2339 } 2340 2341 /* 2342 * Wait for remote DMA complete. This is necessary because on the 2343 * transmit side, data is handled internally by the NIC in bursts and 2344 * we can't start another remote DMA until this one completes. Not 2345 * waiting causes really bad things to happen - like the NIC 2346 * irrecoverably jamming the ISA bus. 2347 */ 2348 while (((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait); 2349 2350 if (!maxwait) { 2351 log(LOG_WARNING, "ed%d: remote transmit DMA failed to complete\n", 2352 sc->arpcom.ac_if.if_unit); 2353 ed_reset(sc->arpcom.ac_if.if_unit); 2354 } 2355 return (len); 2356} 2357 2358/* 2359 * Given a source and destination address, copy 'amount' of a packet from 2360 * the ring buffer into a linear destination buffer. Takes into account 2361 * ring-wrap. 2362 */ 2363static inline char * 2364ed_ring_copy(sc, src, dst, amount) 2365 struct ed_softc *sc; 2366 char *src; 2367 char *dst; 2368 u_short amount; 2369{ 2370 u_short tmp_amount; 2371 2372 /* does copy wrap to lower addr in ring buffer? */ 2373 if (src + amount > sc->mem_end) { 2374 tmp_amount = sc->mem_end - src; 2375 2376 /* copy amount up to end of NIC memory */ 2377 if (sc->mem_shared) 2378 bcopy(src, dst, tmp_amount); 2379 else 2380 ed_pio_readmem(sc, src, dst, tmp_amount); 2381 2382 amount -= tmp_amount; 2383 src = sc->mem_ring; 2384 dst += tmp_amount; 2385 } 2386 if (sc->mem_shared) 2387 bcopy(src, dst, amount); 2388 else 2389 ed_pio_readmem(sc, src, dst, amount); 2390 2391 return (src + amount); 2392} 2393 2394/* 2395 * Copy data from receive buffer to end of mbuf chain 2396 * allocate additional mbufs as needed. return pointer 2397 * to last mbuf in chain. 2398 * sc = ed info (softc) 2399 * src = pointer in ed ring buffer 2400 * dst = pointer to last mbuf in mbuf chain to copy to 2401 * amount = amount of data to copy 2402 */ 2403struct mbuf * 2404ed_ring_to_mbuf(sc, src, dst, total_len) 2405 struct ed_softc *sc; 2406 char *src; 2407 struct mbuf *dst; 2408 u_short total_len; 2409{ 2410 register struct mbuf *m = dst; 2411 2412 while (total_len) { 2413 register u_short amount = min(total_len, M_TRAILINGSPACE(m)); 2414 2415 if (amount == 0) { /* no more data in this mbuf, alloc 2416 * another */ 2417 2418 /* 2419 * If there is enough data for an mbuf cluster, 2420 * attempt to allocate one of those, otherwise, a 2421 * regular mbuf will do. Note that a regular mbuf is 2422 * always required, even if we get a cluster - getting 2423 * a cluster does not allocate any mbufs, and one is 2424 * needed to assign the cluster to. The mbuf that has 2425 * a cluster extension can not be used to contain data 2426 * - only the cluster can contain data. 2427 */ 2428 dst = m; 2429 MGET(m, M_DONTWAIT, MT_DATA); 2430 if (m == 0) 2431 return (0); 2432 2433 if (total_len >= MINCLSIZE) 2434 MCLGET(m, M_DONTWAIT); 2435 2436 m->m_len = 0; 2437 dst->m_next = m; 2438 amount = min(total_len, M_TRAILINGSPACE(m)); 2439 } 2440 src = ed_ring_copy(sc, src, mtod(m, caddr_t) + m->m_len, amount); 2441 2442 m->m_len += amount; 2443 total_len -= amount; 2444 2445 } 2446 return (m); 2447} 2448 2449void 2450ed_setrcr(ifp, sc) 2451 struct ifnet *ifp; 2452 struct ed_softc *sc; 2453{ 2454 int i; 2455 2456 /* set page 1 registers */ 2457 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP); 2458 2459 if (ifp->if_flags & IFF_PROMISC) { 2460 2461 /* 2462 * Reconfigure the multicast filter. 2463 */ 2464 for (i = 0; i < 8; i++) 2465 outb(sc->nic_addr + ED_P1_MAR0 + i, 0xff); 2466 2467 /* 2468 * And turn on promiscuous mode. Also enable reception of 2469 * runts and packets with CRC & alignment errors. 2470 */ 2471 /* Set page 0 registers */ 2472 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP); 2473 2474 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_PRO | ED_RCR_AM | 2475 ED_RCR_AB | ED_RCR_AR | ED_RCR_SEP); 2476 } else { 2477 /* set up multicast addresses and filter modes */ 2478 if (ifp->if_flags & IFF_MULTICAST) { 2479 u_long mcaf[2]; 2480 2481 if (ifp->if_flags & IFF_ALLMULTI) { 2482 mcaf[0] = 0xffffffff; 2483 mcaf[1] = 0xffffffff; 2484 } else 2485 ds_getmcaf(sc, mcaf); 2486 2487 /* 2488 * Set multicast filter on chip. 2489 */ 2490 for (i = 0; i < 8; i++) 2491 outb(sc->nic_addr + ED_P1_MAR0 + i, ((u_char *) mcaf)[i]); 2492 2493 /* Set page 0 registers */ 2494 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP); 2495 2496 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_AM | ED_RCR_AB); 2497 } else { 2498 2499 /* 2500 * Initialize multicast address hashing registers to 2501 * not accept multicasts. 2502 */ 2503 for (i = 0; i < 8; ++i) 2504 outb(sc->nic_addr + ED_P1_MAR0 + i, 0x00); 2505 2506 /* Set page 0 registers */ 2507 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP); 2508 2509 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_AB); 2510 } 2511 } 2512 2513 /* 2514 * Start interface. 2515 */ 2516 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA); 2517} 2518 2519/* 2520 * Compute crc for ethernet address 2521 */ 2522u_long 2523ds_crc(ep) 2524 u_char *ep; 2525{ 2526#define POLYNOMIAL 0x04c11db6 2527 register u_long crc = 0xffffffffL; 2528 register int carry, i, j; 2529 register u_char b; 2530 2531 for (i = 6; --i >= 0;) { 2532 b = *ep++; 2533 for (j = 8; --j >= 0;) { 2534 carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01); 2535 crc <<= 1; 2536 b >>= 1; 2537 if (carry) 2538 crc = ((crc ^ POLYNOMIAL) | carry); 2539 } 2540 } 2541 return crc; 2542#undef POLYNOMIAL 2543} 2544 2545/* 2546 * Compute the multicast address filter from the 2547 * list of multicast addresses we need to listen to. 2548 */ 2549void 2550ds_getmcaf(sc, mcaf) 2551 struct ed_softc *sc; 2552 u_long *mcaf; 2553{ 2554 register u_int index; 2555 register u_char *af = (u_char *) mcaf; 2556 register struct ether_multi *enm; 2557 register struct ether_multistep step; 2558 2559 mcaf[0] = 0; 2560 mcaf[1] = 0; 2561 2562 ETHER_FIRST_MULTI(step, &sc->arpcom, enm); 2563 while (enm != NULL) { 2564 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 6) != 0) { 2565 mcaf[0] = 0xffffffff; 2566 mcaf[1] = 0xffffffff; 2567 return; 2568 } 2569 index = ds_crc(enm->enm_addrlo, 6) >> 26; 2570 af[index >> 3] |= 1 << (index & 7); 2571 2572 ETHER_NEXT_MULTI(step, enm); 2573 } 2574} 2575