if_ed.c revision 44829
1/* 2 * Copyright (c) 1995, David Greenman 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $Id: if_ed.c,v 1.149 1999/01/28 01:59:53 dillon Exp $ 28 */ 29 30/* 31 * Device driver for National Semiconductor DS8390/WD83C690 based ethernet 32 * adapters. By David Greenman, 29-April-1993 33 * 34 * Currently supports the Western Digital/SMC 8003 and 8013 series, 35 * the SMC Elite Ultra (8216), the 3Com 3c503, the NE1000 and NE2000, 36 * and a variety of similar clones. 37 * 38 */ 39 40#include "ed.h" 41#include "bpfilter.h" 42#include "pnp.h" 43 44#ifndef EXTRA_ED 45# if NPNP > 0 46# define EXTRA_ED 8 47# else 48# define EXTRA_ED 0 49# endif 50#endif 51 52#define NEDTOT (NED + EXTRA_ED) 53 54#include <sys/param.h> 55#include <sys/systm.h> 56#include <sys/sockio.h> 57#include <sys/malloc.h> 58#include <sys/mbuf.h> 59#include <sys/socket.h> 60#include <sys/syslog.h> 61 62#include <net/ethernet.h> 63#include <net/if.h> 64#include <net/if_arp.h> 65#include <net/if_dl.h> 66#include <net/if_mib.h> 67 68#if NBPFILTER > 0 69#include <net/bpf.h> 70#endif 71#include "opt_bdg.h" 72#ifdef BRIDGE 73#include <net/bridge.h> 74#endif 75 76#include <machine/clock.h> 77#include <machine/md_var.h> 78 79#include <i386/isa/isa_device.h> 80#include <i386/isa/icu.h> 81#include <i386/isa/if_edreg.h> 82 83#if NPNP > 0 84#include <i386/isa/pnp.h> 85#endif 86 87/* 88 * ed_softc: per line info and status 89 */ 90struct ed_softc { 91 struct arpcom arpcom; /* ethernet common */ 92 93 char *type_str; /* pointer to type string */ 94 u_char vendor; /* interface vendor */ 95 u_char type; /* interface type code */ 96 u_char gone; /* HW missing, presumed having a good time */ 97 98 u_short asic_addr; /* ASIC I/O bus address */ 99 u_short nic_addr; /* NIC (DS8390) I/O bus address */ 100 101/* 102 * The following 'proto' variable is part of a work-around for 8013EBT asics 103 * being write-only. It's sort of a prototype/shadow of the real thing. 104 */ 105 u_char wd_laar_proto; 106 u_char cr_proto; 107 u_char isa16bit; /* width of access to card 0=8 or 1=16 */ 108 int is790; /* set by the probe code if the card is 790 109 * based */ 110 111/* 112 * HP PC LAN PLUS card support. 113 */ 114 115 u_short hpp_options; /* flags controlling behaviour of the HP card */ 116 u_short hpp_id; /* software revision and other fields */ 117 caddr_t hpp_mem_start; /* Memory-mapped IO register address */ 118 119 caddr_t mem_start; /* NIC memory start address */ 120 caddr_t mem_end; /* NIC memory end address */ 121 u_long mem_size; /* total NIC memory size */ 122 caddr_t mem_ring; /* start of RX ring-buffer (in NIC mem) */ 123 124 u_char mem_shared; /* NIC memory is shared with host */ 125 u_char xmit_busy; /* transmitter is busy */ 126 u_char txb_cnt; /* number of transmit buffers */ 127 u_char txb_inuse; /* number of TX buffers currently in-use */ 128 129 u_char txb_new; /* pointer to where new buffer will be added */ 130 u_char txb_next_tx; /* pointer to next buffer ready to xmit */ 131 u_short txb_len[8]; /* buffered xmit buffer lengths */ 132 u_char tx_page_start; /* first page of TX buffer area */ 133 u_char rec_page_start; /* first page of RX ring-buffer */ 134 u_char rec_page_stop; /* last page of RX ring-buffer */ 135 u_char next_packet; /* pointer to next unread RX packet */ 136 struct ifmib_iso_8802_3 mibdata; /* stuff for network mgmt */ 137}; 138 139static struct ed_softc ed_softc[NEDTOT]; 140 141static int ed_attach __P((struct ed_softc *, int, int)); 142static int ed_attach_isa __P((struct isa_device *)); 143 144static void ed_init __P((void *)); 145static ointhand2_t edintr; 146static int ed_ioctl __P((struct ifnet *, u_long, caddr_t)); 147static int ed_probe __P((struct isa_device *)); 148static void ed_start __P((struct ifnet *)); 149static void ed_reset __P((struct ifnet *)); 150static void ed_watchdog __P((struct ifnet *)); 151 152static void ed_stop __P((struct ed_softc *)); 153static int ed_probe_generic8390 __P((struct ed_softc *)); 154static int ed_probe_WD80x3 __P((struct isa_device *)); 155static int ed_probe_3Com __P((struct isa_device *)); 156static int ed_probe_Novell __P((struct isa_device *)); 157static int ed_probe_Novell_generic __P((struct ed_softc *, int, int, int)); 158static int ed_probe_HP_pclanp __P((struct isa_device *)); 159 160#include "pci.h" 161#if NPCI > 0 162void *ed_attach_NE2000_pci __P((int, int)); 163#endif 164 165#include "card.h" 166#if NCARD > 0 167static int ed_probe_pccard __P((struct isa_device *, u_char *)); 168#endif 169 170static void ds_getmcaf __P((struct ed_softc *, u_long *)); 171 172static void ed_get_packet __P((struct ed_softc *, char *, /* u_short */ int, int)); 173 174static __inline void ed_rint __P((struct ed_softc *)); 175static __inline void ed_xmit __P((struct ed_softc *)); 176static __inline char * ed_ring_copy __P((struct ed_softc *, char *, char *, 177 /* u_short */ int)); 178static void ed_hpp_set_physical_link __P((struct ed_softc *)); 179static void ed_hpp_readmem __P((struct ed_softc *, int, unsigned char *, 180 /* u_short */ int)); 181static u_short ed_hpp_write_mbufs __P((struct ed_softc *, struct mbuf *, 182 int)); 183 184static void ed_pio_readmem __P((struct ed_softc *, int, unsigned char *, 185 /* u_short */ int)); 186static void ed_pio_writemem __P((struct ed_softc *, char *, 187 /* u_short */ int, /* u_short */ int)); 188static u_short ed_pio_write_mbufs __P((struct ed_softc *, struct mbuf *, 189 int)); 190void edintr_sc __P((struct ed_softc *)); 191 192static void ed_setrcr __P((struct ed_softc *)); 193 194static u_long ds_crc __P((u_char *ep)); 195 196#if (NCARD > 0) || (NPNP > 0) 197#include <sys/kernel.h> 198#endif 199#if NCARD > 0 200#include <sys/select.h> 201#include <sys/module.h> 202#include <pccard/cardinfo.h> 203#include <pccard/slot.h> 204 205/* 206 * PC-Card (PCMCIA) specific code. 207 */ 208static int edinit __P((struct pccard_devinfo *)); 209static void edunload __P((struct pccard_devinfo *)); 210static int card_intr __P((struct pccard_devinfo *)); 211 212PCCARD_MODULE(ed, edinit, edunload, card_intr, 0, net_imask); 213 214/* 215 * Initialize the device - called from Slot manager. 216 */ 217static int 218edinit(struct pccard_devinfo *devi) 219{ 220 int i; 221 u_char e; 222 struct ed_softc *sc = &ed_softc[devi->isahd.id_unit]; 223 224 /* validate unit number. */ 225 if (devi->isahd.id_unit >= NEDTOT) 226 return(ENODEV); 227 /* 228 * Probe the device. If a value is returned, the 229 * device was found at the location. 230 */ 231 sc->gone = 0; 232 if (ed_probe_pccard(&devi->isahd, devi->misc) == 0) 233 return(ENXIO); 234 e = 0; 235 for (i = 0; i < ETHER_ADDR_LEN; ++i) 236 e |= devi->misc[i]; 237 if (e) 238 for (i = 0; i < ETHER_ADDR_LEN; ++i) 239 sc->arpcom.ac_enaddr[i] = devi->misc[i]; 240 if (ed_attach_isa(&devi->isahd) == 0) 241 return(ENXIO); 242 243 return(0); 244} 245 246/* 247 * edunload - unload the driver and clear the table. 248 * XXX TODO: 249 * This is usually called when the card is ejected, but 250 * can be caused by a modunload of a controller driver. 251 * The idea is to reset the driver's view of the device 252 * and ensure that any driver entry points such as 253 * read and write do not hang. 254 */ 255static void 256edunload(struct pccard_devinfo *devi) 257{ 258 struct ed_softc *sc = &ed_softc[devi->isahd.id_unit]; 259 struct ifnet *ifp = &sc->arpcom.ac_if; 260 261 if (sc->gone) { 262 printf("ed%d: already unloaded\n", devi->isahd.id_unit); 263 return; 264 } 265 ifp->if_flags &= ~IFF_RUNNING; 266 if_down(ifp); 267 sc->gone = 1; 268 printf("ed%d: unload\n", devi->isahd.id_unit); 269} 270 271/* 272 * card_intr - Shared interrupt called from 273 * front end of PC-Card handler. 274 */ 275static int 276card_intr(struct pccard_devinfo *devi) 277{ 278 edintr_sc(&ed_softc[devi->isahd.id_unit]); 279 return(1); 280} 281#endif /* NCARD > 0 */ 282 283struct isa_driver eddriver = { 284 ed_probe, 285 ed_attach_isa, 286 "ed", 287 1 /* We are ultra sensitive */ 288}; 289 290/* 291 * Interrupt conversion table for WD/SMC ASIC/83C584 292 * (IRQ* are defined in icu.h) 293 */ 294static unsigned short ed_intr_mask[] = { 295 IRQ9, 296 IRQ3, 297 IRQ5, 298 IRQ7, 299 IRQ10, 300 IRQ11, 301 IRQ15, 302 IRQ4 303}; 304 305/* 306 * Interrupt conversion table for 83C790 307 */ 308static unsigned short ed_790_intr_mask[] = { 309 0, 310 IRQ9, 311 IRQ3, 312 IRQ5, 313 IRQ7, 314 IRQ10, 315 IRQ11, 316 IRQ15 317}; 318 319/* 320 * Interrupt conversion table for the HP PC LAN+ 321 */ 322 323static unsigned short ed_hpp_intr_mask[] = { 324 0, /* 0 */ 325 0, /* 1 */ 326 0, /* 2 */ 327 IRQ3, /* 3 */ 328 IRQ4, /* 4 */ 329 IRQ5, /* 5 */ 330 IRQ6, /* 6 */ 331 IRQ7, /* 7 */ 332 0, /* 8 */ 333 IRQ9, /* 9 */ 334 IRQ10, /* 10 */ 335 IRQ11, /* 11 */ 336 IRQ12, /* 12 */ 337 0, /* 13 */ 338 0, /* 14 */ 339 IRQ15 /* 15 */ 340}; 341 342/* 343 * Determine if the device is present 344 * 345 * on entry: 346 * a pointer to an isa_device struct 347 * on exit: 348 * NULL if device not found 349 * or # of i/o addresses used (if found) 350 */ 351static int 352ed_probe(isa_dev) 353 struct isa_device *isa_dev; 354{ 355 int nports; 356 357 nports = ed_probe_WD80x3(isa_dev); 358 if (nports) 359 return (nports); 360 361 nports = ed_probe_3Com(isa_dev); 362 if (nports) 363 return (nports); 364 365 nports = ed_probe_Novell(isa_dev); 366 if (nports) 367 return (nports); 368 369 nports = ed_probe_HP_pclanp(isa_dev); 370 if (nports) 371 return (nports); 372 373 return (0); 374} 375 376/* 377 * Generic probe routine for testing for the existance of a DS8390. 378 * Must be called after the NIC has just been reset. This routine 379 * works by looking at certain register values that are guaranteed 380 * to be initialized a certain way after power-up or reset. Seems 381 * not to currently work on the 83C690. 382 * 383 * Specifically: 384 * 385 * Register reset bits set bits 386 * Command Register (CR) TXP, STA RD2, STP 387 * Interrupt Status (ISR) RST 388 * Interrupt Mask (IMR) All bits 389 * Data Control (DCR) LAS 390 * Transmit Config. (TCR) LB1, LB0 391 * 392 * We only look at the CR and ISR registers, however, because looking at 393 * the others would require changing register pages (which would be 394 * intrusive if this isn't an 8390). 395 * 396 * Return 1 if 8390 was found, 0 if not. 397 */ 398 399static int 400ed_probe_generic8390(sc) 401 struct ed_softc *sc; 402{ 403 if ((inb(sc->nic_addr + ED_P0_CR) & 404 (ED_CR_RD2 | ED_CR_TXP | ED_CR_STA | ED_CR_STP)) != 405 (ED_CR_RD2 | ED_CR_STP)) 406 return (0); 407 if ((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RST) != ED_ISR_RST) 408 return (0); 409 410 return (1); 411} 412 413/* 414 * Probe and vendor-specific initialization routine for SMC/WD80x3 boards 415 */ 416static int 417ed_probe_WD80x3(isa_dev) 418 struct isa_device *isa_dev; 419{ 420 struct ed_softc *sc = &ed_softc[isa_dev->id_unit]; 421 int i; 422 u_int memsize, maddr; 423 u_char iptr, isa16bit, sum; 424 425 sc->asic_addr = isa_dev->id_iobase; 426 sc->nic_addr = sc->asic_addr + ED_WD_NIC_OFFSET; 427 sc->is790 = 0; 428 429#ifdef TOSH_ETHER 430 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_POW); 431 DELAY(10000); 432#endif 433 434 /* 435 * Attempt to do a checksum over the station address PROM. If it 436 * fails, it's probably not a SMC/WD board. There is a problem with 437 * this, though: some clone WD boards don't pass the checksum test. 438 * Danpex boards for one. 439 */ 440 for (sum = 0, i = 0; i < 8; ++i) 441 sum += inb(sc->asic_addr + ED_WD_PROM + i); 442 443 if (sum != ED_WD_ROM_CHECKSUM_TOTAL) { 444 445 /* 446 * Checksum is invalid. This often happens with cheap WD8003E 447 * clones. In this case, the checksum byte (the eighth byte) 448 * seems to always be zero. 449 */ 450 if (inb(sc->asic_addr + ED_WD_CARD_ID) != ED_TYPE_WD8003E || 451 inb(sc->asic_addr + ED_WD_PROM + 7) != 0) 452 return (0); 453 } 454 /* reset card to force it into a known state. */ 455#ifdef TOSH_ETHER 456 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_RST | ED_WD_MSR_POW); 457#else 458 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_RST); 459#endif 460 DELAY(100); 461 outb(sc->asic_addr + ED_WD_MSR, inb(sc->asic_addr + ED_WD_MSR) & ~ED_WD_MSR_RST); 462 /* wait in the case this card is reading its EEROM */ 463 DELAY(5000); 464 465 sc->vendor = ED_VENDOR_WD_SMC; 466 sc->type = inb(sc->asic_addr + ED_WD_CARD_ID); 467 468 /* 469 * Set initial values for width/size. 470 */ 471 memsize = 8192; 472 isa16bit = 0; 473 switch (sc->type) { 474 case ED_TYPE_WD8003S: 475 sc->type_str = "WD8003S"; 476 break; 477 case ED_TYPE_WD8003E: 478 sc->type_str = "WD8003E"; 479 break; 480 case ED_TYPE_WD8003EB: 481 sc->type_str = "WD8003EB"; 482 break; 483 case ED_TYPE_WD8003W: 484 sc->type_str = "WD8003W"; 485 break; 486 case ED_TYPE_WD8013EBT: 487 sc->type_str = "WD8013EBT"; 488 memsize = 16384; 489 isa16bit = 1; 490 break; 491 case ED_TYPE_WD8013W: 492 sc->type_str = "WD8013W"; 493 memsize = 16384; 494 isa16bit = 1; 495 break; 496 case ED_TYPE_WD8013EP: /* also WD8003EP */ 497 if (inb(sc->asic_addr + ED_WD_ICR) 498 & ED_WD_ICR_16BIT) { 499 isa16bit = 1; 500 memsize = 16384; 501 sc->type_str = "WD8013EP"; 502 } else { 503 sc->type_str = "WD8003EP"; 504 } 505 break; 506 case ED_TYPE_WD8013WC: 507 sc->type_str = "WD8013WC"; 508 memsize = 16384; 509 isa16bit = 1; 510 break; 511 case ED_TYPE_WD8013EBP: 512 sc->type_str = "WD8013EBP"; 513 memsize = 16384; 514 isa16bit = 1; 515 break; 516 case ED_TYPE_WD8013EPC: 517 sc->type_str = "WD8013EPC"; 518 memsize = 16384; 519 isa16bit = 1; 520 break; 521 case ED_TYPE_SMC8216C: /* 8216 has 16K shared mem -- 8416 has 8K */ 522 case ED_TYPE_SMC8216T: 523 if (sc->type == ED_TYPE_SMC8216C) { 524 sc->type_str = "SMC8216/SMC8216C"; 525 } else { 526 sc->type_str = "SMC8216T"; 527 } 528 529 outb(sc->asic_addr + ED_WD790_HWR, 530 inb(sc->asic_addr + ED_WD790_HWR) | ED_WD790_HWR_SWH); 531 switch (inb(sc->asic_addr + ED_WD790_RAR) & ED_WD790_RAR_SZ64) { 532 case ED_WD790_RAR_SZ64: 533 memsize = 65536; 534 break; 535 case ED_WD790_RAR_SZ32: 536 memsize = 32768; 537 break; 538 case ED_WD790_RAR_SZ16: 539 memsize = 16384; 540 break; 541 case ED_WD790_RAR_SZ8: 542 /* 8216 has 16K shared mem -- 8416 has 8K */ 543 if (sc->type == ED_TYPE_SMC8216C) { 544 sc->type_str = "SMC8416C/SMC8416BT"; 545 } else { 546 sc->type_str = "SMC8416T"; 547 } 548 memsize = 8192; 549 break; 550 } 551 outb(sc->asic_addr + ED_WD790_HWR, 552 inb(sc->asic_addr + ED_WD790_HWR) & ~ED_WD790_HWR_SWH); 553 554 isa16bit = 1; 555 sc->is790 = 1; 556 break; 557#ifdef TOSH_ETHER 558 case ED_TYPE_TOSHIBA1: 559 sc->type_str = "Toshiba1"; 560 memsize = 32768; 561 isa16bit = 1; 562 break; 563 case ED_TYPE_TOSHIBA4: 564 sc->type_str = "Toshiba4"; 565 memsize = 32768; 566 isa16bit = 1; 567 break; 568#endif 569 default: 570 sc->type_str = ""; 571 break; 572 } 573 574 /* 575 * Make some adjustments to initial values depending on what is found 576 * in the ICR. 577 */ 578 if (isa16bit && (sc->type != ED_TYPE_WD8013EBT) 579#ifdef TOSH_ETHER 580 && (sc->type != ED_TYPE_TOSHIBA1) && (sc->type != ED_TYPE_TOSHIBA4) 581#endif 582 && ((inb(sc->asic_addr + ED_WD_ICR) & ED_WD_ICR_16BIT) == 0)) { 583 isa16bit = 0; 584 memsize = 8192; 585 } 586 587#if ED_DEBUG 588 printf("type = %x type_str=%s isa16bit=%d memsize=%d id_msize=%d\n", 589 sc->type, sc->type_str, isa16bit, memsize, isa_dev->id_msize); 590 for (i = 0; i < 8; i++) 591 printf("%x -> %x\n", i, inb(sc->asic_addr + i)); 592#endif 593 594 /* 595 * Allow the user to override the autoconfiguration 596 */ 597 if (isa_dev->id_msize) 598 memsize = isa_dev->id_msize; 599 600 maddr = (u_int) isa_dev->id_maddr & 0xffffff; 601 if (maddr < 0xa0000 || maddr + memsize > 0x1000000) { 602 printf("ed%d: Invalid ISA memory address range configured: 0x%x - 0x%x\n", 603 isa_dev->id_unit, maddr, maddr + memsize); 604 return 0; 605 } 606 607 /* 608 * (note that if the user specifies both of the following flags that 609 * '8bit' mode intentionally has precedence) 610 */ 611 if (isa_dev->id_flags & ED_FLAGS_FORCE_16BIT_MODE) 612 isa16bit = 1; 613 if (isa_dev->id_flags & ED_FLAGS_FORCE_8BIT_MODE) 614 isa16bit = 0; 615 616 /* 617 * If possible, get the assigned interrupt number from the card and 618 * use it. 619 */ 620 if ((sc->type & ED_WD_SOFTCONFIG) && (!sc->is790)) { 621 622 /* 623 * Assemble together the encoded interrupt number. 624 */ 625 iptr = (inb(isa_dev->id_iobase + ED_WD_ICR) & ED_WD_ICR_IR2) | 626 ((inb(isa_dev->id_iobase + ED_WD_IRR) & 627 (ED_WD_IRR_IR0 | ED_WD_IRR_IR1)) >> 5); 628 629 /* 630 * If no interrupt specified (or "?"), use what the board tells us. 631 */ 632 if (isa_dev->id_irq <= 0) 633 isa_dev->id_irq = ed_intr_mask[iptr]; 634 635 /* 636 * Enable the interrupt. 637 */ 638 outb(isa_dev->id_iobase + ED_WD_IRR, 639 inb(isa_dev->id_iobase + ED_WD_IRR) | ED_WD_IRR_IEN); 640 } 641 if (sc->is790) { 642 outb(isa_dev->id_iobase + ED_WD790_HWR, 643 inb(isa_dev->id_iobase + ED_WD790_HWR) | ED_WD790_HWR_SWH); 644 iptr = (((inb(isa_dev->id_iobase + ED_WD790_GCR) & ED_WD790_GCR_IR2) >> 4) | 645 (inb(isa_dev->id_iobase + ED_WD790_GCR) & 646 (ED_WD790_GCR_IR1 | ED_WD790_GCR_IR0)) >> 2); 647 outb(isa_dev->id_iobase + ED_WD790_HWR, 648 inb(isa_dev->id_iobase + ED_WD790_HWR) & ~ED_WD790_HWR_SWH); 649 650 /* 651 * If no interrupt specified (or "?"), use what the board tells us. 652 */ 653 if (isa_dev->id_irq <= 0) 654 isa_dev->id_irq = ed_790_intr_mask[iptr]; 655 656 /* 657 * Enable interrupts. 658 */ 659 outb(isa_dev->id_iobase + ED_WD790_ICR, 660 inb(isa_dev->id_iobase + ED_WD790_ICR) | ED_WD790_ICR_EIL); 661 } 662 if (isa_dev->id_irq <= 0) { 663 printf("ed%d: %s cards don't support auto-detected/assigned interrupts.\n", 664 isa_dev->id_unit, sc->type_str); 665 return (0); 666 } 667 sc->isa16bit = isa16bit; 668 sc->mem_shared = 1; 669 isa_dev->id_msize = memsize; 670 sc->mem_start = (caddr_t) isa_dev->id_maddr; 671 672 /* 673 * allocate one xmit buffer if < 16k, two buffers otherwise 674 */ 675 if ((memsize < 16384) || 676 (isa_dev->id_flags & ED_FLAGS_NO_MULTI_BUFFERING)) { 677 sc->txb_cnt = 1; 678 } else { 679 sc->txb_cnt = 2; 680 } 681 sc->tx_page_start = ED_WD_PAGE_OFFSET; 682 sc->rec_page_start = ED_WD_PAGE_OFFSET + ED_TXBUF_SIZE * sc->txb_cnt; 683 sc->rec_page_stop = ED_WD_PAGE_OFFSET + memsize / ED_PAGE_SIZE; 684 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * sc->rec_page_start); 685 sc->mem_size = memsize; 686 sc->mem_end = sc->mem_start + memsize; 687 688 /* 689 * Get station address from on-board ROM 690 */ 691 for (i = 0; i < ETHER_ADDR_LEN; ++i) 692 sc->arpcom.ac_enaddr[i] = inb(sc->asic_addr + ED_WD_PROM + i); 693 694 /* 695 * Set upper address bits and 8/16 bit access to shared memory. 696 */ 697 if (isa16bit) { 698 if (sc->is790) { 699 sc->wd_laar_proto = inb(sc->asic_addr + ED_WD_LAAR); 700 } else { 701 sc->wd_laar_proto = ED_WD_LAAR_L16EN | 702 ((kvtop(sc->mem_start) >> 19) & ED_WD_LAAR_ADDRHI); 703 } 704 /* 705 * Enable 16bit access 706 */ 707 outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto | 708 ED_WD_LAAR_M16EN); 709 } else { 710 if (((sc->type & ED_WD_SOFTCONFIG) || 711#ifdef TOSH_ETHER 712 (sc->type == ED_TYPE_TOSHIBA1) || (sc->type == ED_TYPE_TOSHIBA4) || 713#endif 714 (sc->type == ED_TYPE_WD8013EBT)) && (!sc->is790)) { 715 sc->wd_laar_proto = (kvtop(sc->mem_start) >> 19) & 716 ED_WD_LAAR_ADDRHI; 717 outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto); 718 } 719 } 720 721 /* 722 * Set address and enable interface shared memory. 723 */ 724 if (!sc->is790) { 725#ifdef TOSH_ETHER 726 outb(sc->asic_addr + ED_WD_MSR + 1, ((kvtop(sc->mem_start) >> 8) & 0xe0) | 4); 727 outb(sc->asic_addr + ED_WD_MSR + 2, ((kvtop(sc->mem_start) >> 16) & 0x0f)); 728 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_MENB | ED_WD_MSR_POW); 729 730#else 731 outb(sc->asic_addr + ED_WD_MSR, ((kvtop(sc->mem_start) >> 13) & 732 ED_WD_MSR_ADDR) | ED_WD_MSR_MENB); 733#endif 734 sc->cr_proto = ED_CR_RD2; 735 } else { 736 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_MENB); 737 outb(sc->asic_addr + ED_WD790_HWR, (inb(sc->asic_addr + ED_WD790_HWR) | ED_WD790_HWR_SWH)); 738 outb(sc->asic_addr + ED_WD790_RAR, ((kvtop(sc->mem_start) >> 13) & 0x0f) | 739 ((kvtop(sc->mem_start) >> 11) & 0x40) | 740 (inb(sc->asic_addr + ED_WD790_RAR) & 0xb0)); 741 outb(sc->asic_addr + ED_WD790_HWR, (inb(sc->asic_addr + ED_WD790_HWR) & ~ED_WD790_HWR_SWH)); 742 sc->cr_proto = 0; 743 } 744 745#if 0 746 printf("starting memory performance test at 0x%x, size %d...\n", 747 sc->mem_start, memsize*16384); 748 for (i = 0; i < 16384; i++) 749 bzero(sc->mem_start, memsize); 750 printf("***DONE***\n"); 751#endif 752 753 /* 754 * Now zero memory and verify that it is clear 755 */ 756 bzero(sc->mem_start, memsize); 757 758 for (i = 0; i < memsize; ++i) { 759 if (sc->mem_start[i]) { 760 printf("ed%d: failed to clear shared memory at %lx - check configuration\n", 761 isa_dev->id_unit, kvtop(sc->mem_start + i)); 762 763 /* 764 * Disable 16 bit access to shared memory 765 */ 766 if (isa16bit) { 767 if (sc->is790) { 768 outb(sc->asic_addr + ED_WD_MSR, 0x00); 769 } 770 outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto & 771 ~ED_WD_LAAR_M16EN); 772 } 773 return (0); 774 } 775 } 776 777 /* 778 * Disable 16bit access to shared memory - we leave it 779 * disabled so that 1) machines reboot properly when the board 780 * is set 16 bit mode and there are conflicting 8bit 781 * devices/ROMS in the same 128k address space as this boards 782 * shared memory. and 2) so that other 8 bit devices with 783 * shared memory can be used in this 128k region, too. 784 */ 785 if (isa16bit) { 786 if (sc->is790) { 787 outb(sc->asic_addr + ED_WD_MSR, 0x00); 788 } 789 outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto & 790 ~ED_WD_LAAR_M16EN); 791 } 792 return (ED_WD_IO_PORTS); 793} 794 795/* 796 * Probe and vendor-specific initialization routine for 3Com 3c503 boards 797 */ 798static int 799ed_probe_3Com(isa_dev) 800 struct isa_device *isa_dev; 801{ 802 struct ed_softc *sc = &ed_softc[isa_dev->id_unit]; 803 int i; 804 u_int memsize; 805 u_char isa16bit; 806 807 sc->asic_addr = isa_dev->id_iobase + ED_3COM_ASIC_OFFSET; 808 sc->nic_addr = isa_dev->id_iobase + ED_3COM_NIC_OFFSET; 809 810 /* 811 * Verify that the kernel configured I/O address matches the board 812 * configured address 813 */ 814 switch (inb(sc->asic_addr + ED_3COM_BCFR)) { 815 case ED_3COM_BCFR_300: 816 if (isa_dev->id_iobase != 0x300) 817 return (0); 818 break; 819 case ED_3COM_BCFR_310: 820 if (isa_dev->id_iobase != 0x310) 821 return (0); 822 break; 823 case ED_3COM_BCFR_330: 824 if (isa_dev->id_iobase != 0x330) 825 return (0); 826 break; 827 case ED_3COM_BCFR_350: 828 if (isa_dev->id_iobase != 0x350) 829 return (0); 830 break; 831 case ED_3COM_BCFR_250: 832 if (isa_dev->id_iobase != 0x250) 833 return (0); 834 break; 835 case ED_3COM_BCFR_280: 836 if (isa_dev->id_iobase != 0x280) 837 return (0); 838 break; 839 case ED_3COM_BCFR_2A0: 840 if (isa_dev->id_iobase != 0x2a0) 841 return (0); 842 break; 843 case ED_3COM_BCFR_2E0: 844 if (isa_dev->id_iobase != 0x2e0) 845 return (0); 846 break; 847 default: 848 return (0); 849 } 850 851 /* 852 * Verify that the kernel shared memory address matches the board 853 * configured address. 854 */ 855 switch (inb(sc->asic_addr + ED_3COM_PCFR)) { 856 case ED_3COM_PCFR_DC000: 857 if (kvtop(isa_dev->id_maddr) != 0xdc000) 858 return (0); 859 break; 860 case ED_3COM_PCFR_D8000: 861 if (kvtop(isa_dev->id_maddr) != 0xd8000) 862 return (0); 863 break; 864 case ED_3COM_PCFR_CC000: 865 if (kvtop(isa_dev->id_maddr) != 0xcc000) 866 return (0); 867 break; 868 case ED_3COM_PCFR_C8000: 869 if (kvtop(isa_dev->id_maddr) != 0xc8000) 870 return (0); 871 break; 872 default: 873 return (0); 874 } 875 876 877 /* 878 * Reset NIC and ASIC. Enable on-board transceiver throughout reset 879 * sequence because it'll lock up if the cable isn't connected if we 880 * don't. 881 */ 882 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_RST | ED_3COM_CR_XSEL); 883 884 /* 885 * Wait for a while, then un-reset it 886 */ 887 DELAY(50); 888 889 /* 890 * The 3Com ASIC defaults to rather strange settings for the CR after 891 * a reset - it's important to set it again after the following outb 892 * (this is done when we map the PROM below). 893 */ 894 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL); 895 896 /* 897 * Wait a bit for the NIC to recover from the reset 898 */ 899 DELAY(5000); 900 901 sc->vendor = ED_VENDOR_3COM; 902 sc->type_str = "3c503"; 903 sc->mem_shared = 1; 904 sc->cr_proto = ED_CR_RD2; 905 906 /* 907 * Hmmm...a 16bit 3Com board has 16k of memory, but only an 8k window 908 * to it. 909 */ 910 memsize = 8192; 911 912 /* 913 * Get station address from on-board ROM 914 */ 915 916 /* 917 * First, map ethernet address PROM over the top of where the NIC 918 * registers normally appear. 919 */ 920 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_EALO | ED_3COM_CR_XSEL); 921 922 for (i = 0; i < ETHER_ADDR_LEN; ++i) 923 sc->arpcom.ac_enaddr[i] = inb(sc->nic_addr + i); 924 925 /* 926 * Unmap PROM - select NIC registers. The proper setting of the 927 * tranceiver is set in ed_init so that the attach code is given a 928 * chance to set the default based on a compile-time config option 929 */ 930 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL); 931 932 /* 933 * Determine if this is an 8bit or 16bit board 934 */ 935 936 /* 937 * select page 0 registers 938 */ 939 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STP); 940 941 /* 942 * Attempt to clear WTS bit. If it doesn't clear, then this is a 16bit 943 * board. 944 */ 945 outb(sc->nic_addr + ED_P0_DCR, 0); 946 947 /* 948 * select page 2 registers 949 */ 950 outb(sc->nic_addr + ED_P0_CR, ED_CR_PAGE_2 | ED_CR_RD2 | ED_CR_STP); 951 952 /* 953 * The 3c503 forces the WTS bit to a one if this is a 16bit board 954 */ 955 if (inb(sc->nic_addr + ED_P2_DCR) & ED_DCR_WTS) 956 isa16bit = 1; 957 else 958 isa16bit = 0; 959 960 /* 961 * select page 0 registers 962 */ 963 outb(sc->nic_addr + ED_P2_CR, ED_CR_RD2 | ED_CR_STP); 964 965 sc->mem_start = (caddr_t) isa_dev->id_maddr; 966 sc->mem_size = memsize; 967 sc->mem_end = sc->mem_start + memsize; 968 969 /* 970 * We have an entire 8k window to put the transmit buffers on the 971 * 16bit boards. But since the 16bit 3c503's shared memory is only 972 * fast enough to overlap the loading of one full-size packet, trying 973 * to load more than 2 buffers can actually leave the transmitter idle 974 * during the load. So 2 seems the best value. (Although a mix of 975 * variable-sized packets might change this assumption. Nonetheless, 976 * we optimize for linear transfers of same-size packets.) 977 */ 978 if (isa16bit) { 979 if (isa_dev->id_flags & ED_FLAGS_NO_MULTI_BUFFERING) 980 sc->txb_cnt = 1; 981 else 982 sc->txb_cnt = 2; 983 984 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_16BIT; 985 sc->rec_page_start = ED_3COM_RX_PAGE_OFFSET_16BIT; 986 sc->rec_page_stop = memsize / ED_PAGE_SIZE + 987 ED_3COM_RX_PAGE_OFFSET_16BIT; 988 sc->mem_ring = sc->mem_start; 989 } else { 990 sc->txb_cnt = 1; 991 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_8BIT; 992 sc->rec_page_start = ED_TXBUF_SIZE + ED_3COM_TX_PAGE_OFFSET_8BIT; 993 sc->rec_page_stop = memsize / ED_PAGE_SIZE + 994 ED_3COM_TX_PAGE_OFFSET_8BIT; 995 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * ED_TXBUF_SIZE); 996 } 997 998 sc->isa16bit = isa16bit; 999 1000 /* 1001 * Initialize GA page start/stop registers. Probably only needed if 1002 * doing DMA, but what the hell. 1003 */ 1004 outb(sc->asic_addr + ED_3COM_PSTR, sc->rec_page_start); 1005 outb(sc->asic_addr + ED_3COM_PSPR, sc->rec_page_stop); 1006 1007 /* 1008 * Set IRQ. 3c503 only allows a choice of irq 2-5. 1009 */ 1010 switch (isa_dev->id_irq) { 1011 case IRQ2: 1012 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ2); 1013 break; 1014 case IRQ3: 1015 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ3); 1016 break; 1017 case IRQ4: 1018 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ4); 1019 break; 1020 case IRQ5: 1021 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ5); 1022 break; 1023 default: 1024 printf("ed%d: Invalid irq configuration (%d) must be 3-5,9 for 3c503\n", 1025 isa_dev->id_unit, ffs(isa_dev->id_irq) - 1); 1026 return (0); 1027 } 1028 1029 /* 1030 * Initialize GA configuration register. Set bank and enable shared 1031 * mem. 1032 */ 1033 outb(sc->asic_addr + ED_3COM_GACFR, ED_3COM_GACFR_RSEL | 1034 ED_3COM_GACFR_MBS0); 1035 1036 /* 1037 * Initialize "Vector Pointer" registers. These gawd-awful things are 1038 * compared to 20 bits of the address on ISA, and if they match, the 1039 * shared memory is disabled. We set them to 0xffff0...allegedly the 1040 * reset vector. 1041 */ 1042 outb(sc->asic_addr + ED_3COM_VPTR2, 0xff); 1043 outb(sc->asic_addr + ED_3COM_VPTR1, 0xff); 1044 outb(sc->asic_addr + ED_3COM_VPTR0, 0x00); 1045 1046 /* 1047 * Zero memory and verify that it is clear 1048 */ 1049 bzero(sc->mem_start, memsize); 1050 1051 for (i = 0; i < memsize; ++i) 1052 if (sc->mem_start[i]) { 1053 printf("ed%d: failed to clear shared memory at %lx - check configuration\n", 1054 isa_dev->id_unit, kvtop(sc->mem_start + i)); 1055 return (0); 1056 } 1057 isa_dev->id_msize = memsize; 1058 return (ED_3COM_IO_PORTS); 1059} 1060 1061/* 1062 * Probe and vendor-specific initialization routine for NE1000/2000 boards 1063 */ 1064static int 1065ed_probe_Novell_generic(sc, port, unit, flags) 1066 struct ed_softc *sc; 1067 int port; 1068 int unit; 1069 int flags; 1070{ 1071 u_int memsize, n; 1072 u_char romdata[16], tmp; 1073 static char test_pattern[32] = "THIS is A memory TEST pattern"; 1074 char test_buffer[32]; 1075 1076 sc->asic_addr = port + ED_NOVELL_ASIC_OFFSET; 1077 sc->nic_addr = port + ED_NOVELL_NIC_OFFSET; 1078 1079 /* XXX - do Novell-specific probe here */ 1080 1081 /* Reset the board */ 1082#ifdef GWETHER 1083 outb(sc->asic_addr + ED_NOVELL_RESET, 0); 1084 DELAY(200); 1085#endif /* GWETHER */ 1086 tmp = inb(sc->asic_addr + ED_NOVELL_RESET); 1087 1088 /* 1089 * I don't know if this is necessary; probably cruft leftover from 1090 * Clarkson packet driver code. Doesn't do a thing on the boards I've 1091 * tested. -DG [note that a outb(0x84, 0) seems to work here, and is 1092 * non-invasive...but some boards don't seem to reset and I don't have 1093 * complete documentation on what the 'right' thing to do is...so we 1094 * do the invasive thing for now. Yuck.] 1095 */ 1096 outb(sc->asic_addr + ED_NOVELL_RESET, tmp); 1097 DELAY(5000); 1098 1099 /* 1100 * This is needed because some NE clones apparently don't reset the 1101 * NIC properly (or the NIC chip doesn't reset fully on power-up) XXX 1102 * - this makes the probe invasive! ...Done against my better 1103 * judgement. -DLG 1104 */ 1105 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STP); 1106 1107 DELAY(5000); 1108 1109 /* Make sure that we really have an 8390 based board */ 1110 if (!ed_probe_generic8390(sc)) 1111 return (0); 1112 1113 sc->vendor = ED_VENDOR_NOVELL; 1114 sc->mem_shared = 0; 1115 sc->cr_proto = ED_CR_RD2; 1116 1117 /* 1118 * Test the ability to read and write to the NIC memory. This has the 1119 * side affect of determining if this is an NE1000 or an NE2000. 1120 */ 1121 1122 /* 1123 * This prevents packets from being stored in the NIC memory when the 1124 * readmem routine turns on the start bit in the CR. 1125 */ 1126 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_MON); 1127 1128 /* Temporarily initialize DCR for byte operations */ 1129 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS); 1130 1131 outb(sc->nic_addr + ED_P0_PSTART, 8192 / ED_PAGE_SIZE); 1132 outb(sc->nic_addr + ED_P0_PSTOP, 16384 / ED_PAGE_SIZE); 1133 1134 sc->isa16bit = 0; 1135 1136 /* 1137 * Write a test pattern in byte mode. If this fails, then there 1138 * probably isn't any memory at 8k - which likely means that the board 1139 * is an NE2000. 1140 */ 1141 ed_pio_writemem(sc, test_pattern, 8192, sizeof(test_pattern)); 1142 ed_pio_readmem(sc, 8192, test_buffer, sizeof(test_pattern)); 1143 1144 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern))) { 1145 /* not an NE1000 - try NE2000 */ 1146 1147 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_WTS | ED_DCR_FT1 | ED_DCR_LS); 1148 outb(sc->nic_addr + ED_P0_PSTART, 16384 / ED_PAGE_SIZE); 1149 outb(sc->nic_addr + ED_P0_PSTOP, 32768 / ED_PAGE_SIZE); 1150 1151 sc->isa16bit = 1; 1152 1153 /* 1154 * Write a test pattern in word mode. If this also fails, then 1155 * we don't know what this board is. 1156 */ 1157 ed_pio_writemem(sc, test_pattern, 16384, sizeof(test_pattern)); 1158 ed_pio_readmem(sc, 16384, test_buffer, sizeof(test_pattern)); 1159 1160 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern))) 1161 return (0); /* not an NE2000 either */ 1162 1163 sc->type = ED_TYPE_NE2000; 1164 sc->type_str = "NE2000"; 1165 } else { 1166 sc->type = ED_TYPE_NE1000; 1167 sc->type_str = "NE1000"; 1168 } 1169 1170 /* 8k of memory plus an additional 8k if 16bit */ 1171 memsize = 8192 + sc->isa16bit * 8192; 1172 1173#if 0 /* probably not useful - NE boards only come two ways */ 1174 /* allow kernel config file overrides */ 1175 if (isa_dev->id_msize) 1176 memsize = isa_dev->id_msize; 1177#endif 1178 1179 sc->mem_size = memsize; 1180 1181 /* NIC memory doesn't start at zero on an NE board */ 1182 /* The start address is tied to the bus width */ 1183 sc->mem_start = (char *) 8192 + sc->isa16bit * 8192; 1184 sc->mem_end = sc->mem_start + memsize; 1185 sc->tx_page_start = memsize / ED_PAGE_SIZE; 1186 1187#ifdef GWETHER 1188 { 1189 int x, i, mstart = 0, msize = 0; 1190 char pbuf0[ED_PAGE_SIZE], pbuf[ED_PAGE_SIZE], tbuf[ED_PAGE_SIZE]; 1191 1192 for (i = 0; i < ED_PAGE_SIZE; i++) 1193 pbuf0[i] = 0; 1194 1195 /* Clear all the memory. */ 1196 for (x = 1; x < 256; x++) 1197 ed_pio_writemem(sc, pbuf0, x * 256, ED_PAGE_SIZE); 1198 1199 /* Search for the start of RAM. */ 1200 for (x = 1; x < 256; x++) { 1201 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE); 1202 if (bcmp(pbuf0, tbuf, ED_PAGE_SIZE) == 0) { 1203 for (i = 0; i < ED_PAGE_SIZE; i++) 1204 pbuf[i] = 255 - x; 1205 ed_pio_writemem(sc, pbuf, x * 256, ED_PAGE_SIZE); 1206 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE); 1207 if (bcmp(pbuf, tbuf, ED_PAGE_SIZE) == 0) { 1208 mstart = x * ED_PAGE_SIZE; 1209 msize = ED_PAGE_SIZE; 1210 break; 1211 } 1212 } 1213 } 1214 1215 if (mstart == 0) { 1216 printf("ed%d: Cannot find start of RAM.\n", unit); 1217 return 0; 1218 } 1219 /* Search for the start of RAM. */ 1220 for (x = (mstart / ED_PAGE_SIZE) + 1; x < 256; x++) { 1221 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE); 1222 if (bcmp(pbuf0, tbuf, ED_PAGE_SIZE) == 0) { 1223 for (i = 0; i < ED_PAGE_SIZE; i++) 1224 pbuf[i] = 255 - x; 1225 ed_pio_writemem(sc, pbuf, x * 256, ED_PAGE_SIZE); 1226 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE); 1227 if (bcmp(pbuf, tbuf, ED_PAGE_SIZE) == 0) 1228 msize += ED_PAGE_SIZE; 1229 else { 1230 break; 1231 } 1232 } else { 1233 break; 1234 } 1235 } 1236 1237 if (msize == 0) { 1238 printf("ed%d: Cannot find any RAM, start : %d, x = %d.\n", unit, mstart, x); 1239 return 0; 1240 } 1241 printf("ed%d: RAM start at %d, size : %d.\n", unit, mstart, msize); 1242 1243 sc->mem_size = msize; 1244 sc->mem_start = (char *) mstart; 1245 sc->mem_end = (char *) (msize + mstart); 1246 sc->tx_page_start = mstart / ED_PAGE_SIZE; 1247 } 1248#endif /* GWETHER */ 1249 1250 /* 1251 * Use one xmit buffer if < 16k, two buffers otherwise (if not told 1252 * otherwise). 1253 */ 1254 if ((memsize < 16384) || (flags & ED_FLAGS_NO_MULTI_BUFFERING)) 1255 sc->txb_cnt = 1; 1256 else 1257 sc->txb_cnt = 2; 1258 1259 sc->rec_page_start = sc->tx_page_start + sc->txb_cnt * ED_TXBUF_SIZE; 1260 sc->rec_page_stop = sc->tx_page_start + memsize / ED_PAGE_SIZE; 1261 1262 sc->mem_ring = sc->mem_start + sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE; 1263 1264 ed_pio_readmem(sc, 0, romdata, 16); 1265 for (n = 0; n < ETHER_ADDR_LEN; n++) 1266 sc->arpcom.ac_enaddr[n] = romdata[n * (sc->isa16bit + 1)]; 1267 1268#ifdef GWETHER 1269 if (sc->arpcom.ac_enaddr[2] == 0x86) { 1270 sc->type_str = "Gateway AT"; 1271 } 1272#endif /* GWETHER */ 1273 1274 /* clear any pending interrupts that might have occurred above */ 1275 outb(sc->nic_addr + ED_P0_ISR, 0xff); 1276 1277 return (ED_NOVELL_IO_PORTS); 1278} 1279 1280static int 1281ed_probe_Novell(isa_dev) 1282 struct isa_device *isa_dev; 1283{ 1284 struct ed_softc *sc = &ed_softc[isa_dev->id_unit]; 1285 1286 isa_dev->id_maddr = 0; 1287 return ed_probe_Novell_generic(sc, isa_dev->id_iobase, 1288 isa_dev->id_unit, isa_dev->id_flags); 1289} 1290 1291#if NCARD > 0 1292/* 1293 * Probe framework for pccards. Replicates the standard framework, 1294 * minus the pccard driver registration and ignores the ether address 1295 * supplied (from the CIS), relying on the probe to find it instead. 1296 */ 1297static int 1298ed_probe_pccard(isa_dev, ether) 1299 struct isa_device *isa_dev; 1300 u_char *ether; 1301{ 1302 int nports; 1303 1304 nports = ed_probe_WD80x3(isa_dev); 1305 if (nports) 1306 return (nports); 1307 1308 nports = ed_probe_Novell(isa_dev); 1309 if (nports) 1310 return (nports); 1311 1312 return (0); 1313} 1314 1315#endif /* NCARD > 0 */ 1316 1317#define ED_HPP_TEST_SIZE 16 1318 1319/* 1320 * Probe and vendor specific initialization for the HP PC Lan+ Cards. 1321 * (HP Part nos: 27247B and 27252A). 1322 * 1323 * The card has an asic wrapper around a DS8390 core. The asic handles 1324 * host accesses and offers both standard register IO and memory mapped 1325 * IO. Memory mapped I/O allows better performance at the expense of greater 1326 * chance of an incompatibility with existing ISA cards. 1327 * 1328 * The card has a few caveats: it isn't tolerant of byte wide accesses, only 1329 * short (16 bit) or word (32 bit) accesses are allowed. Some card revisions 1330 * don't allow 32 bit accesses; these are indicated by a bit in the software 1331 * ID register (see if_edreg.h). 1332 * 1333 * Other caveats are: we should read the MAC address only when the card 1334 * is inactive. 1335 * 1336 * For more information; please consult the CRYNWR packet driver. 1337 * 1338 * The AUI port is turned on using the "link2" option on the ifconfig 1339 * command line. 1340 */ 1341static int 1342ed_probe_HP_pclanp(isa_dev) 1343 struct isa_device *isa_dev; 1344{ 1345 struct ed_softc *sc = &ed_softc[isa_dev->id_unit]; 1346 int n; /* temp var */ 1347 int memsize; /* mem on board */ 1348 u_char checksum; /* checksum of board address */ 1349 u_char irq; /* board configured IRQ */ 1350 char test_pattern[ED_HPP_TEST_SIZE]; /* read/write areas for */ 1351 char test_buffer[ED_HPP_TEST_SIZE]; /* probing card */ 1352 1353 1354 /* Fill in basic information */ 1355 sc->asic_addr = isa_dev->id_iobase + ED_HPP_ASIC_OFFSET; 1356 sc->nic_addr = isa_dev->id_iobase + ED_HPP_NIC_OFFSET; 1357 sc->is790 = 0; 1358 sc->isa16bit = 0; /* the 8390 core needs to be in byte mode */ 1359 1360 /* 1361 * Look for the HP PCLAN+ signature: "0x50,0x48,0x00,0x53" 1362 */ 1363 1364 if ((inb(sc->asic_addr + ED_HPP_ID) != 0x50) || 1365 (inb(sc->asic_addr + ED_HPP_ID + 1) != 0x48) || 1366 ((inb(sc->asic_addr + ED_HPP_ID + 2) & 0xF0) != 0) || 1367 (inb(sc->asic_addr + ED_HPP_ID + 3) != 0x53)) 1368 return 0; 1369 1370 /* 1371 * Read the MAC address and verify checksum on the address. 1372 */ 1373 1374 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_MAC); 1375 for (n = 0, checksum = 0; n < ETHER_ADDR_LEN; n++) 1376 checksum += (sc->arpcom.ac_enaddr[n] = 1377 inb(sc->asic_addr + ED_HPP_MAC_ADDR + n)); 1378 1379 checksum += inb(sc->asic_addr + ED_HPP_MAC_ADDR + ETHER_ADDR_LEN); 1380 1381 if (checksum != 0xFF) 1382 return 0; 1383 1384 /* 1385 * Verify that the software model number is 0. 1386 */ 1387 1388 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_ID); 1389 if (((sc->hpp_id = inw(sc->asic_addr + ED_HPP_PAGE_4)) & 1390 ED_HPP_ID_SOFT_MODEL_MASK) != 0x0000) 1391 return 0; 1392 1393 /* 1394 * Read in and save the current options configured on card. 1395 */ 1396 1397 sc->hpp_options = inw(sc->asic_addr + ED_HPP_OPTION); 1398 1399 sc->hpp_options |= (ED_HPP_OPTION_NIC_RESET | 1400 ED_HPP_OPTION_CHIP_RESET | 1401 ED_HPP_OPTION_ENABLE_IRQ); 1402 1403 /* 1404 * Reset the chip. This requires writing to the option register 1405 * so take care to preserve the other bits. 1406 */ 1407 1408 outw(sc->asic_addr + ED_HPP_OPTION, 1409 (sc->hpp_options & ~(ED_HPP_OPTION_NIC_RESET | 1410 ED_HPP_OPTION_CHIP_RESET))); 1411 1412 DELAY(5000); /* wait for chip reset to complete */ 1413 1414 outw(sc->asic_addr + ED_HPP_OPTION, 1415 (sc->hpp_options | (ED_HPP_OPTION_NIC_RESET | 1416 ED_HPP_OPTION_CHIP_RESET | 1417 ED_HPP_OPTION_ENABLE_IRQ))); 1418 1419 DELAY(5000); 1420 1421 if (!(inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RST)) 1422 return 0; /* reset did not complete */ 1423 1424 /* 1425 * Read out configuration information. 1426 */ 1427 1428 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_HW); 1429 1430 irq = inb(sc->asic_addr + ED_HPP_HW_IRQ); 1431 1432 /* 1433 * Check for impossible IRQ. 1434 */ 1435 1436 if (irq >= (sizeof(ed_hpp_intr_mask) / sizeof(ed_hpp_intr_mask[0]))) 1437 return 0; 1438 1439 /* 1440 * If the kernel IRQ was specified with a '?' use the cards idea 1441 * of the IRQ. If the kernel IRQ was explicitly specified, it 1442 * should match that of the hardware. 1443 */ 1444 1445 if (isa_dev->id_irq <= 0) 1446 isa_dev->id_irq = ed_hpp_intr_mask[irq]; 1447 else if (isa_dev->id_irq != ed_hpp_intr_mask[irq]) 1448 return 0; 1449 1450 /* 1451 * Fill in softconfig info. 1452 */ 1453 1454 sc->vendor = ED_VENDOR_HP; 1455 sc->type = ED_TYPE_HP_PCLANPLUS; 1456 sc->type_str = "HP-PCLAN+"; 1457 1458 sc->mem_shared = 0; /* we DON'T have dual ported RAM */ 1459 sc->mem_start = 0; /* we use offsets inside the card RAM */ 1460 1461 sc->hpp_mem_start = NULL;/* no memory mapped I/O by default */ 1462 1463 /* 1464 * Check if memory mapping of the I/O registers possible. 1465 */ 1466 1467 if (sc->hpp_options & ED_HPP_OPTION_MEM_ENABLE) 1468 { 1469 u_long mem_addr; 1470 1471 /* 1472 * determine the memory address from the board. 1473 */ 1474 1475 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_HW); 1476 mem_addr = (inw(sc->asic_addr + ED_HPP_HW_MEM_MAP) << 8); 1477 1478 /* 1479 * Check that the kernel specified start of memory and 1480 * hardware's idea of it match. 1481 */ 1482 1483 if (mem_addr != kvtop(isa_dev->id_maddr)) 1484 return 0; 1485 1486 sc->hpp_mem_start = isa_dev->id_maddr; 1487 } 1488 1489 /* 1490 * The board has 32KB of memory. Is there a way to determine 1491 * this programmatically? 1492 */ 1493 1494 memsize = 32768; 1495 1496 /* 1497 * Fill in the rest of the soft config structure. 1498 */ 1499 1500 /* 1501 * The transmit page index. 1502 */ 1503 1504 sc->tx_page_start = ED_HPP_TX_PAGE_OFFSET; 1505 1506 if (isa_dev->id_flags & ED_FLAGS_NO_MULTI_BUFFERING) 1507 sc->txb_cnt = 1; 1508 else 1509 sc->txb_cnt = 2; 1510 1511 /* 1512 * Memory description 1513 */ 1514 1515 sc->mem_size = memsize; 1516 sc->mem_ring = sc->mem_start + 1517 (sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE); 1518 sc->mem_end = sc->mem_start + sc->mem_size; 1519 1520 /* 1521 * Receive area starts after the transmit area and 1522 * continues till the end of memory. 1523 */ 1524 1525 sc->rec_page_start = sc->tx_page_start + 1526 (sc->txb_cnt * ED_TXBUF_SIZE); 1527 sc->rec_page_stop = (sc->mem_size / ED_PAGE_SIZE); 1528 1529 1530 sc->cr_proto = 0; /* value works */ 1531 1532 /* 1533 * Set the wrap registers for string I/O reads. 1534 */ 1535 1536 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_HW); 1537 outw(sc->asic_addr + ED_HPP_HW_WRAP, 1538 ((sc->rec_page_start / ED_PAGE_SIZE) | 1539 (((sc->rec_page_stop / ED_PAGE_SIZE) - 1) << 8))); 1540 1541 /* 1542 * Reset the register page to normal operation. 1543 */ 1544 1545 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_PERF); 1546 1547 /* 1548 * Verify that we can read/write from adapter memory. 1549 * Create test pattern. 1550 */ 1551 1552 for (n = 0; n < ED_HPP_TEST_SIZE; n++) 1553 { 1554 test_pattern[n] = (n*n) ^ ~n; 1555 } 1556 1557#undef ED_HPP_TEST_SIZE 1558 1559 /* 1560 * Check that the memory is accessible thru the I/O ports. 1561 * Write out the contents of "test_pattern", read back 1562 * into "test_buffer" and compare the two for any 1563 * mismatch. 1564 */ 1565 1566 for (n = 0; n < (32768 / ED_PAGE_SIZE); n ++) { 1567 1568 ed_pio_writemem(sc, test_pattern, (n * ED_PAGE_SIZE), 1569 sizeof(test_pattern)); 1570 ed_pio_readmem(sc, (n * ED_PAGE_SIZE), 1571 test_buffer, sizeof(test_pattern)); 1572 1573 if (bcmp(test_pattern, test_buffer, 1574 sizeof(test_pattern))) 1575 return 0; 1576 } 1577 1578 return (ED_HPP_IO_PORTS); 1579 1580} 1581 1582/* 1583 * HP PC Lan+ : Set the physical link to use AUI or TP/TL. 1584 */ 1585 1586void 1587ed_hpp_set_physical_link(struct ed_softc *sc) 1588{ 1589 struct ifnet *ifp = &sc->arpcom.ac_if; 1590 int lan_page; 1591 1592 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_LAN); 1593 lan_page = inw(sc->asic_addr + ED_HPP_PAGE_0); 1594 1595 if (ifp->if_flags & IFF_ALTPHYS) { 1596 1597 /* 1598 * Use the AUI port. 1599 */ 1600 1601 lan_page |= ED_HPP_LAN_AUI; 1602 1603 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_LAN); 1604 outw(sc->asic_addr + ED_HPP_PAGE_0, lan_page); 1605 1606 1607 } else { 1608 1609 /* 1610 * Use the ThinLan interface 1611 */ 1612 1613 lan_page &= ~ED_HPP_LAN_AUI; 1614 1615 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_LAN); 1616 outw(sc->asic_addr + ED_HPP_PAGE_0, lan_page); 1617 1618 } 1619 1620 /* 1621 * Wait for the lan card to re-initialize itself 1622 */ 1623 1624 DELAY(150000); /* wait 150 ms */ 1625 1626 /* 1627 * Restore normal pages. 1628 */ 1629 1630 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_PERF); 1631 1632} 1633 1634 1635/* 1636 * Install interface into kernel networking data structures 1637 */ 1638static int 1639ed_attach(sc, unit, flags) 1640 struct ed_softc *sc; 1641 int unit; 1642 int flags; 1643{ 1644 struct ifnet *ifp = &sc->arpcom.ac_if; 1645 1646 /* 1647 * Set interface to stopped condition (reset) 1648 */ 1649 ed_stop(sc); 1650 1651 if (!ifp->if_name) { 1652 /* 1653 * Initialize ifnet structure 1654 */ 1655 ifp->if_softc = sc; 1656 ifp->if_unit = unit; 1657 ifp->if_name = "ed"; 1658 ifp->if_output = ether_output; 1659 ifp->if_start = ed_start; 1660 ifp->if_ioctl = ed_ioctl; 1661 ifp->if_watchdog = ed_watchdog; 1662 ifp->if_init = ed_init; 1663 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 1664 ifp->if_linkmib = &sc->mibdata; 1665 ifp->if_linkmiblen = sizeof sc->mibdata; 1666 /* 1667 * XXX - should do a better job. 1668 */ 1669 if (sc->is790) 1670 sc->mibdata.dot3StatsEtherChipSet = 1671 DOT3CHIPSET(dot3VendorWesternDigital, 1672 dot3ChipSetWesternDigital83C790); 1673 else 1674 sc->mibdata.dot3StatsEtherChipSet = 1675 DOT3CHIPSET(dot3VendorNational, 1676 dot3ChipSetNational8390); 1677 sc->mibdata.dot3Compliance = DOT3COMPLIANCE_COLLS; 1678 1679 /* 1680 * Set default state for ALTPHYS flag (used to disable the 1681 * tranceiver for AUI operation), based on compile-time 1682 * config option. 1683 */ 1684 if (flags & ED_FLAGS_DISABLE_TRANCEIVER) 1685 ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX | 1686 IFF_MULTICAST | IFF_ALTPHYS); 1687 else 1688 ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX | 1689 IFF_MULTICAST); 1690 1691 /* 1692 * Attach the interface 1693 */ 1694 if_attach(ifp); 1695 ether_ifattach(ifp); 1696 } 1697 /* device attach does transition from UNCONFIGURED to IDLE state */ 1698 1699 /* 1700 * Print additional info when attached 1701 */ 1702 printf("%s%d: address %6D, ", ifp->if_name, ifp->if_unit, 1703 sc->arpcom.ac_enaddr, ":"); 1704 1705 if (sc->type_str && (*sc->type_str != 0)) 1706 printf("type %s ", sc->type_str); 1707 else 1708 printf("type unknown (0x%x) ", sc->type); 1709 1710 if (sc->vendor == ED_VENDOR_HP) 1711 printf("(%s %s IO)", (sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS) ? 1712 "16-bit" : "32-bit", 1713 sc->hpp_mem_start ? "memory mapped" : "regular"); 1714 else 1715 printf("%s ", sc->isa16bit ? "(16 bit)" : "(8 bit)"); 1716 1717 printf("%s\n", (((sc->vendor == ED_VENDOR_3COM) || 1718 (sc->vendor == ED_VENDOR_HP)) && 1719 (ifp->if_flags & IFF_ALTPHYS)) ? " tranceiver disabled" : ""); 1720 1721 /* 1722 * If BPF is in the kernel, call the attach for it 1723 */ 1724#if NBPFILTER > 0 1725 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header)); 1726#endif 1727 return 1; 1728} 1729 1730static int 1731ed_attach_isa(isa_dev) 1732 struct isa_device *isa_dev; 1733{ 1734 int unit = isa_dev->id_unit; 1735 struct ed_softc *sc = &ed_softc[unit]; 1736 int flags = isa_dev->id_flags; 1737 1738 isa_dev->id_ointr = edintr; 1739 return ed_attach(sc, unit, flags); 1740} 1741 1742#if NPCI > 0 1743void * 1744ed_attach_NE2000_pci(unit, port) 1745 int unit; 1746 int port; 1747{ 1748 struct ed_softc *sc = malloc(sizeof *sc, M_DEVBUF, M_NOWAIT); 1749 int isa_flags = 0; 1750 1751 if (!sc) 1752 return sc; 1753 1754 bzero(sc, sizeof *sc); 1755 if (ed_probe_Novell_generic(sc, port, unit, isa_flags) == 0 1756 || ed_attach(sc, unit, isa_flags) == 0) { 1757 free(sc, M_DEVBUF); 1758 return NULL; 1759 } 1760 return sc; 1761} 1762#endif 1763 1764/* 1765 * Reset interface. 1766 */ 1767static void 1768ed_reset(ifp) 1769 struct ifnet *ifp; 1770{ 1771 struct ed_softc *sc = ifp->if_softc; 1772 int s; 1773 1774 if (sc->gone) 1775 return; 1776 s = splimp(); 1777 1778 /* 1779 * Stop interface and re-initialize. 1780 */ 1781 ed_stop(sc); 1782 ed_init(sc); 1783 1784 (void) splx(s); 1785} 1786 1787/* 1788 * Take interface offline. 1789 */ 1790static void 1791ed_stop(sc) 1792 struct ed_softc *sc; 1793{ 1794 int n = 5000; 1795 1796 if (sc->gone) 1797 return; 1798 /* 1799 * Stop everything on the interface, and select page 0 registers. 1800 */ 1801 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP); 1802 1803 /* 1804 * Wait for interface to enter stopped state, but limit # of checks to 1805 * 'n' (about 5ms). It shouldn't even take 5us on modern DS8390's, but 1806 * just in case it's an old one. 1807 */ 1808 while (((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RST) == 0) && --n); 1809} 1810 1811/* 1812 * Device timeout/watchdog routine. Entered if the device neglects to 1813 * generate an interrupt after a transmit has been started on it. 1814 */ 1815static void 1816ed_watchdog(ifp) 1817 struct ifnet *ifp; 1818{ 1819 struct ed_softc *sc = ifp->if_softc; 1820 1821 if (sc->gone) 1822 return; 1823 log(LOG_ERR, "ed%d: device timeout\n", ifp->if_unit); 1824 ifp->if_oerrors++; 1825 1826 ed_reset(ifp); 1827} 1828 1829/* 1830 * Initialize device. 1831 */ 1832static void 1833ed_init(xsc) 1834 void *xsc; 1835{ 1836 struct ed_softc *sc = xsc; 1837 struct ifnet *ifp = &sc->arpcom.ac_if; 1838 int i, s; 1839 1840 if (sc->gone) 1841 return; 1842 1843 /* address not known */ 1844 if (TAILQ_EMPTY(&ifp->if_addrhead)) /* unlikely? XXX */ 1845 return; 1846 1847 /* 1848 * Initialize the NIC in the exact order outlined in the NS manual. 1849 * This init procedure is "mandatory"...don't change what or when 1850 * things happen. 1851 */ 1852 s = splimp(); 1853 1854 /* reset transmitter flags */ 1855 sc->xmit_busy = 0; 1856 ifp->if_timer = 0; 1857 1858 sc->txb_inuse = 0; 1859 sc->txb_new = 0; 1860 sc->txb_next_tx = 0; 1861 1862 /* This variable is used below - don't move this assignment */ 1863 sc->next_packet = sc->rec_page_start + 1; 1864 1865 /* 1866 * Set interface for page 0, Remote DMA complete, Stopped 1867 */ 1868 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP); 1869 1870 if (sc->isa16bit) { 1871 1872 /* 1873 * Set FIFO threshold to 8, No auto-init Remote DMA, byte 1874 * order=80x86, word-wide DMA xfers, 1875 */ 1876 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1 | ED_DCR_WTS | ED_DCR_LS); 1877 } else { 1878 1879 /* 1880 * Same as above, but byte-wide DMA xfers 1881 */ 1882 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS); 1883 } 1884 1885 /* 1886 * Clear Remote Byte Count Registers 1887 */ 1888 outb(sc->nic_addr + ED_P0_RBCR0, 0); 1889 outb(sc->nic_addr + ED_P0_RBCR1, 0); 1890 1891 /* 1892 * For the moment, don't store incoming packets in memory. 1893 */ 1894 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_MON); 1895 1896 /* 1897 * Place NIC in internal loopback mode 1898 */ 1899 outb(sc->nic_addr + ED_P0_TCR, ED_TCR_LB0); 1900 1901 /* 1902 * Initialize transmit/receive (ring-buffer) Page Start 1903 */ 1904 outb(sc->nic_addr + ED_P0_TPSR, sc->tx_page_start); 1905 outb(sc->nic_addr + ED_P0_PSTART, sc->rec_page_start); 1906 /* Set lower bits of byte addressable framing to 0 */ 1907 if (sc->is790) 1908 outb(sc->nic_addr + 0x09, 0); 1909 1910 /* 1911 * Initialize Receiver (ring-buffer) Page Stop and Boundry 1912 */ 1913 outb(sc->nic_addr + ED_P0_PSTOP, sc->rec_page_stop); 1914 outb(sc->nic_addr + ED_P0_BNRY, sc->rec_page_start); 1915 1916 /* 1917 * Clear all interrupts. A '1' in each bit position clears the 1918 * corresponding flag. 1919 */ 1920 outb(sc->nic_addr + ED_P0_ISR, 0xff); 1921 1922 /* 1923 * Enable the following interrupts: receive/transmit complete, 1924 * receive/transmit error, and Receiver OverWrite. 1925 * 1926 * Counter overflow and Remote DMA complete are *not* enabled. 1927 */ 1928 outb(sc->nic_addr + ED_P0_IMR, 1929 ED_IMR_PRXE | ED_IMR_PTXE | ED_IMR_RXEE | ED_IMR_TXEE | ED_IMR_OVWE); 1930 1931 /* 1932 * Program Command Register for page 1 1933 */ 1934 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP); 1935 1936 /* 1937 * Copy out our station address 1938 */ 1939 for (i = 0; i < ETHER_ADDR_LEN; ++i) 1940 outb(sc->nic_addr + ED_P1_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1941 1942 /* 1943 * Set Current Page pointer to next_packet (initialized above) 1944 */ 1945 outb(sc->nic_addr + ED_P1_CURR, sc->next_packet); 1946 1947 /* 1948 * Program Receiver Configuration Register and multicast filter. CR is 1949 * set to page 0 on return. 1950 */ 1951 ed_setrcr(sc); 1952 1953 /* 1954 * Take interface out of loopback 1955 */ 1956 outb(sc->nic_addr + ED_P0_TCR, 0); 1957 1958 /* 1959 * If this is a 3Com board, the tranceiver must be software enabled 1960 * (there is no settable hardware default). 1961 */ 1962 if (sc->vendor == ED_VENDOR_3COM) { 1963 if (ifp->if_flags & IFF_ALTPHYS) { 1964 outb(sc->asic_addr + ED_3COM_CR, 0); 1965 } else { 1966 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL); 1967 } 1968 } 1969 1970 /* 1971 * Set 'running' flag, and clear output active flag. 1972 */ 1973 ifp->if_flags |= IFF_RUNNING; 1974 ifp->if_flags &= ~IFF_OACTIVE; 1975 1976 /* 1977 * ...and attempt to start output 1978 */ 1979 ed_start(ifp); 1980 1981 (void) splx(s); 1982} 1983 1984/* 1985 * This routine actually starts the transmission on the interface 1986 */ 1987static __inline void 1988ed_xmit(sc) 1989 struct ed_softc *sc; 1990{ 1991 struct ifnet *ifp = (struct ifnet *)sc; 1992 unsigned short len; 1993 1994 if (sc->gone) 1995 return; 1996 len = sc->txb_len[sc->txb_next_tx]; 1997 1998 /* 1999 * Set NIC for page 0 register access 2000 */ 2001 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA); 2002 2003 /* 2004 * Set TX buffer start page 2005 */ 2006 outb(sc->nic_addr + ED_P0_TPSR, sc->tx_page_start + 2007 sc->txb_next_tx * ED_TXBUF_SIZE); 2008 2009 /* 2010 * Set TX length 2011 */ 2012 outb(sc->nic_addr + ED_P0_TBCR0, len); 2013 outb(sc->nic_addr + ED_P0_TBCR1, len >> 8); 2014 2015 /* 2016 * Set page 0, Remote DMA complete, Transmit Packet, and *Start* 2017 */ 2018 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_TXP | ED_CR_STA); 2019 sc->xmit_busy = 1; 2020 2021 /* 2022 * Point to next transmit buffer slot and wrap if necessary. 2023 */ 2024 sc->txb_next_tx++; 2025 if (sc->txb_next_tx == sc->txb_cnt) 2026 sc->txb_next_tx = 0; 2027 2028 /* 2029 * Set a timer just in case we never hear from the board again 2030 */ 2031 ifp->if_timer = 2; 2032} 2033 2034/* 2035 * Start output on interface. 2036 * We make two assumptions here: 2037 * 1) that the current priority is set to splimp _before_ this code 2038 * is called *and* is returned to the appropriate priority after 2039 * return 2040 * 2) that the IFF_OACTIVE flag is checked before this code is called 2041 * (i.e. that the output part of the interface is idle) 2042 */ 2043static void 2044ed_start(ifp) 2045 struct ifnet *ifp; 2046{ 2047 struct ed_softc *sc = ifp->if_softc; 2048 struct mbuf *m0, *m; 2049 caddr_t buffer; 2050 int len; 2051 2052 if (sc->gone) { 2053 printf("ed_start(%p) GONE\n",ifp); 2054 return; 2055 } 2056outloop: 2057 2058 /* 2059 * First, see if there are buffered packets and an idle transmitter - 2060 * should never happen at this point. 2061 */ 2062 if (sc->txb_inuse && (sc->xmit_busy == 0)) { 2063 printf("ed: packets buffered, but transmitter idle\n"); 2064 ed_xmit(sc); 2065 } 2066 2067 /* 2068 * See if there is room to put another packet in the buffer. 2069 */ 2070 if (sc->txb_inuse == sc->txb_cnt) { 2071 2072 /* 2073 * No room. Indicate this to the outside world and exit. 2074 */ 2075 ifp->if_flags |= IFF_OACTIVE; 2076 return; 2077 } 2078 IF_DEQUEUE(&ifp->if_snd, m); 2079 if (m == 0) { 2080 2081 /* 2082 * We are using the !OACTIVE flag to indicate to the outside 2083 * world that we can accept an additional packet rather than 2084 * that the transmitter is _actually_ active. Indeed, the 2085 * transmitter may be active, but if we haven't filled all the 2086 * buffers with data then we still want to accept more. 2087 */ 2088 ifp->if_flags &= ~IFF_OACTIVE; 2089 return; 2090 } 2091 2092 /* 2093 * Copy the mbuf chain into the transmit buffer 2094 */ 2095 2096 m0 = m; 2097 2098 /* txb_new points to next open buffer slot */ 2099 buffer = sc->mem_start + (sc->txb_new * ED_TXBUF_SIZE * ED_PAGE_SIZE); 2100 2101 if (sc->mem_shared) { 2102 2103 /* 2104 * Special case setup for 16 bit boards... 2105 */ 2106 if (sc->isa16bit) { 2107 switch (sc->vendor) { 2108 2109 /* 2110 * For 16bit 3Com boards (which have 16k of 2111 * memory), we have the xmit buffers in a 2112 * different page of memory ('page 0') - so 2113 * change pages. 2114 */ 2115 case ED_VENDOR_3COM: 2116 outb(sc->asic_addr + ED_3COM_GACFR, 2117 ED_3COM_GACFR_RSEL); 2118 break; 2119 2120 /* 2121 * Enable 16bit access to shared memory on 2122 * WD/SMC boards. 2123 */ 2124 case ED_VENDOR_WD_SMC:{ 2125 outb(sc->asic_addr + ED_WD_LAAR, 2126 sc->wd_laar_proto | ED_WD_LAAR_M16EN); 2127 if (sc->is790) { 2128 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_MENB); 2129 } 2130 break; 2131 } 2132 } 2133 } 2134 for (len = 0; m != 0; m = m->m_next) { 2135 bcopy(mtod(m, caddr_t), buffer, m->m_len); 2136 buffer += m->m_len; 2137 len += m->m_len; 2138 } 2139 2140 /* 2141 * Restore previous shared memory access 2142 */ 2143 if (sc->isa16bit) { 2144 switch (sc->vendor) { 2145 case ED_VENDOR_3COM: 2146 outb(sc->asic_addr + ED_3COM_GACFR, 2147 ED_3COM_GACFR_RSEL | ED_3COM_GACFR_MBS0); 2148 break; 2149 case ED_VENDOR_WD_SMC:{ 2150 if (sc->is790) { 2151 outb(sc->asic_addr + ED_WD_MSR, 0x00); 2152 } 2153 outb(sc->asic_addr + ED_WD_LAAR, 2154 sc->wd_laar_proto & ~ED_WD_LAAR_M16EN); 2155 break; 2156 } 2157 } 2158 } 2159 } else { 2160 len = ed_pio_write_mbufs(sc, m, (int)buffer); 2161 if (len == 0) 2162 goto outloop; 2163 } 2164 2165 sc->txb_len[sc->txb_new] = max(len, (ETHER_MIN_LEN-ETHER_CRC_LEN)); 2166 2167 sc->txb_inuse++; 2168 2169 /* 2170 * Point to next buffer slot and wrap if necessary. 2171 */ 2172 sc->txb_new++; 2173 if (sc->txb_new == sc->txb_cnt) 2174 sc->txb_new = 0; 2175 2176 if (sc->xmit_busy == 0) 2177 ed_xmit(sc); 2178 2179 /* 2180 * Tap off here if there is a bpf listener. 2181 */ 2182#if NBPFILTER > 0 2183 if (ifp->if_bpf) { 2184 bpf_mtap(ifp, m0); 2185 } 2186#endif 2187 2188 m_freem(m0); 2189 2190 /* 2191 * Loop back to the top to possibly buffer more packets 2192 */ 2193 goto outloop; 2194} 2195 2196/* 2197 * Ethernet interface receiver interrupt. 2198 */ 2199static __inline void 2200ed_rint(sc) 2201 struct ed_softc *sc; 2202{ 2203 struct ifnet *ifp = &sc->arpcom.ac_if; 2204 u_char boundry; 2205 u_short len; 2206 struct ed_ring packet_hdr; 2207 char *packet_ptr; 2208 2209 if (sc->gone) 2210 return; 2211 2212 /* 2213 * Set NIC to page 1 registers to get 'current' pointer 2214 */ 2215 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA); 2216 2217 /* 2218 * 'sc->next_packet' is the logical beginning of the ring-buffer - 2219 * i.e. it points to where new data has been buffered. The 'CURR' 2220 * (current) register points to the logical end of the ring-buffer - 2221 * i.e. it points to where additional new data will be added. We loop 2222 * here until the logical beginning equals the logical end (or in 2223 * other words, until the ring-buffer is empty). 2224 */ 2225 while (sc->next_packet != inb(sc->nic_addr + ED_P1_CURR)) { 2226 2227 /* get pointer to this buffer's header structure */ 2228 packet_ptr = sc->mem_ring + 2229 (sc->next_packet - sc->rec_page_start) * ED_PAGE_SIZE; 2230 2231 /* 2232 * The byte count includes a 4 byte header that was added by 2233 * the NIC. 2234 */ 2235 if (sc->mem_shared) 2236 packet_hdr = *(struct ed_ring *) packet_ptr; 2237 else 2238 ed_pio_readmem(sc, (int)packet_ptr, (char *) &packet_hdr, 2239 sizeof(packet_hdr)); 2240 len = packet_hdr.count; 2241 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring)) || 2242 len < (ETHER_MIN_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring))) { 2243 /* 2244 * Length is a wild value. There's a good chance that 2245 * this was caused by the NIC being old and buggy. 2246 * The bug is that the length low byte is duplicated in 2247 * the high byte. Try to recalculate the length based on 2248 * the pointer to the next packet. 2249 */ 2250 /* 2251 * NOTE: sc->next_packet is pointing at the current packet. 2252 */ 2253 len &= ED_PAGE_SIZE - 1; /* preserve offset into page */ 2254 if (packet_hdr.next_packet >= sc->next_packet) { 2255 len += (packet_hdr.next_packet - sc->next_packet) * ED_PAGE_SIZE; 2256 } else { 2257 len += ((packet_hdr.next_packet - sc->rec_page_start) + 2258 (sc->rec_page_stop - sc->next_packet)) * ED_PAGE_SIZE; 2259 } 2260 /* 2261 * because buffers are aligned on 256-byte boundary, 2262 * the length computed above is off by 256 in almost 2263 * all cases. Fix it... 2264 */ 2265 if (len & 0xff) 2266 len -= 256 ; 2267 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN 2268 + sizeof(struct ed_ring))) 2269 sc->mibdata.dot3StatsFrameTooLongs++; 2270 } 2271 /* 2272 * Be fairly liberal about what we allow as a "reasonable" length 2273 * so that a [crufty] packet will make it to BPF (and can thus 2274 * be analyzed). Note that all that is really important is that 2275 * we have a length that will fit into one mbuf cluster or less; 2276 * the upper layer protocols can then figure out the length from 2277 * their own length field(s). 2278 */ 2279 if ((len > sizeof(struct ed_ring)) && 2280 (len <= MCLBYTES) && 2281 (packet_hdr.next_packet >= sc->rec_page_start) && 2282 (packet_hdr.next_packet < sc->rec_page_stop)) { 2283 /* 2284 * Go get packet. 2285 */ 2286 ed_get_packet(sc, packet_ptr + sizeof(struct ed_ring), 2287 len - sizeof(struct ed_ring), packet_hdr.rsr & ED_RSR_PHY); 2288 ifp->if_ipackets++; 2289 } else { 2290 /* 2291 * Really BAD. The ring pointers are corrupted. 2292 */ 2293 log(LOG_ERR, 2294 "ed%d: NIC memory corrupt - invalid packet length %d\n", 2295 ifp->if_unit, len); 2296 ifp->if_ierrors++; 2297 ed_reset(ifp); 2298 return; 2299 } 2300 2301 /* 2302 * Update next packet pointer 2303 */ 2304 sc->next_packet = packet_hdr.next_packet; 2305 2306 /* 2307 * Update NIC boundry pointer - being careful to keep it one 2308 * buffer behind. (as recommended by NS databook) 2309 */ 2310 boundry = sc->next_packet - 1; 2311 if (boundry < sc->rec_page_start) 2312 boundry = sc->rec_page_stop - 1; 2313 2314 /* 2315 * Set NIC to page 0 registers to update boundry register 2316 */ 2317 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA); 2318 2319 outb(sc->nic_addr + ED_P0_BNRY, boundry); 2320 2321 /* 2322 * Set NIC to page 1 registers before looping to top (prepare 2323 * to get 'CURR' current pointer) 2324 */ 2325 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA); 2326 } 2327} 2328 2329/* 2330 * Ethernet interface interrupt processor 2331 */ 2332void 2333edintr_sc(sc) 2334 struct ed_softc *sc; 2335{ 2336 struct ifnet *ifp = (struct ifnet *)sc; 2337 u_char isr; 2338 2339 if (sc->gone) 2340 return; 2341 /* 2342 * Set NIC to page 0 registers 2343 */ 2344 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA); 2345 2346 /* 2347 * loop until there are no more new interrupts 2348 */ 2349 while ((isr = inb(sc->nic_addr + ED_P0_ISR)) != 0) { 2350 2351 /* 2352 * reset all the bits that we are 'acknowledging' by writing a 2353 * '1' to each bit position that was set (writing a '1' 2354 * *clears* the bit) 2355 */ 2356 outb(sc->nic_addr + ED_P0_ISR, isr); 2357 2358 /* 2359 * Handle transmitter interrupts. Handle these first because 2360 * the receiver will reset the board under some conditions. 2361 */ 2362 if (isr & (ED_ISR_PTX | ED_ISR_TXE)) { 2363 u_char collisions = inb(sc->nic_addr + ED_P0_NCR) & 0x0f; 2364 2365 /* 2366 * Check for transmit error. If a TX completed with an 2367 * error, we end up throwing the packet away. Really 2368 * the only error that is possible is excessive 2369 * collisions, and in this case it is best to allow 2370 * the automatic mechanisms of TCP to backoff the 2371 * flow. Of course, with UDP we're screwed, but this 2372 * is expected when a network is heavily loaded. 2373 */ 2374 (void) inb(sc->nic_addr + ED_P0_TSR); 2375 if (isr & ED_ISR_TXE) { 2376 u_char tsr; 2377 2378 /* 2379 * Excessive collisions (16) 2380 */ 2381 tsr = inb(sc->nic_addr + ED_P0_TSR); 2382 if ((tsr & ED_TSR_ABT) 2383 && (collisions == 0)) { 2384 2385 /* 2386 * When collisions total 16, the 2387 * P0_NCR will indicate 0, and the 2388 * TSR_ABT is set. 2389 */ 2390 collisions = 16; 2391 sc->mibdata.dot3StatsExcessiveCollisions++; 2392 sc->mibdata.dot3StatsCollFrequencies[15]++; 2393 } 2394 if (tsr & ED_TSR_OWC) 2395 sc->mibdata.dot3StatsLateCollisions++; 2396 if (tsr & ED_TSR_CDH) 2397 sc->mibdata.dot3StatsSQETestErrors++; 2398 if (tsr & ED_TSR_CRS) 2399 sc->mibdata.dot3StatsCarrierSenseErrors++; 2400 if (tsr & ED_TSR_FU) 2401 sc->mibdata.dot3StatsInternalMacTransmitErrors++; 2402 2403 /* 2404 * update output errors counter 2405 */ 2406 ifp->if_oerrors++; 2407 } else { 2408 2409 /* 2410 * Update total number of successfully 2411 * transmitted packets. 2412 */ 2413 ifp->if_opackets++; 2414 } 2415 2416 /* 2417 * reset tx busy and output active flags 2418 */ 2419 sc->xmit_busy = 0; 2420 ifp->if_flags &= ~IFF_OACTIVE; 2421 2422 /* 2423 * clear watchdog timer 2424 */ 2425 ifp->if_timer = 0; 2426 2427 /* 2428 * Add in total number of collisions on last 2429 * transmission. 2430 */ 2431 ifp->if_collisions += collisions; 2432 switch(collisions) { 2433 case 0: 2434 case 16: 2435 break; 2436 case 1: 2437 sc->mibdata.dot3StatsSingleCollisionFrames++; 2438 sc->mibdata.dot3StatsCollFrequencies[0]++; 2439 break; 2440 default: 2441 sc->mibdata.dot3StatsMultipleCollisionFrames++; 2442 sc->mibdata. 2443 dot3StatsCollFrequencies[collisions-1] 2444 ++; 2445 break; 2446 } 2447 2448 /* 2449 * Decrement buffer in-use count if not zero (can only 2450 * be zero if a transmitter interrupt occured while 2451 * not actually transmitting). If data is ready to 2452 * transmit, start it transmitting, otherwise defer 2453 * until after handling receiver 2454 */ 2455 if (sc->txb_inuse && --sc->txb_inuse) 2456 ed_xmit(sc); 2457 } 2458 2459 /* 2460 * Handle receiver interrupts 2461 */ 2462 if (isr & (ED_ISR_PRX | ED_ISR_RXE | ED_ISR_OVW)) { 2463 2464 /* 2465 * Overwrite warning. In order to make sure that a 2466 * lockup of the local DMA hasn't occurred, we reset 2467 * and re-init the NIC. The NSC manual suggests only a 2468 * partial reset/re-init is necessary - but some chips 2469 * seem to want more. The DMA lockup has been seen 2470 * only with early rev chips - Methinks this bug was 2471 * fixed in later revs. -DG 2472 */ 2473 if (isr & ED_ISR_OVW) { 2474 ifp->if_ierrors++; 2475#ifdef DIAGNOSTIC 2476 log(LOG_WARNING, 2477 "ed%d: warning - receiver ring buffer overrun\n", 2478 ifp->if_unit); 2479#endif 2480 2481 /* 2482 * Stop/reset/re-init NIC 2483 */ 2484 ed_reset(ifp); 2485 } else { 2486 2487 /* 2488 * Receiver Error. One or more of: CRC error, 2489 * frame alignment error FIFO overrun, or 2490 * missed packet. 2491 */ 2492 if (isr & ED_ISR_RXE) { 2493 u_char rsr; 2494 rsr = inb(sc->nic_addr + ED_P0_RSR); 2495 if (rsr & ED_RSR_CRC) 2496 sc->mibdata.dot3StatsFCSErrors++; 2497 if (rsr & ED_RSR_FAE) 2498 sc->mibdata.dot3StatsAlignmentErrors++; 2499 if (rsr & ED_RSR_FO) 2500 sc->mibdata.dot3StatsInternalMacReceiveErrors++; 2501 ifp->if_ierrors++; 2502#ifdef ED_DEBUG 2503 printf("ed%d: receive error %x\n", ifp->if_unit, 2504 inb(sc->nic_addr + ED_P0_RSR)); 2505#endif 2506 } 2507 2508 /* 2509 * Go get the packet(s) XXX - Doing this on an 2510 * error is dubious because there shouldn't be 2511 * any data to get (we've configured the 2512 * interface to not accept packets with 2513 * errors). 2514 */ 2515 2516 /* 2517 * Enable 16bit access to shared memory first 2518 * on WD/SMC boards. 2519 */ 2520 if (sc->isa16bit && 2521 (sc->vendor == ED_VENDOR_WD_SMC)) { 2522 2523 outb(sc->asic_addr + ED_WD_LAAR, 2524 sc->wd_laar_proto | ED_WD_LAAR_M16EN); 2525 if (sc->is790) { 2526 outb(sc->asic_addr + ED_WD_MSR, 2527 ED_WD_MSR_MENB); 2528 } 2529 } 2530 ed_rint(sc); 2531 2532 /* disable 16bit access */ 2533 if (sc->isa16bit && 2534 (sc->vendor == ED_VENDOR_WD_SMC)) { 2535 2536 if (sc->is790) { 2537 outb(sc->asic_addr + ED_WD_MSR, 0x00); 2538 } 2539 outb(sc->asic_addr + ED_WD_LAAR, 2540 sc->wd_laar_proto & ~ED_WD_LAAR_M16EN); 2541 } 2542 } 2543 } 2544 2545 /* 2546 * If it looks like the transmitter can take more data, 2547 * attempt to start output on the interface. This is done 2548 * after handling the receiver to give the receiver priority. 2549 */ 2550 if ((ifp->if_flags & IFF_OACTIVE) == 0) 2551 ed_start(ifp); 2552 2553 /* 2554 * return NIC CR to standard state: page 0, remote DMA 2555 * complete, start (toggling the TXP bit off, even if was just 2556 * set in the transmit routine, is *okay* - it is 'edge' 2557 * triggered from low to high) 2558 */ 2559 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA); 2560 2561 /* 2562 * If the Network Talley Counters overflow, read them to reset 2563 * them. It appears that old 8390's won't clear the ISR flag 2564 * otherwise - resulting in an infinite loop. 2565 */ 2566 if (isr & ED_ISR_CNT) { 2567 (void) inb(sc->nic_addr + ED_P0_CNTR0); 2568 (void) inb(sc->nic_addr + ED_P0_CNTR1); 2569 (void) inb(sc->nic_addr + ED_P0_CNTR2); 2570 } 2571 } 2572} 2573 2574static void 2575edintr(unit) 2576 int unit; 2577{ 2578 edintr_sc (&ed_softc[unit]); 2579} 2580 2581/* 2582 * Process an ioctl request. This code needs some work - it looks 2583 * pretty ugly. 2584 */ 2585static int 2586ed_ioctl(ifp, command, data) 2587 register struct ifnet *ifp; 2588 u_long command; 2589 caddr_t data; 2590{ 2591 struct ed_softc *sc = ifp->if_softc; 2592 int s, error = 0; 2593 2594 if (sc->gone) { 2595 ifp->if_flags &= ~IFF_RUNNING; 2596 return ENXIO; 2597 } 2598 s = splimp(); 2599 2600 switch (command) { 2601 2602 case SIOCSIFADDR: 2603 case SIOCGIFADDR: 2604 case SIOCSIFMTU: 2605 error = ether_ioctl(ifp, command, data); 2606 break; 2607 2608 case SIOCSIFFLAGS: 2609 2610 /* 2611 * If the interface is marked up and stopped, then start it. 2612 * If it is marked down and running, then stop it. 2613 */ 2614 if (ifp->if_flags & IFF_UP) { 2615 if ((ifp->if_flags & IFF_RUNNING) == 0) 2616 ed_init(sc); 2617 } else { 2618 if (ifp->if_flags & IFF_RUNNING) { 2619 ed_stop(sc); 2620 ifp->if_flags &= ~IFF_RUNNING; 2621 } 2622 } 2623 2624#if NBPFILTER > 0 2625 2626 /* 2627 * Promiscuous flag may have changed, so reprogram the RCR. 2628 */ 2629 ed_setrcr(sc); 2630#endif 2631 2632 /* 2633 * An unfortunate hack to provide the (required) software 2634 * control of the tranceiver for 3Com boards. The ALTPHYS flag 2635 * disables the tranceiver if set. 2636 */ 2637 if (sc->vendor == ED_VENDOR_3COM) { 2638 if (ifp->if_flags & IFF_ALTPHYS) { 2639 outb(sc->asic_addr + ED_3COM_CR, 0); 2640 } else { 2641 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL); 2642 } 2643 } else if (sc->vendor == ED_VENDOR_HP) 2644 ed_hpp_set_physical_link(sc); 2645 break; 2646 2647 case SIOCADDMULTI: 2648 case SIOCDELMULTI: 2649 /* 2650 * Multicast list has changed; set the hardware filter 2651 * accordingly. 2652 */ 2653 ed_setrcr(sc); 2654 error = 0; 2655 break; 2656 2657 default: 2658 error = EINVAL; 2659 } 2660 (void) splx(s); 2661 return (error); 2662} 2663 2664/* 2665 * Given a source and destination address, copy 'amount' of a packet from 2666 * the ring buffer into a linear destination buffer. Takes into account 2667 * ring-wrap. 2668 */ 2669static __inline char * 2670ed_ring_copy(sc, src, dst, amount) 2671 struct ed_softc *sc; 2672 char *src; 2673 char *dst; 2674 u_short amount; 2675{ 2676 u_short tmp_amount; 2677 2678 /* does copy wrap to lower addr in ring buffer? */ 2679 if (src + amount > sc->mem_end) { 2680 tmp_amount = sc->mem_end - src; 2681 2682 /* copy amount up to end of NIC memory */ 2683 if (sc->mem_shared) 2684 bcopy(src, dst, tmp_amount); 2685 else 2686 ed_pio_readmem(sc, (int)src, dst, tmp_amount); 2687 2688 amount -= tmp_amount; 2689 src = sc->mem_ring; 2690 dst += tmp_amount; 2691 } 2692 if (sc->mem_shared) 2693 bcopy(src, dst, amount); 2694 else 2695 ed_pio_readmem(sc, (int)src, dst, amount); 2696 2697 return (src + amount); 2698} 2699 2700/* 2701 * Retreive packet from shared memory and send to the next level up via 2702 * ether_input(). If there is a BPF listener, give a copy to BPF, too. 2703 */ 2704static void 2705ed_get_packet(sc, buf, len, multicast) 2706 struct ed_softc *sc; 2707 char *buf; 2708 u_short len; 2709 int multicast; 2710{ 2711 struct ether_header *eh; 2712 struct mbuf *m; 2713 2714 /* Allocate a header mbuf */ 2715 MGETHDR(m, M_DONTWAIT, MT_DATA); 2716 if (m == NULL) 2717 return; 2718 m->m_pkthdr.rcvif = &sc->arpcom.ac_if; 2719 m->m_pkthdr.len = m->m_len = len; 2720 2721 /* 2722 * We always put the received packet in a single buffer - 2723 * either with just an mbuf header or in a cluster attached 2724 * to the header. The +2 is to compensate for the alignment 2725 * fixup below. 2726 */ 2727 if ((len + 2) > MHLEN) { 2728 /* Attach an mbuf cluster */ 2729 MCLGET(m, M_DONTWAIT); 2730 2731 /* Insist on getting a cluster */ 2732 if ((m->m_flags & M_EXT) == 0) { 2733 m_freem(m); 2734 return; 2735 } 2736 } 2737 2738 /* 2739 * The +2 is to longword align the start of the real packet. 2740 * This is important for NFS. 2741 */ 2742 m->m_data += 2; 2743 eh = mtod(m, struct ether_header *); 2744 2745#ifdef BRIDGE 2746 /* 2747 * Get link layer header, invoke brige_in, then 2748 * depending on the outcome of the test fetch the rest of the 2749 * packet and either pass up or call bdg_forward. 2750 */ 2751 if (do_bridge) { 2752 struct ifnet *ifp ; 2753 int need_more = 1 ; /* in case not bpf */ 2754 2755#if NBPFILTER > 0 2756 if (sc->arpcom.ac_if.if_bpf) { 2757 need_more = 0 ; 2758 ed_ring_copy(sc, buf, (char *)eh, len); 2759 bpf_mtap(&sc->arpcom.ac_if, m); 2760 } else 2761#endif 2762 ed_ring_copy(sc, buf, (char *)eh, 14); 2763 ifp = bridge_in(m); 2764 if (ifp == BDG_DROP) { 2765 m_freem(m); 2766 return ; 2767 } 2768 /* else fetch rest of pkt and continue */ 2769 if (need_more && len > 14) 2770 ed_ring_copy(sc, buf+14, (char *)(eh+1), len - 14); 2771 if (ifp != BDG_LOCAL ) 2772 bdg_forward(&m, ifp); /* not local, need forwarding */ 2773 if (ifp == BDG_LOCAL || ifp == BDG_BCAST || ifp == BDG_MCAST) 2774 goto getit ; 2775 /* not local and not multicast, just drop it */ 2776 if (m) 2777 m_freem(m); 2778 return ; 2779 } 2780#endif 2781 /* 2782 * Get packet, including link layer address, from interface. 2783 */ 2784 ed_ring_copy(sc, buf, (char *)eh, len); 2785 2786#if NBPFILTER > 0 2787 2788 /* 2789 * Check if there's a BPF listener on this interface. If so, hand off 2790 * the raw packet to bpf. 2791 */ 2792 if (sc->arpcom.ac_if.if_bpf) 2793 bpf_mtap(&sc->arpcom.ac_if, m); 2794#endif 2795 /* 2796 * If we are in promiscuous mode, we have to check whether 2797 * this packet is really for us. 2798 */ 2799 if ((sc->arpcom.ac_if.if_flags & IFF_PROMISC) && 2800 bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr, 2801 sizeof(eh->ether_dhost)) != 0 && multicast == 0) { 2802 m_freem(m); 2803 return; 2804 } 2805 2806getit: 2807 /* 2808 * Remove link layer address. 2809 */ 2810 m->m_pkthdr.len = m->m_len = len - sizeof(struct ether_header); 2811 m->m_data += sizeof(struct ether_header); 2812 2813 ether_input(&sc->arpcom.ac_if, eh, m); 2814 return; 2815} 2816 2817/* 2818 * Supporting routines 2819 */ 2820 2821/* 2822 * Given a NIC memory source address and a host memory destination 2823 * address, copy 'amount' from NIC to host using Programmed I/O. 2824 * The 'amount' is rounded up to a word - okay as long as mbufs 2825 * are word sized. 2826 * This routine is currently Novell-specific. 2827 */ 2828static void 2829ed_pio_readmem(sc, src, dst, amount) 2830 struct ed_softc *sc; 2831 int src; 2832 unsigned char *dst; 2833 unsigned short amount; 2834{ 2835 /* HP cards need special handling */ 2836 if (sc->vendor == ED_VENDOR_HP && sc->type == ED_TYPE_HP_PCLANPLUS) { 2837 ed_hpp_readmem(sc, src, dst, amount); 2838 return; 2839 } 2840 2841 /* Regular Novell cards */ 2842 /* select page 0 registers */ 2843 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STA); 2844 2845 /* round up to a word */ 2846 if (amount & 1) 2847 ++amount; 2848 2849 /* set up DMA byte count */ 2850 outb(sc->nic_addr + ED_P0_RBCR0, amount); 2851 outb(sc->nic_addr + ED_P0_RBCR1, amount >> 8); 2852 2853 /* set up source address in NIC mem */ 2854 outb(sc->nic_addr + ED_P0_RSAR0, src); 2855 outb(sc->nic_addr + ED_P0_RSAR1, src >> 8); 2856 2857 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD0 | ED_CR_STA); 2858 2859 if (sc->isa16bit) { 2860 insw(sc->asic_addr + ED_NOVELL_DATA, dst, amount / 2); 2861 } else 2862 insb(sc->asic_addr + ED_NOVELL_DATA, dst, amount); 2863 2864} 2865 2866/* 2867 * Stripped down routine for writing a linear buffer to NIC memory. 2868 * Only used in the probe routine to test the memory. 'len' must 2869 * be even. 2870 */ 2871static void 2872ed_pio_writemem(sc, src, dst, len) 2873 struct ed_softc *sc; 2874 char *src; 2875 unsigned short dst; 2876 unsigned short len; 2877{ 2878 int maxwait = 200; /* about 240us */ 2879 2880 if (sc->vendor == ED_VENDOR_NOVELL) { 2881 2882 /* select page 0 registers */ 2883 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STA); 2884 2885 /* reset remote DMA complete flag */ 2886 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC); 2887 2888 /* set up DMA byte count */ 2889 outb(sc->nic_addr + ED_P0_RBCR0, len); 2890 outb(sc->nic_addr + ED_P0_RBCR1, len >> 8); 2891 2892 /* set up destination address in NIC mem */ 2893 outb(sc->nic_addr + ED_P0_RSAR0, dst); 2894 outb(sc->nic_addr + ED_P0_RSAR1, dst >> 8); 2895 2896 /* set remote DMA write */ 2897 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD1 | ED_CR_STA); 2898 2899 if (sc->isa16bit) 2900 outsw(sc->asic_addr + ED_NOVELL_DATA, src, len / 2); 2901 else 2902 outsb(sc->asic_addr + ED_NOVELL_DATA, src, len); 2903 2904 /* 2905 * Wait for remote DMA complete. This is necessary because on the 2906 * transmit side, data is handled internally by the NIC in bursts and 2907 * we can't start another remote DMA until this one completes. Not 2908 * waiting causes really bad things to happen - like the NIC 2909 * irrecoverably jamming the ISA bus. 2910 */ 2911 while (((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait); 2912 2913 } else if ((sc->vendor == ED_VENDOR_HP) && 2914 (sc->type == ED_TYPE_HP_PCLANPLUS)) { 2915 2916 /* HP PCLAN+ */ 2917 2918 /* reset remote DMA complete flag */ 2919 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC); 2920 2921 /* program the write address in RAM */ 2922 outw(sc->asic_addr + ED_HPP_PAGE_0, dst); 2923 2924 if (sc->hpp_mem_start) { 2925 u_short *s = (u_short *) src; 2926 volatile u_short *d = (u_short *) sc->hpp_mem_start; 2927 u_short *const fence = s + (len >> 1); 2928 2929 /* 2930 * Enable memory mapped access. 2931 */ 2932 2933 outw(sc->asic_addr + ED_HPP_OPTION, 2934 sc->hpp_options & 2935 ~(ED_HPP_OPTION_MEM_DISABLE | 2936 ED_HPP_OPTION_BOOT_ROM_ENB)); 2937 2938 /* 2939 * Copy to NIC memory. 2940 */ 2941 2942 while (s < fence) 2943 *d = *s++; 2944 2945 /* 2946 * Restore Boot ROM access. 2947 */ 2948 2949 outw(sc->asic_addr + ED_HPP_OPTION, 2950 sc->hpp_options); 2951 2952 } else { 2953 /* write data using I/O writes */ 2954 outsw(sc->asic_addr + ED_HPP_PAGE_4, src, len / 2); 2955 } 2956 2957 } 2958} 2959 2960/* 2961 * Write an mbuf chain to the destination NIC memory address using 2962 * programmed I/O. 2963 */ 2964static u_short 2965ed_pio_write_mbufs(sc, m, dst) 2966 struct ed_softc *sc; 2967 struct mbuf *m; 2968 int dst; 2969{ 2970 struct ifnet *ifp = (struct ifnet *)sc; 2971 unsigned short total_len, dma_len; 2972 struct mbuf *mp; 2973 int maxwait = 200; /* about 240us */ 2974 2975 /* HP PC Lan+ cards need special handling */ 2976 if ((sc->vendor == ED_VENDOR_HP) && 2977 (sc->type == ED_TYPE_HP_PCLANPLUS)) { 2978 return ed_hpp_write_mbufs(sc, m, dst); 2979 } 2980 2981 /* First, count up the total number of bytes to copy */ 2982 for (total_len = 0, mp = m; mp; mp = mp->m_next) 2983 total_len += mp->m_len; 2984 2985 dma_len = total_len; 2986 if (sc->isa16bit && (dma_len & 1)) 2987 dma_len++; 2988 2989 /* select page 0 registers */ 2990 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STA); 2991 2992 /* reset remote DMA complete flag */ 2993 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC); 2994 2995 /* set up DMA byte count */ 2996 outb(sc->nic_addr + ED_P0_RBCR0, dma_len); 2997 outb(sc->nic_addr + ED_P0_RBCR1, dma_len >> 8); 2998 2999 /* set up destination address in NIC mem */ 3000 outb(sc->nic_addr + ED_P0_RSAR0, dst); 3001 outb(sc->nic_addr + ED_P0_RSAR1, dst >> 8); 3002 3003 /* set remote DMA write */ 3004 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD1 | ED_CR_STA); 3005 3006 /* 3007 * Transfer the mbuf chain to the NIC memory. 3008 * 16-bit cards require that data be transferred as words, and only words. 3009 * So that case requires some extra code to patch over odd-length mbufs. 3010 */ 3011 3012 if (!sc->isa16bit) { 3013 /* NE1000s are easy */ 3014 while (m) { 3015 if (m->m_len) { 3016 outsb(sc->asic_addr + ED_NOVELL_DATA, 3017 m->m_data, m->m_len); 3018 } 3019 m = m->m_next; 3020 } 3021 } else { 3022 /* NE2000s are a pain */ 3023 unsigned char *data; 3024 int len, wantbyte; 3025 unsigned char savebyte[2]; 3026 3027 wantbyte = 0; 3028 3029 while (m) { 3030 len = m->m_len; 3031 if (len) { 3032 data = mtod(m, caddr_t); 3033 /* finish the last word */ 3034 if (wantbyte) { 3035 savebyte[1] = *data; 3036 outw(sc->asic_addr + ED_NOVELL_DATA, *(u_short *)savebyte); 3037 data++; 3038 len--; 3039 wantbyte = 0; 3040 } 3041 /* output contiguous words */ 3042 if (len > 1) { 3043 outsw(sc->asic_addr + ED_NOVELL_DATA, 3044 data, len >> 1); 3045 data += len & ~1; 3046 len &= 1; 3047 } 3048 /* save last byte, if necessary */ 3049 if (len == 1) { 3050 savebyte[0] = *data; 3051 wantbyte = 1; 3052 } 3053 } 3054 m = m->m_next; 3055 } 3056 /* spit last byte */ 3057 if (wantbyte) { 3058 outw(sc->asic_addr + ED_NOVELL_DATA, *(u_short *)savebyte); 3059 } 3060 } 3061 3062 /* 3063 * Wait for remote DMA complete. This is necessary because on the 3064 * transmit side, data is handled internally by the NIC in bursts and 3065 * we can't start another remote DMA until this one completes. Not 3066 * waiting causes really bad things to happen - like the NIC 3067 * irrecoverably jamming the ISA bus. 3068 */ 3069 while (((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait); 3070 3071 if (!maxwait) { 3072 log(LOG_WARNING, "ed%d: remote transmit DMA failed to complete\n", 3073 ifp->if_unit); 3074 ed_reset(ifp); 3075 return(0); 3076 } 3077 return (total_len); 3078} 3079 3080/* 3081 * Support routines to handle the HP PC Lan+ card. 3082 */ 3083 3084/* 3085 * HP PC Lan+: Read from NIC memory, using either PIO or memory mapped 3086 * IO. 3087 */ 3088 3089static void 3090ed_hpp_readmem(sc, src, dst, amount) 3091 struct ed_softc *sc; 3092 unsigned short src; 3093 unsigned char *dst; 3094 unsigned short amount; 3095{ 3096 3097 int use_32bit_access = !(sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS); 3098 3099 3100 /* Program the source address in RAM */ 3101 outw(sc->asic_addr + ED_HPP_PAGE_2, src); 3102 3103 /* 3104 * The HP PC Lan+ card supports word reads as well as 3105 * a memory mapped i/o port that is aliased to every 3106 * even address on the board. 3107 */ 3108 3109 if (sc->hpp_mem_start) { 3110 3111 /* Enable memory mapped access. */ 3112 outw(sc->asic_addr + ED_HPP_OPTION, 3113 sc->hpp_options & 3114 ~(ED_HPP_OPTION_MEM_DISABLE | 3115 ED_HPP_OPTION_BOOT_ROM_ENB)); 3116 3117 if (use_32bit_access && (amount > 3)) { 3118 u_long *dl = (u_long *) dst; 3119 volatile u_long *const sl = 3120 (u_long *) sc->hpp_mem_start; 3121 u_long *const fence = dl + (amount >> 2); 3122 3123 /* Copy out NIC data. We could probably write this 3124 as a `movsl'. The currently generated code is lousy. 3125 */ 3126 3127 while (dl < fence) 3128 *dl++ = *sl; 3129 3130 dst += (amount & ~3); 3131 amount &= 3; 3132 3133 } 3134 3135 /* Finish off any words left, as a series of short reads */ 3136 if (amount > 1) { 3137 u_short *d = (u_short *) dst; 3138 volatile u_short *const s = 3139 (u_short *) sc->hpp_mem_start; 3140 u_short *const fence = d + (amount >> 1); 3141 3142 /* Copy out NIC data. */ 3143 3144 while (d < fence) 3145 *d++ = *s; 3146 3147 dst += (amount & ~1); 3148 amount &= 1; 3149 } 3150 3151 /* 3152 * read in a byte; however we need to always read 16 bits 3153 * at a time or the hardware gets into a funny state 3154 */ 3155 3156 if (amount == 1) { 3157 /* need to read in a short and copy LSB */ 3158 volatile u_short *const s = 3159 (volatile u_short *) sc->hpp_mem_start; 3160 3161 *dst = (*s) & 0xFF; 3162 } 3163 3164 /* Restore Boot ROM access. */ 3165 3166 outw(sc->asic_addr + ED_HPP_OPTION, 3167 sc->hpp_options); 3168 3169 3170 } else { 3171 /* Read in data using the I/O port */ 3172 if (use_32bit_access && (amount > 3)) { 3173 insl(sc->asic_addr + ED_HPP_PAGE_4, dst, amount >> 2); 3174 dst += (amount & ~3); 3175 amount &= 3; 3176 } 3177 if (amount > 1) { 3178 insw(sc->asic_addr + ED_HPP_PAGE_4, dst, amount >> 1); 3179 dst += (amount & ~1); 3180 amount &= 1; 3181 } 3182 if (amount == 1) { /* read in a short and keep the LSB */ 3183 *dst = inw(sc->asic_addr + ED_HPP_PAGE_4) & 0xFF; 3184 } 3185 } 3186} 3187 3188/* 3189 * Write to HP PC Lan+ NIC memory. Access to the NIC can be by using 3190 * outsw() or via the memory mapped interface to the same register. 3191 * Writes have to be in word units; byte accesses won't work and may cause 3192 * the NIC to behave wierdly. Long word accesses are permitted if the ASIC 3193 * allows it. 3194 */ 3195 3196static u_short 3197ed_hpp_write_mbufs(struct ed_softc *sc, struct mbuf *m, int dst) 3198{ 3199 int len, wantbyte; 3200 unsigned short total_len; 3201 unsigned char savebyte[2]; 3202 volatile u_short * const d = 3203 (volatile u_short *) sc->hpp_mem_start; 3204 int use_32bit_accesses = !(sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS); 3205 3206 /* select page 0 registers */ 3207 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA); 3208 3209 /* reset remote DMA complete flag */ 3210 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC); 3211 3212 /* program the write address in RAM */ 3213 outw(sc->asic_addr + ED_HPP_PAGE_0, dst); 3214 3215 if (sc->hpp_mem_start) /* enable memory mapped I/O */ 3216 outw(sc->asic_addr + ED_HPP_OPTION, sc->hpp_options & 3217 ~(ED_HPP_OPTION_MEM_DISABLE | 3218 ED_HPP_OPTION_BOOT_ROM_ENB)); 3219 3220 wantbyte = 0; 3221 total_len = 0; 3222 3223 if (sc->hpp_mem_start) { /* Memory mapped I/O port */ 3224 while (m) { 3225 total_len += (len = m->m_len); 3226 if (len) { 3227 caddr_t data = mtod(m, caddr_t); 3228 /* finish the last word of the previous mbuf */ 3229 if (wantbyte) { 3230 savebyte[1] = *data; 3231 *d = *((ushort *) savebyte); 3232 data++; len--; wantbyte = 0; 3233 } 3234 /* output contiguous words */ 3235 if ((len > 3) && (use_32bit_accesses)) { 3236 volatile u_long *const dl = 3237 (volatile u_long *) d; 3238 u_long *sl = (u_long *) data; 3239 u_long *fence = sl + (len >> 2); 3240 3241 while (sl < fence) 3242 *dl = *sl++; 3243 3244 data += (len & ~3); 3245 len &= 3; 3246 } 3247 /* finish off remain 16 bit writes */ 3248 if (len > 1) { 3249 u_short *s = (u_short *) data; 3250 u_short *fence = s + (len >> 1); 3251 3252 while (s < fence) 3253 *d = *s++; 3254 3255 data += (len & ~1); 3256 len &= 1; 3257 } 3258 /* save last byte if needed */ 3259 if ((wantbyte = (len == 1)) != 0) 3260 savebyte[0] = *data; 3261 } 3262 m = m->m_next; /* to next mbuf */ 3263 } 3264 if (wantbyte) /* write last byte */ 3265 *d = *((u_short *) savebyte); 3266 } else { 3267 /* use programmed I/O */ 3268 while (m) { 3269 total_len += (len = m->m_len); 3270 if (len) { 3271 caddr_t data = mtod(m, caddr_t); 3272 /* finish the last word of the previous mbuf */ 3273 if (wantbyte) { 3274 savebyte[1] = *data; 3275 outw(sc->asic_addr + ED_HPP_PAGE_4, 3276 *((u_short *)savebyte)); 3277 data++; 3278 len--; 3279 wantbyte = 0; 3280 } 3281 /* output contiguous words */ 3282 if ((len > 3) && use_32bit_accesses) { 3283 outsl(sc->asic_addr + ED_HPP_PAGE_4, 3284 data, len >> 2); 3285 data += (len & ~3); 3286 len &= 3; 3287 } 3288 /* finish off remaining 16 bit accesses */ 3289 if (len > 1) { 3290 outsw(sc->asic_addr + ED_HPP_PAGE_4, 3291 data, len >> 1); 3292 data += (len & ~1); 3293 len &= 1; 3294 } 3295 if ((wantbyte = (len == 1)) != 0) 3296 savebyte[0] = *data; 3297 3298 } /* if len != 0 */ 3299 m = m->m_next; 3300 } 3301 if (wantbyte) /* spit last byte */ 3302 outw(sc->asic_addr + ED_HPP_PAGE_4, 3303 *(u_short *)savebyte); 3304 3305 } 3306 3307 if (sc->hpp_mem_start) /* turn off memory mapped i/o */ 3308 outw(sc->asic_addr + ED_HPP_OPTION, 3309 sc->hpp_options); 3310 3311 return (total_len); 3312} 3313 3314static void 3315ed_setrcr(sc) 3316 struct ed_softc *sc; 3317{ 3318 struct ifnet *ifp = (struct ifnet *)sc; 3319 int i; 3320 3321 /* set page 1 registers */ 3322 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP); 3323 3324 if (ifp->if_flags & IFF_PROMISC) { 3325 3326 /* 3327 * Reconfigure the multicast filter. 3328 */ 3329 for (i = 0; i < 8; i++) 3330 outb(sc->nic_addr + ED_P1_MAR0 + i, 0xff); 3331 3332 /* 3333 * And turn on promiscuous mode. Also enable reception of 3334 * runts and packets with CRC & alignment errors. 3335 */ 3336 /* Set page 0 registers */ 3337 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP); 3338 3339 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_PRO | ED_RCR_AM | 3340 ED_RCR_AB | ED_RCR_AR | ED_RCR_SEP); 3341 } else { 3342 /* set up multicast addresses and filter modes */ 3343 if (ifp->if_flags & IFF_MULTICAST) { 3344 u_long mcaf[2]; 3345 3346 if (ifp->if_flags & IFF_ALLMULTI) { 3347 mcaf[0] = 0xffffffff; 3348 mcaf[1] = 0xffffffff; 3349 } else 3350 ds_getmcaf(sc, mcaf); 3351 3352 /* 3353 * Set multicast filter on chip. 3354 */ 3355 for (i = 0; i < 8; i++) 3356 outb(sc->nic_addr + ED_P1_MAR0 + i, ((u_char *) mcaf)[i]); 3357 3358 /* Set page 0 registers */ 3359 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP); 3360 3361 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_AM | ED_RCR_AB); 3362 } else { 3363 3364 /* 3365 * Initialize multicast address hashing registers to 3366 * not accept multicasts. 3367 */ 3368 for (i = 0; i < 8; ++i) 3369 outb(sc->nic_addr + ED_P1_MAR0 + i, 0x00); 3370 3371 /* Set page 0 registers */ 3372 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP); 3373 3374 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_AB); 3375 } 3376 } 3377 3378 /* 3379 * Start interface. 3380 */ 3381 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA); 3382} 3383 3384/* 3385 * Compute crc for ethernet address 3386 */ 3387static u_long 3388ds_crc(ep) 3389 u_char *ep; 3390{ 3391#define POLYNOMIAL 0x04c11db6 3392 register u_long crc = 0xffffffffL; 3393 register int carry, i, j; 3394 register u_char b; 3395 3396 for (i = 6; --i >= 0;) { 3397 b = *ep++; 3398 for (j = 8; --j >= 0;) { 3399 carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01); 3400 crc <<= 1; 3401 b >>= 1; 3402 if (carry) 3403 crc = ((crc ^ POLYNOMIAL) | carry); 3404 } 3405 } 3406 return crc; 3407#undef POLYNOMIAL 3408} 3409 3410/* 3411 * Compute the multicast address filter from the 3412 * list of multicast addresses we need to listen to. 3413 */ 3414static void 3415ds_getmcaf(sc, mcaf) 3416 struct ed_softc *sc; 3417 u_long *mcaf; 3418{ 3419 register u_int index; 3420 register u_char *af = (u_char *) mcaf; 3421 struct ifmultiaddr *ifma; 3422 3423 mcaf[0] = 0; 3424 mcaf[1] = 0; 3425 3426 for (ifma = sc->arpcom.ac_if.if_multiaddrs.lh_first; ifma; 3427 ifma = ifma->ifma_link.le_next) { 3428 if (ifma->ifma_addr->sa_family != AF_LINK) 3429 continue; 3430 index = ds_crc(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)) 3431 >> 26; 3432 af[index >> 3] |= 1 << (index & 7); 3433 } 3434} 3435 3436/* 3437 * support PnP cards if we are using 'em 3438 */ 3439 3440#if NPNP > 0 3441 3442static pnpid_t edpnp_ids[] = { 3443 { 0xd680d041, "NE2000"}, 3444 { 0 } 3445}; 3446 3447static char *edpnp_probe(u_long csn, u_long vend_id); 3448static void edpnp_attach(u_long csn, u_long vend_id, char *name, 3449 struct isa_device *dev); 3450static u_long nedpnp = NED; 3451 3452static struct pnp_device edpnp = { 3453 "edpnp", 3454 edpnp_probe, 3455 edpnp_attach, 3456 &nedpnp, 3457 &net_imask 3458}; 3459DATA_SET (pnpdevice_set, edpnp); 3460 3461static char * 3462edpnp_probe(u_long csn, u_long vend_id) 3463{ 3464 pnpid_t *id; 3465 char *s = NULL; 3466 3467 for(id = edpnp_ids; id->vend_id != 0; id++) { 3468 if (vend_id == id->vend_id) { 3469 s = id->id_str; 3470 break; 3471 } 3472 } 3473 3474 if (s) { 3475 struct pnp_cinfo d; 3476 read_pnp_parms(&d, 0); 3477 if (d.enable == 0 || d.flags & 1) { 3478 printf("CSN %lu is disabled.\n", csn); 3479 return (NULL); 3480 } 3481 3482 } 3483 3484 return (s); 3485} 3486 3487static void 3488edpnp_attach(u_long csn, u_long vend_id, char *name, struct isa_device *dev) 3489{ 3490 struct pnp_cinfo d; 3491 struct isa_device *dvp; 3492 3493 if (dev->id_unit >= NEDTOT) 3494 return; 3495 3496 if (read_pnp_parms(&d, 0) == 0) { 3497 printf("failed to read pnp parms\n"); 3498 return; 3499 } 3500 3501 write_pnp_parms(&d, 0); 3502 3503 enable_pnp_card(); 3504 3505 dev->id_iobase = d.port[0]; 3506 dev->id_irq = (1 << d.irq[0]); 3507 dev->id_ointr = edintr; 3508 dev->id_drq = -1; 3509 3510 if (dev->id_driver == NULL) { 3511 dev->id_driver = &eddriver; 3512 dvp = find_isadev(isa_devtab_net, &eddriver, 0); 3513 if (dvp != NULL) 3514 dev->id_id = dvp->id_id; 3515 } 3516 3517 if ((dev->id_alive = ed_probe(dev)) != 0) 3518 ed_attach_isa(dev); 3519 else 3520 printf("ed%d: probe failed\n", dev->id_unit); 3521} 3522#endif 3523