if_ed.c revision 38505
1/* 2 * Copyright (c) 1995, David Greenman 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $Id: if_ed.c,v 1.143 1998/06/21 18:02:35 bde Exp $ 28 */ 29 30/* 31 * Device driver for National Semiconductor DS8390/WD83C690 based ethernet 32 * adapters. By David Greenman, 29-April-1993 33 * 34 * Currently supports the Western Digital/SMC 8003 and 8013 series, 35 * the SMC Elite Ultra (8216), the 3Com 3c503, the NE1000 and NE2000, 36 * and a variety of similar clones. 37 * 38 */ 39 40#include "ed.h" 41#include "bpfilter.h" 42#include "pnp.h" 43 44#ifndef EXTRA_ED 45# if NPNP > 0 46# define EXTRA_ED 8 47# else 48# define EXTRA_ED 0 49# endif 50#endif 51 52#define NEDTOT (NED + EXTRA_ED) 53 54#include <sys/param.h> 55#include <sys/systm.h> 56#include <sys/sockio.h> 57#include <sys/malloc.h> 58#include <sys/mbuf.h> 59#include <sys/socket.h> 60#include <sys/syslog.h> 61 62#include <net/ethernet.h> 63#include <net/if.h> 64#include <net/if_arp.h> 65#include <net/if_dl.h> 66#include <net/if_mib.h> 67 68#if NBPFILTER > 0 69#include <net/bpf.h> 70#endif 71 72#include <machine/clock.h> 73#include <machine/md_var.h> 74 75#include <i386/isa/isa_device.h> 76#include <i386/isa/icu.h> 77#include <i386/isa/if_edreg.h> 78 79#if NPNP > 0 80#include <i386/isa/pnp.h> 81#endif 82 83/* 84 * ed_softc: per line info and status 85 */ 86struct ed_softc { 87 struct arpcom arpcom; /* ethernet common */ 88 89 char *type_str; /* pointer to type string */ 90 u_char vendor; /* interface vendor */ 91 u_char type; /* interface type code */ 92 u_char gone; /* HW missing, presumed having a good time */ 93 94 u_short asic_addr; /* ASIC I/O bus address */ 95 u_short nic_addr; /* NIC (DS8390) I/O bus address */ 96 97/* 98 * The following 'proto' variable is part of a work-around for 8013EBT asics 99 * being write-only. It's sort of a prototype/shadow of the real thing. 100 */ 101 u_char wd_laar_proto; 102 u_char cr_proto; 103 u_char isa16bit; /* width of access to card 0=8 or 1=16 */ 104 int is790; /* set by the probe code if the card is 790 105 * based */ 106 107/* 108 * HP PC LAN PLUS card support. 109 */ 110 111 u_short hpp_options; /* flags controlling behaviour of the HP card */ 112 u_short hpp_id; /* software revision and other fields */ 113 caddr_t hpp_mem_start; /* Memory-mapped IO register address */ 114 115 caddr_t mem_start; /* NIC memory start address */ 116 caddr_t mem_end; /* NIC memory end address */ 117 u_long mem_size; /* total NIC memory size */ 118 caddr_t mem_ring; /* start of RX ring-buffer (in NIC mem) */ 119 120 u_char mem_shared; /* NIC memory is shared with host */ 121 u_char xmit_busy; /* transmitter is busy */ 122 u_char txb_cnt; /* number of transmit buffers */ 123 u_char txb_inuse; /* number of TX buffers currently in-use */ 124 125 u_char txb_new; /* pointer to where new buffer will be added */ 126 u_char txb_next_tx; /* pointer to next buffer ready to xmit */ 127 u_short txb_len[8]; /* buffered xmit buffer lengths */ 128 u_char tx_page_start; /* first page of TX buffer area */ 129 u_char rec_page_start; /* first page of RX ring-buffer */ 130 u_char rec_page_stop; /* last page of RX ring-buffer */ 131 u_char next_packet; /* pointer to next unread RX packet */ 132 struct ifmib_iso_8802_3 mibdata; /* stuff for network mgmt */ 133}; 134 135static struct ed_softc ed_softc[NEDTOT]; 136 137static int ed_attach __P((struct ed_softc *, int, int)); 138static int ed_attach_isa __P((struct isa_device *)); 139 140static void ed_init __P((void *)); 141static int ed_ioctl __P((struct ifnet *, u_long, caddr_t)); 142static int ed_probe __P((struct isa_device *)); 143static void ed_start __P((struct ifnet *)); 144static void ed_reset __P((struct ifnet *)); 145static void ed_watchdog __P((struct ifnet *)); 146 147static void ed_stop __P((struct ed_softc *)); 148static int ed_probe_generic8390 __P((struct ed_softc *)); 149static int ed_probe_WD80x3 __P((struct isa_device *)); 150static int ed_probe_3Com __P((struct isa_device *)); 151static int ed_probe_Novell __P((struct isa_device *)); 152static int ed_probe_Novell_generic __P((struct ed_softc *, int, int, int)); 153static int ed_probe_HP_pclanp __P((struct isa_device *)); 154 155#include "pci.h" 156#if NPCI > 0 157void *ed_attach_NE2000_pci __P((int, int)); 158#endif 159 160#include "card.h" 161#if NCARD > 0 162static int ed_probe_pccard __P((struct isa_device *, u_char *)); 163#endif 164 165static void ds_getmcaf __P((struct ed_softc *, u_long *)); 166 167static void ed_get_packet __P((struct ed_softc *, char *, /* u_short */ int, int)); 168 169static __inline void ed_rint __P((struct ed_softc *)); 170static __inline void ed_xmit __P((struct ed_softc *)); 171static __inline char * ed_ring_copy __P((struct ed_softc *, char *, char *, 172 /* u_short */ int)); 173static void ed_hpp_set_physical_link __P((struct ed_softc *)); 174static void ed_hpp_readmem __P((struct ed_softc *, int, unsigned char *, 175 /* u_short */ int)); 176static u_short ed_hpp_write_mbufs __P((struct ed_softc *, struct mbuf *, 177 int)); 178 179static void ed_pio_readmem __P((struct ed_softc *, int, unsigned char *, 180 /* u_short */ int)); 181static void ed_pio_writemem __P((struct ed_softc *, char *, 182 /* u_short */ int, /* u_short */ int)); 183static u_short ed_pio_write_mbufs __P((struct ed_softc *, struct mbuf *, 184 int)); 185void edintr_sc __P((struct ed_softc *)); 186 187static void ed_setrcr __P((struct ed_softc *)); 188 189static u_long ds_crc __P((u_char *ep)); 190 191#if (NCARD > 0) || (NPNP > 0) 192#include <sys/kernel.h> 193#endif 194#if NCARD > 0 195#include <sys/select.h> 196#include <pccard/cardinfo.h> 197#include <pccard/slot.h> 198 199/* 200 * PC-Card (PCMCIA) specific code. 201 */ 202static int edinit __P((struct pccard_devinfo *)); 203static void edunload __P((struct pccard_devinfo *)); 204static int card_intr __P((struct pccard_devinfo *)); 205 206static struct pccard_device ed_info = { 207 "ed", 208 edinit, 209 edunload, 210 card_intr, 211 0, /* Attributes - presently unused */ 212 &net_imask /* Interrupt mask for device */ 213 /* XXX - Should this also include net_imask? */ 214}; 215 216DATA_SET(pccarddrv_set, ed_info); 217 218/* 219 * Initialize the device - called from Slot manager. 220 */ 221static int 222edinit(struct pccard_devinfo *devi) 223{ 224 int i; 225 u_char e; 226 struct ed_softc *sc = &ed_softc[devi->isahd.id_unit]; 227 228 /* validate unit number. */ 229 if (devi->isahd.id_unit >= NEDTOT) 230 return(ENODEV); 231 /* 232 * Probe the device. If a value is returned, the 233 * device was found at the location. 234 */ 235 sc->gone = 0; 236 if (ed_probe_pccard(&devi->isahd, devi->misc) == 0) 237 return(ENXIO); 238 e = 0; 239 for (i = 0; i < ETHER_ADDR_LEN; ++i) 240 e |= devi->misc[i]; 241 if (e) 242 for (i = 0; i < ETHER_ADDR_LEN; ++i) 243 sc->arpcom.ac_enaddr[i] = devi->misc[i]; 244 if (ed_attach_isa(&devi->isahd) == 0) 245 return(ENXIO); 246 247 return(0); 248} 249 250/* 251 * edunload - unload the driver and clear the table. 252 * XXX TODO: 253 * This is usually called when the card is ejected, but 254 * can be caused by a modunload of a controller driver. 255 * The idea is to reset the driver's view of the device 256 * and ensure that any driver entry points such as 257 * read and write do not hang. 258 */ 259static void 260edunload(struct pccard_devinfo *devi) 261{ 262 struct ed_softc *sc = &ed_softc[devi->isahd.id_unit]; 263 struct ifnet *ifp = &sc->arpcom.ac_if; 264 265 if (sc->gone) { 266 printf("ed%d: already unloaded\n", devi->isahd.id_unit); 267 return; 268 } 269 ifp->if_flags &= ~IFF_RUNNING; 270 if_down(ifp); 271 sc->gone = 1; 272 printf("ed%d: unload\n", devi->isahd.id_unit); 273} 274 275/* 276 * card_intr - Shared interrupt called from 277 * front end of PC-Card handler. 278 */ 279static int 280card_intr(struct pccard_devinfo *devi) 281{ 282 edintr_sc(&ed_softc[devi->isahd.id_unit]); 283 return(1); 284} 285#endif /* NCARD > 0 */ 286 287struct isa_driver eddriver = { 288 ed_probe, 289 ed_attach_isa, 290 "ed", 291 1 /* We are ultra sensitive */ 292}; 293 294/* 295 * Interrupt conversion table for WD/SMC ASIC/83C584 296 * (IRQ* are defined in icu.h) 297 */ 298static unsigned short ed_intr_mask[] = { 299 IRQ9, 300 IRQ3, 301 IRQ5, 302 IRQ7, 303 IRQ10, 304 IRQ11, 305 IRQ15, 306 IRQ4 307}; 308 309/* 310 * Interrupt conversion table for 83C790 311 */ 312static unsigned short ed_790_intr_mask[] = { 313 0, 314 IRQ9, 315 IRQ3, 316 IRQ5, 317 IRQ7, 318 IRQ10, 319 IRQ11, 320 IRQ15 321}; 322 323/* 324 * Interrupt conversion table for the HP PC LAN+ 325 */ 326 327static unsigned short ed_hpp_intr_mask[] = { 328 0, /* 0 */ 329 0, /* 1 */ 330 0, /* 2 */ 331 IRQ3, /* 3 */ 332 IRQ4, /* 4 */ 333 IRQ5, /* 5 */ 334 IRQ6, /* 6 */ 335 IRQ7, /* 7 */ 336 0, /* 8 */ 337 IRQ9, /* 9 */ 338 IRQ10, /* 10 */ 339 IRQ11, /* 11 */ 340 IRQ12, /* 12 */ 341 0, /* 13 */ 342 0, /* 14 */ 343 IRQ15 /* 15 */ 344}; 345 346/* 347 * Determine if the device is present 348 * 349 * on entry: 350 * a pointer to an isa_device struct 351 * on exit: 352 * NULL if device not found 353 * or # of i/o addresses used (if found) 354 */ 355static int 356ed_probe(isa_dev) 357 struct isa_device *isa_dev; 358{ 359 int nports; 360 361 nports = ed_probe_WD80x3(isa_dev); 362 if (nports) 363 return (nports); 364 365 nports = ed_probe_3Com(isa_dev); 366 if (nports) 367 return (nports); 368 369 nports = ed_probe_Novell(isa_dev); 370 if (nports) 371 return (nports); 372 373 nports = ed_probe_HP_pclanp(isa_dev); 374 if (nports) 375 return (nports); 376 377 return (0); 378} 379 380/* 381 * Generic probe routine for testing for the existance of a DS8390. 382 * Must be called after the NIC has just been reset. This routine 383 * works by looking at certain register values that are guaranteed 384 * to be initialized a certain way after power-up or reset. Seems 385 * not to currently work on the 83C690. 386 * 387 * Specifically: 388 * 389 * Register reset bits set bits 390 * Command Register (CR) TXP, STA RD2, STP 391 * Interrupt Status (ISR) RST 392 * Interrupt Mask (IMR) All bits 393 * Data Control (DCR) LAS 394 * Transmit Config. (TCR) LB1, LB0 395 * 396 * We only look at the CR and ISR registers, however, because looking at 397 * the others would require changing register pages (which would be 398 * intrusive if this isn't an 8390). 399 * 400 * Return 1 if 8390 was found, 0 if not. 401 */ 402 403static int 404ed_probe_generic8390(sc) 405 struct ed_softc *sc; 406{ 407 if ((inb(sc->nic_addr + ED_P0_CR) & 408 (ED_CR_RD2 | ED_CR_TXP | ED_CR_STA | ED_CR_STP)) != 409 (ED_CR_RD2 | ED_CR_STP)) 410 return (0); 411 if ((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RST) != ED_ISR_RST) 412 return (0); 413 414 return (1); 415} 416 417/* 418 * Probe and vendor-specific initialization routine for SMC/WD80x3 boards 419 */ 420static int 421ed_probe_WD80x3(isa_dev) 422 struct isa_device *isa_dev; 423{ 424 struct ed_softc *sc = &ed_softc[isa_dev->id_unit]; 425 int i; 426 u_int memsize, maddr; 427 u_char iptr, isa16bit, sum; 428 429 sc->asic_addr = isa_dev->id_iobase; 430 sc->nic_addr = sc->asic_addr + ED_WD_NIC_OFFSET; 431 sc->is790 = 0; 432 433#ifdef TOSH_ETHER 434 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_POW); 435 DELAY(10000); 436#endif 437 438 /* 439 * Attempt to do a checksum over the station address PROM. If it 440 * fails, it's probably not a SMC/WD board. There is a problem with 441 * this, though: some clone WD boards don't pass the checksum test. 442 * Danpex boards for one. 443 */ 444 for (sum = 0, i = 0; i < 8; ++i) 445 sum += inb(sc->asic_addr + ED_WD_PROM + i); 446 447 if (sum != ED_WD_ROM_CHECKSUM_TOTAL) { 448 449 /* 450 * Checksum is invalid. This often happens with cheap WD8003E 451 * clones. In this case, the checksum byte (the eighth byte) 452 * seems to always be zero. 453 */ 454 if (inb(sc->asic_addr + ED_WD_CARD_ID) != ED_TYPE_WD8003E || 455 inb(sc->asic_addr + ED_WD_PROM + 7) != 0) 456 return (0); 457 } 458 /* reset card to force it into a known state. */ 459#ifdef TOSH_ETHER 460 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_RST | ED_WD_MSR_POW); 461#else 462 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_RST); 463#endif 464 DELAY(100); 465 outb(sc->asic_addr + ED_WD_MSR, inb(sc->asic_addr + ED_WD_MSR) & ~ED_WD_MSR_RST); 466 /* wait in the case this card is reading its EEROM */ 467 DELAY(5000); 468 469 sc->vendor = ED_VENDOR_WD_SMC; 470 sc->type = inb(sc->asic_addr + ED_WD_CARD_ID); 471 472 /* 473 * Set initial values for width/size. 474 */ 475 memsize = 8192; 476 isa16bit = 0; 477 switch (sc->type) { 478 case ED_TYPE_WD8003S: 479 sc->type_str = "WD8003S"; 480 break; 481 case ED_TYPE_WD8003E: 482 sc->type_str = "WD8003E"; 483 break; 484 case ED_TYPE_WD8003EB: 485 sc->type_str = "WD8003EB"; 486 break; 487 case ED_TYPE_WD8003W: 488 sc->type_str = "WD8003W"; 489 break; 490 case ED_TYPE_WD8013EBT: 491 sc->type_str = "WD8013EBT"; 492 memsize = 16384; 493 isa16bit = 1; 494 break; 495 case ED_TYPE_WD8013W: 496 sc->type_str = "WD8013W"; 497 memsize = 16384; 498 isa16bit = 1; 499 break; 500 case ED_TYPE_WD8013EP: /* also WD8003EP */ 501 if (inb(sc->asic_addr + ED_WD_ICR) 502 & ED_WD_ICR_16BIT) { 503 isa16bit = 1; 504 memsize = 16384; 505 sc->type_str = "WD8013EP"; 506 } else { 507 sc->type_str = "WD8003EP"; 508 } 509 break; 510 case ED_TYPE_WD8013WC: 511 sc->type_str = "WD8013WC"; 512 memsize = 16384; 513 isa16bit = 1; 514 break; 515 case ED_TYPE_WD8013EBP: 516 sc->type_str = "WD8013EBP"; 517 memsize = 16384; 518 isa16bit = 1; 519 break; 520 case ED_TYPE_WD8013EPC: 521 sc->type_str = "WD8013EPC"; 522 memsize = 16384; 523 isa16bit = 1; 524 break; 525 case ED_TYPE_SMC8216C: /* 8216 has 16K shared mem -- 8416 has 8K */ 526 case ED_TYPE_SMC8216T: 527 if (sc->type == ED_TYPE_SMC8216C) { 528 sc->type_str = "SMC8216/SMC8216C"; 529 } else { 530 sc->type_str = "SMC8216T"; 531 } 532 533 outb(sc->asic_addr + ED_WD790_HWR, 534 inb(sc->asic_addr + ED_WD790_HWR) | ED_WD790_HWR_SWH); 535 switch (inb(sc->asic_addr + ED_WD790_RAR) & ED_WD790_RAR_SZ64) { 536 case ED_WD790_RAR_SZ64: 537 memsize = 65536; 538 break; 539 case ED_WD790_RAR_SZ32: 540 memsize = 32768; 541 break; 542 case ED_WD790_RAR_SZ16: 543 memsize = 16384; 544 break; 545 case ED_WD790_RAR_SZ8: 546 /* 8216 has 16K shared mem -- 8416 has 8K */ 547 if (sc->type == ED_TYPE_SMC8216C) { 548 sc->type_str = "SMC8416C/SMC8416BT"; 549 } else { 550 sc->type_str = "SMC8416T"; 551 } 552 memsize = 8192; 553 break; 554 } 555 outb(sc->asic_addr + ED_WD790_HWR, 556 inb(sc->asic_addr + ED_WD790_HWR) & ~ED_WD790_HWR_SWH); 557 558 isa16bit = 1; 559 sc->is790 = 1; 560 break; 561#ifdef TOSH_ETHER 562 case ED_TYPE_TOSHIBA1: 563 sc->type_str = "Toshiba1"; 564 memsize = 32768; 565 isa16bit = 1; 566 break; 567 case ED_TYPE_TOSHIBA4: 568 sc->type_str = "Toshiba4"; 569 memsize = 32768; 570 isa16bit = 1; 571 break; 572#endif 573 default: 574 sc->type_str = ""; 575 break; 576 } 577 578 /* 579 * Make some adjustments to initial values depending on what is found 580 * in the ICR. 581 */ 582 if (isa16bit && (sc->type != ED_TYPE_WD8013EBT) 583#ifdef TOSH_ETHER 584 && (sc->type != ED_TYPE_TOSHIBA1) && (sc->type != ED_TYPE_TOSHIBA4) 585#endif 586 && ((inb(sc->asic_addr + ED_WD_ICR) & ED_WD_ICR_16BIT) == 0)) { 587 isa16bit = 0; 588 memsize = 8192; 589 } 590 591#if ED_DEBUG 592 printf("type = %x type_str=%s isa16bit=%d memsize=%d id_msize=%d\n", 593 sc->type, sc->type_str, isa16bit, memsize, isa_dev->id_msize); 594 for (i = 0; i < 8; i++) 595 printf("%x -> %x\n", i, inb(sc->asic_addr + i)); 596#endif 597 598 /* 599 * Allow the user to override the autoconfiguration 600 */ 601 if (isa_dev->id_msize) 602 memsize = isa_dev->id_msize; 603 604 maddr = (u_int) isa_dev->id_maddr & 0xffffff; 605 if (maddr < 0xa0000 || maddr + memsize > 0x1000000) { 606 printf("ed%d: Invalid ISA memory address range configured: 0x%x - 0x%x\n", 607 isa_dev->id_unit, maddr, maddr + memsize); 608 return 0; 609 } 610 611 /* 612 * (note that if the user specifies both of the following flags that 613 * '8bit' mode intentionally has precedence) 614 */ 615 if (isa_dev->id_flags & ED_FLAGS_FORCE_16BIT_MODE) 616 isa16bit = 1; 617 if (isa_dev->id_flags & ED_FLAGS_FORCE_8BIT_MODE) 618 isa16bit = 0; 619 620 /* 621 * If possible, get the assigned interrupt number from the card and 622 * use it. 623 */ 624 if ((sc->type & ED_WD_SOFTCONFIG) && (!sc->is790)) { 625 626 /* 627 * Assemble together the encoded interrupt number. 628 */ 629 iptr = (inb(isa_dev->id_iobase + ED_WD_ICR) & ED_WD_ICR_IR2) | 630 ((inb(isa_dev->id_iobase + ED_WD_IRR) & 631 (ED_WD_IRR_IR0 | ED_WD_IRR_IR1)) >> 5); 632 633 /* 634 * If no interrupt specified (or "?"), use what the board tells us. 635 */ 636 if (isa_dev->id_irq <= 0) 637 isa_dev->id_irq = ed_intr_mask[iptr]; 638 639 /* 640 * Enable the interrupt. 641 */ 642 outb(isa_dev->id_iobase + ED_WD_IRR, 643 inb(isa_dev->id_iobase + ED_WD_IRR) | ED_WD_IRR_IEN); 644 } 645 if (sc->is790) { 646 outb(isa_dev->id_iobase + ED_WD790_HWR, 647 inb(isa_dev->id_iobase + ED_WD790_HWR) | ED_WD790_HWR_SWH); 648 iptr = (((inb(isa_dev->id_iobase + ED_WD790_GCR) & ED_WD790_GCR_IR2) >> 4) | 649 (inb(isa_dev->id_iobase + ED_WD790_GCR) & 650 (ED_WD790_GCR_IR1 | ED_WD790_GCR_IR0)) >> 2); 651 outb(isa_dev->id_iobase + ED_WD790_HWR, 652 inb(isa_dev->id_iobase + ED_WD790_HWR) & ~ED_WD790_HWR_SWH); 653 654 /* 655 * If no interrupt specified (or "?"), use what the board tells us. 656 */ 657 if (isa_dev->id_irq <= 0) 658 isa_dev->id_irq = ed_790_intr_mask[iptr]; 659 660 /* 661 * Enable interrupts. 662 */ 663 outb(isa_dev->id_iobase + ED_WD790_ICR, 664 inb(isa_dev->id_iobase + ED_WD790_ICR) | ED_WD790_ICR_EIL); 665 } 666 if (isa_dev->id_irq <= 0) { 667 printf("ed%d: %s cards don't support auto-detected/assigned interrupts.\n", 668 isa_dev->id_unit, sc->type_str); 669 return (0); 670 } 671 sc->isa16bit = isa16bit; 672 sc->mem_shared = 1; 673 isa_dev->id_msize = memsize; 674 sc->mem_start = (caddr_t) isa_dev->id_maddr; 675 676 /* 677 * allocate one xmit buffer if < 16k, two buffers otherwise 678 */ 679 if ((memsize < 16384) || 680 (isa_dev->id_flags & ED_FLAGS_NO_MULTI_BUFFERING)) { 681 sc->txb_cnt = 1; 682 } else { 683 sc->txb_cnt = 2; 684 } 685 sc->tx_page_start = ED_WD_PAGE_OFFSET; 686 sc->rec_page_start = ED_WD_PAGE_OFFSET + ED_TXBUF_SIZE * sc->txb_cnt; 687 sc->rec_page_stop = ED_WD_PAGE_OFFSET + memsize / ED_PAGE_SIZE; 688 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * sc->rec_page_start); 689 sc->mem_size = memsize; 690 sc->mem_end = sc->mem_start + memsize; 691 692 /* 693 * Get station address from on-board ROM 694 */ 695 for (i = 0; i < ETHER_ADDR_LEN; ++i) 696 sc->arpcom.ac_enaddr[i] = inb(sc->asic_addr + ED_WD_PROM + i); 697 698 /* 699 * Set upper address bits and 8/16 bit access to shared memory. 700 */ 701 if (isa16bit) { 702 if (sc->is790) { 703 sc->wd_laar_proto = inb(sc->asic_addr + ED_WD_LAAR); 704 } else { 705 sc->wd_laar_proto = ED_WD_LAAR_L16EN | 706 ((kvtop(sc->mem_start) >> 19) & ED_WD_LAAR_ADDRHI); 707 } 708 /* 709 * Enable 16bit access 710 */ 711 outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto | 712 ED_WD_LAAR_M16EN); 713 } else { 714 if (((sc->type & ED_WD_SOFTCONFIG) || 715#ifdef TOSH_ETHER 716 (sc->type == ED_TYPE_TOSHIBA1) || (sc->type == ED_TYPE_TOSHIBA4) || 717#endif 718 (sc->type == ED_TYPE_WD8013EBT)) && (!sc->is790)) { 719 sc->wd_laar_proto = (kvtop(sc->mem_start) >> 19) & 720 ED_WD_LAAR_ADDRHI; 721 outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto); 722 } 723 } 724 725 /* 726 * Set address and enable interface shared memory. 727 */ 728 if (!sc->is790) { 729#ifdef TOSH_ETHER 730 outb(sc->asic_addr + ED_WD_MSR + 1, ((kvtop(sc->mem_start) >> 8) & 0xe0) | 4); 731 outb(sc->asic_addr + ED_WD_MSR + 2, ((kvtop(sc->mem_start) >> 16) & 0x0f)); 732 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_MENB | ED_WD_MSR_POW); 733 734#else 735 outb(sc->asic_addr + ED_WD_MSR, ((kvtop(sc->mem_start) >> 13) & 736 ED_WD_MSR_ADDR) | ED_WD_MSR_MENB); 737#endif 738 sc->cr_proto = ED_CR_RD2; 739 } else { 740 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_MENB); 741 outb(sc->asic_addr + ED_WD790_HWR, (inb(sc->asic_addr + ED_WD790_HWR) | ED_WD790_HWR_SWH)); 742 outb(sc->asic_addr + ED_WD790_RAR, ((kvtop(sc->mem_start) >> 13) & 0x0f) | 743 ((kvtop(sc->mem_start) >> 11) & 0x40) | 744 (inb(sc->asic_addr + ED_WD790_RAR) & 0xb0)); 745 outb(sc->asic_addr + ED_WD790_HWR, (inb(sc->asic_addr + ED_WD790_HWR) & ~ED_WD790_HWR_SWH)); 746 sc->cr_proto = 0; 747 } 748 749#if 0 750 printf("starting memory performance test at 0x%x, size %d...\n", 751 sc->mem_start, memsize*16384); 752 for (i = 0; i < 16384; i++) 753 bzero(sc->mem_start, memsize); 754 printf("***DONE***\n"); 755#endif 756 757 /* 758 * Now zero memory and verify that it is clear 759 */ 760 bzero(sc->mem_start, memsize); 761 762 for (i = 0; i < memsize; ++i) { 763 if (sc->mem_start[i]) { 764 printf("ed%d: failed to clear shared memory at %lx - check configuration\n", 765 isa_dev->id_unit, kvtop(sc->mem_start + i)); 766 767 /* 768 * Disable 16 bit access to shared memory 769 */ 770 if (isa16bit) { 771 if (sc->is790) { 772 outb(sc->asic_addr + ED_WD_MSR, 0x00); 773 } 774 outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto & 775 ~ED_WD_LAAR_M16EN); 776 } 777 return (0); 778 } 779 } 780 781 /* 782 * Disable 16bit access to shared memory - we leave it 783 * disabled so that 1) machines reboot properly when the board 784 * is set 16 bit mode and there are conflicting 8bit 785 * devices/ROMS in the same 128k address space as this boards 786 * shared memory. and 2) so that other 8 bit devices with 787 * shared memory can be used in this 128k region, too. 788 */ 789 if (isa16bit) { 790 if (sc->is790) { 791 outb(sc->asic_addr + ED_WD_MSR, 0x00); 792 } 793 outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto & 794 ~ED_WD_LAAR_M16EN); 795 } 796 return (ED_WD_IO_PORTS); 797} 798 799/* 800 * Probe and vendor-specific initialization routine for 3Com 3c503 boards 801 */ 802static int 803ed_probe_3Com(isa_dev) 804 struct isa_device *isa_dev; 805{ 806 struct ed_softc *sc = &ed_softc[isa_dev->id_unit]; 807 int i; 808 u_int memsize; 809 u_char isa16bit; 810 811 sc->asic_addr = isa_dev->id_iobase + ED_3COM_ASIC_OFFSET; 812 sc->nic_addr = isa_dev->id_iobase + ED_3COM_NIC_OFFSET; 813 814 /* 815 * Verify that the kernel configured I/O address matches the board 816 * configured address 817 */ 818 switch (inb(sc->asic_addr + ED_3COM_BCFR)) { 819 case ED_3COM_BCFR_300: 820 if (isa_dev->id_iobase != 0x300) 821 return (0); 822 break; 823 case ED_3COM_BCFR_310: 824 if (isa_dev->id_iobase != 0x310) 825 return (0); 826 break; 827 case ED_3COM_BCFR_330: 828 if (isa_dev->id_iobase != 0x330) 829 return (0); 830 break; 831 case ED_3COM_BCFR_350: 832 if (isa_dev->id_iobase != 0x350) 833 return (0); 834 break; 835 case ED_3COM_BCFR_250: 836 if (isa_dev->id_iobase != 0x250) 837 return (0); 838 break; 839 case ED_3COM_BCFR_280: 840 if (isa_dev->id_iobase != 0x280) 841 return (0); 842 break; 843 case ED_3COM_BCFR_2A0: 844 if (isa_dev->id_iobase != 0x2a0) 845 return (0); 846 break; 847 case ED_3COM_BCFR_2E0: 848 if (isa_dev->id_iobase != 0x2e0) 849 return (0); 850 break; 851 default: 852 return (0); 853 } 854 855 /* 856 * Verify that the kernel shared memory address matches the board 857 * configured address. 858 */ 859 switch (inb(sc->asic_addr + ED_3COM_PCFR)) { 860 case ED_3COM_PCFR_DC000: 861 if (kvtop(isa_dev->id_maddr) != 0xdc000) 862 return (0); 863 break; 864 case ED_3COM_PCFR_D8000: 865 if (kvtop(isa_dev->id_maddr) != 0xd8000) 866 return (0); 867 break; 868 case ED_3COM_PCFR_CC000: 869 if (kvtop(isa_dev->id_maddr) != 0xcc000) 870 return (0); 871 break; 872 case ED_3COM_PCFR_C8000: 873 if (kvtop(isa_dev->id_maddr) != 0xc8000) 874 return (0); 875 break; 876 default: 877 return (0); 878 } 879 880 881 /* 882 * Reset NIC and ASIC. Enable on-board transceiver throughout reset 883 * sequence because it'll lock up if the cable isn't connected if we 884 * don't. 885 */ 886 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_RST | ED_3COM_CR_XSEL); 887 888 /* 889 * Wait for a while, then un-reset it 890 */ 891 DELAY(50); 892 893 /* 894 * The 3Com ASIC defaults to rather strange settings for the CR after 895 * a reset - it's important to set it again after the following outb 896 * (this is done when we map the PROM below). 897 */ 898 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL); 899 900 /* 901 * Wait a bit for the NIC to recover from the reset 902 */ 903 DELAY(5000); 904 905 sc->vendor = ED_VENDOR_3COM; 906 sc->type_str = "3c503"; 907 sc->mem_shared = 1; 908 sc->cr_proto = ED_CR_RD2; 909 910 /* 911 * Hmmm...a 16bit 3Com board has 16k of memory, but only an 8k window 912 * to it. 913 */ 914 memsize = 8192; 915 916 /* 917 * Get station address from on-board ROM 918 */ 919 920 /* 921 * First, map ethernet address PROM over the top of where the NIC 922 * registers normally appear. 923 */ 924 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_EALO | ED_3COM_CR_XSEL); 925 926 for (i = 0; i < ETHER_ADDR_LEN; ++i) 927 sc->arpcom.ac_enaddr[i] = inb(sc->nic_addr + i); 928 929 /* 930 * Unmap PROM - select NIC registers. The proper setting of the 931 * tranceiver is set in ed_init so that the attach code is given a 932 * chance to set the default based on a compile-time config option 933 */ 934 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL); 935 936 /* 937 * Determine if this is an 8bit or 16bit board 938 */ 939 940 /* 941 * select page 0 registers 942 */ 943 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STP); 944 945 /* 946 * Attempt to clear WTS bit. If it doesn't clear, then this is a 16bit 947 * board. 948 */ 949 outb(sc->nic_addr + ED_P0_DCR, 0); 950 951 /* 952 * select page 2 registers 953 */ 954 outb(sc->nic_addr + ED_P0_CR, ED_CR_PAGE_2 | ED_CR_RD2 | ED_CR_STP); 955 956 /* 957 * The 3c503 forces the WTS bit to a one if this is a 16bit board 958 */ 959 if (inb(sc->nic_addr + ED_P2_DCR) & ED_DCR_WTS) 960 isa16bit = 1; 961 else 962 isa16bit = 0; 963 964 /* 965 * select page 0 registers 966 */ 967 outb(sc->nic_addr + ED_P2_CR, ED_CR_RD2 | ED_CR_STP); 968 969 sc->mem_start = (caddr_t) isa_dev->id_maddr; 970 sc->mem_size = memsize; 971 sc->mem_end = sc->mem_start + memsize; 972 973 /* 974 * We have an entire 8k window to put the transmit buffers on the 975 * 16bit boards. But since the 16bit 3c503's shared memory is only 976 * fast enough to overlap the loading of one full-size packet, trying 977 * to load more than 2 buffers can actually leave the transmitter idle 978 * during the load. So 2 seems the best value. (Although a mix of 979 * variable-sized packets might change this assumption. Nonetheless, 980 * we optimize for linear transfers of same-size packets.) 981 */ 982 if (isa16bit) { 983 if (isa_dev->id_flags & ED_FLAGS_NO_MULTI_BUFFERING) 984 sc->txb_cnt = 1; 985 else 986 sc->txb_cnt = 2; 987 988 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_16BIT; 989 sc->rec_page_start = ED_3COM_RX_PAGE_OFFSET_16BIT; 990 sc->rec_page_stop = memsize / ED_PAGE_SIZE + 991 ED_3COM_RX_PAGE_OFFSET_16BIT; 992 sc->mem_ring = sc->mem_start; 993 } else { 994 sc->txb_cnt = 1; 995 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_8BIT; 996 sc->rec_page_start = ED_TXBUF_SIZE + ED_3COM_TX_PAGE_OFFSET_8BIT; 997 sc->rec_page_stop = memsize / ED_PAGE_SIZE + 998 ED_3COM_TX_PAGE_OFFSET_8BIT; 999 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * ED_TXBUF_SIZE); 1000 } 1001 1002 sc->isa16bit = isa16bit; 1003 1004 /* 1005 * Initialize GA page start/stop registers. Probably only needed if 1006 * doing DMA, but what the hell. 1007 */ 1008 outb(sc->asic_addr + ED_3COM_PSTR, sc->rec_page_start); 1009 outb(sc->asic_addr + ED_3COM_PSPR, sc->rec_page_stop); 1010 1011 /* 1012 * Set IRQ. 3c503 only allows a choice of irq 2-5. 1013 */ 1014 switch (isa_dev->id_irq) { 1015 case IRQ2: 1016 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ2); 1017 break; 1018 case IRQ3: 1019 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ3); 1020 break; 1021 case IRQ4: 1022 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ4); 1023 break; 1024 case IRQ5: 1025 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ5); 1026 break; 1027 default: 1028 printf("ed%d: Invalid irq configuration (%d) must be 3-5,9 for 3c503\n", 1029 isa_dev->id_unit, ffs(isa_dev->id_irq) - 1); 1030 return (0); 1031 } 1032 1033 /* 1034 * Initialize GA configuration register. Set bank and enable shared 1035 * mem. 1036 */ 1037 outb(sc->asic_addr + ED_3COM_GACFR, ED_3COM_GACFR_RSEL | 1038 ED_3COM_GACFR_MBS0); 1039 1040 /* 1041 * Initialize "Vector Pointer" registers. These gawd-awful things are 1042 * compared to 20 bits of the address on ISA, and if they match, the 1043 * shared memory is disabled. We set them to 0xffff0...allegedly the 1044 * reset vector. 1045 */ 1046 outb(sc->asic_addr + ED_3COM_VPTR2, 0xff); 1047 outb(sc->asic_addr + ED_3COM_VPTR1, 0xff); 1048 outb(sc->asic_addr + ED_3COM_VPTR0, 0x00); 1049 1050 /* 1051 * Zero memory and verify that it is clear 1052 */ 1053 bzero(sc->mem_start, memsize); 1054 1055 for (i = 0; i < memsize; ++i) 1056 if (sc->mem_start[i]) { 1057 printf("ed%d: failed to clear shared memory at %lx - check configuration\n", 1058 isa_dev->id_unit, kvtop(sc->mem_start + i)); 1059 return (0); 1060 } 1061 isa_dev->id_msize = memsize; 1062 return (ED_3COM_IO_PORTS); 1063} 1064 1065/* 1066 * Probe and vendor-specific initialization routine for NE1000/2000 boards 1067 */ 1068static int 1069ed_probe_Novell_generic(sc, port, unit, flags) 1070 struct ed_softc *sc; 1071 int port; 1072 int unit; 1073 int flags; 1074{ 1075 u_int memsize, n; 1076 u_char romdata[16], tmp; 1077 static char test_pattern[32] = "THIS is A memory TEST pattern"; 1078 char test_buffer[32]; 1079 1080 sc->asic_addr = port + ED_NOVELL_ASIC_OFFSET; 1081 sc->nic_addr = port + ED_NOVELL_NIC_OFFSET; 1082 1083 /* XXX - do Novell-specific probe here */ 1084 1085 /* Reset the board */ 1086#ifdef GWETHER 1087 outb(sc->asic_addr + ED_NOVELL_RESET, 0); 1088 DELAY(200); 1089#endif /* GWETHER */ 1090 tmp = inb(sc->asic_addr + ED_NOVELL_RESET); 1091 1092 /* 1093 * I don't know if this is necessary; probably cruft leftover from 1094 * Clarkson packet driver code. Doesn't do a thing on the boards I've 1095 * tested. -DG [note that a outb(0x84, 0) seems to work here, and is 1096 * non-invasive...but some boards don't seem to reset and I don't have 1097 * complete documentation on what the 'right' thing to do is...so we 1098 * do the invasive thing for now. Yuck.] 1099 */ 1100 outb(sc->asic_addr + ED_NOVELL_RESET, tmp); 1101 DELAY(5000); 1102 1103 /* 1104 * This is needed because some NE clones apparently don't reset the 1105 * NIC properly (or the NIC chip doesn't reset fully on power-up) XXX 1106 * - this makes the probe invasive! ...Done against my better 1107 * judgement. -DLG 1108 */ 1109 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STP); 1110 1111 DELAY(5000); 1112 1113 /* Make sure that we really have an 8390 based board */ 1114 if (!ed_probe_generic8390(sc)) 1115 return (0); 1116 1117 sc->vendor = ED_VENDOR_NOVELL; 1118 sc->mem_shared = 0; 1119 sc->cr_proto = ED_CR_RD2; 1120 1121 /* 1122 * Test the ability to read and write to the NIC memory. This has the 1123 * side affect of determining if this is an NE1000 or an NE2000. 1124 */ 1125 1126 /* 1127 * This prevents packets from being stored in the NIC memory when the 1128 * readmem routine turns on the start bit in the CR. 1129 */ 1130 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_MON); 1131 1132 /* Temporarily initialize DCR for byte operations */ 1133 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS); 1134 1135 outb(sc->nic_addr + ED_P0_PSTART, 8192 / ED_PAGE_SIZE); 1136 outb(sc->nic_addr + ED_P0_PSTOP, 16384 / ED_PAGE_SIZE); 1137 1138 sc->isa16bit = 0; 1139 1140 /* 1141 * Write a test pattern in byte mode. If this fails, then there 1142 * probably isn't any memory at 8k - which likely means that the board 1143 * is an NE2000. 1144 */ 1145 ed_pio_writemem(sc, test_pattern, 8192, sizeof(test_pattern)); 1146 ed_pio_readmem(sc, 8192, test_buffer, sizeof(test_pattern)); 1147 1148 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern))) { 1149 /* not an NE1000 - try NE2000 */ 1150 1151 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_WTS | ED_DCR_FT1 | ED_DCR_LS); 1152 outb(sc->nic_addr + ED_P0_PSTART, 16384 / ED_PAGE_SIZE); 1153 outb(sc->nic_addr + ED_P0_PSTOP, 32768 / ED_PAGE_SIZE); 1154 1155 sc->isa16bit = 1; 1156 1157 /* 1158 * Write a test pattern in word mode. If this also fails, then 1159 * we don't know what this board is. 1160 */ 1161 ed_pio_writemem(sc, test_pattern, 16384, sizeof(test_pattern)); 1162 ed_pio_readmem(sc, 16384, test_buffer, sizeof(test_pattern)); 1163 1164 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern))) 1165 return (0); /* not an NE2000 either */ 1166 1167 sc->type = ED_TYPE_NE2000; 1168 sc->type_str = "NE2000"; 1169 } else { 1170 sc->type = ED_TYPE_NE1000; 1171 sc->type_str = "NE1000"; 1172 } 1173 1174 /* 8k of memory plus an additional 8k if 16bit */ 1175 memsize = 8192 + sc->isa16bit * 8192; 1176 1177#if 0 /* probably not useful - NE boards only come two ways */ 1178 /* allow kernel config file overrides */ 1179 if (isa_dev->id_msize) 1180 memsize = isa_dev->id_msize; 1181#endif 1182 1183 sc->mem_size = memsize; 1184 1185 /* NIC memory doesn't start at zero on an NE board */ 1186 /* The start address is tied to the bus width */ 1187 sc->mem_start = (char *) 8192 + sc->isa16bit * 8192; 1188 sc->mem_end = sc->mem_start + memsize; 1189 sc->tx_page_start = memsize / ED_PAGE_SIZE; 1190 1191#ifdef GWETHER 1192 { 1193 int x, i, mstart = 0, msize = 0; 1194 char pbuf0[ED_PAGE_SIZE], pbuf[ED_PAGE_SIZE], tbuf[ED_PAGE_SIZE]; 1195 1196 for (i = 0; i < ED_PAGE_SIZE; i++) 1197 pbuf0[i] = 0; 1198 1199 /* Clear all the memory. */ 1200 for (x = 1; x < 256; x++) 1201 ed_pio_writemem(sc, pbuf0, x * 256, ED_PAGE_SIZE); 1202 1203 /* Search for the start of RAM. */ 1204 for (x = 1; x < 256; x++) { 1205 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE); 1206 if (bcmp(pbuf0, tbuf, ED_PAGE_SIZE) == 0) { 1207 for (i = 0; i < ED_PAGE_SIZE; i++) 1208 pbuf[i] = 255 - x; 1209 ed_pio_writemem(sc, pbuf, x * 256, ED_PAGE_SIZE); 1210 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE); 1211 if (bcmp(pbuf, tbuf, ED_PAGE_SIZE) == 0) { 1212 mstart = x * ED_PAGE_SIZE; 1213 msize = ED_PAGE_SIZE; 1214 break; 1215 } 1216 } 1217 } 1218 1219 if (mstart == 0) { 1220 printf("ed%d: Cannot find start of RAM.\n", unit); 1221 return 0; 1222 } 1223 /* Search for the start of RAM. */ 1224 for (x = (mstart / ED_PAGE_SIZE) + 1; x < 256; x++) { 1225 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE); 1226 if (bcmp(pbuf0, tbuf, ED_PAGE_SIZE) == 0) { 1227 for (i = 0; i < ED_PAGE_SIZE; i++) 1228 pbuf[i] = 255 - x; 1229 ed_pio_writemem(sc, pbuf, x * 256, ED_PAGE_SIZE); 1230 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE); 1231 if (bcmp(pbuf, tbuf, ED_PAGE_SIZE) == 0) 1232 msize += ED_PAGE_SIZE; 1233 else { 1234 break; 1235 } 1236 } else { 1237 break; 1238 } 1239 } 1240 1241 if (msize == 0) { 1242 printf("ed%d: Cannot find any RAM, start : %d, x = %d.\n", unit, mstart, x); 1243 return 0; 1244 } 1245 printf("ed%d: RAM start at %d, size : %d.\n", unit, mstart, msize); 1246 1247 sc->mem_size = msize; 1248 sc->mem_start = (char *) mstart; 1249 sc->mem_end = (char *) (msize + mstart); 1250 sc->tx_page_start = mstart / ED_PAGE_SIZE; 1251 } 1252#endif /* GWETHER */ 1253 1254 /* 1255 * Use one xmit buffer if < 16k, two buffers otherwise (if not told 1256 * otherwise). 1257 */ 1258 if ((memsize < 16384) || (flags & ED_FLAGS_NO_MULTI_BUFFERING)) 1259 sc->txb_cnt = 1; 1260 else 1261 sc->txb_cnt = 2; 1262 1263 sc->rec_page_start = sc->tx_page_start + sc->txb_cnt * ED_TXBUF_SIZE; 1264 sc->rec_page_stop = sc->tx_page_start + memsize / ED_PAGE_SIZE; 1265 1266 sc->mem_ring = sc->mem_start + sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE; 1267 1268 ed_pio_readmem(sc, 0, romdata, 16); 1269 for (n = 0; n < ETHER_ADDR_LEN; n++) 1270 sc->arpcom.ac_enaddr[n] = romdata[n * (sc->isa16bit + 1)]; 1271 1272#ifdef GWETHER 1273 if (sc->arpcom.ac_enaddr[2] == 0x86) { 1274 sc->type_str = "Gateway AT"; 1275 } 1276#endif /* GWETHER */ 1277 1278 /* clear any pending interrupts that might have occurred above */ 1279 outb(sc->nic_addr + ED_P0_ISR, 0xff); 1280 1281 return (ED_NOVELL_IO_PORTS); 1282} 1283 1284static int 1285ed_probe_Novell(isa_dev) 1286 struct isa_device *isa_dev; 1287{ 1288 struct ed_softc *sc = &ed_softc[isa_dev->id_unit]; 1289 1290 isa_dev->id_maddr = 0; 1291 return ed_probe_Novell_generic(sc, isa_dev->id_iobase, 1292 isa_dev->id_unit, isa_dev->id_flags); 1293} 1294 1295#if NCARD > 0 1296/* 1297 * Probe framework for pccards. Replicates the standard framework, 1298 * minus the pccard driver registration and ignores the ether address 1299 * supplied (from the CIS), relying on the probe to find it instead. 1300 */ 1301static int 1302ed_probe_pccard(isa_dev, ether) 1303 struct isa_device *isa_dev; 1304 u_char *ether; 1305{ 1306 int nports; 1307 1308 nports = ed_probe_WD80x3(isa_dev); 1309 if (nports) 1310 return (nports); 1311 1312 nports = ed_probe_Novell(isa_dev); 1313 if (nports) 1314 return (nports); 1315 1316 return (0); 1317} 1318 1319#endif /* NCARD > 0 */ 1320 1321#define ED_HPP_TEST_SIZE 16 1322 1323/* 1324 * Probe and vendor specific initialization for the HP PC Lan+ Cards. 1325 * (HP Part nos: 27247B and 27252A). 1326 * 1327 * The card has an asic wrapper around a DS8390 core. The asic handles 1328 * host accesses and offers both standard register IO and memory mapped 1329 * IO. Memory mapped I/O allows better performance at the expense of greater 1330 * chance of an incompatibility with existing ISA cards. 1331 * 1332 * The card has a few caveats: it isn't tolerant of byte wide accesses, only 1333 * short (16 bit) or word (32 bit) accesses are allowed. Some card revisions 1334 * don't allow 32 bit accesses; these are indicated by a bit in the software 1335 * ID register (see if_edreg.h). 1336 * 1337 * Other caveats are: we should read the MAC address only when the card 1338 * is inactive. 1339 * 1340 * For more information; please consult the CRYNWR packet driver. 1341 * 1342 * The AUI port is turned on using the "link2" option on the ifconfig 1343 * command line. 1344 */ 1345static int 1346ed_probe_HP_pclanp(isa_dev) 1347 struct isa_device *isa_dev; 1348{ 1349 struct ed_softc *sc = &ed_softc[isa_dev->id_unit]; 1350 int n; /* temp var */ 1351 int memsize; /* mem on board */ 1352 u_char checksum; /* checksum of board address */ 1353 u_char irq; /* board configured IRQ */ 1354 char test_pattern[ED_HPP_TEST_SIZE]; /* read/write areas for */ 1355 char test_buffer[ED_HPP_TEST_SIZE]; /* probing card */ 1356 1357 1358 /* Fill in basic information */ 1359 sc->asic_addr = isa_dev->id_iobase + ED_HPP_ASIC_OFFSET; 1360 sc->nic_addr = isa_dev->id_iobase + ED_HPP_NIC_OFFSET; 1361 sc->is790 = 0; 1362 sc->isa16bit = 0; /* the 8390 core needs to be in byte mode */ 1363 1364 /* 1365 * Look for the HP PCLAN+ signature: "0x50,0x48,0x00,0x53" 1366 */ 1367 1368 if ((inb(sc->asic_addr + ED_HPP_ID) != 0x50) || 1369 (inb(sc->asic_addr + ED_HPP_ID + 1) != 0x48) || 1370 ((inb(sc->asic_addr + ED_HPP_ID + 2) & 0xF0) != 0) || 1371 (inb(sc->asic_addr + ED_HPP_ID + 3) != 0x53)) 1372 return 0; 1373 1374 /* 1375 * Read the MAC address and verify checksum on the address. 1376 */ 1377 1378 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_MAC); 1379 for (n = 0, checksum = 0; n < ETHER_ADDR_LEN; n++) 1380 checksum += (sc->arpcom.ac_enaddr[n] = 1381 inb(sc->asic_addr + ED_HPP_MAC_ADDR + n)); 1382 1383 checksum += inb(sc->asic_addr + ED_HPP_MAC_ADDR + ETHER_ADDR_LEN); 1384 1385 if (checksum != 0xFF) 1386 return 0; 1387 1388 /* 1389 * Verify that the software model number is 0. 1390 */ 1391 1392 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_ID); 1393 if (((sc->hpp_id = inw(sc->asic_addr + ED_HPP_PAGE_4)) & 1394 ED_HPP_ID_SOFT_MODEL_MASK) != 0x0000) 1395 return 0; 1396 1397 /* 1398 * Read in and save the current options configured on card. 1399 */ 1400 1401 sc->hpp_options = inw(sc->asic_addr + ED_HPP_OPTION); 1402 1403 sc->hpp_options |= (ED_HPP_OPTION_NIC_RESET | 1404 ED_HPP_OPTION_CHIP_RESET | 1405 ED_HPP_OPTION_ENABLE_IRQ); 1406 1407 /* 1408 * Reset the chip. This requires writing to the option register 1409 * so take care to preserve the other bits. 1410 */ 1411 1412 outw(sc->asic_addr + ED_HPP_OPTION, 1413 (sc->hpp_options & ~(ED_HPP_OPTION_NIC_RESET | 1414 ED_HPP_OPTION_CHIP_RESET))); 1415 1416 DELAY(5000); /* wait for chip reset to complete */ 1417 1418 outw(sc->asic_addr + ED_HPP_OPTION, 1419 (sc->hpp_options | (ED_HPP_OPTION_NIC_RESET | 1420 ED_HPP_OPTION_CHIP_RESET | 1421 ED_HPP_OPTION_ENABLE_IRQ))); 1422 1423 DELAY(5000); 1424 1425 if (!(inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RST)) 1426 return 0; /* reset did not complete */ 1427 1428 /* 1429 * Read out configuration information. 1430 */ 1431 1432 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_HW); 1433 1434 irq = inb(sc->asic_addr + ED_HPP_HW_IRQ); 1435 1436 /* 1437 * Check for impossible IRQ. 1438 */ 1439 1440 if (irq >= (sizeof(ed_hpp_intr_mask) / sizeof(ed_hpp_intr_mask[0]))) 1441 return 0; 1442 1443 /* 1444 * If the kernel IRQ was specified with a '?' use the cards idea 1445 * of the IRQ. If the kernel IRQ was explicitly specified, it 1446 * should match that of the hardware. 1447 */ 1448 1449 if (isa_dev->id_irq <= 0) 1450 isa_dev->id_irq = ed_hpp_intr_mask[irq]; 1451 else if (isa_dev->id_irq != ed_hpp_intr_mask[irq]) 1452 return 0; 1453 1454 /* 1455 * Fill in softconfig info. 1456 */ 1457 1458 sc->vendor = ED_VENDOR_HP; 1459 sc->type = ED_TYPE_HP_PCLANPLUS; 1460 sc->type_str = "HP-PCLAN+"; 1461 1462 sc->mem_shared = 0; /* we DON'T have dual ported RAM */ 1463 sc->mem_start = 0; /* we use offsets inside the card RAM */ 1464 1465 sc->hpp_mem_start = NULL;/* no memory mapped I/O by default */ 1466 1467 /* 1468 * Check if memory mapping of the I/O registers possible. 1469 */ 1470 1471 if (sc->hpp_options & ED_HPP_OPTION_MEM_ENABLE) 1472 { 1473 u_long mem_addr; 1474 1475 /* 1476 * determine the memory address from the board. 1477 */ 1478 1479 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_HW); 1480 mem_addr = (inw(sc->asic_addr + ED_HPP_HW_MEM_MAP) << 8); 1481 1482 /* 1483 * Check that the kernel specified start of memory and 1484 * hardware's idea of it match. 1485 */ 1486 1487 if (mem_addr != kvtop(isa_dev->id_maddr)) 1488 return 0; 1489 1490 sc->hpp_mem_start = isa_dev->id_maddr; 1491 } 1492 1493 /* 1494 * The board has 32KB of memory. Is there a way to determine 1495 * this programmatically? 1496 */ 1497 1498 memsize = 32768; 1499 1500 /* 1501 * Fill in the rest of the soft config structure. 1502 */ 1503 1504 /* 1505 * The transmit page index. 1506 */ 1507 1508 sc->tx_page_start = ED_HPP_TX_PAGE_OFFSET; 1509 1510 if (isa_dev->id_flags & ED_FLAGS_NO_MULTI_BUFFERING) 1511 sc->txb_cnt = 1; 1512 else 1513 sc->txb_cnt = 2; 1514 1515 /* 1516 * Memory description 1517 */ 1518 1519 sc->mem_size = memsize; 1520 sc->mem_ring = sc->mem_start + 1521 (sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE); 1522 sc->mem_end = sc->mem_start + sc->mem_size; 1523 1524 /* 1525 * Receive area starts after the transmit area and 1526 * continues till the end of memory. 1527 */ 1528 1529 sc->rec_page_start = sc->tx_page_start + 1530 (sc->txb_cnt * ED_TXBUF_SIZE); 1531 sc->rec_page_stop = (sc->mem_size / ED_PAGE_SIZE); 1532 1533 1534 sc->cr_proto = 0; /* value works */ 1535 1536 /* 1537 * Set the wrap registers for string I/O reads. 1538 */ 1539 1540 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_HW); 1541 outw(sc->asic_addr + ED_HPP_HW_WRAP, 1542 ((sc->rec_page_start / ED_PAGE_SIZE) | 1543 (((sc->rec_page_stop / ED_PAGE_SIZE) - 1) << 8))); 1544 1545 /* 1546 * Reset the register page to normal operation. 1547 */ 1548 1549 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_PERF); 1550 1551 /* 1552 * Verify that we can read/write from adapter memory. 1553 * Create test pattern. 1554 */ 1555 1556 for (n = 0; n < ED_HPP_TEST_SIZE; n++) 1557 { 1558 test_pattern[n] = (n*n) ^ ~n; 1559 } 1560 1561#undef ED_HPP_TEST_SIZE 1562 1563 /* 1564 * Check that the memory is accessible thru the I/O ports. 1565 * Write out the contents of "test_pattern", read back 1566 * into "test_buffer" and compare the two for any 1567 * mismatch. 1568 */ 1569 1570 for (n = 0; n < (32768 / ED_PAGE_SIZE); n ++) { 1571 1572 ed_pio_writemem(sc, test_pattern, (n * ED_PAGE_SIZE), 1573 sizeof(test_pattern)); 1574 ed_pio_readmem(sc, (n * ED_PAGE_SIZE), 1575 test_buffer, sizeof(test_pattern)); 1576 1577 if (bcmp(test_pattern, test_buffer, 1578 sizeof(test_pattern))) 1579 return 0; 1580 } 1581 1582 return (ED_HPP_IO_PORTS); 1583 1584} 1585 1586/* 1587 * HP PC Lan+ : Set the physical link to use AUI or TP/TL. 1588 */ 1589 1590void 1591ed_hpp_set_physical_link(struct ed_softc *sc) 1592{ 1593 struct ifnet *ifp = &sc->arpcom.ac_if; 1594 int lan_page; 1595 1596 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_LAN); 1597 lan_page = inw(sc->asic_addr + ED_HPP_PAGE_0); 1598 1599 if (ifp->if_flags & IFF_ALTPHYS) { 1600 1601 /* 1602 * Use the AUI port. 1603 */ 1604 1605 lan_page |= ED_HPP_LAN_AUI; 1606 1607 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_LAN); 1608 outw(sc->asic_addr + ED_HPP_PAGE_0, lan_page); 1609 1610 1611 } else { 1612 1613 /* 1614 * Use the ThinLan interface 1615 */ 1616 1617 lan_page &= ~ED_HPP_LAN_AUI; 1618 1619 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_LAN); 1620 outw(sc->asic_addr + ED_HPP_PAGE_0, lan_page); 1621 1622 } 1623 1624 /* 1625 * Wait for the lan card to re-initialize itself 1626 */ 1627 1628 DELAY(150000); /* wait 150 ms */ 1629 1630 /* 1631 * Restore normal pages. 1632 */ 1633 1634 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_PERF); 1635 1636} 1637 1638 1639/* 1640 * Install interface into kernel networking data structures 1641 */ 1642static int 1643ed_attach(sc, unit, flags) 1644 struct ed_softc *sc; 1645 int unit; 1646 int flags; 1647{ 1648 struct ifnet *ifp = &sc->arpcom.ac_if; 1649 1650 /* 1651 * Set interface to stopped condition (reset) 1652 */ 1653 ed_stop(sc); 1654 1655 if (!ifp->if_name) { 1656 /* 1657 * Initialize ifnet structure 1658 */ 1659 ifp->if_softc = sc; 1660 ifp->if_unit = unit; 1661 ifp->if_name = "ed"; 1662 ifp->if_output = ether_output; 1663 ifp->if_start = ed_start; 1664 ifp->if_ioctl = ed_ioctl; 1665 ifp->if_watchdog = ed_watchdog; 1666 ifp->if_init = ed_init; 1667 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 1668 ifp->if_linkmib = &sc->mibdata; 1669 ifp->if_linkmiblen = sizeof sc->mibdata; 1670 /* 1671 * XXX - should do a better job. 1672 */ 1673 if (sc->is790) 1674 sc->mibdata.dot3StatsEtherChipSet = 1675 DOT3CHIPSET(dot3VendorWesternDigital, 1676 dot3ChipSetWesternDigital83C790); 1677 else 1678 sc->mibdata.dot3StatsEtherChipSet = 1679 DOT3CHIPSET(dot3VendorNational, 1680 dot3ChipSetNational8390); 1681 sc->mibdata.dot3Compliance = DOT3COMPLIANCE_COLLS; 1682 1683 /* 1684 * Set default state for ALTPHYS flag (used to disable the 1685 * tranceiver for AUI operation), based on compile-time 1686 * config option. 1687 */ 1688 if (flags & ED_FLAGS_DISABLE_TRANCEIVER) 1689 ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX | 1690 IFF_MULTICAST | IFF_ALTPHYS); 1691 else 1692 ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX | 1693 IFF_MULTICAST); 1694 1695 /* 1696 * Attach the interface 1697 */ 1698 if_attach(ifp); 1699 ether_ifattach(ifp); 1700 } 1701 /* device attach does transition from UNCONFIGURED to IDLE state */ 1702 1703 /* 1704 * Print additional info when attached 1705 */ 1706 printf("%s%d: address %6D, ", ifp->if_name, ifp->if_unit, 1707 sc->arpcom.ac_enaddr, ":"); 1708 1709 if (sc->type_str && (*sc->type_str != 0)) 1710 printf("type %s ", sc->type_str); 1711 else 1712 printf("type unknown (0x%x) ", sc->type); 1713 1714 if (sc->vendor == ED_VENDOR_HP) 1715 printf("(%s %s IO)", (sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS) ? 1716 "16-bit" : "32-bit", 1717 sc->hpp_mem_start ? "memory mapped" : "regular"); 1718 else 1719 printf("%s ", sc->isa16bit ? "(16 bit)" : "(8 bit)"); 1720 1721 printf("%s\n", (((sc->vendor == ED_VENDOR_3COM) || 1722 (sc->vendor == ED_VENDOR_HP)) && 1723 (ifp->if_flags & IFF_ALTPHYS)) ? " tranceiver disabled" : ""); 1724 1725 /* 1726 * If BPF is in the kernel, call the attach for it 1727 */ 1728#if NBPFILTER > 0 1729 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header)); 1730#endif 1731 return 1; 1732} 1733 1734static int 1735ed_attach_isa(isa_dev) 1736 struct isa_device *isa_dev; 1737{ 1738 int unit = isa_dev->id_unit; 1739 struct ed_softc *sc = &ed_softc[unit]; 1740 int flags = isa_dev->id_flags; 1741 1742 return ed_attach(sc, unit, flags); 1743} 1744 1745#if NPCI > 0 1746void * 1747ed_attach_NE2000_pci(unit, port) 1748 int unit; 1749 int port; 1750{ 1751 struct ed_softc *sc = malloc(sizeof *sc, M_DEVBUF, M_NOWAIT); 1752 int isa_flags = 0; 1753 1754 if (!sc) 1755 return sc; 1756 1757 bzero(sc, sizeof *sc); 1758 if (ed_probe_Novell_generic(sc, port, unit, isa_flags) == 0 1759 || ed_attach(sc, unit, isa_flags) == 0) { 1760 free(sc, M_DEVBUF); 1761 return NULL; 1762 } 1763 return sc; 1764} 1765#endif 1766 1767/* 1768 * Reset interface. 1769 */ 1770static void 1771ed_reset(ifp) 1772 struct ifnet *ifp; 1773{ 1774 struct ed_softc *sc = ifp->if_softc; 1775 int s; 1776 1777 if (sc->gone) 1778 return; 1779 s = splimp(); 1780 1781 /* 1782 * Stop interface and re-initialize. 1783 */ 1784 ed_stop(sc); 1785 ed_init(sc); 1786 1787 (void) splx(s); 1788} 1789 1790/* 1791 * Take interface offline. 1792 */ 1793static void 1794ed_stop(sc) 1795 struct ed_softc *sc; 1796{ 1797 int n = 5000; 1798 1799 if (sc->gone) 1800 return; 1801 /* 1802 * Stop everything on the interface, and select page 0 registers. 1803 */ 1804 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP); 1805 1806 /* 1807 * Wait for interface to enter stopped state, but limit # of checks to 1808 * 'n' (about 5ms). It shouldn't even take 5us on modern DS8390's, but 1809 * just in case it's an old one. 1810 */ 1811 while (((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RST) == 0) && --n); 1812} 1813 1814/* 1815 * Device timeout/watchdog routine. Entered if the device neglects to 1816 * generate an interrupt after a transmit has been started on it. 1817 */ 1818static void 1819ed_watchdog(ifp) 1820 struct ifnet *ifp; 1821{ 1822 struct ed_softc *sc = ifp->if_softc; 1823 1824 if (sc->gone) 1825 return; 1826 log(LOG_ERR, "ed%d: device timeout\n", ifp->if_unit); 1827 ifp->if_oerrors++; 1828 1829 ed_reset(ifp); 1830} 1831 1832/* 1833 * Initialize device. 1834 */ 1835static void 1836ed_init(xsc) 1837 void *xsc; 1838{ 1839 struct ed_softc *sc = xsc; 1840 struct ifnet *ifp = &sc->arpcom.ac_if; 1841 int i, s; 1842 1843 if (sc->gone) 1844 return; 1845 1846 /* address not known */ 1847 if (TAILQ_EMPTY(&ifp->if_addrhead)) /* unlikely? XXX */ 1848 return; 1849 1850 /* 1851 * Initialize the NIC in the exact order outlined in the NS manual. 1852 * This init procedure is "mandatory"...don't change what or when 1853 * things happen. 1854 */ 1855 s = splimp(); 1856 1857 /* reset transmitter flags */ 1858 sc->xmit_busy = 0; 1859 ifp->if_timer = 0; 1860 1861 sc->txb_inuse = 0; 1862 sc->txb_new = 0; 1863 sc->txb_next_tx = 0; 1864 1865 /* This variable is used below - don't move this assignment */ 1866 sc->next_packet = sc->rec_page_start + 1; 1867 1868 /* 1869 * Set interface for page 0, Remote DMA complete, Stopped 1870 */ 1871 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP); 1872 1873 if (sc->isa16bit) { 1874 1875 /* 1876 * Set FIFO threshold to 8, No auto-init Remote DMA, byte 1877 * order=80x86, word-wide DMA xfers, 1878 */ 1879 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1 | ED_DCR_WTS | ED_DCR_LS); 1880 } else { 1881 1882 /* 1883 * Same as above, but byte-wide DMA xfers 1884 */ 1885 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS); 1886 } 1887 1888 /* 1889 * Clear Remote Byte Count Registers 1890 */ 1891 outb(sc->nic_addr + ED_P0_RBCR0, 0); 1892 outb(sc->nic_addr + ED_P0_RBCR1, 0); 1893 1894 /* 1895 * For the moment, don't store incoming packets in memory. 1896 */ 1897 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_MON); 1898 1899 /* 1900 * Place NIC in internal loopback mode 1901 */ 1902 outb(sc->nic_addr + ED_P0_TCR, ED_TCR_LB0); 1903 1904 /* 1905 * Initialize transmit/receive (ring-buffer) Page Start 1906 */ 1907 outb(sc->nic_addr + ED_P0_TPSR, sc->tx_page_start); 1908 outb(sc->nic_addr + ED_P0_PSTART, sc->rec_page_start); 1909 /* Set lower bits of byte addressable framing to 0 */ 1910 if (sc->is790) 1911 outb(sc->nic_addr + 0x09, 0); 1912 1913 /* 1914 * Initialize Receiver (ring-buffer) Page Stop and Boundry 1915 */ 1916 outb(sc->nic_addr + ED_P0_PSTOP, sc->rec_page_stop); 1917 outb(sc->nic_addr + ED_P0_BNRY, sc->rec_page_start); 1918 1919 /* 1920 * Clear all interrupts. A '1' in each bit position clears the 1921 * corresponding flag. 1922 */ 1923 outb(sc->nic_addr + ED_P0_ISR, 0xff); 1924 1925 /* 1926 * Enable the following interrupts: receive/transmit complete, 1927 * receive/transmit error, and Receiver OverWrite. 1928 * 1929 * Counter overflow and Remote DMA complete are *not* enabled. 1930 */ 1931 outb(sc->nic_addr + ED_P0_IMR, 1932 ED_IMR_PRXE | ED_IMR_PTXE | ED_IMR_RXEE | ED_IMR_TXEE | ED_IMR_OVWE); 1933 1934 /* 1935 * Program Command Register for page 1 1936 */ 1937 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP); 1938 1939 /* 1940 * Copy out our station address 1941 */ 1942 for (i = 0; i < ETHER_ADDR_LEN; ++i) 1943 outb(sc->nic_addr + ED_P1_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1944 1945 /* 1946 * Set Current Page pointer to next_packet (initialized above) 1947 */ 1948 outb(sc->nic_addr + ED_P1_CURR, sc->next_packet); 1949 1950 /* 1951 * Program Receiver Configuration Register and multicast filter. CR is 1952 * set to page 0 on return. 1953 */ 1954 ed_setrcr(sc); 1955 1956 /* 1957 * Take interface out of loopback 1958 */ 1959 outb(sc->nic_addr + ED_P0_TCR, 0); 1960 1961 /* 1962 * If this is a 3Com board, the tranceiver must be software enabled 1963 * (there is no settable hardware default). 1964 */ 1965 if (sc->vendor == ED_VENDOR_3COM) { 1966 if (ifp->if_flags & IFF_ALTPHYS) { 1967 outb(sc->asic_addr + ED_3COM_CR, 0); 1968 } else { 1969 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL); 1970 } 1971 } 1972 1973 /* 1974 * Set 'running' flag, and clear output active flag. 1975 */ 1976 ifp->if_flags |= IFF_RUNNING; 1977 ifp->if_flags &= ~IFF_OACTIVE; 1978 1979 /* 1980 * ...and attempt to start output 1981 */ 1982 ed_start(ifp); 1983 1984 (void) splx(s); 1985} 1986 1987/* 1988 * This routine actually starts the transmission on the interface 1989 */ 1990static __inline void 1991ed_xmit(sc) 1992 struct ed_softc *sc; 1993{ 1994 struct ifnet *ifp = (struct ifnet *)sc; 1995 unsigned short len; 1996 1997 if (sc->gone) 1998 return; 1999 len = sc->txb_len[sc->txb_next_tx]; 2000 2001 /* 2002 * Set NIC for page 0 register access 2003 */ 2004 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA); 2005 2006 /* 2007 * Set TX buffer start page 2008 */ 2009 outb(sc->nic_addr + ED_P0_TPSR, sc->tx_page_start + 2010 sc->txb_next_tx * ED_TXBUF_SIZE); 2011 2012 /* 2013 * Set TX length 2014 */ 2015 outb(sc->nic_addr + ED_P0_TBCR0, len); 2016 outb(sc->nic_addr + ED_P0_TBCR1, len >> 8); 2017 2018 /* 2019 * Set page 0, Remote DMA complete, Transmit Packet, and *Start* 2020 */ 2021 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_TXP | ED_CR_STA); 2022 sc->xmit_busy = 1; 2023 2024 /* 2025 * Point to next transmit buffer slot and wrap if necessary. 2026 */ 2027 sc->txb_next_tx++; 2028 if (sc->txb_next_tx == sc->txb_cnt) 2029 sc->txb_next_tx = 0; 2030 2031 /* 2032 * Set a timer just in case we never hear from the board again 2033 */ 2034 ifp->if_timer = 2; 2035} 2036 2037/* 2038 * Start output on interface. 2039 * We make two assumptions here: 2040 * 1) that the current priority is set to splimp _before_ this code 2041 * is called *and* is returned to the appropriate priority after 2042 * return 2043 * 2) that the IFF_OACTIVE flag is checked before this code is called 2044 * (i.e. that the output part of the interface is idle) 2045 */ 2046static void 2047ed_start(ifp) 2048 struct ifnet *ifp; 2049{ 2050 struct ed_softc *sc = ifp->if_softc; 2051 struct mbuf *m0, *m; 2052 caddr_t buffer; 2053 int len; 2054 2055 if (sc->gone) { 2056 printf("ed_start(%p) GONE\n",ifp); 2057 return; 2058 } 2059outloop: 2060 2061 /* 2062 * First, see if there are buffered packets and an idle transmitter - 2063 * should never happen at this point. 2064 */ 2065 if (sc->txb_inuse && (sc->xmit_busy == 0)) { 2066 printf("ed: packets buffered, but transmitter idle\n"); 2067 ed_xmit(sc); 2068 } 2069 2070 /* 2071 * See if there is room to put another packet in the buffer. 2072 */ 2073 if (sc->txb_inuse == sc->txb_cnt) { 2074 2075 /* 2076 * No room. Indicate this to the outside world and exit. 2077 */ 2078 ifp->if_flags |= IFF_OACTIVE; 2079 return; 2080 } 2081 IF_DEQUEUE(&ifp->if_snd, m); 2082 if (m == 0) { 2083 2084 /* 2085 * We are using the !OACTIVE flag to indicate to the outside 2086 * world that we can accept an additional packet rather than 2087 * that the transmitter is _actually_ active. Indeed, the 2088 * transmitter may be active, but if we haven't filled all the 2089 * buffers with data then we still want to accept more. 2090 */ 2091 ifp->if_flags &= ~IFF_OACTIVE; 2092 return; 2093 } 2094 2095 /* 2096 * Copy the mbuf chain into the transmit buffer 2097 */ 2098 2099 m0 = m; 2100 2101 /* txb_new points to next open buffer slot */ 2102 buffer = sc->mem_start + (sc->txb_new * ED_TXBUF_SIZE * ED_PAGE_SIZE); 2103 2104 if (sc->mem_shared) { 2105 2106 /* 2107 * Special case setup for 16 bit boards... 2108 */ 2109 if (sc->isa16bit) { 2110 switch (sc->vendor) { 2111 2112 /* 2113 * For 16bit 3Com boards (which have 16k of 2114 * memory), we have the xmit buffers in a 2115 * different page of memory ('page 0') - so 2116 * change pages. 2117 */ 2118 case ED_VENDOR_3COM: 2119 outb(sc->asic_addr + ED_3COM_GACFR, 2120 ED_3COM_GACFR_RSEL); 2121 break; 2122 2123 /* 2124 * Enable 16bit access to shared memory on 2125 * WD/SMC boards. 2126 */ 2127 case ED_VENDOR_WD_SMC:{ 2128 outb(sc->asic_addr + ED_WD_LAAR, 2129 sc->wd_laar_proto | ED_WD_LAAR_M16EN); 2130 if (sc->is790) { 2131 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_MENB); 2132 } 2133 break; 2134 } 2135 } 2136 } 2137 for (len = 0; m != 0; m = m->m_next) { 2138 bcopy(mtod(m, caddr_t), buffer, m->m_len); 2139 buffer += m->m_len; 2140 len += m->m_len; 2141 } 2142 2143 /* 2144 * Restore previous shared memory access 2145 */ 2146 if (sc->isa16bit) { 2147 switch (sc->vendor) { 2148 case ED_VENDOR_3COM: 2149 outb(sc->asic_addr + ED_3COM_GACFR, 2150 ED_3COM_GACFR_RSEL | ED_3COM_GACFR_MBS0); 2151 break; 2152 case ED_VENDOR_WD_SMC:{ 2153 if (sc->is790) { 2154 outb(sc->asic_addr + ED_WD_MSR, 0x00); 2155 } 2156 outb(sc->asic_addr + ED_WD_LAAR, 2157 sc->wd_laar_proto & ~ED_WD_LAAR_M16EN); 2158 break; 2159 } 2160 } 2161 } 2162 } else { 2163 len = ed_pio_write_mbufs(sc, m, (int)buffer); 2164 if (len == 0) 2165 goto outloop; 2166 } 2167 2168 sc->txb_len[sc->txb_new] = max(len, (ETHER_MIN_LEN-ETHER_CRC_LEN)); 2169 2170 sc->txb_inuse++; 2171 2172 /* 2173 * Point to next buffer slot and wrap if necessary. 2174 */ 2175 sc->txb_new++; 2176 if (sc->txb_new == sc->txb_cnt) 2177 sc->txb_new = 0; 2178 2179 if (sc->xmit_busy == 0) 2180 ed_xmit(sc); 2181 2182 /* 2183 * Tap off here if there is a bpf listener. 2184 */ 2185#if NBPFILTER > 0 2186 if (ifp->if_bpf) { 2187 bpf_mtap(ifp, m0); 2188 } 2189#endif 2190 2191 m_freem(m0); 2192 2193 /* 2194 * Loop back to the top to possibly buffer more packets 2195 */ 2196 goto outloop; 2197} 2198 2199/* 2200 * Ethernet interface receiver interrupt. 2201 */ 2202static __inline void 2203ed_rint(sc) 2204 struct ed_softc *sc; 2205{ 2206 struct ifnet *ifp = &sc->arpcom.ac_if; 2207 u_char boundry; 2208 u_short len; 2209 struct ed_ring packet_hdr; 2210 char *packet_ptr; 2211 2212 if (sc->gone) 2213 return; 2214 2215 /* 2216 * Set NIC to page 1 registers to get 'current' pointer 2217 */ 2218 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA); 2219 2220 /* 2221 * 'sc->next_packet' is the logical beginning of the ring-buffer - 2222 * i.e. it points to where new data has been buffered. The 'CURR' 2223 * (current) register points to the logical end of the ring-buffer - 2224 * i.e. it points to where additional new data will be added. We loop 2225 * here until the logical beginning equals the logical end (or in 2226 * other words, until the ring-buffer is empty). 2227 */ 2228 while (sc->next_packet != inb(sc->nic_addr + ED_P1_CURR)) { 2229 2230 /* get pointer to this buffer's header structure */ 2231 packet_ptr = sc->mem_ring + 2232 (sc->next_packet - sc->rec_page_start) * ED_PAGE_SIZE; 2233 2234 /* 2235 * The byte count includes a 4 byte header that was added by 2236 * the NIC. 2237 */ 2238 if (sc->mem_shared) 2239 packet_hdr = *(struct ed_ring *) packet_ptr; 2240 else 2241 ed_pio_readmem(sc, (int)packet_ptr, (char *) &packet_hdr, 2242 sizeof(packet_hdr)); 2243 len = packet_hdr.count; 2244 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring)) || 2245 len < (ETHER_MIN_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring))) { 2246 /* 2247 * Length is a wild value. There's a good chance that 2248 * this was caused by the NIC being old and buggy. 2249 * The bug is that the length low byte is duplicated in 2250 * the high byte. Try to recalculate the length based on 2251 * the pointer to the next packet. 2252 */ 2253 /* 2254 * NOTE: sc->next_packet is pointing at the current packet. 2255 */ 2256 len &= ED_PAGE_SIZE - 1; /* preserve offset into page */ 2257 if (packet_hdr.next_packet >= sc->next_packet) { 2258 len += (packet_hdr.next_packet - sc->next_packet) * ED_PAGE_SIZE; 2259 } else { 2260 len += ((packet_hdr.next_packet - sc->rec_page_start) + 2261 (sc->rec_page_stop - sc->next_packet)) * ED_PAGE_SIZE; 2262 } 2263 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN 2264 + sizeof(struct ed_ring))) 2265 sc->mibdata.dot3StatsFrameTooLongs++; 2266 } 2267 /* 2268 * Be fairly liberal about what we allow as a "reasonable" length 2269 * so that a [crufty] packet will make it to BPF (and can thus 2270 * be analyzed). Note that all that is really important is that 2271 * we have a length that will fit into one mbuf cluster or less; 2272 * the upper layer protocols can then figure out the length from 2273 * their own length field(s). 2274 */ 2275 if ((len > sizeof(struct ed_ring)) && 2276 (len <= MCLBYTES) && 2277 (packet_hdr.next_packet >= sc->rec_page_start) && 2278 (packet_hdr.next_packet < sc->rec_page_stop)) { 2279 /* 2280 * Go get packet. 2281 */ 2282 ed_get_packet(sc, packet_ptr + sizeof(struct ed_ring), 2283 len - sizeof(struct ed_ring), packet_hdr.rsr & ED_RSR_PHY); 2284 ifp->if_ipackets++; 2285 } else { 2286 /* 2287 * Really BAD. The ring pointers are corrupted. 2288 */ 2289 log(LOG_ERR, 2290 "ed%d: NIC memory corrupt - invalid packet length %d\n", 2291 ifp->if_unit, len); 2292 ifp->if_ierrors++; 2293 ed_reset(ifp); 2294 return; 2295 } 2296 2297 /* 2298 * Update next packet pointer 2299 */ 2300 sc->next_packet = packet_hdr.next_packet; 2301 2302 /* 2303 * Update NIC boundry pointer - being careful to keep it one 2304 * buffer behind. (as recommended by NS databook) 2305 */ 2306 boundry = sc->next_packet - 1; 2307 if (boundry < sc->rec_page_start) 2308 boundry = sc->rec_page_stop - 1; 2309 2310 /* 2311 * Set NIC to page 0 registers to update boundry register 2312 */ 2313 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA); 2314 2315 outb(sc->nic_addr + ED_P0_BNRY, boundry); 2316 2317 /* 2318 * Set NIC to page 1 registers before looping to top (prepare 2319 * to get 'CURR' current pointer) 2320 */ 2321 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA); 2322 } 2323} 2324 2325/* 2326 * Ethernet interface interrupt processor 2327 */ 2328void 2329edintr_sc(sc) 2330 struct ed_softc *sc; 2331{ 2332 struct ifnet *ifp = (struct ifnet *)sc; 2333 u_char isr; 2334 2335 if (sc->gone) 2336 return; 2337 /* 2338 * Set NIC to page 0 registers 2339 */ 2340 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA); 2341 2342 /* 2343 * loop until there are no more new interrupts 2344 */ 2345 while ((isr = inb(sc->nic_addr + ED_P0_ISR)) != 0) { 2346 2347 /* 2348 * reset all the bits that we are 'acknowledging' by writing a 2349 * '1' to each bit position that was set (writing a '1' 2350 * *clears* the bit) 2351 */ 2352 outb(sc->nic_addr + ED_P0_ISR, isr); 2353 2354 /* 2355 * Handle transmitter interrupts. Handle these first because 2356 * the receiver will reset the board under some conditions. 2357 */ 2358 if (isr & (ED_ISR_PTX | ED_ISR_TXE)) { 2359 u_char collisions = inb(sc->nic_addr + ED_P0_NCR) & 0x0f; 2360 2361 /* 2362 * Check for transmit error. If a TX completed with an 2363 * error, we end up throwing the packet away. Really 2364 * the only error that is possible is excessive 2365 * collisions, and in this case it is best to allow 2366 * the automatic mechanisms of TCP to backoff the 2367 * flow. Of course, with UDP we're screwed, but this 2368 * is expected when a network is heavily loaded. 2369 */ 2370 (void) inb(sc->nic_addr + ED_P0_TSR); 2371 if (isr & ED_ISR_TXE) { 2372 u_char tsr; 2373 2374 /* 2375 * Excessive collisions (16) 2376 */ 2377 tsr = inb(sc->nic_addr + ED_P0_TSR); 2378 if ((tsr & ED_TSR_ABT) 2379 && (collisions == 0)) { 2380 2381 /* 2382 * When collisions total 16, the 2383 * P0_NCR will indicate 0, and the 2384 * TSR_ABT is set. 2385 */ 2386 collisions = 16; 2387 sc->mibdata.dot3StatsExcessiveCollisions++; 2388 sc->mibdata.dot3StatsCollFrequencies[15]++; 2389 } 2390 if (tsr & ED_TSR_OWC) 2391 sc->mibdata.dot3StatsLateCollisions++; 2392 if (tsr & ED_TSR_CDH) 2393 sc->mibdata.dot3StatsSQETestErrors++; 2394 if (tsr & ED_TSR_CRS) 2395 sc->mibdata.dot3StatsCarrierSenseErrors++; 2396 if (tsr & ED_TSR_FU) 2397 sc->mibdata.dot3StatsInternalMacTransmitErrors++; 2398 2399 /* 2400 * update output errors counter 2401 */ 2402 ifp->if_oerrors++; 2403 } else { 2404 2405 /* 2406 * Update total number of successfully 2407 * transmitted packets. 2408 */ 2409 ifp->if_opackets++; 2410 } 2411 2412 /* 2413 * reset tx busy and output active flags 2414 */ 2415 sc->xmit_busy = 0; 2416 ifp->if_flags &= ~IFF_OACTIVE; 2417 2418 /* 2419 * clear watchdog timer 2420 */ 2421 ifp->if_timer = 0; 2422 2423 /* 2424 * Add in total number of collisions on last 2425 * transmission. 2426 */ 2427 ifp->if_collisions += collisions; 2428 switch(collisions) { 2429 case 0: 2430 case 16: 2431 break; 2432 case 1: 2433 sc->mibdata.dot3StatsSingleCollisionFrames++; 2434 sc->mibdata.dot3StatsCollFrequencies[0]++; 2435 break; 2436 default: 2437 sc->mibdata.dot3StatsMultipleCollisionFrames++; 2438 sc->mibdata. 2439 dot3StatsCollFrequencies[collisions-1] 2440 ++; 2441 break; 2442 } 2443 2444 /* 2445 * Decrement buffer in-use count if not zero (can only 2446 * be zero if a transmitter interrupt occured while 2447 * not actually transmitting). If data is ready to 2448 * transmit, start it transmitting, otherwise defer 2449 * until after handling receiver 2450 */ 2451 if (sc->txb_inuse && --sc->txb_inuse) 2452 ed_xmit(sc); 2453 } 2454 2455 /* 2456 * Handle receiver interrupts 2457 */ 2458 if (isr & (ED_ISR_PRX | ED_ISR_RXE | ED_ISR_OVW)) { 2459 2460 /* 2461 * Overwrite warning. In order to make sure that a 2462 * lockup of the local DMA hasn't occurred, we reset 2463 * and re-init the NIC. The NSC manual suggests only a 2464 * partial reset/re-init is necessary - but some chips 2465 * seem to want more. The DMA lockup has been seen 2466 * only with early rev chips - Methinks this bug was 2467 * fixed in later revs. -DG 2468 */ 2469 if (isr & ED_ISR_OVW) { 2470 ifp->if_ierrors++; 2471#ifdef DIAGNOSTIC 2472 log(LOG_WARNING, 2473 "ed%d: warning - receiver ring buffer overrun\n", 2474 ifp->if_unit); 2475#endif 2476 2477 /* 2478 * Stop/reset/re-init NIC 2479 */ 2480 ed_reset(ifp); 2481 } else { 2482 2483 /* 2484 * Receiver Error. One or more of: CRC error, 2485 * frame alignment error FIFO overrun, or 2486 * missed packet. 2487 */ 2488 if (isr & ED_ISR_RXE) { 2489 u_char rsr; 2490 rsr = inb(sc->nic_addr + ED_P0_RSR); 2491 if (rsr & ED_RSR_CRC) 2492 sc->mibdata.dot3StatsFCSErrors++; 2493 if (rsr & ED_RSR_FAE) 2494 sc->mibdata.dot3StatsAlignmentErrors++; 2495 if (rsr & ED_RSR_FO) 2496 sc->mibdata.dot3StatsInternalMacReceiveErrors++; 2497 ifp->if_ierrors++; 2498#ifdef ED_DEBUG 2499 printf("ed%d: receive error %x\n", ifp->if_unit, 2500 inb(sc->nic_addr + ED_P0_RSR)); 2501#endif 2502 } 2503 2504 /* 2505 * Go get the packet(s) XXX - Doing this on an 2506 * error is dubious because there shouldn't be 2507 * any data to get (we've configured the 2508 * interface to not accept packets with 2509 * errors). 2510 */ 2511 2512 /* 2513 * Enable 16bit access to shared memory first 2514 * on WD/SMC boards. 2515 */ 2516 if (sc->isa16bit && 2517 (sc->vendor == ED_VENDOR_WD_SMC)) { 2518 2519 outb(sc->asic_addr + ED_WD_LAAR, 2520 sc->wd_laar_proto | ED_WD_LAAR_M16EN); 2521 if (sc->is790) { 2522 outb(sc->asic_addr + ED_WD_MSR, 2523 ED_WD_MSR_MENB); 2524 } 2525 } 2526 ed_rint(sc); 2527 2528 /* disable 16bit access */ 2529 if (sc->isa16bit && 2530 (sc->vendor == ED_VENDOR_WD_SMC)) { 2531 2532 if (sc->is790) { 2533 outb(sc->asic_addr + ED_WD_MSR, 0x00); 2534 } 2535 outb(sc->asic_addr + ED_WD_LAAR, 2536 sc->wd_laar_proto & ~ED_WD_LAAR_M16EN); 2537 } 2538 } 2539 } 2540 2541 /* 2542 * If it looks like the transmitter can take more data, 2543 * attempt to start output on the interface. This is done 2544 * after handling the receiver to give the receiver priority. 2545 */ 2546 if ((ifp->if_flags & IFF_OACTIVE) == 0) 2547 ed_start(ifp); 2548 2549 /* 2550 * return NIC CR to standard state: page 0, remote DMA 2551 * complete, start (toggling the TXP bit off, even if was just 2552 * set in the transmit routine, is *okay* - it is 'edge' 2553 * triggered from low to high) 2554 */ 2555 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA); 2556 2557 /* 2558 * If the Network Talley Counters overflow, read them to reset 2559 * them. It appears that old 8390's won't clear the ISR flag 2560 * otherwise - resulting in an infinite loop. 2561 */ 2562 if (isr & ED_ISR_CNT) { 2563 (void) inb(sc->nic_addr + ED_P0_CNTR0); 2564 (void) inb(sc->nic_addr + ED_P0_CNTR1); 2565 (void) inb(sc->nic_addr + ED_P0_CNTR2); 2566 } 2567 } 2568} 2569 2570void 2571edintr(unit) 2572 int unit; 2573{ 2574 edintr_sc (&ed_softc[unit]); 2575} 2576 2577/* 2578 * Process an ioctl request. This code needs some work - it looks 2579 * pretty ugly. 2580 */ 2581static int 2582ed_ioctl(ifp, command, data) 2583 register struct ifnet *ifp; 2584 u_long command; 2585 caddr_t data; 2586{ 2587 struct ed_softc *sc = ifp->if_softc; 2588 int s, error = 0; 2589 2590 if (sc->gone) { 2591 ifp->if_flags &= ~IFF_RUNNING; 2592 return ENXIO; 2593 } 2594 s = splimp(); 2595 2596 switch (command) { 2597 2598 case SIOCSIFADDR: 2599 case SIOCGIFADDR: 2600 case SIOCSIFMTU: 2601 error = ether_ioctl(ifp, command, data); 2602 break; 2603 2604 case SIOCSIFFLAGS: 2605 2606 /* 2607 * If the interface is marked up and stopped, then start it. 2608 * If it is marked down and running, then stop it. 2609 */ 2610 if (ifp->if_flags & IFF_UP) { 2611 if ((ifp->if_flags & IFF_RUNNING) == 0) 2612 ed_init(sc); 2613 } else { 2614 if (ifp->if_flags & IFF_RUNNING) { 2615 ed_stop(sc); 2616 ifp->if_flags &= ~IFF_RUNNING; 2617 } 2618 } 2619 2620#if NBPFILTER > 0 2621 2622 /* 2623 * Promiscuous flag may have changed, so reprogram the RCR. 2624 */ 2625 ed_setrcr(sc); 2626#endif 2627 2628 /* 2629 * An unfortunate hack to provide the (required) software 2630 * control of the tranceiver for 3Com boards. The ALTPHYS flag 2631 * disables the tranceiver if set. 2632 */ 2633 if (sc->vendor == ED_VENDOR_3COM) { 2634 if (ifp->if_flags & IFF_ALTPHYS) { 2635 outb(sc->asic_addr + ED_3COM_CR, 0); 2636 } else { 2637 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL); 2638 } 2639 } else if (sc->vendor == ED_VENDOR_HP) 2640 ed_hpp_set_physical_link(sc); 2641 break; 2642 2643 case SIOCADDMULTI: 2644 case SIOCDELMULTI: 2645 /* 2646 * Multicast list has changed; set the hardware filter 2647 * accordingly. 2648 */ 2649 ed_setrcr(sc); 2650 error = 0; 2651 break; 2652 2653 default: 2654 error = EINVAL; 2655 } 2656 (void) splx(s); 2657 return (error); 2658} 2659 2660/* 2661 * Given a source and destination address, copy 'amount' of a packet from 2662 * the ring buffer into a linear destination buffer. Takes into account 2663 * ring-wrap. 2664 */ 2665static __inline char * 2666ed_ring_copy(sc, src, dst, amount) 2667 struct ed_softc *sc; 2668 char *src; 2669 char *dst; 2670 u_short amount; 2671{ 2672 u_short tmp_amount; 2673 2674 /* does copy wrap to lower addr in ring buffer? */ 2675 if (src + amount > sc->mem_end) { 2676 tmp_amount = sc->mem_end - src; 2677 2678 /* copy amount up to end of NIC memory */ 2679 if (sc->mem_shared) 2680 bcopy(src, dst, tmp_amount); 2681 else 2682 ed_pio_readmem(sc, (int)src, dst, tmp_amount); 2683 2684 amount -= tmp_amount; 2685 src = sc->mem_ring; 2686 dst += tmp_amount; 2687 } 2688 if (sc->mem_shared) 2689 bcopy(src, dst, amount); 2690 else 2691 ed_pio_readmem(sc, (int)src, dst, amount); 2692 2693 return (src + amount); 2694} 2695 2696/* 2697 * Retreive packet from shared memory and send to the next level up via 2698 * ether_input(). If there is a BPF listener, give a copy to BPF, too. 2699 */ 2700static void 2701ed_get_packet(sc, buf, len, multicast) 2702 struct ed_softc *sc; 2703 char *buf; 2704 u_short len; 2705 int multicast; 2706{ 2707 struct ether_header *eh; 2708 struct mbuf *m; 2709 2710 /* Allocate a header mbuf */ 2711 MGETHDR(m, M_DONTWAIT, MT_DATA); 2712 if (m == NULL) 2713 return; 2714 m->m_pkthdr.rcvif = &sc->arpcom.ac_if; 2715 m->m_pkthdr.len = m->m_len = len; 2716 2717 /* 2718 * We always put the received packet in a single buffer - 2719 * either with just an mbuf header or in a cluster attached 2720 * to the header. The +2 is to compensate for the alignment 2721 * fixup below. 2722 */ 2723 if ((len + 2) > MHLEN) { 2724 /* Attach an mbuf cluster */ 2725 MCLGET(m, M_DONTWAIT); 2726 2727 /* Insist on getting a cluster */ 2728 if ((m->m_flags & M_EXT) == 0) { 2729 m_freem(m); 2730 return; 2731 } 2732 } 2733 2734 /* 2735 * The +2 is to longword align the start of the real packet. 2736 * This is important for NFS. 2737 */ 2738 m->m_data += 2; 2739 eh = mtod(m, struct ether_header *); 2740 2741 /* 2742 * Get packet, including link layer address, from interface. 2743 */ 2744 ed_ring_copy(sc, buf, (char *)eh, len); 2745 2746#if NBPFILTER > 0 2747 2748 /* 2749 * Check if there's a BPF listener on this interface. If so, hand off 2750 * the raw packet to bpf. 2751 */ 2752 if (sc->arpcom.ac_if.if_bpf) { 2753 bpf_mtap(&sc->arpcom.ac_if, m); 2754 2755 /* 2756 * Note that the interface cannot be in promiscuous mode if 2757 * there are no BPF listeners. And if we are in promiscuous 2758 * mode, we have to check if this packet is really ours. 2759 */ 2760 if ((sc->arpcom.ac_if.if_flags & IFF_PROMISC) && 2761 bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr, 2762 sizeof(eh->ether_dhost)) != 0 && multicast == 0) { 2763 m_freem(m); 2764 return; 2765 } 2766 } 2767#endif 2768 2769 /* 2770 * Remove link layer address. 2771 */ 2772 m->m_pkthdr.len = m->m_len = len - sizeof(struct ether_header); 2773 m->m_data += sizeof(struct ether_header); 2774 2775 ether_input(&sc->arpcom.ac_if, eh, m); 2776 return; 2777} 2778 2779/* 2780 * Supporting routines 2781 */ 2782 2783/* 2784 * Given a NIC memory source address and a host memory destination 2785 * address, copy 'amount' from NIC to host using Programmed I/O. 2786 * The 'amount' is rounded up to a word - okay as long as mbufs 2787 * are word sized. 2788 * This routine is currently Novell-specific. 2789 */ 2790static void 2791ed_pio_readmem(sc, src, dst, amount) 2792 struct ed_softc *sc; 2793 int src; 2794 unsigned char *dst; 2795 unsigned short amount; 2796{ 2797 /* HP cards need special handling */ 2798 if (sc->vendor == ED_VENDOR_HP && sc->type == ED_TYPE_HP_PCLANPLUS) { 2799 ed_hpp_readmem(sc, src, dst, amount); 2800 return; 2801 } 2802 2803 /* Regular Novell cards */ 2804 /* select page 0 registers */ 2805 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STA); 2806 2807 /* round up to a word */ 2808 if (amount & 1) 2809 ++amount; 2810 2811 /* set up DMA byte count */ 2812 outb(sc->nic_addr + ED_P0_RBCR0, amount); 2813 outb(sc->nic_addr + ED_P0_RBCR1, amount >> 8); 2814 2815 /* set up source address in NIC mem */ 2816 outb(sc->nic_addr + ED_P0_RSAR0, src); 2817 outb(sc->nic_addr + ED_P0_RSAR1, src >> 8); 2818 2819 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD0 | ED_CR_STA); 2820 2821 if (sc->isa16bit) { 2822 insw(sc->asic_addr + ED_NOVELL_DATA, dst, amount / 2); 2823 } else 2824 insb(sc->asic_addr + ED_NOVELL_DATA, dst, amount); 2825 2826} 2827 2828/* 2829 * Stripped down routine for writing a linear buffer to NIC memory. 2830 * Only used in the probe routine to test the memory. 'len' must 2831 * be even. 2832 */ 2833static void 2834ed_pio_writemem(sc, src, dst, len) 2835 struct ed_softc *sc; 2836 char *src; 2837 unsigned short dst; 2838 unsigned short len; 2839{ 2840 int maxwait = 200; /* about 240us */ 2841 2842 if (sc->vendor == ED_VENDOR_NOVELL) { 2843 2844 /* select page 0 registers */ 2845 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STA); 2846 2847 /* reset remote DMA complete flag */ 2848 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC); 2849 2850 /* set up DMA byte count */ 2851 outb(sc->nic_addr + ED_P0_RBCR0, len); 2852 outb(sc->nic_addr + ED_P0_RBCR1, len >> 8); 2853 2854 /* set up destination address in NIC mem */ 2855 outb(sc->nic_addr + ED_P0_RSAR0, dst); 2856 outb(sc->nic_addr + ED_P0_RSAR1, dst >> 8); 2857 2858 /* set remote DMA write */ 2859 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD1 | ED_CR_STA); 2860 2861 if (sc->isa16bit) 2862 outsw(sc->asic_addr + ED_NOVELL_DATA, src, len / 2); 2863 else 2864 outsb(sc->asic_addr + ED_NOVELL_DATA, src, len); 2865 2866 /* 2867 * Wait for remote DMA complete. This is necessary because on the 2868 * transmit side, data is handled internally by the NIC in bursts and 2869 * we can't start another remote DMA until this one completes. Not 2870 * waiting causes really bad things to happen - like the NIC 2871 * irrecoverably jamming the ISA bus. 2872 */ 2873 while (((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait); 2874 2875 } else if ((sc->vendor == ED_VENDOR_HP) && 2876 (sc->type == ED_TYPE_HP_PCLANPLUS)) { 2877 2878 /* HP PCLAN+ */ 2879 2880 /* reset remote DMA complete flag */ 2881 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC); 2882 2883 /* program the write address in RAM */ 2884 outw(sc->asic_addr + ED_HPP_PAGE_0, dst); 2885 2886 if (sc->hpp_mem_start) { 2887 u_short *s = (u_short *) src; 2888 volatile u_short *d = (u_short *) sc->hpp_mem_start; 2889 u_short *const fence = s + (len >> 1); 2890 2891 /* 2892 * Enable memory mapped access. 2893 */ 2894 2895 outw(sc->asic_addr + ED_HPP_OPTION, 2896 sc->hpp_options & 2897 ~(ED_HPP_OPTION_MEM_DISABLE | 2898 ED_HPP_OPTION_BOOT_ROM_ENB)); 2899 2900 /* 2901 * Copy to NIC memory. 2902 */ 2903 2904 while (s < fence) 2905 *d = *s++; 2906 2907 /* 2908 * Restore Boot ROM access. 2909 */ 2910 2911 outw(sc->asic_addr + ED_HPP_OPTION, 2912 sc->hpp_options); 2913 2914 } else { 2915 /* write data using I/O writes */ 2916 outsw(sc->asic_addr + ED_HPP_PAGE_4, src, len / 2); 2917 } 2918 2919 } 2920} 2921 2922/* 2923 * Write an mbuf chain to the destination NIC memory address using 2924 * programmed I/O. 2925 */ 2926static u_short 2927ed_pio_write_mbufs(sc, m, dst) 2928 struct ed_softc *sc; 2929 struct mbuf *m; 2930 int dst; 2931{ 2932 struct ifnet *ifp = (struct ifnet *)sc; 2933 unsigned short total_len, dma_len; 2934 struct mbuf *mp; 2935 int maxwait = 200; /* about 240us */ 2936 2937 /* HP PC Lan+ cards need special handling */ 2938 if ((sc->vendor == ED_VENDOR_HP) && 2939 (sc->type == ED_TYPE_HP_PCLANPLUS)) { 2940 return ed_hpp_write_mbufs(sc, m, dst); 2941 } 2942 2943 /* First, count up the total number of bytes to copy */ 2944 for (total_len = 0, mp = m; mp; mp = mp->m_next) 2945 total_len += mp->m_len; 2946 2947 dma_len = total_len; 2948 if (sc->isa16bit && (dma_len & 1)) 2949 dma_len++; 2950 2951 /* select page 0 registers */ 2952 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STA); 2953 2954 /* reset remote DMA complete flag */ 2955 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC); 2956 2957 /* set up DMA byte count */ 2958 outb(sc->nic_addr + ED_P0_RBCR0, dma_len); 2959 outb(sc->nic_addr + ED_P0_RBCR1, dma_len >> 8); 2960 2961 /* set up destination address in NIC mem */ 2962 outb(sc->nic_addr + ED_P0_RSAR0, dst); 2963 outb(sc->nic_addr + ED_P0_RSAR1, dst >> 8); 2964 2965 /* set remote DMA write */ 2966 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD1 | ED_CR_STA); 2967 2968 /* 2969 * Transfer the mbuf chain to the NIC memory. 2970 * 16-bit cards require that data be transferred as words, and only words. 2971 * So that case requires some extra code to patch over odd-length mbufs. 2972 */ 2973 2974 if (!sc->isa16bit) { 2975 /* NE1000s are easy */ 2976 while (m) { 2977 if (m->m_len) { 2978 outsb(sc->asic_addr + ED_NOVELL_DATA, 2979 m->m_data, m->m_len); 2980 } 2981 m = m->m_next; 2982 } 2983 } else { 2984 /* NE2000s are a pain */ 2985 unsigned char *data; 2986 int len, wantbyte; 2987 unsigned char savebyte[2]; 2988 2989 wantbyte = 0; 2990 2991 while (m) { 2992 len = m->m_len; 2993 if (len) { 2994 data = mtod(m, caddr_t); 2995 /* finish the last word */ 2996 if (wantbyte) { 2997 savebyte[1] = *data; 2998 outw(sc->asic_addr + ED_NOVELL_DATA, *(u_short *)savebyte); 2999 data++; 3000 len--; 3001 wantbyte = 0; 3002 } 3003 /* output contiguous words */ 3004 if (len > 1) { 3005 outsw(sc->asic_addr + ED_NOVELL_DATA, 3006 data, len >> 1); 3007 data += len & ~1; 3008 len &= 1; 3009 } 3010 /* save last byte, if necessary */ 3011 if (len == 1) { 3012 savebyte[0] = *data; 3013 wantbyte = 1; 3014 } 3015 } 3016 m = m->m_next; 3017 } 3018 /* spit last byte */ 3019 if (wantbyte) { 3020 outw(sc->asic_addr + ED_NOVELL_DATA, *(u_short *)savebyte); 3021 } 3022 } 3023 3024 /* 3025 * Wait for remote DMA complete. This is necessary because on the 3026 * transmit side, data is handled internally by the NIC in bursts and 3027 * we can't start another remote DMA until this one completes. Not 3028 * waiting causes really bad things to happen - like the NIC 3029 * irrecoverably jamming the ISA bus. 3030 */ 3031 while (((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait); 3032 3033 if (!maxwait) { 3034 log(LOG_WARNING, "ed%d: remote transmit DMA failed to complete\n", 3035 ifp->if_unit); 3036 ed_reset(ifp); 3037 return(0); 3038 } 3039 return (total_len); 3040} 3041 3042/* 3043 * Support routines to handle the HP PC Lan+ card. 3044 */ 3045 3046/* 3047 * HP PC Lan+: Read from NIC memory, using either PIO or memory mapped 3048 * IO. 3049 */ 3050 3051static void 3052ed_hpp_readmem(sc, src, dst, amount) 3053 struct ed_softc *sc; 3054 unsigned short src; 3055 unsigned char *dst; 3056 unsigned short amount; 3057{ 3058 3059 int use_32bit_access = !(sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS); 3060 3061 3062 /* Program the source address in RAM */ 3063 outw(sc->asic_addr + ED_HPP_PAGE_2, src); 3064 3065 /* 3066 * The HP PC Lan+ card supports word reads as well as 3067 * a memory mapped i/o port that is aliased to every 3068 * even address on the board. 3069 */ 3070 3071 if (sc->hpp_mem_start) { 3072 3073 /* Enable memory mapped access. */ 3074 outw(sc->asic_addr + ED_HPP_OPTION, 3075 sc->hpp_options & 3076 ~(ED_HPP_OPTION_MEM_DISABLE | 3077 ED_HPP_OPTION_BOOT_ROM_ENB)); 3078 3079 if (use_32bit_access && (amount > 3)) { 3080 u_long *dl = (u_long *) dst; 3081 volatile u_long *const sl = 3082 (u_long *) sc->hpp_mem_start; 3083 u_long *const fence = dl + (amount >> 2); 3084 3085 /* Copy out NIC data. We could probably write this 3086 as a `movsl'. The currently generated code is lousy. 3087 */ 3088 3089 while (dl < fence) 3090 *dl++ = *sl; 3091 3092 dst += (amount & ~3); 3093 amount &= 3; 3094 3095 } 3096 3097 /* Finish off any words left, as a series of short reads */ 3098 if (amount > 1) { 3099 u_short *d = (u_short *) dst; 3100 volatile u_short *const s = 3101 (u_short *) sc->hpp_mem_start; 3102 u_short *const fence = d + (amount >> 1); 3103 3104 /* Copy out NIC data. */ 3105 3106 while (d < fence) 3107 *d++ = *s; 3108 3109 dst += (amount & ~1); 3110 amount &= 1; 3111 } 3112 3113 /* 3114 * read in a byte; however we need to always read 16 bits 3115 * at a time or the hardware gets into a funny state 3116 */ 3117 3118 if (amount == 1) { 3119 /* need to read in a short and copy LSB */ 3120 volatile u_short *const s = 3121 (volatile u_short *) sc->hpp_mem_start; 3122 3123 *dst = (*s) & 0xFF; 3124 } 3125 3126 /* Restore Boot ROM access. */ 3127 3128 outw(sc->asic_addr + ED_HPP_OPTION, 3129 sc->hpp_options); 3130 3131 3132 } else { 3133 /* Read in data using the I/O port */ 3134 if (use_32bit_access && (amount > 3)) { 3135 insl(sc->asic_addr + ED_HPP_PAGE_4, dst, amount >> 2); 3136 dst += (amount & ~3); 3137 amount &= 3; 3138 } 3139 if (amount > 1) { 3140 insw(sc->asic_addr + ED_HPP_PAGE_4, dst, amount >> 1); 3141 dst += (amount & ~1); 3142 amount &= 1; 3143 } 3144 if (amount == 1) { /* read in a short and keep the LSB */ 3145 *dst = inw(sc->asic_addr + ED_HPP_PAGE_4) & 0xFF; 3146 } 3147 } 3148} 3149 3150/* 3151 * Write to HP PC Lan+ NIC memory. Access to the NIC can be by using 3152 * outsw() or via the memory mapped interface to the same register. 3153 * Writes have to be in word units; byte accesses won't work and may cause 3154 * the NIC to behave wierdly. Long word accesses are permitted if the ASIC 3155 * allows it. 3156 */ 3157 3158static u_short 3159ed_hpp_write_mbufs(struct ed_softc *sc, struct mbuf *m, int dst) 3160{ 3161 int len, wantbyte; 3162 unsigned short total_len; 3163 unsigned char savebyte[2]; 3164 volatile u_short * const d = 3165 (volatile u_short *) sc->hpp_mem_start; 3166 int use_32bit_accesses = !(sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS); 3167 3168 /* select page 0 registers */ 3169 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA); 3170 3171 /* reset remote DMA complete flag */ 3172 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC); 3173 3174 /* program the write address in RAM */ 3175 outw(sc->asic_addr + ED_HPP_PAGE_0, dst); 3176 3177 if (sc->hpp_mem_start) /* enable memory mapped I/O */ 3178 outw(sc->asic_addr + ED_HPP_OPTION, sc->hpp_options & 3179 ~(ED_HPP_OPTION_MEM_DISABLE | 3180 ED_HPP_OPTION_BOOT_ROM_ENB)); 3181 3182 wantbyte = 0; 3183 total_len = 0; 3184 3185 if (sc->hpp_mem_start) { /* Memory mapped I/O port */ 3186 while (m) { 3187 total_len += (len = m->m_len); 3188 if (len) { 3189 caddr_t data = mtod(m, caddr_t); 3190 /* finish the last word of the previous mbuf */ 3191 if (wantbyte) { 3192 savebyte[1] = *data; 3193 *d = *((ushort *) savebyte); 3194 data++; len--; wantbyte = 0; 3195 } 3196 /* output contiguous words */ 3197 if ((len > 3) && (use_32bit_accesses)) { 3198 volatile u_long *const dl = 3199 (volatile u_long *) d; 3200 u_long *sl = (u_long *) data; 3201 u_long *fence = sl + (len >> 2); 3202 3203 while (sl < fence) 3204 *dl = *sl++; 3205 3206 data += (len & ~3); 3207 len &= 3; 3208 } 3209 /* finish off remain 16 bit writes */ 3210 if (len > 1) { 3211 u_short *s = (u_short *) data; 3212 u_short *fence = s + (len >> 1); 3213 3214 while (s < fence) 3215 *d = *s++; 3216 3217 data += (len & ~1); 3218 len &= 1; 3219 } 3220 /* save last byte if needed */ 3221 if (wantbyte = (len == 1)) 3222 savebyte[0] = *data; 3223 } 3224 m = m->m_next; /* to next mbuf */ 3225 } 3226 if (wantbyte) /* write last byte */ 3227 *d = *((u_short *) savebyte); 3228 } else { 3229 /* use programmed I/O */ 3230 while (m) { 3231 total_len += (len = m->m_len); 3232 if (len) { 3233 caddr_t data = mtod(m, caddr_t); 3234 /* finish the last word of the previous mbuf */ 3235 if (wantbyte) { 3236 savebyte[1] = *data; 3237 outw(sc->asic_addr + ED_HPP_PAGE_4, 3238 *((u_short *)savebyte)); 3239 data++; 3240 len--; 3241 wantbyte = 0; 3242 } 3243 /* output contiguous words */ 3244 if ((len > 3) && use_32bit_accesses) { 3245 outsl(sc->asic_addr + ED_HPP_PAGE_4, 3246 data, len >> 2); 3247 data += (len & ~3); 3248 len &= 3; 3249 } 3250 /* finish off remaining 16 bit accesses */ 3251 if (len > 1) { 3252 outsw(sc->asic_addr + ED_HPP_PAGE_4, 3253 data, len >> 1); 3254 data += (len & ~1); 3255 len &= 1; 3256 } 3257 if (wantbyte = (len == 1)) 3258 savebyte[0] = *data; 3259 3260 } /* if len != 0 */ 3261 m = m->m_next; 3262 } 3263 if (wantbyte) /* spit last byte */ 3264 outw(sc->asic_addr + ED_HPP_PAGE_4, 3265 *(u_short *)savebyte); 3266 3267 } 3268 3269 if (sc->hpp_mem_start) /* turn off memory mapped i/o */ 3270 outw(sc->asic_addr + ED_HPP_OPTION, 3271 sc->hpp_options); 3272 3273 return (total_len); 3274} 3275 3276static void 3277ed_setrcr(sc) 3278 struct ed_softc *sc; 3279{ 3280 struct ifnet *ifp = (struct ifnet *)sc; 3281 int i; 3282 3283 /* set page 1 registers */ 3284 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP); 3285 3286 if (ifp->if_flags & IFF_PROMISC) { 3287 3288 /* 3289 * Reconfigure the multicast filter. 3290 */ 3291 for (i = 0; i < 8; i++) 3292 outb(sc->nic_addr + ED_P1_MAR0 + i, 0xff); 3293 3294 /* 3295 * And turn on promiscuous mode. Also enable reception of 3296 * runts and packets with CRC & alignment errors. 3297 */ 3298 /* Set page 0 registers */ 3299 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP); 3300 3301 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_PRO | ED_RCR_AM | 3302 ED_RCR_AB | ED_RCR_AR | ED_RCR_SEP); 3303 } else { 3304 /* set up multicast addresses and filter modes */ 3305 if (ifp->if_flags & IFF_MULTICAST) { 3306 u_long mcaf[2]; 3307 3308 if (ifp->if_flags & IFF_ALLMULTI) { 3309 mcaf[0] = 0xffffffff; 3310 mcaf[1] = 0xffffffff; 3311 } else 3312 ds_getmcaf(sc, mcaf); 3313 3314 /* 3315 * Set multicast filter on chip. 3316 */ 3317 for (i = 0; i < 8; i++) 3318 outb(sc->nic_addr + ED_P1_MAR0 + i, ((u_char *) mcaf)[i]); 3319 3320 /* Set page 0 registers */ 3321 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP); 3322 3323 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_AM | ED_RCR_AB); 3324 } else { 3325 3326 /* 3327 * Initialize multicast address hashing registers to 3328 * not accept multicasts. 3329 */ 3330 for (i = 0; i < 8; ++i) 3331 outb(sc->nic_addr + ED_P1_MAR0 + i, 0x00); 3332 3333 /* Set page 0 registers */ 3334 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP); 3335 3336 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_AB); 3337 } 3338 } 3339 3340 /* 3341 * Start interface. 3342 */ 3343 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA); 3344} 3345 3346/* 3347 * Compute crc for ethernet address 3348 */ 3349static u_long 3350ds_crc(ep) 3351 u_char *ep; 3352{ 3353#define POLYNOMIAL 0x04c11db6 3354 register u_long crc = 0xffffffffL; 3355 register int carry, i, j; 3356 register u_char b; 3357 3358 for (i = 6; --i >= 0;) { 3359 b = *ep++; 3360 for (j = 8; --j >= 0;) { 3361 carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01); 3362 crc <<= 1; 3363 b >>= 1; 3364 if (carry) 3365 crc = ((crc ^ POLYNOMIAL) | carry); 3366 } 3367 } 3368 return crc; 3369#undef POLYNOMIAL 3370} 3371 3372/* 3373 * Compute the multicast address filter from the 3374 * list of multicast addresses we need to listen to. 3375 */ 3376static void 3377ds_getmcaf(sc, mcaf) 3378 struct ed_softc *sc; 3379 u_long *mcaf; 3380{ 3381 register u_int index; 3382 register u_char *af = (u_char *) mcaf; 3383 struct ifmultiaddr *ifma; 3384 3385 mcaf[0] = 0; 3386 mcaf[1] = 0; 3387 3388 for (ifma = sc->arpcom.ac_if.if_multiaddrs.lh_first; ifma; 3389 ifma = ifma->ifma_link.le_next) { 3390 if (ifma->ifma_addr->sa_family != AF_LINK) 3391 continue; 3392 index = ds_crc(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)) 3393 >> 26; 3394 af[index >> 3] |= 1 << (index & 7); 3395 } 3396} 3397 3398/* 3399 * support PnP cards if we are using 'em 3400 */ 3401 3402#if NPNP > 0 3403 3404static struct edpnp_ids { 3405 u_long vend_id; 3406 char *id_str; 3407} edpnp_ids[] = { 3408 { 0x1980635e, "WSC8019"}, 3409 { 0 } 3410}; 3411 3412static char *edpnp_probe(u_long csn, u_long vend_id); 3413static void edpnp_attach(u_long csn, u_long vend_id, char *name, 3414 struct isa_device *dev); 3415static u_long nedpnp = NED; 3416 3417static struct pnp_device edpnp = { 3418 "edpnp", 3419 edpnp_probe, 3420 edpnp_attach, 3421 &nedpnp, 3422 &net_imask 3423}; 3424DATA_SET (pnpdevice_set, edpnp); 3425 3426static char * 3427edpnp_probe(u_long csn, u_long vend_id) 3428{ 3429 struct edpnp_ids *ids; 3430 char *s = NULL; 3431 3432 for(ids = edpnp_ids; ids->vend_id != 0; ids++) { 3433 if (vend_id == ids->vend_id) { 3434 s = ids->id_str; 3435 break; 3436 } 3437 } 3438 3439 if (s) { 3440 struct pnp_cinfo d; 3441 read_pnp_parms(&d, 0); 3442 if (d.enable == 0 || d.flags & 1) { 3443 printf("CSN %lu is disabled.\n", csn); 3444 return (NULL); 3445 } 3446 3447 } 3448 3449 return (s); 3450} 3451 3452static void 3453edpnp_attach(u_long csn, u_long vend_id, char *name, struct isa_device *dev) 3454{ 3455 struct pnp_cinfo d; 3456 struct isa_device *dvp; 3457 3458 if (dev->id_unit >= NEDTOT) 3459 return; 3460 3461 if (read_pnp_parms(&d, 0) == 0) { 3462 printf("failed to read pnp parms\n"); 3463 return; 3464 } 3465 3466 write_pnp_parms(&d, 0); 3467 3468 enable_pnp_card(); 3469 3470 dev->id_iobase = d.port[0]; 3471 dev->id_irq = (1 << d.irq[0]); 3472 dev->id_intr = edintr; 3473 dev->id_drq = -1; 3474 3475 if (dev->id_driver == NULL) { 3476 dev->id_driver = &eddriver; 3477 dvp = find_isadev(isa_devtab_net, &eddriver, 0); 3478 if (dvp != NULL) 3479 dev->id_id = dvp->id_id; 3480 } 3481 3482 if ((dev->id_alive = ed_probe(dev)) != 0) 3483 ed_attach_isa(dev); 3484 else 3485 printf("ed%d: probe failed\n", dev->id_unit); 3486} 3487#endif 3488