if_ed.c revision 29261
150276Speter/* 2166124Srafan * Copyright (c) 1995, David Greenman 350276Speter * All rights reserved. 450276Speter * 550276Speter * Redistribution and use in source and binary forms, with or without 650276Speter * modification, are permitted provided that the following conditions 750276Speter * are met: 850276Speter * 1. Redistributions of source code must retain the above copyright 950276Speter * notice unmodified, this list of conditions, and the following 1050276Speter * disclaimer. 1150276Speter * 2. Redistributions in binary form must reproduce the above copyright 1250276Speter * notice, this list of conditions and the following disclaimer in the 1350276Speter * documentation and/or other materials provided with the distribution. 1450276Speter * 1550276Speter * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 1650276Speter * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1750276Speter * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1850276Speter * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 1950276Speter * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2050276Speter * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2150276Speter * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2250276Speter * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2350276Speter * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2450276Speter * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2550276Speter * SUCH DAMAGE. 2650276Speter * 2750276Speter * $Id: if_ed.c,v 1.120 1997/09/08 20:00:21 davidg Exp $ 2850276Speter */ 2950276Speter 30166124Srafan/* 3150276Speter * Device driver for National Semiconductor DS8390/WD83C690 based ethernet 3250276Speter * adapters. By David Greenman, 29-April-1993 3350276Speter * 3450276Speter * Currently supports the Western Digital/SMC 8003 and 8013 series, 35166124Srafan * the SMC Elite Ultra (8216), the 3Com 3c503, the NE1000 and NE2000, 3650276Speter * and a variety of similar clones. 3750276Speter * 3850276Speter */ 3950276Speter 4050276Speter#include "ed.h" 4150276Speter#include "bpfilter.h" 4250276Speter 4350276Speter#include <sys/param.h> 4450276Speter#include <sys/systm.h> 4550276Speter#include <sys/conf.h> 4650276Speter#include <sys/sockio.h> 4750276Speter#include <sys/malloc.h> 4850276Speter#include <sys/mbuf.h> 4976726Speter#include <sys/socket.h> 50166124Srafan#include <sys/syslog.h> 5150276Speter 5250276Speter#include <net/if.h> 5350276Speter#include <net/if_dl.h> 54166124Srafan#include <net/if_mib.h> 55166124Srafan 56166124Srafan#ifdef INET 5750276Speter#include <netinet/in.h> 5850276Speter#include <netinet/if_ether.h> 5950276Speter#endif 6050276Speter 6150276Speter#ifdef NS 6250276Speter#include <netns/ns.h> 63166124Srafan#include <netns/ns_if.h> 6450276Speter#endif 6550276Speter 66166124Srafan#if NBPFILTER > 0 6750276Speter#include <net/bpf.h> 6850276Speter#endif 6950276Speter 7050276Speter#include <machine/clock.h> 7150276Speter#include <machine/md_var.h> 72166124Srafan 7350276Speter#include <i386/isa/isa_device.h> 7450276Speter#include <i386/isa/icu.h> 7550276Speter#include <i386/isa/if_edreg.h> 76166124Srafan 77166124Srafan/* 78166124Srafan * ed_softc: per line info and status 79166124Srafan */ 80166124Srafanstruct ed_softc { 8150276Speter struct arpcom arpcom; /* ethernet common */ 8250276Speter 8350276Speter char *type_str; /* pointer to type string */ 8450276Speter u_char vendor; /* interface vendor */ 8550276Speter u_char type; /* interface type code */ 8650276Speter u_char gone; /* HW missing, presumed having a good time */ 8750276Speter 8850276Speter u_short asic_addr; /* ASIC I/O bus address */ 8950276Speter u_short nic_addr; /* NIC (DS8390) I/O bus address */ 9050276Speter 9150276Speter/* 9250276Speter * The following 'proto' variable is part of a work-around for 8013EBT asics 9350276Speter * being write-only. It's sort of a prototype/shadow of the real thing. 9450276Speter */ 9550276Speter u_char wd_laar_proto; 9650276Speter u_char cr_proto; 9750276Speter u_char isa16bit; /* width of access to card 0=8 or 1=16 */ 9876726Speter int is790; /* set by the probe code if the card is 790 99166124Srafan * based */ 10050276Speter 101166124Srafan/* 102166124Srafan * HP PC LAN PLUS card support. 103166124Srafan */ 10450276Speter 10550276Speter u_short hpp_options; /* flags controlling behaviour of the HP card */ 10650276Speter u_short hpp_id; /* software revision and other fields */ 107 caddr_t hpp_mem_start; /* Memory-mapped IO register address */ 108 109 caddr_t mem_start; /* NIC memory start address */ 110 caddr_t mem_end; /* NIC memory end address */ 111 u_long mem_size; /* total NIC memory size */ 112 caddr_t mem_ring; /* start of RX ring-buffer (in NIC mem) */ 113 114 u_char mem_shared; /* NIC memory is shared with host */ 115 u_char xmit_busy; /* transmitter is busy */ 116 u_char txb_cnt; /* number of transmit buffers */ 117 u_char txb_inuse; /* number of TX buffers currently in-use */ 118 119 u_char txb_new; /* pointer to where new buffer will be added */ 120 u_char txb_next_tx; /* pointer to next buffer ready to xmit */ 121 u_short txb_len[8]; /* buffered xmit buffer lengths */ 122 u_char tx_page_start; /* first page of TX buffer area */ 123 u_char rec_page_start; /* first page of RX ring-buffer */ 124 u_char rec_page_stop; /* last page of RX ring-buffer */ 125 u_char next_packet; /* pointer to next unread RX packet */ 126 struct ifmib_iso_8802_3 mibdata; /* stuff for network mgmt */ 127}; 128 129static struct ed_softc ed_softc[NED]; 130 131static int ed_attach __P((struct ed_softc *, int, int)); 132static int ed_attach_isa __P((struct isa_device *)); 133 134static void ed_init __P((void *)); 135static int ed_ioctl __P((struct ifnet *, int, caddr_t)); 136static int ed_probe __P((struct isa_device *)); 137static void ed_start __P((struct ifnet *)); 138static void ed_reset __P((struct ifnet *)); 139static void ed_watchdog __P((struct ifnet *)); 140 141static void ed_stop __P((struct ed_softc *)); 142static int ed_probe_generic8390 __P((struct ed_softc *)); 143static int ed_probe_WD80x3 __P((struct isa_device *)); 144static int ed_probe_3Com __P((struct isa_device *)); 145static int ed_probe_Novell __P((struct isa_device *)); 146static int ed_probe_Novell_generic __P((struct ed_softc *, int, int, int)); 147static int ed_probe_HP_pclanp __P((struct isa_device *)); 148 149#include "pci.h" 150#if NPCI > 0 151void *ed_attach_NE2000_pci __P((int, int)); 152#endif 153 154#include "crd.h" 155#if NCRD > 0 156static int ed_probe_pccard __P((struct isa_device *, u_char *)); 157#endif 158 159static void ds_getmcaf __P((struct ed_softc *, u_long *)); 160 161static void ed_get_packet(struct ed_softc *, char *, /* u_short */ int, int); 162 163static void ed_rint __P((struct ed_softc *)); 164static void ed_xmit __P((struct ed_softc *)); 165static char * ed_ring_copy __P((struct ed_softc *, char *, char *, 166 /* u_short */ int)); 167static void ed_hpp_set_physical_link __P((struct ed_softc *)); 168static void ed_hpp_readmem __P((struct ed_softc *, int, unsigned char *, 169 /* u_short */ int)); 170static u_short ed_hpp_write_mbufs __P((struct ed_softc *, struct mbuf *, 171 int)); 172 173static void ed_pio_readmem __P((struct ed_softc *, int, unsigned char *, 174 /* u_short */ int)); 175static void ed_pio_writemem __P((struct ed_softc *, char *, 176 /* u_short */ int, /* u_short */ int)); 177static u_short ed_pio_write_mbufs __P((struct ed_softc *, struct mbuf *, 178 int)); 179void edintr_sc __P((struct ed_softc *)); 180 181static void ed_setrcr(struct ed_softc *); 182 183static u_long ds_crc(u_char *ep); 184 185#if NCRD > 0 186#include <sys/select.h> 187#include <pccard/card.h> 188#include <pccard/driver.h> 189#include <pccard/slot.h> 190 191/* 192 * PC-Card (PCMCIA) specific code. 193 */ 194static int card_intr(struct pccard_dev *); /* Interrupt handler */ 195static void edunload(struct pccard_dev *); /* Disable driver */ 196static void edsuspend(struct pccard_dev *); /* Suspend driver */ 197static int edinit(struct pccard_dev *, int); /* init device */ 198 199static struct pccard_drv ed_info = { 200 "ed", 201 card_intr, 202 edunload, 203 edsuspend, 204 edinit, 205 0, /* Attributes - presently unused */ 206 &net_imask /* Interrupt mask for device */ 207 /* XXX - Should this also include net_imask? */ 208}; 209 210/* 211 * Called when a power down is requested. Shuts down the 212 * device and configures the device as unavailable (but 213 * still loaded...). A resume is done by calling 214 * edinit with first=0. This is called when the user suspends 215 * the system, or the APM code suspends the system. 216 */ 217static void 218edsuspend(struct pccard_dev *dp) 219{ 220 struct ed_softc *sc = &ed_softc[dp->isahd.id_unit]; 221 /* 222 * Some 'ed' cards will generate a interrupt as they go away, 223 * and by the time the interrupt handler gets to the card, 224 * the interrupt can't be cleared. 225 * By setting gone here, we tell the handler to ignore the 226 * interrupt when it happens. 227 */ 228 sc->gone = 1; /* avoid spinning endlessly in interrupt handler */ 229 230 printf("ed%d: suspending\n", dp->isahd.id_unit); 231} 232 233/* 234 * Initialize the device - called from Slot manager. 235 * If first is set, then check for the device's existence 236 * before initializing it. Once initialized, the device table may 237 * be set up. 238 */ 239static int 240edinit(struct pccard_dev *dp, int first) 241{ 242 struct ed_softc *sc = &ed_softc[dp->isahd.id_unit]; 243 244 /* validate unit number. */ 245 if (first) { 246 if (dp->isahd.id_unit >= NED) 247 return(ENODEV); 248 /* 249 * Probe the device. If a value is returned, the 250 * device was found at the location. 251 */ 252 sc->gone = 0; 253 if (ed_probe_pccard(&dp->isahd,dp->misc)==0) 254 return(ENXIO); 255 if (ed_attach_isa(&dp->isahd)==0) 256 return(ENXIO); 257 } else { 258 sc->gone = 0; /* reenable after a suspend */ 259 } 260 /* 261 * XXX TODO: 262 * If it was initialized before, the device structure 263 * should also be initialized. We should 264 * reset (and possibly restart) the hardware, but 265 * I am not sure of the best way to do this... 266 */ 267 return(0); 268} 269 270/* 271 * edunload - unload the driver and clear the table. 272 * XXX TODO: 273 * This is usually called when the card is ejected, but 274 * can be caused by a modunload of a controller driver. 275 * The idea is to reset the driver's view of the device 276 * and ensure that any driver entry points such as 277 * read and write do not hang. 278 */ 279static void 280edunload(struct pccard_dev *dp) 281{ 282 struct ed_softc *sc = &ed_softc[dp->isahd.id_unit]; 283 struct ifnet *ifp = &sc->arpcom.ac_if; 284 285 if (sc->gone) { 286 printf("ed%d: already unloaded\n", dp->isahd.id_unit); 287 return; 288 } 289 ifp->if_flags &= ~IFF_RUNNING; 290 if_down(ifp); 291 sc->gone = 1; 292 printf("ed%d: unload\n", dp->isahd.id_unit); 293} 294 295/* 296 * card_intr - Shared interrupt called from 297 * front end of PC-Card handler. 298 */ 299static int 300card_intr(struct pccard_dev *dp) 301{ 302 edintr_sc(&ed_softc[dp->isahd.id_unit]); 303 return(1); 304} 305#endif /* NCRD > 0 */ 306 307struct isa_driver eddriver = { 308 ed_probe, 309 ed_attach_isa, 310 "ed", 311 1 /* We are ultra sensitive */ 312}; 313 314/* 315 * Interrupt conversion table for WD/SMC ASIC/83C584 316 * (IRQ* are defined in icu.h) 317 */ 318static unsigned short ed_intr_mask[] = { 319 IRQ9, 320 IRQ3, 321 IRQ5, 322 IRQ7, 323 IRQ10, 324 IRQ11, 325 IRQ15, 326 IRQ4 327}; 328 329/* 330 * Interrupt conversion table for 83C790 331 */ 332static unsigned short ed_790_intr_mask[] = { 333 0, 334 IRQ9, 335 IRQ3, 336 IRQ5, 337 IRQ7, 338 IRQ10, 339 IRQ11, 340 IRQ15 341}; 342 343/* 344 * Interrupt conversion table for the HP PC LAN+ 345 */ 346 347static unsigned short ed_hpp_intr_mask[] = { 348 0, /* 0 */ 349 0, /* 1 */ 350 0, /* 2 */ 351 IRQ3, /* 3 */ 352 IRQ4, /* 4 */ 353 IRQ5, /* 5 */ 354 IRQ6, /* 6 */ 355 IRQ7, /* 7 */ 356 0, /* 8 */ 357 IRQ9, /* 9 */ 358 IRQ10, /* 10 */ 359 IRQ11, /* 11 */ 360 IRQ12, /* 12 */ 361 0, /* 13 */ 362 0, /* 14 */ 363 IRQ15 /* 15 */ 364}; 365 366/* 367 * Determine if the device is present 368 * 369 * on entry: 370 * a pointer to an isa_device struct 371 * on exit: 372 * NULL if device not found 373 * or # of i/o addresses used (if found) 374 */ 375static int 376ed_probe(isa_dev) 377 struct isa_device *isa_dev; 378{ 379 int nports; 380 381#if NCRD > 0 382 /* 383 * If PC-Card probe required, then register driver with 384 * slot manager. 385 */ 386 pccard_add_driver(&ed_info); 387#endif 388 389 nports = ed_probe_WD80x3(isa_dev); 390 if (nports) 391 return (nports); 392 393 nports = ed_probe_3Com(isa_dev); 394 if (nports) 395 return (nports); 396 397 nports = ed_probe_Novell(isa_dev); 398 if (nports) 399 return (nports); 400 401 nports = ed_probe_HP_pclanp(isa_dev); 402 if (nports) 403 return (nports); 404 405 return (0); 406} 407 408/* 409 * Generic probe routine for testing for the existance of a DS8390. 410 * Must be called after the NIC has just been reset. This routine 411 * works by looking at certain register values that are guaranteed 412 * to be initialized a certain way after power-up or reset. Seems 413 * not to currently work on the 83C690. 414 * 415 * Specifically: 416 * 417 * Register reset bits set bits 418 * Command Register (CR) TXP, STA RD2, STP 419 * Interrupt Status (ISR) RST 420 * Interrupt Mask (IMR) All bits 421 * Data Control (DCR) LAS 422 * Transmit Config. (TCR) LB1, LB0 423 * 424 * We only look at the CR and ISR registers, however, because looking at 425 * the others would require changing register pages (which would be 426 * intrusive if this isn't an 8390). 427 * 428 * Return 1 if 8390 was found, 0 if not. 429 */ 430 431static int 432ed_probe_generic8390(sc) 433 struct ed_softc *sc; 434{ 435 if ((inb(sc->nic_addr + ED_P0_CR) & 436 (ED_CR_RD2 | ED_CR_TXP | ED_CR_STA | ED_CR_STP)) != 437 (ED_CR_RD2 | ED_CR_STP)) 438 return (0); 439 if ((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RST) != ED_ISR_RST) 440 return (0); 441 442 return (1); 443} 444 445/* 446 * Probe and vendor-specific initialization routine for SMC/WD80x3 boards 447 */ 448static int 449ed_probe_WD80x3(isa_dev) 450 struct isa_device *isa_dev; 451{ 452 struct ed_softc *sc = &ed_softc[isa_dev->id_unit]; 453 int i; 454 u_int memsize, maddr; 455 u_char iptr, isa16bit, sum; 456 457 sc->asic_addr = isa_dev->id_iobase; 458 sc->nic_addr = sc->asic_addr + ED_WD_NIC_OFFSET; 459 sc->is790 = 0; 460 461#ifdef TOSH_ETHER 462 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_POW); 463 DELAY(10000); 464#endif 465 466 /* 467 * Attempt to do a checksum over the station address PROM. If it 468 * fails, it's probably not a SMC/WD board. There is a problem with 469 * this, though: some clone WD boards don't pass the checksum test. 470 * Danpex boards for one. 471 */ 472 for (sum = 0, i = 0; i < 8; ++i) 473 sum += inb(sc->asic_addr + ED_WD_PROM + i); 474 475 if (sum != ED_WD_ROM_CHECKSUM_TOTAL) { 476 477 /* 478 * Checksum is invalid. This often happens with cheap WD8003E 479 * clones. In this case, the checksum byte (the eighth byte) 480 * seems to always be zero. 481 */ 482 if (inb(sc->asic_addr + ED_WD_CARD_ID) != ED_TYPE_WD8003E || 483 inb(sc->asic_addr + ED_WD_PROM + 7) != 0) 484 return (0); 485 } 486 /* reset card to force it into a known state. */ 487#ifdef TOSH_ETHER 488 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_RST | ED_WD_MSR_POW); 489#else 490 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_RST); 491#endif 492 DELAY(100); 493 outb(sc->asic_addr + ED_WD_MSR, inb(sc->asic_addr + ED_WD_MSR) & ~ED_WD_MSR_RST); 494 /* wait in the case this card is reading it's EEROM */ 495 DELAY(5000); 496 497 sc->vendor = ED_VENDOR_WD_SMC; 498 sc->type = inb(sc->asic_addr + ED_WD_CARD_ID); 499 500 /* 501 * Set initial values for width/size. 502 */ 503 memsize = 8192; 504 isa16bit = 0; 505 switch (sc->type) { 506 case ED_TYPE_WD8003S: 507 sc->type_str = "WD8003S"; 508 break; 509 case ED_TYPE_WD8003E: 510 sc->type_str = "WD8003E"; 511 break; 512 case ED_TYPE_WD8003EB: 513 sc->type_str = "WD8003EB"; 514 break; 515 case ED_TYPE_WD8003W: 516 sc->type_str = "WD8003W"; 517 break; 518 case ED_TYPE_WD8013EBT: 519 sc->type_str = "WD8013EBT"; 520 memsize = 16384; 521 isa16bit = 1; 522 break; 523 case ED_TYPE_WD8013W: 524 sc->type_str = "WD8013W"; 525 memsize = 16384; 526 isa16bit = 1; 527 break; 528 case ED_TYPE_WD8013EP: /* also WD8003EP */ 529 if (inb(sc->asic_addr + ED_WD_ICR) 530 & ED_WD_ICR_16BIT) { 531 isa16bit = 1; 532 memsize = 16384; 533 sc->type_str = "WD8013EP"; 534 } else { 535 sc->type_str = "WD8003EP"; 536 } 537 break; 538 case ED_TYPE_WD8013WC: 539 sc->type_str = "WD8013WC"; 540 memsize = 16384; 541 isa16bit = 1; 542 break; 543 case ED_TYPE_WD8013EBP: 544 sc->type_str = "WD8013EBP"; 545 memsize = 16384; 546 isa16bit = 1; 547 break; 548 case ED_TYPE_WD8013EPC: 549 sc->type_str = "WD8013EPC"; 550 memsize = 16384; 551 isa16bit = 1; 552 break; 553 case ED_TYPE_SMC8216C: /* 8216 has 16K shared mem -- 8416 has 8K */ 554 case ED_TYPE_SMC8216T: 555 if (sc->type == ED_TYPE_SMC8216C) { 556 sc->type_str = "SMC8216/SMC8216C"; 557 } else { 558 sc->type_str = "SMC8216T"; 559 } 560 561 outb(sc->asic_addr + ED_WD790_HWR, 562 inb(sc->asic_addr + ED_WD790_HWR) | ED_WD790_HWR_SWH); 563 switch (inb(sc->asic_addr + ED_WD790_RAR) & ED_WD790_RAR_SZ64) { 564 case ED_WD790_RAR_SZ64: 565 memsize = 65536; 566 break; 567 case ED_WD790_RAR_SZ32: 568 memsize = 32768; 569 break; 570 case ED_WD790_RAR_SZ16: 571 memsize = 16384; 572 break; 573 case ED_WD790_RAR_SZ8: 574 /* 8216 has 16K shared mem -- 8416 has 8K */ 575 if (sc->type == ED_TYPE_SMC8216C) { 576 sc->type_str = "SMC8416C/SMC8416BT"; 577 } else { 578 sc->type_str = "SMC8416T"; 579 } 580 memsize = 8192; 581 break; 582 } 583 outb(sc->asic_addr + ED_WD790_HWR, 584 inb(sc->asic_addr + ED_WD790_HWR) & ~ED_WD790_HWR_SWH); 585 586 isa16bit = 1; 587 sc->is790 = 1; 588 break; 589#ifdef TOSH_ETHER 590 case ED_TYPE_TOSHIBA1: 591 sc->type_str = "Toshiba1"; 592 memsize = 32768; 593 isa16bit = 1; 594 break; 595 case ED_TYPE_TOSHIBA4: 596 sc->type_str = "Toshiba4"; 597 memsize = 32768; 598 isa16bit = 1; 599 break; 600#endif 601 default: 602 sc->type_str = ""; 603 break; 604 } 605 606 /* 607 * Make some adjustments to initial values depending on what is found 608 * in the ICR. 609 */ 610 if (isa16bit && (sc->type != ED_TYPE_WD8013EBT) 611#ifdef TOSH_ETHER 612 && (sc->type != ED_TYPE_TOSHIBA1) && (sc->type != ED_TYPE_TOSHIBA4) 613#endif 614 && ((inb(sc->asic_addr + ED_WD_ICR) & ED_WD_ICR_16BIT) == 0)) { 615 isa16bit = 0; 616 memsize = 8192; 617 } 618 619#if ED_DEBUG 620 printf("type = %x type_str=%s isa16bit=%d memsize=%d id_msize=%d\n", 621 sc->type, sc->type_str, isa16bit, memsize, isa_dev->id_msize); 622 for (i = 0; i < 8; i++) 623 printf("%x -> %x\n", i, inb(sc->asic_addr + i)); 624#endif 625 626 /* 627 * Allow the user to override the autoconfiguration 628 */ 629 if (isa_dev->id_msize) 630 memsize = isa_dev->id_msize; 631 632 maddr = (u_int) isa_dev->id_maddr & 0xffffff; 633 if (maddr < 0xa0000 || maddr + memsize > 0x1000000) { 634 printf("ed%d: Invalid ISA memory address range configured: 0x%x - 0x%x\n", 635 isa_dev->id_unit, maddr, maddr + memsize); 636 return 0; 637 } 638 639 /* 640 * (note that if the user specifies both of the following flags that 641 * '8bit' mode intentionally has precedence) 642 */ 643 if (isa_dev->id_flags & ED_FLAGS_FORCE_16BIT_MODE) 644 isa16bit = 1; 645 if (isa_dev->id_flags & ED_FLAGS_FORCE_8BIT_MODE) 646 isa16bit = 0; 647 648 /* 649 * If possible, get the assigned interrupt number from the card and 650 * use it. 651 */ 652 if ((sc->type & ED_WD_SOFTCONFIG) && (!sc->is790)) { 653 654 /* 655 * Assemble together the encoded interrupt number. 656 */ 657 iptr = (inb(isa_dev->id_iobase + ED_WD_ICR) & ED_WD_ICR_IR2) | 658 ((inb(isa_dev->id_iobase + ED_WD_IRR) & 659 (ED_WD_IRR_IR0 | ED_WD_IRR_IR1)) >> 5); 660 661 /* 662 * If no interrupt specified (or "?"), use what the board tells us. 663 */ 664 if (isa_dev->id_irq <= 0) 665 isa_dev->id_irq = ed_intr_mask[iptr]; 666 667 /* 668 * Enable the interrupt. 669 */ 670 outb(isa_dev->id_iobase + ED_WD_IRR, 671 inb(isa_dev->id_iobase + ED_WD_IRR) | ED_WD_IRR_IEN); 672 } 673 if (sc->is790) { 674 outb(isa_dev->id_iobase + ED_WD790_HWR, 675 inb(isa_dev->id_iobase + ED_WD790_HWR) | ED_WD790_HWR_SWH); 676 iptr = (((inb(isa_dev->id_iobase + ED_WD790_GCR) & ED_WD790_GCR_IR2) >> 4) | 677 (inb(isa_dev->id_iobase + ED_WD790_GCR) & 678 (ED_WD790_GCR_IR1 | ED_WD790_GCR_IR0)) >> 2); 679 outb(isa_dev->id_iobase + ED_WD790_HWR, 680 inb(isa_dev->id_iobase + ED_WD790_HWR) & ~ED_WD790_HWR_SWH); 681 682 /* 683 * If no interrupt specified (or "?"), use what the board tells us. 684 */ 685 if (isa_dev->id_irq <= 0) 686 isa_dev->id_irq = ed_790_intr_mask[iptr]; 687 688 /* 689 * Enable interrupts. 690 */ 691 outb(isa_dev->id_iobase + ED_WD790_ICR, 692 inb(isa_dev->id_iobase + ED_WD790_ICR) | ED_WD790_ICR_EIL); 693 } 694 if (isa_dev->id_irq <= 0) { 695 printf("ed%d: %s cards don't support auto-detected/assigned interrupts.\n", 696 isa_dev->id_unit, sc->type_str); 697 return (0); 698 } 699 sc->isa16bit = isa16bit; 700 sc->mem_shared = 1; 701 isa_dev->id_msize = memsize; 702 sc->mem_start = (caddr_t) isa_dev->id_maddr; 703 704 /* 705 * allocate one xmit buffer if < 16k, two buffers otherwise 706 */ 707 if ((memsize < 16384) || 708 (isa_dev->id_flags & ED_FLAGS_NO_MULTI_BUFFERING)) { 709 sc->txb_cnt = 1; 710 } else { 711 sc->txb_cnt = 2; 712 } 713 sc->tx_page_start = ED_WD_PAGE_OFFSET; 714 sc->rec_page_start = ED_WD_PAGE_OFFSET + ED_TXBUF_SIZE * sc->txb_cnt; 715 sc->rec_page_stop = ED_WD_PAGE_OFFSET + memsize / ED_PAGE_SIZE; 716 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * sc->rec_page_start); 717 sc->mem_size = memsize; 718 sc->mem_end = sc->mem_start + memsize; 719 720 /* 721 * Get station address from on-board ROM 722 */ 723 for (i = 0; i < ETHER_ADDR_LEN; ++i) 724 sc->arpcom.ac_enaddr[i] = inb(sc->asic_addr + ED_WD_PROM + i); 725 726 /* 727 * Set upper address bits, 8/16 bit access to shared memory, and 728 * zero waitstate operation for 16 bit cards. 729 */ 730 if (isa16bit) { 731 if (sc->is790) { 732 sc->wd_laar_proto = inb(sc->asic_addr + ED_WD_LAAR); 733 /* 734 * Enable zero waitstate operation 735 */ 736 outb(sc->asic_addr + ED_WD790_GCR, inb(sc->asic_addr + 737 ED_WD790_GCR) | ED_WD790_GCR_ZWSEN); 738 } else { 739 sc->wd_laar_proto = ED_WD_LAAR_L16EN | ED_WD_LAAR_0WS16 | 740 ((kvtop(sc->mem_start) >> 19) & ED_WD_LAAR_ADDRHI); 741 } 742 /* 743 * Enable 16bit access 744 */ 745 outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto | 746 ED_WD_LAAR_M16EN); 747 } else { 748 if (((sc->type & ED_WD_SOFTCONFIG) || 749#ifdef TOSH_ETHER 750 (sc->type == ED_TYPE_TOSHIBA1) || (sc->type == ED_TYPE_TOSHIBA4) || 751#endif 752 (sc->type == ED_TYPE_WD8013EBT)) && (!sc->is790)) { 753 sc->wd_laar_proto = (kvtop(sc->mem_start) >> 19) & 754 ED_WD_LAAR_ADDRHI; 755 outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto); 756 } 757 } 758 759 /* 760 * Set address and enable interface shared memory. 761 */ 762 if (!sc->is790) { 763#ifdef TOSH_ETHER 764 outb(sc->asic_addr + ED_WD_MSR + 1, ((kvtop(sc->mem_start) >> 8) & 0xe0) | 4); 765 outb(sc->asic_addr + ED_WD_MSR + 2, ((kvtop(sc->mem_start) >> 16) & 0x0f)); 766 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_MENB | ED_WD_MSR_POW); 767 768#else 769 outb(sc->asic_addr + ED_WD_MSR, ((kvtop(sc->mem_start) >> 13) & 770 ED_WD_MSR_ADDR) | ED_WD_MSR_MENB); 771#endif 772 sc->cr_proto = ED_CR_RD2; 773 } else { 774 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_MENB); 775 outb(sc->asic_addr + ED_WD790_HWR, (inb(sc->asic_addr + ED_WD790_HWR) | ED_WD790_HWR_SWH)); 776 outb(sc->asic_addr + ED_WD790_RAR, ((kvtop(sc->mem_start) >> 13) & 0x0f) | 777 ((kvtop(sc->mem_start) >> 11) & 0x40) | 778 (inb(sc->asic_addr + ED_WD790_RAR) & 0xb0)); 779 outb(sc->asic_addr + ED_WD790_HWR, (inb(sc->asic_addr + ED_WD790_HWR) & ~ED_WD790_HWR_SWH)); 780 sc->cr_proto = 0; 781 } 782 783#if 0 784 printf("starting memory performance test at 0x%x, size %d...\n", 785 sc->mem_start, memsize*16384); 786 for (i = 0; i < 16384; i++) 787 bzero(sc->mem_start, memsize); 788 printf("***DONE***\n"); 789#endif 790 791 /* 792 * Now zero memory and verify that it is clear 793 */ 794 bzero(sc->mem_start, memsize); 795 796 for (i = 0; i < memsize; ++i) { 797 if (sc->mem_start[i]) { 798 printf("ed%d: failed to clear shared memory at %lx - check configuration\n", 799 isa_dev->id_unit, kvtop(sc->mem_start + i)); 800 801 /* 802 * Disable 16 bit access to shared memory 803 */ 804 if (isa16bit) { 805 if (sc->is790) { 806 outb(sc->asic_addr + ED_WD_MSR, 0x00); 807 } 808 outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto & 809 ~ED_WD_LAAR_M16EN); 810 } 811 return (0); 812 } 813 } 814 815 /* 816 * Disable 16bit access to shared memory - we leave it 817 * disabled so that 1) machines reboot properly when the board 818 * is set 16 bit mode and there are conflicting 8bit 819 * devices/ROMS in the same 128k address space as this boards 820 * shared memory. and 2) so that other 8 bit devices with 821 * shared memory can be used in this 128k region, too. 822 */ 823 if (isa16bit) { 824 if (sc->is790) { 825 outb(sc->asic_addr + ED_WD_MSR, 0x00); 826 } 827 outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto & 828 ~ED_WD_LAAR_M16EN); 829 } 830 return (ED_WD_IO_PORTS); 831} 832 833/* 834 * Probe and vendor-specific initialization routine for 3Com 3c503 boards 835 */ 836static int 837ed_probe_3Com(isa_dev) 838 struct isa_device *isa_dev; 839{ 840 struct ed_softc *sc = &ed_softc[isa_dev->id_unit]; 841 int i; 842 u_int memsize; 843 u_char isa16bit; 844 845 sc->asic_addr = isa_dev->id_iobase + ED_3COM_ASIC_OFFSET; 846 sc->nic_addr = isa_dev->id_iobase + ED_3COM_NIC_OFFSET; 847 848 /* 849 * Verify that the kernel configured I/O address matches the board 850 * configured address 851 */ 852 switch (inb(sc->asic_addr + ED_3COM_BCFR)) { 853 case ED_3COM_BCFR_300: 854 if (isa_dev->id_iobase != 0x300) 855 return (0); 856 break; 857 case ED_3COM_BCFR_310: 858 if (isa_dev->id_iobase != 0x310) 859 return (0); 860 break; 861 case ED_3COM_BCFR_330: 862 if (isa_dev->id_iobase != 0x330) 863 return (0); 864 break; 865 case ED_3COM_BCFR_350: 866 if (isa_dev->id_iobase != 0x350) 867 return (0); 868 break; 869 case ED_3COM_BCFR_250: 870 if (isa_dev->id_iobase != 0x250) 871 return (0); 872 break; 873 case ED_3COM_BCFR_280: 874 if (isa_dev->id_iobase != 0x280) 875 return (0); 876 break; 877 case ED_3COM_BCFR_2A0: 878 if (isa_dev->id_iobase != 0x2a0) 879 return (0); 880 break; 881 case ED_3COM_BCFR_2E0: 882 if (isa_dev->id_iobase != 0x2e0) 883 return (0); 884 break; 885 default: 886 return (0); 887 } 888 889 /* 890 * Verify that the kernel shared memory address matches the board 891 * configured address. 892 */ 893 switch (inb(sc->asic_addr + ED_3COM_PCFR)) { 894 case ED_3COM_PCFR_DC000: 895 if (kvtop(isa_dev->id_maddr) != 0xdc000) 896 return (0); 897 break; 898 case ED_3COM_PCFR_D8000: 899 if (kvtop(isa_dev->id_maddr) != 0xd8000) 900 return (0); 901 break; 902 case ED_3COM_PCFR_CC000: 903 if (kvtop(isa_dev->id_maddr) != 0xcc000) 904 return (0); 905 break; 906 case ED_3COM_PCFR_C8000: 907 if (kvtop(isa_dev->id_maddr) != 0xc8000) 908 return (0); 909 break; 910 default: 911 return (0); 912 } 913 914 915 /* 916 * Reset NIC and ASIC. Enable on-board transceiver throughout reset 917 * sequence because it'll lock up if the cable isn't connected if we 918 * don't. 919 */ 920 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_RST | ED_3COM_CR_XSEL); 921 922 /* 923 * Wait for a while, then un-reset it 924 */ 925 DELAY(50); 926 927 /* 928 * The 3Com ASIC defaults to rather strange settings for the CR after 929 * a reset - it's important to set it again after the following outb 930 * (this is done when we map the PROM below). 931 */ 932 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL); 933 934 /* 935 * Wait a bit for the NIC to recover from the reset 936 */ 937 DELAY(5000); 938 939 sc->vendor = ED_VENDOR_3COM; 940 sc->type_str = "3c503"; 941 sc->mem_shared = 1; 942 sc->cr_proto = ED_CR_RD2; 943 944 /* 945 * Hmmm...a 16bit 3Com board has 16k of memory, but only an 8k window 946 * to it. 947 */ 948 memsize = 8192; 949 950 /* 951 * Get station address from on-board ROM 952 */ 953 954 /* 955 * First, map ethernet address PROM over the top of where the NIC 956 * registers normally appear. 957 */ 958 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_EALO | ED_3COM_CR_XSEL); 959 960 for (i = 0; i < ETHER_ADDR_LEN; ++i) 961 sc->arpcom.ac_enaddr[i] = inb(sc->nic_addr + i); 962 963 /* 964 * Unmap PROM - select NIC registers. The proper setting of the 965 * tranceiver is set in ed_init so that the attach code is given a 966 * chance to set the default based on a compile-time config option 967 */ 968 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL); 969 970 /* 971 * Determine if this is an 8bit or 16bit board 972 */ 973 974 /* 975 * select page 0 registers 976 */ 977 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STP); 978 979 /* 980 * Attempt to clear WTS bit. If it doesn't clear, then this is a 16bit 981 * board. 982 */ 983 outb(sc->nic_addr + ED_P0_DCR, 0); 984 985 /* 986 * select page 2 registers 987 */ 988 outb(sc->nic_addr + ED_P0_CR, ED_CR_PAGE_2 | ED_CR_RD2 | ED_CR_STP); 989 990 /* 991 * The 3c503 forces the WTS bit to a one if this is a 16bit board 992 */ 993 if (inb(sc->nic_addr + ED_P2_DCR) & ED_DCR_WTS) 994 isa16bit = 1; 995 else 996 isa16bit = 0; 997 998 /* 999 * select page 0 registers 1000 */ 1001 outb(sc->nic_addr + ED_P2_CR, ED_CR_RD2 | ED_CR_STP); 1002 1003 sc->mem_start = (caddr_t) isa_dev->id_maddr; 1004 sc->mem_size = memsize; 1005 sc->mem_end = sc->mem_start + memsize; 1006 1007 /* 1008 * We have an entire 8k window to put the transmit buffers on the 1009 * 16bit boards. But since the 16bit 3c503's shared memory is only 1010 * fast enough to overlap the loading of one full-size packet, trying 1011 * to load more than 2 buffers can actually leave the transmitter idle 1012 * during the load. So 2 seems the best value. (Although a mix of 1013 * variable-sized packets might change this assumption. Nonetheless, 1014 * we optimize for linear transfers of same-size packets.) 1015 */ 1016 if (isa16bit) { 1017 if (isa_dev->id_flags & ED_FLAGS_NO_MULTI_BUFFERING) 1018 sc->txb_cnt = 1; 1019 else 1020 sc->txb_cnt = 2; 1021 1022 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_16BIT; 1023 sc->rec_page_start = ED_3COM_RX_PAGE_OFFSET_16BIT; 1024 sc->rec_page_stop = memsize / ED_PAGE_SIZE + 1025 ED_3COM_RX_PAGE_OFFSET_16BIT; 1026 sc->mem_ring = sc->mem_start; 1027 } else { 1028 sc->txb_cnt = 1; 1029 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_8BIT; 1030 sc->rec_page_start = ED_TXBUF_SIZE + ED_3COM_TX_PAGE_OFFSET_8BIT; 1031 sc->rec_page_stop = memsize / ED_PAGE_SIZE + 1032 ED_3COM_TX_PAGE_OFFSET_8BIT; 1033 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * ED_TXBUF_SIZE); 1034 } 1035 1036 sc->isa16bit = isa16bit; 1037 1038 /* 1039 * Initialize GA page start/stop registers. Probably only needed if 1040 * doing DMA, but what the hell. 1041 */ 1042 outb(sc->asic_addr + ED_3COM_PSTR, sc->rec_page_start); 1043 outb(sc->asic_addr + ED_3COM_PSPR, sc->rec_page_stop); 1044 1045 /* 1046 * Set IRQ. 3c503 only allows a choice of irq 2-5. 1047 */ 1048 switch (isa_dev->id_irq) { 1049 case IRQ2: 1050 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ2); 1051 break; 1052 case IRQ3: 1053 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ3); 1054 break; 1055 case IRQ4: 1056 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ4); 1057 break; 1058 case IRQ5: 1059 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ5); 1060 break; 1061 default: 1062 printf("ed%d: Invalid irq configuration (%d) must be 3-5,9 for 3c503\n", 1063 isa_dev->id_unit, ffs(isa_dev->id_irq) - 1); 1064 return (0); 1065 } 1066 1067 /* 1068 * Initialize GA configuration register. Set bank and enable shared 1069 * mem. 1070 */ 1071 outb(sc->asic_addr + ED_3COM_GACFR, ED_3COM_GACFR_RSEL | 1072 ED_3COM_GACFR_MBS0); 1073 1074 /* 1075 * Initialize "Vector Pointer" registers. These gawd-awful things are 1076 * compared to 20 bits of the address on ISA, and if they match, the 1077 * shared memory is disabled. We set them to 0xffff0...allegedly the 1078 * reset vector. 1079 */ 1080 outb(sc->asic_addr + ED_3COM_VPTR2, 0xff); 1081 outb(sc->asic_addr + ED_3COM_VPTR1, 0xff); 1082 outb(sc->asic_addr + ED_3COM_VPTR0, 0x00); 1083 1084 /* 1085 * Zero memory and verify that it is clear 1086 */ 1087 bzero(sc->mem_start, memsize); 1088 1089 for (i = 0; i < memsize; ++i) 1090 if (sc->mem_start[i]) { 1091 printf("ed%d: failed to clear shared memory at %lx - check configuration\n", 1092 isa_dev->id_unit, kvtop(sc->mem_start + i)); 1093 return (0); 1094 } 1095 isa_dev->id_msize = memsize; 1096 return (ED_3COM_IO_PORTS); 1097} 1098 1099/* 1100 * Probe and vendor-specific initialization routine for NE1000/2000 boards 1101 */ 1102static int 1103ed_probe_Novell_generic(sc, port, unit, flags) 1104 struct ed_softc *sc; 1105 int port; 1106 int unit; 1107 int flags; 1108{ 1109 u_int memsize, n; 1110 u_char romdata[16], tmp; 1111 static char test_pattern[32] = "THIS is A memory TEST pattern"; 1112 char test_buffer[32]; 1113 1114 sc->asic_addr = port + ED_NOVELL_ASIC_OFFSET; 1115 sc->nic_addr = port + ED_NOVELL_NIC_OFFSET; 1116 1117 /* XXX - do Novell-specific probe here */ 1118 1119 /* Reset the board */ 1120#ifdef GWETHER 1121 outb(sc->asic_addr + ED_NOVELL_RESET, 0); 1122 DELAY(200); 1123#endif /* GWETHER */ 1124 tmp = inb(sc->asic_addr + ED_NOVELL_RESET); 1125 1126 /* 1127 * I don't know if this is necessary; probably cruft leftover from 1128 * Clarkson packet driver code. Doesn't do a thing on the boards I've 1129 * tested. -DG [note that a outb(0x84, 0) seems to work here, and is 1130 * non-invasive...but some boards don't seem to reset and I don't have 1131 * complete documentation on what the 'right' thing to do is...so we 1132 * do the invasive thing for now. Yuck.] 1133 */ 1134 outb(sc->asic_addr + ED_NOVELL_RESET, tmp); 1135 DELAY(5000); 1136 1137 /* 1138 * This is needed because some NE clones apparently don't reset the 1139 * NIC properly (or the NIC chip doesn't reset fully on power-up) XXX 1140 * - this makes the probe invasive! ...Done against my better 1141 * judgement. -DLG 1142 */ 1143 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STP); 1144 1145 DELAY(5000); 1146 1147 /* Make sure that we really have an 8390 based board */ 1148 if (!ed_probe_generic8390(sc)) 1149 return (0); 1150 1151 sc->vendor = ED_VENDOR_NOVELL; 1152 sc->mem_shared = 0; 1153 sc->cr_proto = ED_CR_RD2; 1154 1155 /* 1156 * Test the ability to read and write to the NIC memory. This has the 1157 * side affect of determining if this is an NE1000 or an NE2000. 1158 */ 1159 1160 /* 1161 * This prevents packets from being stored in the NIC memory when the 1162 * readmem routine turns on the start bit in the CR. 1163 */ 1164 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_MON); 1165 1166 /* Temporarily initialize DCR for byte operations */ 1167 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS); 1168 1169 outb(sc->nic_addr + ED_P0_PSTART, 8192 / ED_PAGE_SIZE); 1170 outb(sc->nic_addr + ED_P0_PSTOP, 16384 / ED_PAGE_SIZE); 1171 1172 sc->isa16bit = 0; 1173 1174 /* 1175 * Write a test pattern in byte mode. If this fails, then there 1176 * probably isn't any memory at 8k - which likely means that the board 1177 * is an NE2000. 1178 */ 1179 ed_pio_writemem(sc, test_pattern, 8192, sizeof(test_pattern)); 1180 ed_pio_readmem(sc, 8192, test_buffer, sizeof(test_pattern)); 1181 1182 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern))) { 1183 /* not an NE1000 - try NE2000 */ 1184 1185 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_WTS | ED_DCR_FT1 | ED_DCR_LS); 1186 outb(sc->nic_addr + ED_P0_PSTART, 16384 / ED_PAGE_SIZE); 1187 outb(sc->nic_addr + ED_P0_PSTOP, 32768 / ED_PAGE_SIZE); 1188 1189 sc->isa16bit = 1; 1190 1191 /* 1192 * Write a test pattern in word mode. If this also fails, then 1193 * we don't know what this board is. 1194 */ 1195 ed_pio_writemem(sc, test_pattern, 16384, sizeof(test_pattern)); 1196 ed_pio_readmem(sc, 16384, test_buffer, sizeof(test_pattern)); 1197 1198 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern))) 1199 return (0); /* not an NE2000 either */ 1200 1201 sc->type = ED_TYPE_NE2000; 1202 sc->type_str = "NE2000"; 1203 } else { 1204 sc->type = ED_TYPE_NE1000; 1205 sc->type_str = "NE1000"; 1206 } 1207 1208 /* 8k of memory plus an additional 8k if 16bit */ 1209 memsize = 8192 + sc->isa16bit * 8192; 1210 1211#if 0 /* probably not useful - NE boards only come two ways */ 1212 /* allow kernel config file overrides */ 1213 if (isa_dev->id_msize) 1214 memsize = isa_dev->id_msize; 1215#endif 1216 1217 sc->mem_size = memsize; 1218 1219 /* NIC memory doesn't start at zero on an NE board */ 1220 /* The start address is tied to the bus width */ 1221 sc->mem_start = (char *) 8192 + sc->isa16bit * 8192; 1222 sc->mem_end = sc->mem_start + memsize; 1223 sc->tx_page_start = memsize / ED_PAGE_SIZE; 1224 1225#ifdef GWETHER 1226 { 1227 int x, i, mstart = 0, msize = 0; 1228 char pbuf0[ED_PAGE_SIZE], pbuf[ED_PAGE_SIZE], tbuf[ED_PAGE_SIZE]; 1229 1230 for (i = 0; i < ED_PAGE_SIZE; i++) 1231 pbuf0[i] = 0; 1232 1233 /* Clear all the memory. */ 1234 for (x = 1; x < 256; x++) 1235 ed_pio_writemem(sc, pbuf0, x * 256, ED_PAGE_SIZE); 1236 1237 /* Search for the start of RAM. */ 1238 for (x = 1; x < 256; x++) { 1239 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE); 1240 if (bcmp(pbuf0, tbuf, ED_PAGE_SIZE) == 0) { 1241 for (i = 0; i < ED_PAGE_SIZE; i++) 1242 pbuf[i] = 255 - x; 1243 ed_pio_writemem(sc, pbuf, x * 256, ED_PAGE_SIZE); 1244 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE); 1245 if (bcmp(pbuf, tbuf, ED_PAGE_SIZE) == 0) { 1246 mstart = x * ED_PAGE_SIZE; 1247 msize = ED_PAGE_SIZE; 1248 break; 1249 } 1250 } 1251 } 1252 1253 if (mstart == 0) { 1254 printf("ed%d: Cannot find start of RAM.\n", unit); 1255 return 0; 1256 } 1257 /* Search for the start of RAM. */ 1258 for (x = (mstart / ED_PAGE_SIZE) + 1; x < 256; x++) { 1259 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE); 1260 if (bcmp(pbuf0, tbuf, ED_PAGE_SIZE) == 0) { 1261 for (i = 0; i < ED_PAGE_SIZE; i++) 1262 pbuf[i] = 255 - x; 1263 ed_pio_writemem(sc, pbuf, x * 256, ED_PAGE_SIZE); 1264 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE); 1265 if (bcmp(pbuf, tbuf, ED_PAGE_SIZE) == 0) 1266 msize += ED_PAGE_SIZE; 1267 else { 1268 break; 1269 } 1270 } else { 1271 break; 1272 } 1273 } 1274 1275 if (msize == 0) { 1276 printf("ed%d: Cannot find any RAM, start : %d, x = %d.\n", unit, mstart, x); 1277 return 0; 1278 } 1279 printf("ed%d: RAM start at %d, size : %d.\n", unit, mstart, msize); 1280 1281 sc->mem_size = msize; 1282 sc->mem_start = (char *) mstart; 1283 sc->mem_end = (char *) (msize + mstart); 1284 sc->tx_page_start = mstart / ED_PAGE_SIZE; 1285 } 1286#endif /* GWETHER */ 1287 1288 /* 1289 * Use one xmit buffer if < 16k, two buffers otherwise (if not told 1290 * otherwise). 1291 */ 1292 if ((memsize < 16384) || (flags & ED_FLAGS_NO_MULTI_BUFFERING)) 1293 sc->txb_cnt = 1; 1294 else 1295 sc->txb_cnt = 2; 1296 1297 sc->rec_page_start = sc->tx_page_start + sc->txb_cnt * ED_TXBUF_SIZE; 1298 sc->rec_page_stop = sc->tx_page_start + memsize / ED_PAGE_SIZE; 1299 1300 sc->mem_ring = sc->mem_start + sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE; 1301 1302 ed_pio_readmem(sc, 0, romdata, 16); 1303 for (n = 0; n < ETHER_ADDR_LEN; n++) 1304 sc->arpcom.ac_enaddr[n] = romdata[n * (sc->isa16bit + 1)]; 1305 1306#ifdef GWETHER 1307 if (sc->arpcom.ac_enaddr[2] == 0x86) { 1308 sc->type_str = "Gateway AT"; 1309 } 1310#endif /* GWETHER */ 1311 1312 /* clear any pending interrupts that might have occurred above */ 1313 outb(sc->nic_addr + ED_P0_ISR, 0xff); 1314 1315 return (ED_NOVELL_IO_PORTS); 1316} 1317 1318static int 1319ed_probe_Novell(isa_dev) 1320 struct isa_device *isa_dev; 1321{ 1322 struct ed_softc *sc = &ed_softc[isa_dev->id_unit]; 1323 1324 isa_dev->id_maddr = 0; 1325 return ed_probe_Novell_generic(sc, isa_dev->id_iobase, 1326 isa_dev->id_unit, isa_dev->id_flags); 1327} 1328 1329#if NCRD > 0 1330 1331/* 1332 * Probe framework for pccards. Replicates the standard framework, 1333 * minus the pccard driver registration and ignores the ether address 1334 * supplied (from the CIS), relying on the probe to find it instead. 1335 */ 1336static int 1337ed_probe_pccard(isa_dev, ether) 1338 struct isa_device *isa_dev; 1339 u_char *ether; 1340{ 1341 int nports; 1342 1343 nports = ed_probe_WD80x3(isa_dev); 1344 if (nports) 1345 return (nports); 1346 1347 nports = ed_probe_Novell(isa_dev); 1348 if (nports) 1349 return (nports); 1350 1351 return (0); 1352} 1353 1354#endif /* NCRD > 0 */ 1355 1356#define ED_HPP_TEST_SIZE 16 1357 1358/* 1359 * Probe and vendor specific initialization for the HP PC Lan+ Cards. 1360 * (HP Part nos: 27247B and 27252A). 1361 * 1362 * The card has an asic wrapper around a DS8390 core. The asic handles 1363 * host accesses and offers both standard register IO and memory mapped 1364 * IO. Memory mapped I/O allows better performance at the expense of greater 1365 * chance of an incompatibility with existing ISA cards. 1366 * 1367 * The card has a few caveats: it isn't tolerant of byte wide accesses, only 1368 * short (16 bit) or word (32 bit) accesses are allowed. Some card revisions 1369 * don't allow 32 bit accesses; these are indicated by a bit in the software 1370 * ID register (see if_edreg.h). 1371 * 1372 * Other caveats are: we should read the MAC address only when the card 1373 * is inactive. 1374 * 1375 * For more information; please consult the CRYNWR packet driver. 1376 * 1377 * The AUI port is turned on using the "link2" option on the ifconfig 1378 * command line. 1379 */ 1380static int 1381ed_probe_HP_pclanp(isa_dev) 1382 struct isa_device *isa_dev; 1383{ 1384 struct ed_softc *sc = &ed_softc[isa_dev->id_unit]; 1385 int n; /* temp var */ 1386 int memsize; /* mem on board */ 1387 u_char checksum; /* checksum of board address */ 1388 u_char irq; /* board configured IRQ */ 1389 char test_pattern[ED_HPP_TEST_SIZE]; /* read/write areas for */ 1390 char test_buffer[ED_HPP_TEST_SIZE]; /* probing card */ 1391 1392 1393 /* Fill in basic information */ 1394 sc->asic_addr = isa_dev->id_iobase + ED_HPP_ASIC_OFFSET; 1395 sc->nic_addr = isa_dev->id_iobase + ED_HPP_NIC_OFFSET; 1396 sc->is790 = 0; 1397 sc->isa16bit = 0; /* the 8390 core needs to be in byte mode */ 1398 1399 /* 1400 * Look for the HP PCLAN+ signature: "0x50,0x48,0x00,0x53" 1401 */ 1402 1403 if ((inb(sc->asic_addr + ED_HPP_ID) != 0x50) || 1404 (inb(sc->asic_addr + ED_HPP_ID + 1) != 0x48) || 1405 ((inb(sc->asic_addr + ED_HPP_ID + 2) & 0xF0) != 0) || 1406 (inb(sc->asic_addr + ED_HPP_ID + 3) != 0x53)) 1407 return 0; 1408 1409 /* 1410 * Read the MAC address and verify checksum on the address. 1411 */ 1412 1413 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_MAC); 1414 for (n = 0, checksum = 0; n < ETHER_ADDR_LEN; n++) 1415 checksum += (sc->arpcom.ac_enaddr[n] = 1416 inb(sc->asic_addr + ED_HPP_MAC_ADDR + n)); 1417 1418 checksum += inb(sc->asic_addr + ED_HPP_MAC_ADDR + ETHER_ADDR_LEN); 1419 1420 if (checksum != 0xFF) 1421 return 0; 1422 1423 /* 1424 * Verify that the software model number is 0. 1425 */ 1426 1427 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_ID); 1428 if (((sc->hpp_id = inw(sc->asic_addr + ED_HPP_PAGE_4)) & 1429 ED_HPP_ID_SOFT_MODEL_MASK) != 0x0000) 1430 return 0; 1431 1432 /* 1433 * Read in and save the current options configured on card. 1434 */ 1435 1436 sc->hpp_options = inw(sc->asic_addr + ED_HPP_OPTION); 1437 1438 sc->hpp_options |= (ED_HPP_OPTION_NIC_RESET | 1439 ED_HPP_OPTION_CHIP_RESET | 1440 ED_HPP_OPTION_ENABLE_IRQ); 1441 1442 /* 1443 * Reset the chip. This requires writing to the option register 1444 * so take care to preserve the other bits. 1445 */ 1446 1447 outw(sc->asic_addr + ED_HPP_OPTION, 1448 (sc->hpp_options & ~(ED_HPP_OPTION_NIC_RESET | 1449 ED_HPP_OPTION_CHIP_RESET))); 1450 1451 DELAY(5000); /* wait for chip reset to complete */ 1452 1453 outw(sc->asic_addr + ED_HPP_OPTION, 1454 (sc->hpp_options | (ED_HPP_OPTION_NIC_RESET | 1455 ED_HPP_OPTION_CHIP_RESET | 1456 ED_HPP_OPTION_ENABLE_IRQ))); 1457 1458 DELAY(5000); 1459 1460 if (!(inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RST)) 1461 return 0; /* reset did not complete */ 1462 1463 /* 1464 * Read out configuration information. 1465 */ 1466 1467 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_HW); 1468 1469 irq = inb(sc->asic_addr + ED_HPP_HW_IRQ); 1470 1471 /* 1472 * Check for impossible IRQ. 1473 */ 1474 1475 if (irq >= (sizeof(ed_hpp_intr_mask) / sizeof(ed_hpp_intr_mask[0]))) 1476 return 0; 1477 1478 /* 1479 * If the kernel IRQ was specified with a '?' use the cards idea 1480 * of the IRQ. If the kernel IRQ was explicitly specified, it 1481 * should match that of the hardware. 1482 */ 1483 1484 if (isa_dev->id_irq <= 0) 1485 isa_dev->id_irq = ed_hpp_intr_mask[irq]; 1486 else if (isa_dev->id_irq != ed_hpp_intr_mask[irq]) 1487 return 0; 1488 1489 /* 1490 * Fill in softconfig info. 1491 */ 1492 1493 sc->vendor = ED_VENDOR_HP; 1494 sc->type = ED_TYPE_HP_PCLANPLUS; 1495 sc->type_str = "HP-PCLAN+"; 1496 1497 sc->mem_shared = 0; /* we DON'T have dual ported RAM */ 1498 sc->mem_start = 0; /* we use offsets inside the card RAM */ 1499 1500 sc->hpp_mem_start = NULL;/* no memory mapped I/O by default */ 1501 1502 /* 1503 * Check if memory mapping of the I/O registers possible. 1504 */ 1505 1506 if (sc->hpp_options & ED_HPP_OPTION_MEM_ENABLE) 1507 { 1508 u_long mem_addr; 1509 1510 /* 1511 * determine the memory address from the board. 1512 */ 1513 1514 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_HW); 1515 mem_addr = (inw(sc->asic_addr + ED_HPP_HW_MEM_MAP) << 8); 1516 1517 /* 1518 * Check that the kernel specified start of memory and 1519 * hardware's idea of it match. 1520 */ 1521 1522 if (mem_addr != kvtop(isa_dev->id_maddr)) 1523 return 0; 1524 1525 sc->hpp_mem_start = isa_dev->id_maddr; 1526 } 1527 1528 /* 1529 * The board has 32KB of memory. Is there a way to determine 1530 * this programmatically? 1531 */ 1532 1533 memsize = 32768; 1534 1535 /* 1536 * Fill in the rest of the soft config structure. 1537 */ 1538 1539 /* 1540 * The transmit page index. 1541 */ 1542 1543 sc->tx_page_start = ED_HPP_TX_PAGE_OFFSET; 1544 1545 if (isa_dev->id_flags & ED_FLAGS_NO_MULTI_BUFFERING) 1546 sc->txb_cnt = 1; 1547 else 1548 sc->txb_cnt = 2; 1549 1550 /* 1551 * Memory description 1552 */ 1553 1554 sc->mem_size = memsize; 1555 sc->mem_ring = sc->mem_start + 1556 (sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE); 1557 sc->mem_end = sc->mem_start + sc->mem_size; 1558 1559 /* 1560 * Receive area starts after the transmit area and 1561 * continues till the end of memory. 1562 */ 1563 1564 sc->rec_page_start = sc->tx_page_start + 1565 (sc->txb_cnt * ED_TXBUF_SIZE); 1566 sc->rec_page_stop = (sc->mem_size / ED_PAGE_SIZE); 1567 1568 1569 sc->cr_proto = 0; /* value works */ 1570 1571 /* 1572 * Set the wrap registers for string I/O reads. 1573 */ 1574 1575 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_HW); 1576 outw(sc->asic_addr + ED_HPP_HW_WRAP, 1577 ((sc->rec_page_start / ED_PAGE_SIZE) | 1578 (((sc->rec_page_stop / ED_PAGE_SIZE) - 1) << 8))); 1579 1580 /* 1581 * Reset the register page to normal operation. 1582 */ 1583 1584 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_PERF); 1585 1586 /* 1587 * Verify that we can read/write from adapter memory. 1588 * Create test pattern. 1589 */ 1590 1591 for (n = 0; n < ED_HPP_TEST_SIZE; n++) 1592 { 1593 test_pattern[n] = (n*n) ^ ~n; 1594 } 1595 1596#undef ED_HPP_TEST_SIZE 1597 1598 /* 1599 * Check that the memory is accessible thru the I/O ports. 1600 * Write out the contents of "test_pattern", read back 1601 * into "test_buffer" and compare the two for any 1602 * mismatch. 1603 */ 1604 1605 for (n = 0; n < (32768 / ED_PAGE_SIZE); n ++) { 1606 1607 ed_pio_writemem(sc, test_pattern, (n * ED_PAGE_SIZE), 1608 sizeof(test_pattern)); 1609 ed_pio_readmem(sc, (n * ED_PAGE_SIZE), 1610 test_buffer, sizeof(test_pattern)); 1611 1612 if (bcmp(test_pattern, test_buffer, 1613 sizeof(test_pattern))) 1614 return 0; 1615 } 1616 1617 return (ED_HPP_IO_PORTS); 1618 1619} 1620 1621/* 1622 * HP PC Lan+ : Set the physical link to use AUI or TP/TL. 1623 */ 1624 1625void 1626ed_hpp_set_physical_link(struct ed_softc *sc) 1627{ 1628 struct ifnet *ifp = &sc->arpcom.ac_if; 1629 int lan_page; 1630 1631 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_LAN); 1632 lan_page = inw(sc->asic_addr + ED_HPP_PAGE_0); 1633 1634 if (ifp->if_flags & IFF_ALTPHYS) { 1635 1636 /* 1637 * Use the AUI port. 1638 */ 1639 1640 lan_page |= ED_HPP_LAN_AUI; 1641 1642 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_LAN); 1643 outw(sc->asic_addr + ED_HPP_PAGE_0, lan_page); 1644 1645 1646 } else { 1647 1648 /* 1649 * Use the ThinLan interface 1650 */ 1651 1652 lan_page &= ~ED_HPP_LAN_AUI; 1653 1654 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_LAN); 1655 outw(sc->asic_addr + ED_HPP_PAGE_0, lan_page); 1656 1657 } 1658 1659 /* 1660 * Wait for the lan card to re-initialize itself 1661 */ 1662 1663 DELAY(150000); /* wait 150 ms */ 1664 1665 /* 1666 * Restore normal pages. 1667 */ 1668 1669 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_PERF); 1670 1671} 1672 1673 1674/* 1675 * Install interface into kernel networking data structures 1676 */ 1677static int 1678ed_attach(sc, unit, flags) 1679 struct ed_softc *sc; 1680 int unit; 1681 int flags; 1682{ 1683 struct ifnet *ifp = &sc->arpcom.ac_if; 1684 1685 /* 1686 * Set interface to stopped condition (reset) 1687 */ 1688 ed_stop(sc); 1689 1690 if (!ifp->if_name) { 1691 /* 1692 * Initialize ifnet structure 1693 */ 1694 ifp->if_softc = sc; 1695 ifp->if_unit = unit; 1696 ifp->if_name = "ed"; 1697 ifp->if_output = ether_output; 1698 ifp->if_start = ed_start; 1699 ifp->if_ioctl = ed_ioctl; 1700 ifp->if_watchdog = ed_watchdog; 1701 ifp->if_init = ed_init; 1702 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 1703 ifp->if_linkmib = &sc->mibdata; 1704 ifp->if_linkmiblen = sizeof sc->mibdata; 1705 /* 1706 * XXX - should do a better job. 1707 */ 1708 if (sc->is790) 1709 sc->mibdata.dot3StatsEtherChipSet = 1710 DOT3CHIPSET(dot3VendorWesternDigital, 1711 dot3ChipSetWesternDigital83C790); 1712 else 1713 sc->mibdata.dot3StatsEtherChipSet = 1714 DOT3CHIPSET(dot3VendorNational, 1715 dot3ChipSetNational8390); 1716 sc->mibdata.dot3Compliance = DOT3COMPLIANCE_COLLS; 1717 1718 /* 1719 * Set default state for ALTPHYS flag (used to disable the 1720 * tranceiver for AUI operation), based on compile-time 1721 * config option. 1722 */ 1723 if (flags & ED_FLAGS_DISABLE_TRANCEIVER) 1724 ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX | 1725 IFF_MULTICAST | IFF_ALTPHYS); 1726 else 1727 ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX | 1728 IFF_MULTICAST); 1729 1730 /* 1731 * Attach the interface 1732 */ 1733 if_attach(ifp); 1734 ether_ifattach(ifp); 1735 } 1736 /* device attach does transition from UNCONFIGURED to IDLE state */ 1737 1738 /* 1739 * Print additional info when attached 1740 */ 1741 printf("%s%d: address %6D, ", ifp->if_name, ifp->if_unit, 1742 sc->arpcom.ac_enaddr, ":"); 1743 1744 if (sc->type_str && (*sc->type_str != 0)) 1745 printf("type %s ", sc->type_str); 1746 else 1747 printf("type unknown (0x%x) ", sc->type); 1748 1749 if (sc->vendor == ED_VENDOR_HP) 1750 printf("(%s %s IO)", (sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS) ? 1751 "16-bit" : "32-bit", 1752 sc->hpp_mem_start ? "memory mapped" : "regular"); 1753 else 1754 printf("%s ", sc->isa16bit ? "(16 bit)" : "(8 bit)"); 1755 1756 printf("%s\n", (((sc->vendor == ED_VENDOR_3COM) || 1757 (sc->vendor == ED_VENDOR_HP)) && 1758 (ifp->if_flags & IFF_ALTPHYS)) ? " tranceiver disabled" : ""); 1759 1760 /* 1761 * If BPF is in the kernel, call the attach for it 1762 */ 1763#if NBPFILTER > 0 1764 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header)); 1765#endif 1766 return 1; 1767} 1768 1769static int 1770ed_attach_isa(isa_dev) 1771 struct isa_device *isa_dev; 1772{ 1773 int unit = isa_dev->id_unit; 1774 struct ed_softc *sc = &ed_softc[unit]; 1775 int flags = isa_dev->id_flags; 1776 1777 return ed_attach(sc, unit, flags); 1778} 1779 1780#if NPCI > 0 1781void * 1782ed_attach_NE2000_pci(unit, port) 1783 int unit; 1784 int port; 1785{ 1786 struct ed_softc *sc = malloc(sizeof *sc, M_DEVBUF, M_NOWAIT); 1787 int isa_flags = 0; 1788 1789 if (!sc) 1790 return sc; 1791 1792 bzero(sc, sizeof *sc); 1793 if (ed_probe_Novell_generic(sc, port, unit, isa_flags) == 0 1794 || ed_attach(sc, unit, isa_flags) == 0) { 1795 free(sc, M_DEVBUF); 1796 return NULL; 1797 } 1798 return sc; 1799} 1800#endif 1801 1802/* 1803 * Reset interface. 1804 */ 1805static void 1806ed_reset(ifp) 1807 struct ifnet *ifp; 1808{ 1809 struct ed_softc *sc = ifp->if_softc; 1810 int s; 1811 1812 if (sc->gone) 1813 return; 1814 s = splimp(); 1815 1816 /* 1817 * Stop interface and re-initialize. 1818 */ 1819 ed_stop(sc); 1820 ed_init(sc); 1821 1822 (void) splx(s); 1823} 1824 1825/* 1826 * Take interface offline. 1827 */ 1828static void 1829ed_stop(sc) 1830 struct ed_softc *sc; 1831{ 1832 int n = 5000; 1833 1834 if (sc->gone) 1835 return; 1836 /* 1837 * Stop everything on the interface, and select page 0 registers. 1838 */ 1839 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP); 1840 1841 /* 1842 * Wait for interface to enter stopped state, but limit # of checks to 1843 * 'n' (about 5ms). It shouldn't even take 5us on modern DS8390's, but 1844 * just in case it's an old one. 1845 */ 1846 while (((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RST) == 0) && --n); 1847} 1848 1849/* 1850 * Device timeout/watchdog routine. Entered if the device neglects to 1851 * generate an interrupt after a transmit has been started on it. 1852 */ 1853static void 1854ed_watchdog(ifp) 1855 struct ifnet *ifp; 1856{ 1857 struct ed_softc *sc = ifp->if_softc; 1858 1859 if (sc->gone) 1860 return; 1861 log(LOG_ERR, "ed%d: device timeout\n", ifp->if_unit); 1862 ifp->if_oerrors++; 1863 1864 ed_reset(ifp); 1865} 1866 1867/* 1868 * Initialize device. 1869 */ 1870static void 1871ed_init(xsc) 1872 void *xsc; 1873{ 1874 struct ed_softc *sc = xsc; 1875 struct ifnet *ifp = &sc->arpcom.ac_if; 1876 int i, s; 1877 1878 if (sc->gone) 1879 return; 1880 1881 /* address not known */ 1882 if (TAILQ_EMPTY(&ifp->if_addrhead)) /* unlikely? XXX */ 1883 return; 1884 1885 /* 1886 * Initialize the NIC in the exact order outlined in the NS manual. 1887 * This init procedure is "mandatory"...don't change what or when 1888 * things happen. 1889 */ 1890 s = splimp(); 1891 1892 /* reset transmitter flags */ 1893 sc->xmit_busy = 0; 1894 ifp->if_timer = 0; 1895 1896 sc->txb_inuse = 0; 1897 sc->txb_new = 0; 1898 sc->txb_next_tx = 0; 1899 1900 /* This variable is used below - don't move this assignment */ 1901 sc->next_packet = sc->rec_page_start + 1; 1902 1903 /* 1904 * Set interface for page 0, Remote DMA complete, Stopped 1905 */ 1906 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP); 1907 1908 if (sc->isa16bit) { 1909 1910 /* 1911 * Set FIFO threshold to 8, No auto-init Remote DMA, byte 1912 * order=80x86, word-wide DMA xfers, 1913 */ 1914 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1 | ED_DCR_WTS | ED_DCR_LS); 1915 } else { 1916 1917 /* 1918 * Same as above, but byte-wide DMA xfers 1919 */ 1920 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS); 1921 } 1922 1923 /* 1924 * Clear Remote Byte Count Registers 1925 */ 1926 outb(sc->nic_addr + ED_P0_RBCR0, 0); 1927 outb(sc->nic_addr + ED_P0_RBCR1, 0); 1928 1929 /* 1930 * For the moment, don't store incoming packets in memory. 1931 */ 1932 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_MON); 1933 1934 /* 1935 * Place NIC in internal loopback mode 1936 */ 1937 outb(sc->nic_addr + ED_P0_TCR, ED_TCR_LB0); 1938 1939 /* 1940 * Initialize transmit/receive (ring-buffer) Page Start 1941 */ 1942 outb(sc->nic_addr + ED_P0_TPSR, sc->tx_page_start); 1943 outb(sc->nic_addr + ED_P0_PSTART, sc->rec_page_start); 1944 /* Set lower bits of byte addressable framing to 0 */ 1945 if (sc->is790) 1946 outb(sc->nic_addr + 0x09, 0); 1947 1948 /* 1949 * Initialize Receiver (ring-buffer) Page Stop and Boundry 1950 */ 1951 outb(sc->nic_addr + ED_P0_PSTOP, sc->rec_page_stop); 1952 outb(sc->nic_addr + ED_P0_BNRY, sc->rec_page_start); 1953 1954 /* 1955 * Clear all interrupts. A '1' in each bit position clears the 1956 * corresponding flag. 1957 */ 1958 outb(sc->nic_addr + ED_P0_ISR, 0xff); 1959 1960 /* 1961 * Enable the following interrupts: receive/transmit complete, 1962 * receive/transmit error, and Receiver OverWrite. 1963 * 1964 * Counter overflow and Remote DMA complete are *not* enabled. 1965 */ 1966 outb(sc->nic_addr + ED_P0_IMR, 1967 ED_IMR_PRXE | ED_IMR_PTXE | ED_IMR_RXEE | ED_IMR_TXEE | ED_IMR_OVWE); 1968 1969 /* 1970 * Program Command Register for page 1 1971 */ 1972 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP); 1973 1974 /* 1975 * Copy out our station address 1976 */ 1977 for (i = 0; i < ETHER_ADDR_LEN; ++i) 1978 outb(sc->nic_addr + ED_P1_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1979 1980 /* 1981 * Set Current Page pointer to next_packet (initialized above) 1982 */ 1983 outb(sc->nic_addr + ED_P1_CURR, sc->next_packet); 1984 1985 /* 1986 * Program Receiver Configuration Register and multicast filter. CR is 1987 * set to page 0 on return. 1988 */ 1989 ed_setrcr(sc); 1990 1991 /* 1992 * Take interface out of loopback 1993 */ 1994 outb(sc->nic_addr + ED_P0_TCR, 0); 1995 1996 /* 1997 * If this is a 3Com board, the tranceiver must be software enabled 1998 * (there is no settable hardware default). 1999 */ 2000 if (sc->vendor == ED_VENDOR_3COM) { 2001 if (ifp->if_flags & IFF_ALTPHYS) { 2002 outb(sc->asic_addr + ED_3COM_CR, 0); 2003 } else { 2004 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL); 2005 } 2006 } 2007 2008 /* 2009 * Set 'running' flag, and clear output active flag. 2010 */ 2011 ifp->if_flags |= IFF_RUNNING; 2012 ifp->if_flags &= ~IFF_OACTIVE; 2013 2014 /* 2015 * ...and attempt to start output 2016 */ 2017 ed_start(ifp); 2018 2019 (void) splx(s); 2020} 2021 2022/* 2023 * This routine actually starts the transmission on the interface 2024 */ 2025static inline void 2026ed_xmit(sc) 2027 struct ed_softc *sc; 2028{ 2029 struct ifnet *ifp = (struct ifnet *)sc; 2030 unsigned short len; 2031 2032 if (sc->gone) 2033 return; 2034 len = sc->txb_len[sc->txb_next_tx]; 2035 2036 /* 2037 * Set NIC for page 0 register access 2038 */ 2039 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA); 2040 2041 /* 2042 * Set TX buffer start page 2043 */ 2044 outb(sc->nic_addr + ED_P0_TPSR, sc->tx_page_start + 2045 sc->txb_next_tx * ED_TXBUF_SIZE); 2046 2047 /* 2048 * Set TX length 2049 */ 2050 outb(sc->nic_addr + ED_P0_TBCR0, len); 2051 outb(sc->nic_addr + ED_P0_TBCR1, len >> 8); 2052 2053 /* 2054 * Set page 0, Remote DMA complete, Transmit Packet, and *Start* 2055 */ 2056 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_TXP | ED_CR_STA); 2057 sc->xmit_busy = 1; 2058 2059 /* 2060 * Point to next transmit buffer slot and wrap if necessary. 2061 */ 2062 sc->txb_next_tx++; 2063 if (sc->txb_next_tx == sc->txb_cnt) 2064 sc->txb_next_tx = 0; 2065 2066 /* 2067 * Set a timer just in case we never hear from the board again 2068 */ 2069 ifp->if_timer = 2; 2070} 2071 2072/* 2073 * Start output on interface. 2074 * We make two assumptions here: 2075 * 1) that the current priority is set to splimp _before_ this code 2076 * is called *and* is returned to the appropriate priority after 2077 * return 2078 * 2) that the IFF_OACTIVE flag is checked before this code is called 2079 * (i.e. that the output part of the interface is idle) 2080 */ 2081static void 2082ed_start(ifp) 2083 struct ifnet *ifp; 2084{ 2085 struct ed_softc *sc = ifp->if_softc; 2086 struct mbuf *m0, *m; 2087 caddr_t buffer; 2088 int len; 2089 2090 if (sc->gone) { 2091 printf("ed_start(%p) GONE\n",ifp); 2092 return; 2093 } 2094outloop: 2095 2096 /* 2097 * First, see if there are buffered packets and an idle transmitter - 2098 * should never happen at this point. 2099 */ 2100 if (sc->txb_inuse && (sc->xmit_busy == 0)) { 2101 printf("ed: packets buffered, but transmitter idle\n"); 2102 ed_xmit(sc); 2103 } 2104 2105 /* 2106 * See if there is room to put another packet in the buffer. 2107 */ 2108 if (sc->txb_inuse == sc->txb_cnt) { 2109 2110 /* 2111 * No room. Indicate this to the outside world and exit. 2112 */ 2113 ifp->if_flags |= IFF_OACTIVE; 2114 return; 2115 } 2116 IF_DEQUEUE(&ifp->if_snd, m); 2117 if (m == 0) { 2118 2119 /* 2120 * We are using the !OACTIVE flag to indicate to the outside 2121 * world that we can accept an additional packet rather than 2122 * that the transmitter is _actually_ active. Indeed, the 2123 * transmitter may be active, but if we haven't filled all the 2124 * buffers with data then we still want to accept more. 2125 */ 2126 ifp->if_flags &= ~IFF_OACTIVE; 2127 return; 2128 } 2129 2130 /* 2131 * Copy the mbuf chain into the transmit buffer 2132 */ 2133 2134 m0 = m; 2135 2136 /* txb_new points to next open buffer slot */ 2137 buffer = sc->mem_start + (sc->txb_new * ED_TXBUF_SIZE * ED_PAGE_SIZE); 2138 2139 if (sc->mem_shared) { 2140 2141 /* 2142 * Special case setup for 16 bit boards... 2143 */ 2144 if (sc->isa16bit) { 2145 switch (sc->vendor) { 2146 2147 /* 2148 * For 16bit 3Com boards (which have 16k of 2149 * memory), we have the xmit buffers in a 2150 * different page of memory ('page 0') - so 2151 * change pages. 2152 */ 2153 case ED_VENDOR_3COM: 2154 outb(sc->asic_addr + ED_3COM_GACFR, 2155 ED_3COM_GACFR_RSEL); 2156 break; 2157 2158 /* 2159 * Enable 16bit access to shared memory on 2160 * WD/SMC boards. 2161 */ 2162 case ED_VENDOR_WD_SMC:{ 2163 outb(sc->asic_addr + ED_WD_LAAR, 2164 sc->wd_laar_proto | ED_WD_LAAR_M16EN); 2165 if (sc->is790) { 2166 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_MENB); 2167 } 2168 break; 2169 } 2170 } 2171 } 2172 for (len = 0; m != 0; m = m->m_next) { 2173 bcopy(mtod(m, caddr_t), buffer, m->m_len); 2174 buffer += m->m_len; 2175 len += m->m_len; 2176 } 2177 2178 /* 2179 * Restore previous shared memory access 2180 */ 2181 if (sc->isa16bit) { 2182 switch (sc->vendor) { 2183 case ED_VENDOR_3COM: 2184 outb(sc->asic_addr + ED_3COM_GACFR, 2185 ED_3COM_GACFR_RSEL | ED_3COM_GACFR_MBS0); 2186 break; 2187 case ED_VENDOR_WD_SMC:{ 2188 if (sc->is790) { 2189 outb(sc->asic_addr + ED_WD_MSR, 0x00); 2190 } 2191 outb(sc->asic_addr + ED_WD_LAAR, 2192 sc->wd_laar_proto & ~ED_WD_LAAR_M16EN); 2193 break; 2194 } 2195 } 2196 } 2197 } else { 2198 len = ed_pio_write_mbufs(sc, m, (int)buffer); 2199 if (len == 0) 2200 goto outloop; 2201 } 2202 2203 sc->txb_len[sc->txb_new] = max(len, (ETHER_MIN_LEN-ETHER_CRC_LEN)); 2204 2205 sc->txb_inuse++; 2206 2207 /* 2208 * Point to next buffer slot and wrap if necessary. 2209 */ 2210 sc->txb_new++; 2211 if (sc->txb_new == sc->txb_cnt) 2212 sc->txb_new = 0; 2213 2214 if (sc->xmit_busy == 0) 2215 ed_xmit(sc); 2216 2217 /* 2218 * Tap off here if there is a bpf listener. 2219 */ 2220#if NBPFILTER > 0 2221 if (ifp->if_bpf) { 2222 bpf_mtap(ifp, m0); 2223 } 2224#endif 2225 2226 m_freem(m0); 2227 2228 /* 2229 * Loop back to the top to possibly buffer more packets 2230 */ 2231 goto outloop; 2232} 2233 2234/* 2235 * Ethernet interface receiver interrupt. 2236 */ 2237static inline void 2238ed_rint(sc) 2239 struct ed_softc *sc; 2240{ 2241 struct ifnet *ifp = &sc->arpcom.ac_if; 2242 u_char boundry; 2243 u_short len; 2244 struct ed_ring packet_hdr; 2245 char *packet_ptr; 2246 2247 if (sc->gone) 2248 return; 2249 2250 /* 2251 * Set NIC to page 1 registers to get 'current' pointer 2252 */ 2253 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA); 2254 2255 /* 2256 * 'sc->next_packet' is the logical beginning of the ring-buffer - 2257 * i.e. it points to where new data has been buffered. The 'CURR' 2258 * (current) register points to the logical end of the ring-buffer - 2259 * i.e. it points to where additional new data will be added. We loop 2260 * here until the logical beginning equals the logical end (or in 2261 * other words, until the ring-buffer is empty). 2262 */ 2263 while (sc->next_packet != inb(sc->nic_addr + ED_P1_CURR)) { 2264 2265 /* get pointer to this buffer's header structure */ 2266 packet_ptr = sc->mem_ring + 2267 (sc->next_packet - sc->rec_page_start) * ED_PAGE_SIZE; 2268 2269 /* 2270 * The byte count includes a 4 byte header that was added by 2271 * the NIC. 2272 */ 2273 if (sc->mem_shared) 2274 packet_hdr = *(struct ed_ring *) packet_ptr; 2275 else 2276 ed_pio_readmem(sc, (int)packet_ptr, (char *) &packet_hdr, 2277 sizeof(packet_hdr)); 2278 len = packet_hdr.count; 2279 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring)) || 2280 len < (ETHER_MIN_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring))) { 2281 /* 2282 * Length is a wild value. There's a good chance that 2283 * this was caused by the NIC being old and buggy. 2284 * The bug is that the length low byte is duplicated in 2285 * the high byte. Try to recalculate the length based on 2286 * the pointer to the next packet. 2287 */ 2288 /* 2289 * NOTE: sc->next_packet is pointing at the current packet. 2290 */ 2291 len &= ED_PAGE_SIZE - 1; /* preserve offset into page */ 2292 if (packet_hdr.next_packet >= sc->next_packet) { 2293 len += (packet_hdr.next_packet - sc->next_packet) * ED_PAGE_SIZE; 2294 } else { 2295 len += ((packet_hdr.next_packet - sc->rec_page_start) + 2296 (sc->rec_page_stop - sc->next_packet)) * ED_PAGE_SIZE; 2297 } 2298 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN 2299 + sizeof(struct ed_ring))) 2300 sc->mibdata.dot3StatsFrameTooLongs++; 2301 } 2302 /* 2303 * Be fairly liberal about what we allow as a "reasonable" length 2304 * so that a [crufty] packet will make it to BPF (and can thus 2305 * be analyzed). Note that all that is really important is that 2306 * we have a length that will fit into one mbuf cluster or less; 2307 * the upper layer protocols can then figure out the length from 2308 * their own length field(s). 2309 */ 2310 if ((len > sizeof(struct ed_ring)) && 2311 (len <= MCLBYTES) && 2312 (packet_hdr.next_packet >= sc->rec_page_start) && 2313 (packet_hdr.next_packet < sc->rec_page_stop)) { 2314 /* 2315 * Go get packet. 2316 */ 2317 ed_get_packet(sc, packet_ptr + sizeof(struct ed_ring), 2318 len - sizeof(struct ed_ring), packet_hdr.rsr & ED_RSR_PHY); 2319 ifp->if_ipackets++; 2320 } else { 2321 /* 2322 * Really BAD. The ring pointers are corrupted. 2323 */ 2324 log(LOG_ERR, 2325 "ed%d: NIC memory corrupt - invalid packet length %d\n", 2326 ifp->if_unit, len); 2327 ifp->if_ierrors++; 2328 ed_reset(ifp); 2329 return; 2330 } 2331 2332 /* 2333 * Update next packet pointer 2334 */ 2335 sc->next_packet = packet_hdr.next_packet; 2336 2337 /* 2338 * Update NIC boundry pointer - being careful to keep it one 2339 * buffer behind. (as recommended by NS databook) 2340 */ 2341 boundry = sc->next_packet - 1; 2342 if (boundry < sc->rec_page_start) 2343 boundry = sc->rec_page_stop - 1; 2344 2345 /* 2346 * Set NIC to page 0 registers to update boundry register 2347 */ 2348 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA); 2349 2350 outb(sc->nic_addr + ED_P0_BNRY, boundry); 2351 2352 /* 2353 * Set NIC to page 1 registers before looping to top (prepare 2354 * to get 'CURR' current pointer) 2355 */ 2356 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA); 2357 } 2358} 2359 2360/* 2361 * Ethernet interface interrupt processor 2362 */ 2363void 2364edintr_sc(sc) 2365 struct ed_softc *sc; 2366{ 2367 struct ifnet *ifp = (struct ifnet *)sc; 2368 u_char isr; 2369 2370 if (sc->gone) 2371 return; 2372 /* 2373 * Set NIC to page 0 registers 2374 */ 2375 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA); 2376 2377 /* 2378 * loop until there are no more new interrupts 2379 */ 2380 while ((isr = inb(sc->nic_addr + ED_P0_ISR)) != 0) { 2381 2382 /* 2383 * reset all the bits that we are 'acknowledging' by writing a 2384 * '1' to each bit position that was set (writing a '1' 2385 * *clears* the bit) 2386 */ 2387 outb(sc->nic_addr + ED_P0_ISR, isr); 2388 2389 /* 2390 * Handle transmitter interrupts. Handle these first because 2391 * the receiver will reset the board under some conditions. 2392 */ 2393 if (isr & (ED_ISR_PTX | ED_ISR_TXE)) { 2394 u_char collisions = inb(sc->nic_addr + ED_P0_NCR) & 0x0f; 2395 2396 /* 2397 * Check for transmit error. If a TX completed with an 2398 * error, we end up throwing the packet away. Really 2399 * the only error that is possible is excessive 2400 * collisions, and in this case it is best to allow 2401 * the automatic mechanisms of TCP to backoff the 2402 * flow. Of course, with UDP we're screwed, but this 2403 * is expected when a network is heavily loaded. 2404 */ 2405 (void) inb(sc->nic_addr + ED_P0_TSR); 2406 if (isr & ED_ISR_TXE) { 2407 u_char tsr; 2408 2409 /* 2410 * Excessive collisions (16) 2411 */ 2412 tsr = inb(sc->nic_addr + ED_P0_TSR); 2413 if ((tsr & ED_TSR_ABT) 2414 && (collisions == 0)) { 2415 2416 /* 2417 * When collisions total 16, the 2418 * P0_NCR will indicate 0, and the 2419 * TSR_ABT is set. 2420 */ 2421 collisions = 16; 2422 sc->mibdata.dot3StatsExcessiveCollisions++; 2423 sc->mibdata.dot3StatsCollFrequencies[15]++; 2424 } 2425 if (tsr & ED_TSR_OWC) 2426 sc->mibdata.dot3StatsLateCollisions++; 2427 if (tsr & ED_TSR_CDH) 2428 sc->mibdata.dot3StatsSQETestErrors++; 2429 if (tsr & ED_TSR_CRS) 2430 sc->mibdata.dot3StatsCarrierSenseErrors++; 2431 if (tsr & ED_TSR_FU) 2432 sc->mibdata.dot3StatsInternalMacTransmitErrors++; 2433 2434 /* 2435 * update output errors counter 2436 */ 2437 ifp->if_oerrors++; 2438 } else { 2439 2440 /* 2441 * Update total number of successfully 2442 * transmitted packets. 2443 */ 2444 ifp->if_opackets++; 2445 } 2446 2447 /* 2448 * reset tx busy and output active flags 2449 */ 2450 sc->xmit_busy = 0; 2451 ifp->if_flags &= ~IFF_OACTIVE; 2452 2453 /* 2454 * clear watchdog timer 2455 */ 2456 ifp->if_timer = 0; 2457 2458 /* 2459 * Add in total number of collisions on last 2460 * transmission. 2461 */ 2462 ifp->if_collisions += collisions; 2463 switch(collisions) { 2464 case 0: 2465 case 16: 2466 break; 2467 case 1: 2468 sc->mibdata.dot3StatsSingleCollisionFrames++; 2469 sc->mibdata.dot3StatsCollFrequencies[0]++; 2470 break; 2471 default: 2472 sc->mibdata.dot3StatsMultipleCollisionFrames++; 2473 sc->mibdata. 2474 dot3StatsCollFrequencies[collisions-1] 2475 ++; 2476 break; 2477 } 2478 2479 /* 2480 * Decrement buffer in-use count if not zero (can only 2481 * be zero if a transmitter interrupt occured while 2482 * not actually transmitting). If data is ready to 2483 * transmit, start it transmitting, otherwise defer 2484 * until after handling receiver 2485 */ 2486 if (sc->txb_inuse && --sc->txb_inuse) 2487 ed_xmit(sc); 2488 } 2489 2490 /* 2491 * Handle receiver interrupts 2492 */ 2493 if (isr & (ED_ISR_PRX | ED_ISR_RXE | ED_ISR_OVW)) { 2494 2495 /* 2496 * Overwrite warning. In order to make sure that a 2497 * lockup of the local DMA hasn't occurred, we reset 2498 * and re-init the NIC. The NSC manual suggests only a 2499 * partial reset/re-init is necessary - but some chips 2500 * seem to want more. The DMA lockup has been seen 2501 * only with early rev chips - Methinks this bug was 2502 * fixed in later revs. -DG 2503 */ 2504 if (isr & ED_ISR_OVW) { 2505 ifp->if_ierrors++; 2506#ifdef DIAGNOSTIC 2507 log(LOG_WARNING, 2508 "ed%d: warning - receiver ring buffer overrun\n", 2509 ifp->if_unit); 2510#endif 2511 2512 /* 2513 * Stop/reset/re-init NIC 2514 */ 2515 ed_reset(ifp); 2516 } else { 2517 2518 /* 2519 * Receiver Error. One or more of: CRC error, 2520 * frame alignment error FIFO overrun, or 2521 * missed packet. 2522 */ 2523 if (isr & ED_ISR_RXE) { 2524 u_char rsr; 2525 rsr = inb(sc->nic_addr + ED_P0_RSR); 2526 if (rsr & ED_RSR_CRC) 2527 sc->mibdata.dot3StatsFCSErrors++; 2528 if (rsr & ED_RSR_FAE) 2529 sc->mibdata.dot3StatsAlignmentErrors++; 2530 if (rsr & ED_RSR_FO) 2531 sc->mibdata.dot3StatsInternalMacReceiveErrors++; 2532 ifp->if_ierrors++; 2533#ifdef ED_DEBUG 2534 printf("ed%d: receive error %x\n", ifp->if_unit, 2535 inb(sc->nic_addr + ED_P0_RSR)); 2536#endif 2537 } 2538 2539 /* 2540 * Go get the packet(s) XXX - Doing this on an 2541 * error is dubious because there shouldn't be 2542 * any data to get (we've configured the 2543 * interface to not accept packets with 2544 * errors). 2545 */ 2546 2547 /* 2548 * Enable 16bit access to shared memory first 2549 * on WD/SMC boards. 2550 */ 2551 if (sc->isa16bit && 2552 (sc->vendor == ED_VENDOR_WD_SMC)) { 2553 2554 outb(sc->asic_addr + ED_WD_LAAR, 2555 sc->wd_laar_proto | ED_WD_LAAR_M16EN); 2556 if (sc->is790) { 2557 outb(sc->asic_addr + ED_WD_MSR, 2558 ED_WD_MSR_MENB); 2559 } 2560 } 2561 ed_rint(sc); 2562 2563 /* disable 16bit access */ 2564 if (sc->isa16bit && 2565 (sc->vendor == ED_VENDOR_WD_SMC)) { 2566 2567 if (sc->is790) { 2568 outb(sc->asic_addr + ED_WD_MSR, 0x00); 2569 } 2570 outb(sc->asic_addr + ED_WD_LAAR, 2571 sc->wd_laar_proto & ~ED_WD_LAAR_M16EN); 2572 } 2573 } 2574 } 2575 2576 /* 2577 * If it looks like the transmitter can take more data, 2578 * attempt to start output on the interface. This is done 2579 * after handling the receiver to give the receiver priority. 2580 */ 2581 if ((ifp->if_flags & IFF_OACTIVE) == 0) 2582 ed_start(ifp); 2583 2584 /* 2585 * return NIC CR to standard state: page 0, remote DMA 2586 * complete, start (toggling the TXP bit off, even if was just 2587 * set in the transmit routine, is *okay* - it is 'edge' 2588 * triggered from low to high) 2589 */ 2590 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA); 2591 2592 /* 2593 * If the Network Talley Counters overflow, read them to reset 2594 * them. It appears that old 8390's won't clear the ISR flag 2595 * otherwise - resulting in an infinite loop. 2596 */ 2597 if (isr & ED_ISR_CNT) { 2598 (void) inb(sc->nic_addr + ED_P0_CNTR0); 2599 (void) inb(sc->nic_addr + ED_P0_CNTR1); 2600 (void) inb(sc->nic_addr + ED_P0_CNTR2); 2601 } 2602 } 2603} 2604 2605void 2606edintr(unit) 2607 int unit; 2608{ 2609 edintr_sc (&ed_softc[unit]); 2610} 2611 2612/* 2613 * Process an ioctl request. This code needs some work - it looks 2614 * pretty ugly. 2615 */ 2616static int 2617ed_ioctl(ifp, command, data) 2618 register struct ifnet *ifp; 2619 int command; 2620 caddr_t data; 2621{ 2622 struct ed_softc *sc = ifp->if_softc; 2623 struct ifreq *ifr = (struct ifreq *) data; 2624 int s, error = 0; 2625 2626 if (sc->gone) { 2627 ifp->if_flags &= ~IFF_RUNNING; 2628 return ENXIO; 2629 } 2630 s = splimp(); 2631 2632 switch (command) { 2633 2634 case SIOCSIFADDR: 2635 case SIOCGIFADDR: 2636 case SIOCSIFMTU: 2637 error = ether_ioctl(ifp, command, data); 2638 break; 2639 2640 case SIOCSIFFLAGS: 2641 2642 /* 2643 * If the interface is marked up and stopped, then start it. 2644 * If it is marked down and running, then stop it. 2645 */ 2646 if (ifp->if_flags & IFF_UP) { 2647 if ((ifp->if_flags & IFF_RUNNING) == 0) 2648 ed_init(sc); 2649 } else { 2650 if (ifp->if_flags & IFF_RUNNING) { 2651 ed_stop(sc); 2652 ifp->if_flags &= ~IFF_RUNNING; 2653 } 2654 } 2655 2656#if NBPFILTER > 0 2657 2658 /* 2659 * Promiscuous flag may have changed, so reprogram the RCR. 2660 */ 2661 ed_setrcr(sc); 2662#endif 2663 2664 /* 2665 * An unfortunate hack to provide the (required) software 2666 * control of the tranceiver for 3Com boards. The ALTPHYS flag 2667 * disables the tranceiver if set. 2668 */ 2669 if (sc->vendor == ED_VENDOR_3COM) { 2670 if (ifp->if_flags & IFF_ALTPHYS) { 2671 outb(sc->asic_addr + ED_3COM_CR, 0); 2672 } else { 2673 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL); 2674 } 2675 } else if (sc->vendor == ED_VENDOR_HP) 2676 ed_hpp_set_physical_link(sc); 2677 break; 2678 2679 case SIOCADDMULTI: 2680 case SIOCDELMULTI: 2681 /* 2682 * Multicast list has changed; set the hardware filter 2683 * accordingly. 2684 */ 2685 ed_setrcr(sc); 2686 error = 0; 2687 break; 2688 2689 default: 2690 error = EINVAL; 2691 } 2692 (void) splx(s); 2693 return (error); 2694} 2695 2696/* 2697 * Given a source and destination address, copy 'amount' of a packet from 2698 * the ring buffer into a linear destination buffer. Takes into account 2699 * ring-wrap. 2700 */ 2701static inline char * 2702ed_ring_copy(sc, src, dst, amount) 2703 struct ed_softc *sc; 2704 char *src; 2705 char *dst; 2706 u_short amount; 2707{ 2708 u_short tmp_amount; 2709 2710 /* does copy wrap to lower addr in ring buffer? */ 2711 if (src + amount > sc->mem_end) { 2712 tmp_amount = sc->mem_end - src; 2713 2714 /* copy amount up to end of NIC memory */ 2715 if (sc->mem_shared) 2716 bcopy(src, dst, tmp_amount); 2717 else 2718 ed_pio_readmem(sc, (int)src, dst, tmp_amount); 2719 2720 amount -= tmp_amount; 2721 src = sc->mem_ring; 2722 dst += tmp_amount; 2723 } 2724 if (sc->mem_shared) 2725 bcopy(src, dst, amount); 2726 else 2727 ed_pio_readmem(sc, (int)src, dst, amount); 2728 2729 return (src + amount); 2730} 2731 2732/* 2733 * Retreive packet from shared memory and send to the next level up via 2734 * ether_input(). If there is a BPF listener, give a copy to BPF, too. 2735 */ 2736static void 2737ed_get_packet(sc, buf, len, multicast) 2738 struct ed_softc *sc; 2739 char *buf; 2740 u_short len; 2741 int multicast; 2742{ 2743 struct ether_header *eh; 2744 struct mbuf *m; 2745 2746 /* Allocate a header mbuf */ 2747 MGETHDR(m, M_DONTWAIT, MT_DATA); 2748 if (m == NULL) 2749 return; 2750 m->m_pkthdr.rcvif = &sc->arpcom.ac_if; 2751 m->m_pkthdr.len = m->m_len = len; 2752 2753 /* 2754 * We always put the received packet in a single buffer - 2755 * either with just an mbuf header or in a cluster attached 2756 * to the header. The +2 is to compensate for the alignment 2757 * fixup below. 2758 */ 2759 if ((len + 2) > MHLEN) { 2760 /* Attach an mbuf cluster */ 2761 MCLGET(m, M_DONTWAIT); 2762 2763 /* Insist on getting a cluster */ 2764 if ((m->m_flags & M_EXT) == 0) { 2765 m_freem(m); 2766 return; 2767 } 2768 } 2769 2770 /* 2771 * The +2 is to longword align the start of the real packet. 2772 * This is important for NFS. 2773 */ 2774 m->m_data += 2; 2775 eh = mtod(m, struct ether_header *); 2776 2777 /* 2778 * Get packet, including link layer address, from interface. 2779 */ 2780 ed_ring_copy(sc, buf, (char *)eh, len); 2781 2782#if NBPFILTER > 0 2783 2784 /* 2785 * Check if there's a BPF listener on this interface. If so, hand off 2786 * the raw packet to bpf. 2787 */ 2788 if (sc->arpcom.ac_if.if_bpf) { 2789 bpf_mtap(&sc->arpcom.ac_if, m); 2790 2791 /* 2792 * Note that the interface cannot be in promiscuous mode if 2793 * there are no BPF listeners. And if we are in promiscuous 2794 * mode, we have to check if this packet is really ours. 2795 */ 2796 if ((sc->arpcom.ac_if.if_flags & IFF_PROMISC) && 2797 bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr, 2798 sizeof(eh->ether_dhost)) != 0 && multicast == 0) { 2799 m_freem(m); 2800 return; 2801 } 2802 } 2803#endif 2804 2805 /* 2806 * Remove link layer address. 2807 */ 2808 m->m_pkthdr.len = m->m_len = len - sizeof(struct ether_header); 2809 m->m_data += sizeof(struct ether_header); 2810 2811 ether_input(&sc->arpcom.ac_if, eh, m); 2812 return; 2813} 2814 2815/* 2816 * Supporting routines 2817 */ 2818 2819/* 2820 * Given a NIC memory source address and a host memory destination 2821 * address, copy 'amount' from NIC to host using Programmed I/O. 2822 * The 'amount' is rounded up to a word - okay as long as mbufs 2823 * are word sized. 2824 * This routine is currently Novell-specific. 2825 */ 2826static void 2827ed_pio_readmem(sc, src, dst, amount) 2828 struct ed_softc *sc; 2829 int src; 2830 unsigned char *dst; 2831 unsigned short amount; 2832{ 2833 /* HP cards need special handling */ 2834 if (sc->vendor == ED_VENDOR_HP && sc->type == ED_TYPE_HP_PCLANPLUS) { 2835 ed_hpp_readmem(sc, src, dst, amount); 2836 return; 2837 } 2838 2839 /* Regular Novell cards */ 2840 /* select page 0 registers */ 2841 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STA); 2842 2843 /* round up to a word */ 2844 if (amount & 1) 2845 ++amount; 2846 2847 /* set up DMA byte count */ 2848 outb(sc->nic_addr + ED_P0_RBCR0, amount); 2849 outb(sc->nic_addr + ED_P0_RBCR1, amount >> 8); 2850 2851 /* set up source address in NIC mem */ 2852 outb(sc->nic_addr + ED_P0_RSAR0, src); 2853 outb(sc->nic_addr + ED_P0_RSAR1, src >> 8); 2854 2855 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD0 | ED_CR_STA); 2856 2857 if (sc->isa16bit) { 2858 insw(sc->asic_addr + ED_NOVELL_DATA, dst, amount / 2); 2859 } else 2860 insb(sc->asic_addr + ED_NOVELL_DATA, dst, amount); 2861 2862} 2863 2864/* 2865 * Stripped down routine for writing a linear buffer to NIC memory. 2866 * Only used in the probe routine to test the memory. 'len' must 2867 * be even. 2868 */ 2869static void 2870ed_pio_writemem(sc, src, dst, len) 2871 struct ed_softc *sc; 2872 char *src; 2873 unsigned short dst; 2874 unsigned short len; 2875{ 2876 int maxwait = 200; /* about 240us */ 2877 2878 if (sc->vendor == ED_VENDOR_NOVELL) { 2879 2880 /* select page 0 registers */ 2881 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STA); 2882 2883 /* reset remote DMA complete flag */ 2884 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC); 2885 2886 /* set up DMA byte count */ 2887 outb(sc->nic_addr + ED_P0_RBCR0, len); 2888 outb(sc->nic_addr + ED_P0_RBCR1, len >> 8); 2889 2890 /* set up destination address in NIC mem */ 2891 outb(sc->nic_addr + ED_P0_RSAR0, dst); 2892 outb(sc->nic_addr + ED_P0_RSAR1, dst >> 8); 2893 2894 /* set remote DMA write */ 2895 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD1 | ED_CR_STA); 2896 2897 if (sc->isa16bit) 2898 outsw(sc->asic_addr + ED_NOVELL_DATA, src, len / 2); 2899 else 2900 outsb(sc->asic_addr + ED_NOVELL_DATA, src, len); 2901 2902 /* 2903 * Wait for remote DMA complete. This is necessary because on the 2904 * transmit side, data is handled internally by the NIC in bursts and 2905 * we can't start another remote DMA until this one completes. Not 2906 * waiting causes really bad things to happen - like the NIC 2907 * irrecoverably jamming the ISA bus. 2908 */ 2909 while (((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait); 2910 2911 } else if ((sc->vendor == ED_VENDOR_HP) && 2912 (sc->type == ED_TYPE_HP_PCLANPLUS)) { 2913 2914 /* HP PCLAN+ */ 2915 2916 /* reset remote DMA complete flag */ 2917 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC); 2918 2919 /* program the write address in RAM */ 2920 outw(sc->asic_addr + ED_HPP_PAGE_0, dst); 2921 2922 if (sc->hpp_mem_start) { 2923 u_short *s = (u_short *) src; 2924 volatile u_short *d = (u_short *) sc->hpp_mem_start; 2925 u_short *const fence = s + (len >> 1); 2926 2927 /* 2928 * Enable memory mapped access. 2929 */ 2930 2931 outw(sc->asic_addr + ED_HPP_OPTION, 2932 sc->hpp_options & 2933 ~(ED_HPP_OPTION_MEM_DISABLE | 2934 ED_HPP_OPTION_BOOT_ROM_ENB)); 2935 2936 /* 2937 * Copy to NIC memory. 2938 */ 2939 2940 while (s < fence) 2941 *d = *s++; 2942 2943 /* 2944 * Restore Boot ROM access. 2945 */ 2946 2947 outw(sc->asic_addr + ED_HPP_OPTION, 2948 sc->hpp_options); 2949 2950 } else { 2951 /* write data using I/O writes */ 2952 outsw(sc->asic_addr + ED_HPP_PAGE_4, src, len / 2); 2953 } 2954 2955 } 2956} 2957 2958/* 2959 * Write an mbuf chain to the destination NIC memory address using 2960 * programmed I/O. 2961 */ 2962static u_short 2963ed_pio_write_mbufs(sc, m, dst) 2964 struct ed_softc *sc; 2965 struct mbuf *m; 2966 int dst; 2967{ 2968 struct ifnet *ifp = (struct ifnet *)sc; 2969 unsigned short total_len, dma_len; 2970 struct mbuf *mp; 2971 int maxwait = 200; /* about 240us */ 2972 2973 /* HP PC Lan+ cards need special handling */ 2974 if ((sc->vendor == ED_VENDOR_HP) && 2975 (sc->type == ED_TYPE_HP_PCLANPLUS)) { 2976 return ed_hpp_write_mbufs(sc, m, dst); 2977 } 2978 2979 /* First, count up the total number of bytes to copy */ 2980 for (total_len = 0, mp = m; mp; mp = mp->m_next) 2981 total_len += mp->m_len; 2982 2983 dma_len = total_len; 2984 if (sc->isa16bit && (dma_len & 1)) 2985 dma_len++; 2986 2987 /* select page 0 registers */ 2988 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STA); 2989 2990 /* reset remote DMA complete flag */ 2991 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC); 2992 2993 /* set up DMA byte count */ 2994 outb(sc->nic_addr + ED_P0_RBCR0, dma_len); 2995 outb(sc->nic_addr + ED_P0_RBCR1, dma_len >> 8); 2996 2997 /* set up destination address in NIC mem */ 2998 outb(sc->nic_addr + ED_P0_RSAR0, dst); 2999 outb(sc->nic_addr + ED_P0_RSAR1, dst >> 8); 3000 3001 /* set remote DMA write */ 3002 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD1 | ED_CR_STA); 3003 3004 /* 3005 * Transfer the mbuf chain to the NIC memory. 3006 * 16-bit cards require that data be transferred as words, and only words. 3007 * So that case requires some extra code to patch over odd-length mbufs. 3008 */ 3009 3010 if (!sc->isa16bit) { 3011 /* NE1000s are easy */ 3012 while (m) { 3013 if (m->m_len) { 3014 outsb(sc->asic_addr + ED_NOVELL_DATA, 3015 m->m_data, m->m_len); 3016 } 3017 m = m->m_next; 3018 } 3019 } else { 3020 /* NE2000s are a pain */ 3021 unsigned char *data; 3022 int len, wantbyte; 3023 unsigned char savebyte[2]; 3024 3025 wantbyte = 0; 3026 3027 while (m) { 3028 len = m->m_len; 3029 if (len) { 3030 data = mtod(m, caddr_t); 3031 /* finish the last word */ 3032 if (wantbyte) { 3033 savebyte[1] = *data; 3034 outw(sc->asic_addr + ED_NOVELL_DATA, *(u_short *)savebyte); 3035 data++; 3036 len--; 3037 wantbyte = 0; 3038 } 3039 /* output contiguous words */ 3040 if (len > 1) { 3041 outsw(sc->asic_addr + ED_NOVELL_DATA, 3042 data, len >> 1); 3043 data += len & ~1; 3044 len &= 1; 3045 } 3046 /* save last byte, if necessary */ 3047 if (len == 1) { 3048 savebyte[0] = *data; 3049 wantbyte = 1; 3050 } 3051 } 3052 m = m->m_next; 3053 } 3054 /* spit last byte */ 3055 if (wantbyte) { 3056 outw(sc->asic_addr + ED_NOVELL_DATA, *(u_short *)savebyte); 3057 } 3058 } 3059 3060 /* 3061 * Wait for remote DMA complete. This is necessary because on the 3062 * transmit side, data is handled internally by the NIC in bursts and 3063 * we can't start another remote DMA until this one completes. Not 3064 * waiting causes really bad things to happen - like the NIC 3065 * irrecoverably jamming the ISA bus. 3066 */ 3067 while (((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait); 3068 3069 if (!maxwait) { 3070 log(LOG_WARNING, "ed%d: remote transmit DMA failed to complete\n", 3071 ifp->if_unit); 3072 ed_reset(ifp); 3073 return(0); 3074 } 3075 return (total_len); 3076} 3077 3078/* 3079 * Support routines to handle the HP PC Lan+ card. 3080 */ 3081 3082/* 3083 * HP PC Lan+: Read from NIC memory, using either PIO or memory mapped 3084 * IO. 3085 */ 3086 3087static void 3088ed_hpp_readmem(sc, src, dst, amount) 3089 struct ed_softc *sc; 3090 unsigned short src; 3091 unsigned char *dst; 3092 unsigned short amount; 3093{ 3094 3095 int use_32bit_access = !(sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS); 3096 3097 3098 /* Program the source address in RAM */ 3099 outw(sc->asic_addr + ED_HPP_PAGE_2, src); 3100 3101 /* 3102 * The HP PC Lan+ card supports word reads as well as 3103 * a memory mapped i/o port that is aliased to every 3104 * even address on the board. 3105 */ 3106 3107 if (sc->hpp_mem_start) { 3108 3109 /* Enable memory mapped access. */ 3110 outw(sc->asic_addr + ED_HPP_OPTION, 3111 sc->hpp_options & 3112 ~(ED_HPP_OPTION_MEM_DISABLE | 3113 ED_HPP_OPTION_BOOT_ROM_ENB)); 3114 3115 if (use_32bit_access && (amount > 3)) { 3116 u_long *dl = (u_long *) dst; 3117 volatile u_long *const sl = 3118 (u_long *) sc->hpp_mem_start; 3119 u_long *const fence = dl + (amount >> 2); 3120 3121 /* Copy out NIC data. We could probably write this 3122 as a `movsl'. The currently generated code is lousy. 3123 */ 3124 3125 while (dl < fence) 3126 *dl++ = *sl; 3127 3128 dst += (amount & ~3); 3129 amount &= 3; 3130 3131 } 3132 3133 /* Finish off any words left, as a series of short reads */ 3134 if (amount > 1) { 3135 u_short *d = (u_short *) dst; 3136 volatile u_short *const s = 3137 (u_short *) sc->hpp_mem_start; 3138 u_short *const fence = d + (amount >> 1); 3139 3140 /* Copy out NIC data. */ 3141 3142 while (d < fence) 3143 *d++ = *s; 3144 3145 dst += (amount & ~1); 3146 amount &= 1; 3147 } 3148 3149 /* 3150 * read in a byte; however we need to always read 16 bits 3151 * at a time or the hardware gets into a funny state 3152 */ 3153 3154 if (amount == 1) { 3155 /* need to read in a short and copy LSB */ 3156 volatile u_short *const s = 3157 (volatile u_short *) sc->hpp_mem_start; 3158 3159 *dst = (*s) & 0xFF; 3160 } 3161 3162 /* Restore Boot ROM access. */ 3163 3164 outw(sc->asic_addr + ED_HPP_OPTION, 3165 sc->hpp_options); 3166 3167 3168 } else { 3169 /* Read in data using the I/O port */ 3170 if (use_32bit_access && (amount > 3)) { 3171 insl(sc->asic_addr + ED_HPP_PAGE_4, dst, amount >> 2); 3172 dst += (amount & ~3); 3173 amount &= 3; 3174 } 3175 if (amount > 1) { 3176 insw(sc->asic_addr + ED_HPP_PAGE_4, dst, amount >> 1); 3177 dst += (amount & ~1); 3178 amount &= 1; 3179 } 3180 if (amount == 1) { /* read in a short and keep the LSB */ 3181 *dst = inw(sc->asic_addr + ED_HPP_PAGE_4) & 0xFF; 3182 } 3183 } 3184} 3185 3186/* 3187 * Write to HP PC Lan+ NIC memory. Access to the NIC can be by using 3188 * outsw() or via the memory mapped interface to the same register. 3189 * Writes have to be in word units; byte accesses won't work and may cause 3190 * the NIC to behave wierdly. Long word accesses are permitted if the ASIC 3191 * allows it. 3192 */ 3193 3194static u_short 3195ed_hpp_write_mbufs(struct ed_softc *sc, struct mbuf *m, int dst) 3196{ 3197 int len, wantbyte; 3198 unsigned short total_len; 3199 unsigned char savebyte[2]; 3200 volatile u_short * const d = 3201 (volatile u_short *) sc->hpp_mem_start; 3202 int use_32bit_accesses = !(sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS); 3203 3204 /* select page 0 registers */ 3205 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA); 3206 3207 /* reset remote DMA complete flag */ 3208 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC); 3209 3210 /* program the write address in RAM */ 3211 outw(sc->asic_addr + ED_HPP_PAGE_0, dst); 3212 3213 if (sc->hpp_mem_start) /* enable memory mapped I/O */ 3214 outw(sc->asic_addr + ED_HPP_OPTION, sc->hpp_options & 3215 ~(ED_HPP_OPTION_MEM_DISABLE | 3216 ED_HPP_OPTION_BOOT_ROM_ENB)); 3217 3218 wantbyte = 0; 3219 total_len = 0; 3220 3221 if (sc->hpp_mem_start) { /* Memory mapped I/O port */ 3222 while (m) { 3223 total_len += (len = m->m_len); 3224 if (len) { 3225 caddr_t data = mtod(m, caddr_t); 3226 /* finish the last word of the previous mbuf */ 3227 if (wantbyte) { 3228 savebyte[1] = *data; 3229 *d = *((ushort *) savebyte); 3230 data++; len--; wantbyte = 0; 3231 } 3232 /* output contiguous words */ 3233 if ((len > 3) && (use_32bit_accesses)) { 3234 volatile u_long *const dl = 3235 (volatile u_long *) d; 3236 u_long *sl = (u_long *) data; 3237 u_long *fence = sl + (len >> 2); 3238 3239 while (sl < fence) 3240 *dl = *sl++; 3241 3242 data += (len & ~3); 3243 len &= 3; 3244 } 3245 /* finish off remain 16 bit writes */ 3246 if (len > 1) { 3247 u_short *s = (u_short *) data; 3248 u_short *fence = s + (len >> 1); 3249 3250 while (s < fence) 3251 *d = *s++; 3252 3253 data += (len & ~1); 3254 len &= 1; 3255 } 3256 /* save last byte if needed */ 3257 if (wantbyte = (len == 1)) 3258 savebyte[0] = *data; 3259 } 3260 m = m->m_next; /* to next mbuf */ 3261 } 3262 if (wantbyte) /* write last byte */ 3263 *d = *((u_short *) savebyte); 3264 } else { 3265 /* use programmed I/O */ 3266 while (m) { 3267 total_len += (len = m->m_len); 3268 if (len) { 3269 caddr_t data = mtod(m, caddr_t); 3270 /* finish the last word of the previous mbuf */ 3271 if (wantbyte) { 3272 savebyte[1] = *data; 3273 outw(sc->asic_addr + ED_HPP_PAGE_4, 3274 *((u_short *)savebyte)); 3275 data++; 3276 len--; 3277 wantbyte = 0; 3278 } 3279 /* output contiguous words */ 3280 if ((len > 3) && use_32bit_accesses) { 3281 outsl(sc->asic_addr + ED_HPP_PAGE_4, 3282 data, len >> 2); 3283 data += (len & ~3); 3284 len &= 3; 3285 } 3286 /* finish off remaining 16 bit accesses */ 3287 if (len > 1) { 3288 outsw(sc->asic_addr + ED_HPP_PAGE_4, 3289 data, len >> 1); 3290 data += (len & ~1); 3291 len &= 1; 3292 } 3293 if (wantbyte = (len == 1)) 3294 savebyte[0] = *data; 3295 3296 } /* if len != 0 */ 3297 m = m->m_next; 3298 } 3299 if (wantbyte) /* spit last byte */ 3300 outw(sc->asic_addr + ED_HPP_PAGE_4, 3301 *(u_short *)savebyte); 3302 3303 } 3304 3305 if (sc->hpp_mem_start) /* turn off memory mapped i/o */ 3306 outw(sc->asic_addr + ED_HPP_OPTION, 3307 sc->hpp_options); 3308 3309 return (total_len); 3310} 3311 3312static void 3313ed_setrcr(sc) 3314 struct ed_softc *sc; 3315{ 3316 struct ifnet *ifp = (struct ifnet *)sc; 3317 int i; 3318 3319 /* set page 1 registers */ 3320 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP); 3321 3322 if (ifp->if_flags & IFF_PROMISC) { 3323 3324 /* 3325 * Reconfigure the multicast filter. 3326 */ 3327 for (i = 0; i < 8; i++) 3328 outb(sc->nic_addr + ED_P1_MAR0 + i, 0xff); 3329 3330 /* 3331 * And turn on promiscuous mode. Also enable reception of 3332 * runts and packets with CRC & alignment errors. 3333 */ 3334 /* Set page 0 registers */ 3335 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP); 3336 3337 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_PRO | ED_RCR_AM | 3338 ED_RCR_AB | ED_RCR_AR | ED_RCR_SEP); 3339 } else { 3340 /* set up multicast addresses and filter modes */ 3341 if (ifp->if_flags & IFF_MULTICAST) { 3342 u_long mcaf[2]; 3343 3344 if (ifp->if_flags & IFF_ALLMULTI) { 3345 mcaf[0] = 0xffffffff; 3346 mcaf[1] = 0xffffffff; 3347 } else 3348 ds_getmcaf(sc, mcaf); 3349 3350 /* 3351 * Set multicast filter on chip. 3352 */ 3353 for (i = 0; i < 8; i++) 3354 outb(sc->nic_addr + ED_P1_MAR0 + i, ((u_char *) mcaf)[i]); 3355 3356 /* Set page 0 registers */ 3357 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP); 3358 3359 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_AM | ED_RCR_AB); 3360 } else { 3361 3362 /* 3363 * Initialize multicast address hashing registers to 3364 * not accept multicasts. 3365 */ 3366 for (i = 0; i < 8; ++i) 3367 outb(sc->nic_addr + ED_P1_MAR0 + i, 0x00); 3368 3369 /* Set page 0 registers */ 3370 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP); 3371 3372 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_AB); 3373 } 3374 } 3375 3376 /* 3377 * Start interface. 3378 */ 3379 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA); 3380} 3381 3382/* 3383 * Compute crc for ethernet address 3384 */ 3385static u_long 3386ds_crc(ep) 3387 u_char *ep; 3388{ 3389#define POLYNOMIAL 0x04c11db6 3390 register u_long crc = 0xffffffffL; 3391 register int carry, i, j; 3392 register u_char b; 3393 3394 for (i = 6; --i >= 0;) { 3395 b = *ep++; 3396 for (j = 8; --j >= 0;) { 3397 carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01); 3398 crc <<= 1; 3399 b >>= 1; 3400 if (carry) 3401 crc = ((crc ^ POLYNOMIAL) | carry); 3402 } 3403 } 3404 return crc; 3405#undef POLYNOMIAL 3406} 3407 3408/* 3409 * Compute the multicast address filter from the 3410 * list of multicast addresses we need to listen to. 3411 */ 3412static void 3413ds_getmcaf(sc, mcaf) 3414 struct ed_softc *sc; 3415 u_long *mcaf; 3416{ 3417 register u_int index; 3418 register u_char *af = (u_char *) mcaf; 3419 struct ifmultiaddr *ifma; 3420 3421 mcaf[0] = 0; 3422 mcaf[1] = 0; 3423 3424 for (ifma = sc->arpcom.ac_if.if_multiaddrs.lh_first; ifma; 3425 ifma = ifma->ifma_link.le_next) { 3426 if (ifma->ifma_addr->sa_family != AF_LINK) 3427 continue; 3428 index = ds_crc(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)) 3429 >> 26; 3430 af[index >> 3] |= 1 << (index & 7); 3431 } 3432} 3433