if_ed.c revision 27555
1/* 2 * Copyright (c) 1995, David Greenman 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $Id: if_ed.c,v 1.116 1997/03/24 11:32:39 bde Exp $ 28 */ 29 30/* 31 * Device driver for National Semiconductor DS8390/WD83C690 based ethernet 32 * adapters. By David Greenman, 29-April-1993 33 * 34 * Currently supports the Western Digital/SMC 8003 and 8013 series, 35 * the SMC Elite Ultra (8216), the 3Com 3c503, the NE1000 and NE2000, 36 * and a variety of similar clones. 37 * 38 */ 39 40#include "ed.h" 41#include "bpfilter.h" 42 43#include <sys/param.h> 44#include <sys/systm.h> 45#include <sys/conf.h> 46#include <sys/sockio.h> 47#include <sys/mbuf.h> 48#include <sys/socket.h> 49#include <sys/syslog.h> 50 51#include <net/if.h> 52#include <net/if_dl.h> 53#include <net/if_mib.h> 54 55#ifdef INET 56#include <netinet/in.h> 57#include <netinet/if_ether.h> 58#endif 59 60#ifdef NS 61#include <netns/ns.h> 62#include <netns/ns_if.h> 63#endif 64 65#if NBPFILTER > 0 66#include <net/bpf.h> 67#endif 68 69#include <machine/clock.h> 70#include <machine/md_var.h> 71 72#include <i386/isa/isa_device.h> 73#include <i386/isa/icu.h> 74#include <i386/isa/if_edreg.h> 75 76/* 77 * ed_softc: per line info and status 78 */ 79struct ed_softc { 80 struct arpcom arpcom; /* ethernet common */ 81 82 char *type_str; /* pointer to type string */ 83 u_char vendor; /* interface vendor */ 84 u_char type; /* interface type code */ 85 u_char gone; /* HW missing, presumed having a good time */ 86 87 u_short asic_addr; /* ASIC I/O bus address */ 88 u_short nic_addr; /* NIC (DS8390) I/O bus address */ 89 90/* 91 * The following 'proto' variable is part of a work-around for 8013EBT asics 92 * being write-only. It's sort of a prototype/shadow of the real thing. 93 */ 94 u_char wd_laar_proto; 95 u_char cr_proto; 96 u_char isa16bit; /* width of access to card 0=8 or 1=16 */ 97 int is790; /* set by the probe code if the card is 790 98 * based */ 99 100/* 101 * HP PC LAN PLUS card support. 102 */ 103 104 u_short hpp_options; /* flags controlling behaviour of the HP card */ 105 u_short hpp_id; /* software revision and other fields */ 106 caddr_t hpp_mem_start; /* Memory-mapped IO register address */ 107 108 caddr_t mem_start; /* NIC memory start address */ 109 caddr_t mem_end; /* NIC memory end address */ 110 u_long mem_size; /* total NIC memory size */ 111 caddr_t mem_ring; /* start of RX ring-buffer (in NIC mem) */ 112 113 u_char mem_shared; /* NIC memory is shared with host */ 114 u_char xmit_busy; /* transmitter is busy */ 115 u_char txb_cnt; /* number of transmit buffers */ 116 u_char txb_inuse; /* number of TX buffers currently in-use */ 117 118 u_char txb_new; /* pointer to where new buffer will be added */ 119 u_char txb_next_tx; /* pointer to next buffer ready to xmit */ 120 u_short txb_len[8]; /* buffered xmit buffer lengths */ 121 u_char tx_page_start; /* first page of TX buffer area */ 122 u_char rec_page_start; /* first page of RX ring-buffer */ 123 u_char rec_page_stop; /* last page of RX ring-buffer */ 124 u_char next_packet; /* pointer to next unread RX packet */ 125 struct ifmib_iso_8802_3 mibdata; /* stuff for network mgmt */ 126}; 127 128static struct ed_softc ed_softc[NED]; 129 130static int ed_attach __P((struct ed_softc *, int, int)); 131static int ed_attach_isa __P((struct isa_device *)); 132 133static void ed_init __P((void *)); 134static int ed_ioctl __P((struct ifnet *, int, caddr_t)); 135static int ed_probe __P((struct isa_device *)); 136static void ed_start __P((struct ifnet *)); 137static void ed_reset __P((struct ifnet *)); 138static void ed_watchdog __P((struct ifnet *)); 139 140static void ed_stop __P((struct ed_softc *)); 141static int ed_probe_generic8390 __P((struct ed_softc *)); 142static int ed_probe_WD80x3 __P((struct isa_device *)); 143static int ed_probe_3Com __P((struct isa_device *)); 144static int ed_probe_Novell __P((struct isa_device *)); 145static int ed_probe_Novell_generic __P((struct ed_softc *, int, int, int)); 146static int ed_probe_HP_pclanp __P((struct isa_device *)); 147 148#include "pci.h" 149#if NPCI > 0 150void *ed_attach_NE2000_pci __P((int, int)); 151#endif 152 153#include "crd.h" 154#if NCRD > 0 155static int ed_probe_pccard __P((struct isa_device *, u_char *)); 156#endif 157 158static void ds_getmcaf __P((struct ed_softc *, u_long *)); 159 160static void ed_get_packet(struct ed_softc *, char *, /* u_short */ int, int); 161 162static void ed_rint __P((struct ed_softc *)); 163static void ed_xmit __P((struct ed_softc *)); 164static char * ed_ring_copy __P((struct ed_softc *, char *, char *, 165 /* u_short */ int)); 166static void ed_hpp_set_physical_link __P((struct ed_softc *)); 167static void ed_hpp_readmem __P((struct ed_softc *, int, unsigned char *, 168 /* u_short */ int)); 169static u_short ed_hpp_write_mbufs __P((struct ed_softc *, struct mbuf *, 170 int)); 171 172static void ed_pio_readmem __P((struct ed_softc *, int, unsigned char *, 173 /* u_short */ int)); 174static void ed_pio_writemem __P((struct ed_softc *, char *, 175 /* u_short */ int, /* u_short */ int)); 176static u_short ed_pio_write_mbufs __P((struct ed_softc *, struct mbuf *, 177 int)); 178void edintr_sc __P((struct ed_softc *)); 179 180static void ed_setrcr(struct ed_softc *); 181 182static u_long ds_crc(u_char *ep); 183 184#if NCRD > 0 185#include <sys/select.h> 186#include <pccard/card.h> 187#include <pccard/driver.h> 188#include <pccard/slot.h> 189 190/* 191 * PC-Card (PCMCIA) specific code. 192 */ 193static int card_intr(struct pccard_dev *); /* Interrupt handler */ 194static void edunload(struct pccard_dev *); /* Disable driver */ 195static void edsuspend(struct pccard_dev *); /* Suspend driver */ 196static int edinit(struct pccard_dev *, int); /* init device */ 197 198static struct pccard_drv ed_info = { 199 "ed", 200 card_intr, 201 edunload, 202 edsuspend, 203 edinit, 204 0, /* Attributes - presently unused */ 205 &net_imask /* Interrupt mask for device */ 206 /* XXX - Should this also include net_imask? */ 207}; 208 209/* 210 * Called when a power down is requested. Shuts down the 211 * device and configures the device as unavailable (but 212 * still loaded...). A resume is done by calling 213 * edinit with first=0. This is called when the user suspends 214 * the system, or the APM code suspends the system. 215 */ 216static void 217edsuspend(struct pccard_dev *dp) 218{ 219 struct ed_softc *sc = &ed_softc[dp->isahd.id_unit]; 220 /* 221 * Some 'ed' cards will generate a interrupt as they go away, 222 * and by the time the interrupt handler gets to the card, 223 * the interrupt can't be cleared. 224 * By setting gone here, we tell the handler to ignore the 225 * interrupt when it happens. 226 */ 227 sc->gone = 1; /* avoid spinning endlessly in interrupt handler */ 228 229 printf("ed%d: suspending\n", dp->isahd.id_unit); 230} 231 232/* 233 * Initialize the device - called from Slot manager. 234 * If first is set, then check for the device's existence 235 * before initializing it. Once initialized, the device table may 236 * be set up. 237 */ 238static int 239edinit(struct pccard_dev *dp, int first) 240{ 241 struct ed_softc *sc = &ed_softc[dp->isahd.id_unit]; 242 243 /* validate unit number. */ 244 if (first) { 245 if (dp->isahd.id_unit >= NED) 246 return(ENODEV); 247 /* 248 * Probe the device. If a value is returned, the 249 * device was found at the location. 250 */ 251 sc->gone = 0; 252 if (ed_probe_pccard(&dp->isahd,dp->misc)==0) 253 return(ENXIO); 254 if (ed_attach_isa(&dp->isahd)==0) 255 return(ENXIO); 256 } else { 257 sc->gone = 0; /* reenable after a suspend */ 258 } 259 /* 260 * XXX TODO: 261 * If it was initialized before, the device structure 262 * should also be initialized. We should 263 * reset (and possibly restart) the hardware, but 264 * I am not sure of the best way to do this... 265 */ 266 return(0); 267} 268 269/* 270 * edunload - unload the driver and clear the table. 271 * XXX TODO: 272 * This is usually called when the card is ejected, but 273 * can be caused by a modunload of a controller driver. 274 * The idea is to reset the driver's view of the device 275 * and ensure that any driver entry points such as 276 * read and write do not hang. 277 */ 278static void 279edunload(struct pccard_dev *dp) 280{ 281 struct ed_softc *sc = &ed_softc[dp->isahd.id_unit]; 282 struct ifnet *ifp = &sc->arpcom.ac_if; 283 284 if (sc->gone) { 285 printf("ed%d: already unloaded\n", dp->isahd.id_unit); 286 return; 287 } 288 ifp->if_flags &= ~IFF_RUNNING; 289 if_down(ifp); 290 sc->gone = 1; 291 printf("ed%d: unload\n", dp->isahd.id_unit); 292} 293 294/* 295 * card_intr - Shared interrupt called from 296 * front end of PC-Card handler. 297 */ 298static int 299card_intr(struct pccard_dev *dp) 300{ 301 edintr_sc(&ed_softc[dp->isahd.id_unit]); 302 return(1); 303} 304#endif /* NCRD > 0 */ 305 306struct isa_driver eddriver = { 307 ed_probe, 308 ed_attach_isa, 309 "ed", 310 1 /* We are ultra sensitive */ 311}; 312 313/* 314 * Interrupt conversion table for WD/SMC ASIC/83C584 315 * (IRQ* are defined in icu.h) 316 */ 317static unsigned short ed_intr_mask[] = { 318 IRQ9, 319 IRQ3, 320 IRQ5, 321 IRQ7, 322 IRQ10, 323 IRQ11, 324 IRQ15, 325 IRQ4 326}; 327 328/* 329 * Interrupt conversion table for 83C790 330 */ 331static unsigned short ed_790_intr_mask[] = { 332 0, 333 IRQ9, 334 IRQ3, 335 IRQ5, 336 IRQ7, 337 IRQ10, 338 IRQ11, 339 IRQ15 340}; 341 342/* 343 * Interrupt conversion table for the HP PC LAN+ 344 */ 345 346static unsigned short ed_hpp_intr_mask[] = { 347 0, /* 0 */ 348 0, /* 1 */ 349 0, /* 2 */ 350 IRQ3, /* 3 */ 351 IRQ4, /* 4 */ 352 IRQ5, /* 5 */ 353 IRQ6, /* 6 */ 354 IRQ7, /* 7 */ 355 0, /* 8 */ 356 IRQ9, /* 9 */ 357 IRQ10, /* 10 */ 358 IRQ11, /* 11 */ 359 IRQ12, /* 12 */ 360 0, /* 13 */ 361 0, /* 14 */ 362 IRQ15 /* 15 */ 363}; 364 365/* 366 * Determine if the device is present 367 * 368 * on entry: 369 * a pointer to an isa_device struct 370 * on exit: 371 * NULL if device not found 372 * or # of i/o addresses used (if found) 373 */ 374static int 375ed_probe(isa_dev) 376 struct isa_device *isa_dev; 377{ 378 int nports; 379 380#if NCRD > 0 381 /* 382 * If PC-Card probe required, then register driver with 383 * slot manager. 384 */ 385 pccard_add_driver(&ed_info); 386#endif 387 388 nports = ed_probe_WD80x3(isa_dev); 389 if (nports) 390 return (nports); 391 392 nports = ed_probe_3Com(isa_dev); 393 if (nports) 394 return (nports); 395 396 nports = ed_probe_Novell(isa_dev); 397 if (nports) 398 return (nports); 399 400 nports = ed_probe_HP_pclanp(isa_dev); 401 if (nports) 402 return (nports); 403 404 return (0); 405} 406 407/* 408 * Generic probe routine for testing for the existance of a DS8390. 409 * Must be called after the NIC has just been reset. This routine 410 * works by looking at certain register values that are guaranteed 411 * to be initialized a certain way after power-up or reset. Seems 412 * not to currently work on the 83C690. 413 * 414 * Specifically: 415 * 416 * Register reset bits set bits 417 * Command Register (CR) TXP, STA RD2, STP 418 * Interrupt Status (ISR) RST 419 * Interrupt Mask (IMR) All bits 420 * Data Control (DCR) LAS 421 * Transmit Config. (TCR) LB1, LB0 422 * 423 * We only look at the CR and ISR registers, however, because looking at 424 * the others would require changing register pages (which would be 425 * intrusive if this isn't an 8390). 426 * 427 * Return 1 if 8390 was found, 0 if not. 428 */ 429 430static int 431ed_probe_generic8390(sc) 432 struct ed_softc *sc; 433{ 434 if ((inb(sc->nic_addr + ED_P0_CR) & 435 (ED_CR_RD2 | ED_CR_TXP | ED_CR_STA | ED_CR_STP)) != 436 (ED_CR_RD2 | ED_CR_STP)) 437 return (0); 438 if ((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RST) != ED_ISR_RST) 439 return (0); 440 441 return (1); 442} 443 444/* 445 * Probe and vendor-specific initialization routine for SMC/WD80x3 boards 446 */ 447static int 448ed_probe_WD80x3(isa_dev) 449 struct isa_device *isa_dev; 450{ 451 struct ed_softc *sc = &ed_softc[isa_dev->id_unit]; 452 int i; 453 u_int memsize; 454 u_char iptr, isa16bit, sum; 455 456 sc->asic_addr = isa_dev->id_iobase; 457 sc->nic_addr = sc->asic_addr + ED_WD_NIC_OFFSET; 458 sc->is790 = 0; 459 460#ifdef TOSH_ETHER 461 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_POW); 462 DELAY(10000); 463#endif 464 465 /* 466 * Attempt to do a checksum over the station address PROM. If it 467 * fails, it's probably not a SMC/WD board. There is a problem with 468 * this, though: some clone WD boards don't pass the checksum test. 469 * Danpex boards for one. 470 */ 471 for (sum = 0, i = 0; i < 8; ++i) 472 sum += inb(sc->asic_addr + ED_WD_PROM + i); 473 474 if (sum != ED_WD_ROM_CHECKSUM_TOTAL) { 475 476 /* 477 * Checksum is invalid. This often happens with cheap WD8003E 478 * clones. In this case, the checksum byte (the eighth byte) 479 * seems to always be zero. 480 */ 481 if (inb(sc->asic_addr + ED_WD_CARD_ID) != ED_TYPE_WD8003E || 482 inb(sc->asic_addr + ED_WD_PROM + 7) != 0) 483 return (0); 484 } 485 /* reset card to force it into a known state. */ 486#ifdef TOSH_ETHER 487 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_RST | ED_WD_MSR_POW); 488#else 489 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_RST); 490#endif 491 DELAY(100); 492 outb(sc->asic_addr + ED_WD_MSR, inb(sc->asic_addr + ED_WD_MSR) & ~ED_WD_MSR_RST); 493 /* wait in the case this card is reading it's EEROM */ 494 DELAY(5000); 495 496 sc->vendor = ED_VENDOR_WD_SMC; 497 sc->type = inb(sc->asic_addr + ED_WD_CARD_ID); 498 499 /* 500 * Set initial values for width/size. 501 */ 502 memsize = 8192; 503 isa16bit = 0; 504 switch (sc->type) { 505 case ED_TYPE_WD8003S: 506 sc->type_str = "WD8003S"; 507 break; 508 case ED_TYPE_WD8003E: 509 sc->type_str = "WD8003E"; 510 break; 511 case ED_TYPE_WD8003EB: 512 sc->type_str = "WD8003EB"; 513 break; 514 case ED_TYPE_WD8003W: 515 sc->type_str = "WD8003W"; 516 break; 517 case ED_TYPE_WD8013EBT: 518 sc->type_str = "WD8013EBT"; 519 memsize = 16384; 520 isa16bit = 1; 521 break; 522 case ED_TYPE_WD8013W: 523 sc->type_str = "WD8013W"; 524 memsize = 16384; 525 isa16bit = 1; 526 break; 527 case ED_TYPE_WD8013EP: /* also WD8003EP */ 528 if (inb(sc->asic_addr + ED_WD_ICR) 529 & ED_WD_ICR_16BIT) { 530 isa16bit = 1; 531 memsize = 16384; 532 sc->type_str = "WD8013EP"; 533 } else { 534 sc->type_str = "WD8003EP"; 535 } 536 break; 537 case ED_TYPE_WD8013WC: 538 sc->type_str = "WD8013WC"; 539 memsize = 16384; 540 isa16bit = 1; 541 break; 542 case ED_TYPE_WD8013EBP: 543 sc->type_str = "WD8013EBP"; 544 memsize = 16384; 545 isa16bit = 1; 546 break; 547 case ED_TYPE_WD8013EPC: 548 sc->type_str = "WD8013EPC"; 549 memsize = 16384; 550 isa16bit = 1; 551 break; 552 case ED_TYPE_SMC8216C: /* 8216 has 16K shared mem -- 8416 has 8K */ 553 case ED_TYPE_SMC8216T: 554 if (sc->type == ED_TYPE_SMC8216C) { 555 sc->type_str = "SMC8216/SMC8216C"; 556 } else { 557 sc->type_str = "SMC8216T"; 558 } 559 560 outb(sc->asic_addr + ED_WD790_HWR, 561 inb(sc->asic_addr + ED_WD790_HWR) | ED_WD790_HWR_SWH); 562 switch (inb(sc->asic_addr + ED_WD790_RAR) & ED_WD790_RAR_SZ64) { 563 case ED_WD790_RAR_SZ64: 564 memsize = 65536; 565 break; 566 case ED_WD790_RAR_SZ32: 567 memsize = 32768; 568 break; 569 case ED_WD790_RAR_SZ16: 570 memsize = 16384; 571 break; 572 case ED_WD790_RAR_SZ8: 573 /* 8216 has 16K shared mem -- 8416 has 8K */ 574 if (sc->type == ED_TYPE_SMC8216C) { 575 sc->type_str = "SMC8416C/SMC8416BT"; 576 } else { 577 sc->type_str = "SMC8416T"; 578 } 579 memsize = 8192; 580 break; 581 } 582 outb(sc->asic_addr + ED_WD790_HWR, 583 inb(sc->asic_addr + ED_WD790_HWR) & ~ED_WD790_HWR_SWH); 584 585 isa16bit = 1; 586 sc->is790 = 1; 587 break; 588#ifdef TOSH_ETHER 589 case ED_TYPE_TOSHIBA1: 590 sc->type_str = "Toshiba1"; 591 memsize = 32768; 592 isa16bit = 1; 593 break; 594 case ED_TYPE_TOSHIBA4: 595 sc->type_str = "Toshiba4"; 596 memsize = 32768; 597 isa16bit = 1; 598 break; 599#endif 600 default: 601 sc->type_str = ""; 602 break; 603 } 604 605 /* 606 * Make some adjustments to initial values depending on what is found 607 * in the ICR. 608 */ 609 if (isa16bit && (sc->type != ED_TYPE_WD8013EBT) 610#ifdef TOSH_ETHER 611 && (sc->type != ED_TYPE_TOSHIBA1) && (sc->type != ED_TYPE_TOSHIBA4) 612#endif 613 && ((inb(sc->asic_addr + ED_WD_ICR) & ED_WD_ICR_16BIT) == 0)) { 614 isa16bit = 0; 615 memsize = 8192; 616 } 617 618#if ED_DEBUG 619 printf("type = %x type_str=%s isa16bit=%d memsize=%d id_msize=%d\n", 620 sc->type, sc->type_str, isa16bit, memsize, isa_dev->id_msize); 621 for (i = 0; i < 8; i++) 622 printf("%x -> %x\n", i, inb(sc->asic_addr + i)); 623#endif 624 625 /* 626 * Allow the user to override the autoconfiguration 627 */ 628 if (isa_dev->id_msize) 629 memsize = isa_dev->id_msize; 630 631 /* 632 * (note that if the user specifies both of the following flags that 633 * '8bit' mode intentionally has precedence) 634 */ 635 if (isa_dev->id_flags & ED_FLAGS_FORCE_16BIT_MODE) 636 isa16bit = 1; 637 if (isa_dev->id_flags & ED_FLAGS_FORCE_8BIT_MODE) 638 isa16bit = 0; 639 640 /* 641 * If possible, get the assigned interrupt number from the card and 642 * use it. 643 */ 644 if ((sc->type & ED_WD_SOFTCONFIG) && (!sc->is790)) { 645 646 /* 647 * Assemble together the encoded interrupt number. 648 */ 649 iptr = (inb(isa_dev->id_iobase + ED_WD_ICR) & ED_WD_ICR_IR2) | 650 ((inb(isa_dev->id_iobase + ED_WD_IRR) & 651 (ED_WD_IRR_IR0 | ED_WD_IRR_IR1)) >> 5); 652 653 /* 654 * If no interrupt specified (or "?"), use what the board tells us. 655 */ 656 if (isa_dev->id_irq <= 0) 657 isa_dev->id_irq = ed_intr_mask[iptr]; 658 659 /* 660 * Enable the interrupt. 661 */ 662 outb(isa_dev->id_iobase + ED_WD_IRR, 663 inb(isa_dev->id_iobase + ED_WD_IRR) | ED_WD_IRR_IEN); 664 } 665 if (sc->is790) { 666 outb(isa_dev->id_iobase + ED_WD790_HWR, 667 inb(isa_dev->id_iobase + ED_WD790_HWR) | ED_WD790_HWR_SWH); 668 iptr = (((inb(isa_dev->id_iobase + ED_WD790_GCR) & ED_WD790_GCR_IR2) >> 4) | 669 (inb(isa_dev->id_iobase + ED_WD790_GCR) & 670 (ED_WD790_GCR_IR1 | ED_WD790_GCR_IR0)) >> 2); 671 outb(isa_dev->id_iobase + ED_WD790_HWR, 672 inb(isa_dev->id_iobase + ED_WD790_HWR) & ~ED_WD790_HWR_SWH); 673 674 /* 675 * If no interrupt specified (or "?"), use what the board tells us. 676 */ 677 if (isa_dev->id_irq <= 0) 678 isa_dev->id_irq = ed_790_intr_mask[iptr]; 679 680 /* 681 * Enable interrupts. 682 */ 683 outb(isa_dev->id_iobase + ED_WD790_ICR, 684 inb(isa_dev->id_iobase + ED_WD790_ICR) | ED_WD790_ICR_EIL); 685 } 686 if (isa_dev->id_irq <= 0) { 687 printf("ed%d: %s cards don't support auto-detected/assigned interrupts.\n", 688 isa_dev->id_unit, sc->type_str); 689 return (0); 690 } 691 sc->isa16bit = isa16bit; 692 sc->mem_shared = 1; 693 isa_dev->id_msize = memsize; 694 sc->mem_start = (caddr_t) isa_dev->id_maddr; 695 696 /* 697 * allocate one xmit buffer if < 16k, two buffers otherwise 698 */ 699 if ((memsize < 16384) || 700 (isa_dev->id_flags & ED_FLAGS_NO_MULTI_BUFFERING)) { 701 sc->txb_cnt = 1; 702 } else { 703 sc->txb_cnt = 2; 704 } 705 sc->tx_page_start = ED_WD_PAGE_OFFSET; 706 sc->rec_page_start = ED_WD_PAGE_OFFSET + ED_TXBUF_SIZE * sc->txb_cnt; 707 sc->rec_page_stop = ED_WD_PAGE_OFFSET + memsize / ED_PAGE_SIZE; 708 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * sc->rec_page_start); 709 sc->mem_size = memsize; 710 sc->mem_end = sc->mem_start + memsize; 711 712 /* 713 * Get station address from on-board ROM 714 */ 715 for (i = 0; i < ETHER_ADDR_LEN; ++i) 716 sc->arpcom.ac_enaddr[i] = inb(sc->asic_addr + ED_WD_PROM + i); 717 718 /* 719 * Set upper address bits and 8/16 bit access to shared memory 720 */ 721 if (isa16bit) { 722 if (sc->is790) { 723 sc->wd_laar_proto = inb(sc->asic_addr + ED_WD_LAAR); 724 outb(sc->asic_addr + ED_WD_LAAR, ED_WD_LAAR_M16EN); 725 } else { 726 outb(sc->asic_addr + ED_WD_LAAR, (sc->wd_laar_proto = 727 ED_WD_LAAR_L16EN | ED_WD_LAAR_M16EN | 728 ((kvtop(sc->mem_start) >> 19) & ED_WD_LAAR_ADDRHI))); 729 } 730 } else { 731 if (((sc->type & ED_WD_SOFTCONFIG) || 732#ifdef TOSH_ETHER 733 (sc->type == ED_TYPE_TOSHIBA1) || (sc->type == ED_TYPE_TOSHIBA4) || 734#endif 735 (sc->type == ED_TYPE_WD8013EBT)) && (!sc->is790)) { 736 outb(sc->asic_addr + ED_WD_LAAR, (sc->wd_laar_proto = 737 ((kvtop(sc->mem_start) >> 19) & ED_WD_LAAR_ADDRHI))); 738 } 739 } 740 741 /* 742 * Set address and enable interface shared memory. 743 */ 744 if (!sc->is790) { 745#ifdef TOSH_ETHER 746 outb(sc->asic_addr + ED_WD_MSR + 1, ((kvtop(sc->mem_start) >> 8) & 0xe0) | 4); 747 outb(sc->asic_addr + ED_WD_MSR + 2, ((kvtop(sc->mem_start) >> 16) & 0x0f)); 748 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_MENB | ED_WD_MSR_POW); 749 750#else 751 outb(sc->asic_addr + ED_WD_MSR, ((kvtop(sc->mem_start) >> 13) & 752 ED_WD_MSR_ADDR) | ED_WD_MSR_MENB); 753#endif 754 sc->cr_proto = ED_CR_RD2; 755 } else { 756 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_MENB); 757 outb(sc->asic_addr + ED_WD790_HWR, (inb(sc->asic_addr + ED_WD790_HWR) | ED_WD790_HWR_SWH)); 758 outb(sc->asic_addr + ED_WD790_RAR, ((kvtop(sc->mem_start) >> 13) & 0x0f) | 759 ((kvtop(sc->mem_start) >> 11) & 0x40) | 760 (inb(sc->asic_addr + ED_WD790_RAR) & 0xb0)); 761 outb(sc->asic_addr + ED_WD790_HWR, (inb(sc->asic_addr + ED_WD790_HWR) & ~ED_WD790_HWR_SWH)); 762 sc->cr_proto = 0; 763 } 764 765#if 0 766 printf("starting memory performance test at 0x%x, size %d...\n", 767 sc->mem_start, memsize*16384); 768 for (i = 0; i < 16384; i++) 769 bzero(sc->mem_start, memsize); 770 printf("***DONE***\n"); 771#endif 772 773 /* 774 * Now zero memory and verify that it is clear 775 */ 776 bzero(sc->mem_start, memsize); 777 778 for (i = 0; i < memsize; ++i) { 779 if (sc->mem_start[i]) { 780 printf("ed%d: failed to clear shared memory at %lx - check configuration\n", 781 isa_dev->id_unit, kvtop(sc->mem_start + i)); 782 783 /* 784 * Disable 16 bit access to shared memory 785 */ 786 if (isa16bit) { 787 if (sc->is790) { 788 outb(sc->asic_addr + ED_WD_MSR, 0x00); 789 } 790 outb(sc->asic_addr + ED_WD_LAAR, (sc->wd_laar_proto &= 791 ~ED_WD_LAAR_M16EN)); 792 } 793 return (0); 794 } 795 } 796 797 /* 798 * Disable 16bit access to shared memory - we leave it 799 * disabled so that 1) machines reboot properly when the board 800 * is set 16 bit mode and there are conflicting 8bit 801 * devices/ROMS in the same 128k address space as this boards 802 * shared memory. and 2) so that other 8 bit devices with 803 * shared memory can be used in this 128k region, too. 804 */ 805 if (isa16bit) { 806 if (sc->is790) { 807 outb(sc->asic_addr + ED_WD_MSR, 0x00); 808 } 809 outb(sc->asic_addr + ED_WD_LAAR, (sc->wd_laar_proto &= 810 ~ED_WD_LAAR_M16EN)); 811 } 812 return (ED_WD_IO_PORTS); 813} 814 815/* 816 * Probe and vendor-specific initialization routine for 3Com 3c503 boards 817 */ 818static int 819ed_probe_3Com(isa_dev) 820 struct isa_device *isa_dev; 821{ 822 struct ed_softc *sc = &ed_softc[isa_dev->id_unit]; 823 int i; 824 u_int memsize; 825 u_char isa16bit; 826 827 sc->asic_addr = isa_dev->id_iobase + ED_3COM_ASIC_OFFSET; 828 sc->nic_addr = isa_dev->id_iobase + ED_3COM_NIC_OFFSET; 829 830 /* 831 * Verify that the kernel configured I/O address matches the board 832 * configured address 833 */ 834 switch (inb(sc->asic_addr + ED_3COM_BCFR)) { 835 case ED_3COM_BCFR_300: 836 if (isa_dev->id_iobase != 0x300) 837 return (0); 838 break; 839 case ED_3COM_BCFR_310: 840 if (isa_dev->id_iobase != 0x310) 841 return (0); 842 break; 843 case ED_3COM_BCFR_330: 844 if (isa_dev->id_iobase != 0x330) 845 return (0); 846 break; 847 case ED_3COM_BCFR_350: 848 if (isa_dev->id_iobase != 0x350) 849 return (0); 850 break; 851 case ED_3COM_BCFR_250: 852 if (isa_dev->id_iobase != 0x250) 853 return (0); 854 break; 855 case ED_3COM_BCFR_280: 856 if (isa_dev->id_iobase != 0x280) 857 return (0); 858 break; 859 case ED_3COM_BCFR_2A0: 860 if (isa_dev->id_iobase != 0x2a0) 861 return (0); 862 break; 863 case ED_3COM_BCFR_2E0: 864 if (isa_dev->id_iobase != 0x2e0) 865 return (0); 866 break; 867 default: 868 return (0); 869 } 870 871 /* 872 * Verify that the kernel shared memory address matches the board 873 * configured address. 874 */ 875 switch (inb(sc->asic_addr + ED_3COM_PCFR)) { 876 case ED_3COM_PCFR_DC000: 877 if (kvtop(isa_dev->id_maddr) != 0xdc000) 878 return (0); 879 break; 880 case ED_3COM_PCFR_D8000: 881 if (kvtop(isa_dev->id_maddr) != 0xd8000) 882 return (0); 883 break; 884 case ED_3COM_PCFR_CC000: 885 if (kvtop(isa_dev->id_maddr) != 0xcc000) 886 return (0); 887 break; 888 case ED_3COM_PCFR_C8000: 889 if (kvtop(isa_dev->id_maddr) != 0xc8000) 890 return (0); 891 break; 892 default: 893 return (0); 894 } 895 896 897 /* 898 * Reset NIC and ASIC. Enable on-board transceiver throughout reset 899 * sequence because it'll lock up if the cable isn't connected if we 900 * don't. 901 */ 902 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_RST | ED_3COM_CR_XSEL); 903 904 /* 905 * Wait for a while, then un-reset it 906 */ 907 DELAY(50); 908 909 /* 910 * The 3Com ASIC defaults to rather strange settings for the CR after 911 * a reset - it's important to set it again after the following outb 912 * (this is done when we map the PROM below). 913 */ 914 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL); 915 916 /* 917 * Wait a bit for the NIC to recover from the reset 918 */ 919 DELAY(5000); 920 921 sc->vendor = ED_VENDOR_3COM; 922 sc->type_str = "3c503"; 923 sc->mem_shared = 1; 924 sc->cr_proto = ED_CR_RD2; 925 926 /* 927 * Hmmm...a 16bit 3Com board has 16k of memory, but only an 8k window 928 * to it. 929 */ 930 memsize = 8192; 931 932 /* 933 * Get station address from on-board ROM 934 */ 935 936 /* 937 * First, map ethernet address PROM over the top of where the NIC 938 * registers normally appear. 939 */ 940 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_EALO | ED_3COM_CR_XSEL); 941 942 for (i = 0; i < ETHER_ADDR_LEN; ++i) 943 sc->arpcom.ac_enaddr[i] = inb(sc->nic_addr + i); 944 945 /* 946 * Unmap PROM - select NIC registers. The proper setting of the 947 * tranceiver is set in ed_init so that the attach code is given a 948 * chance to set the default based on a compile-time config option 949 */ 950 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL); 951 952 /* 953 * Determine if this is an 8bit or 16bit board 954 */ 955 956 /* 957 * select page 0 registers 958 */ 959 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STP); 960 961 /* 962 * Attempt to clear WTS bit. If it doesn't clear, then this is a 16bit 963 * board. 964 */ 965 outb(sc->nic_addr + ED_P0_DCR, 0); 966 967 /* 968 * select page 2 registers 969 */ 970 outb(sc->nic_addr + ED_P0_CR, ED_CR_PAGE_2 | ED_CR_RD2 | ED_CR_STP); 971 972 /* 973 * The 3c503 forces the WTS bit to a one if this is a 16bit board 974 */ 975 if (inb(sc->nic_addr + ED_P2_DCR) & ED_DCR_WTS) 976 isa16bit = 1; 977 else 978 isa16bit = 0; 979 980 /* 981 * select page 0 registers 982 */ 983 outb(sc->nic_addr + ED_P2_CR, ED_CR_RD2 | ED_CR_STP); 984 985 sc->mem_start = (caddr_t) isa_dev->id_maddr; 986 sc->mem_size = memsize; 987 sc->mem_end = sc->mem_start + memsize; 988 989 /* 990 * We have an entire 8k window to put the transmit buffers on the 991 * 16bit boards. But since the 16bit 3c503's shared memory is only 992 * fast enough to overlap the loading of one full-size packet, trying 993 * to load more than 2 buffers can actually leave the transmitter idle 994 * during the load. So 2 seems the best value. (Although a mix of 995 * variable-sized packets might change this assumption. Nonetheless, 996 * we optimize for linear transfers of same-size packets.) 997 */ 998 if (isa16bit) { 999 if (isa_dev->id_flags & ED_FLAGS_NO_MULTI_BUFFERING) 1000 sc->txb_cnt = 1; 1001 else 1002 sc->txb_cnt = 2; 1003 1004 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_16BIT; 1005 sc->rec_page_start = ED_3COM_RX_PAGE_OFFSET_16BIT; 1006 sc->rec_page_stop = memsize / ED_PAGE_SIZE + 1007 ED_3COM_RX_PAGE_OFFSET_16BIT; 1008 sc->mem_ring = sc->mem_start; 1009 } else { 1010 sc->txb_cnt = 1; 1011 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_8BIT; 1012 sc->rec_page_start = ED_TXBUF_SIZE + ED_3COM_TX_PAGE_OFFSET_8BIT; 1013 sc->rec_page_stop = memsize / ED_PAGE_SIZE + 1014 ED_3COM_TX_PAGE_OFFSET_8BIT; 1015 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * ED_TXBUF_SIZE); 1016 } 1017 1018 sc->isa16bit = isa16bit; 1019 1020 /* 1021 * Initialize GA page start/stop registers. Probably only needed if 1022 * doing DMA, but what the hell. 1023 */ 1024 outb(sc->asic_addr + ED_3COM_PSTR, sc->rec_page_start); 1025 outb(sc->asic_addr + ED_3COM_PSPR, sc->rec_page_stop); 1026 1027 /* 1028 * Set IRQ. 3c503 only allows a choice of irq 2-5. 1029 */ 1030 switch (isa_dev->id_irq) { 1031 case IRQ2: 1032 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ2); 1033 break; 1034 case IRQ3: 1035 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ3); 1036 break; 1037 case IRQ4: 1038 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ4); 1039 break; 1040 case IRQ5: 1041 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ5); 1042 break; 1043 default: 1044 printf("ed%d: Invalid irq configuration (%d) must be 3-5,9 for 3c503\n", 1045 isa_dev->id_unit, ffs(isa_dev->id_irq) - 1); 1046 return (0); 1047 } 1048 1049 /* 1050 * Initialize GA configuration register. Set bank and enable shared 1051 * mem. 1052 */ 1053 outb(sc->asic_addr + ED_3COM_GACFR, ED_3COM_GACFR_RSEL | 1054 ED_3COM_GACFR_MBS0); 1055 1056 /* 1057 * Initialize "Vector Pointer" registers. These gawd-awful things are 1058 * compared to 20 bits of the address on ISA, and if they match, the 1059 * shared memory is disabled. We set them to 0xffff0...allegedly the 1060 * reset vector. 1061 */ 1062 outb(sc->asic_addr + ED_3COM_VPTR2, 0xff); 1063 outb(sc->asic_addr + ED_3COM_VPTR1, 0xff); 1064 outb(sc->asic_addr + ED_3COM_VPTR0, 0x00); 1065 1066 /* 1067 * Zero memory and verify that it is clear 1068 */ 1069 bzero(sc->mem_start, memsize); 1070 1071 for (i = 0; i < memsize; ++i) 1072 if (sc->mem_start[i]) { 1073 printf("ed%d: failed to clear shared memory at %lx - check configuration\n", 1074 isa_dev->id_unit, kvtop(sc->mem_start + i)); 1075 return (0); 1076 } 1077 isa_dev->id_msize = memsize; 1078 return (ED_3COM_IO_PORTS); 1079} 1080 1081/* 1082 * Probe and vendor-specific initialization routine for NE1000/2000 boards 1083 */ 1084static int 1085ed_probe_Novell_generic(sc, port, unit, flags) 1086 struct ed_softc *sc; 1087 int port; 1088 int unit; 1089 int flags; 1090{ 1091 u_int memsize, n; 1092 u_char romdata[16], tmp; 1093 static char test_pattern[32] = "THIS is A memory TEST pattern"; 1094 char test_buffer[32]; 1095 1096 sc->asic_addr = port + ED_NOVELL_ASIC_OFFSET; 1097 sc->nic_addr = port + ED_NOVELL_NIC_OFFSET; 1098 1099 /* XXX - do Novell-specific probe here */ 1100 1101 /* Reset the board */ 1102#ifdef GWETHER 1103 outb(sc->asic_addr + ED_NOVELL_RESET, 0); 1104 DELAY(200); 1105#endif /* GWETHER */ 1106 tmp = inb(sc->asic_addr + ED_NOVELL_RESET); 1107 1108 /* 1109 * I don't know if this is necessary; probably cruft leftover from 1110 * Clarkson packet driver code. Doesn't do a thing on the boards I've 1111 * tested. -DG [note that a outb(0x84, 0) seems to work here, and is 1112 * non-invasive...but some boards don't seem to reset and I don't have 1113 * complete documentation on what the 'right' thing to do is...so we 1114 * do the invasive thing for now. Yuck.] 1115 */ 1116 outb(sc->asic_addr + ED_NOVELL_RESET, tmp); 1117 DELAY(5000); 1118 1119 /* 1120 * This is needed because some NE clones apparently don't reset the 1121 * NIC properly (or the NIC chip doesn't reset fully on power-up) XXX 1122 * - this makes the probe invasive! ...Done against my better 1123 * judgement. -DLG 1124 */ 1125 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STP); 1126 1127 DELAY(5000); 1128 1129 /* Make sure that we really have an 8390 based board */ 1130 if (!ed_probe_generic8390(sc)) 1131 return (0); 1132 1133 sc->vendor = ED_VENDOR_NOVELL; 1134 sc->mem_shared = 0; 1135 sc->cr_proto = ED_CR_RD2; 1136 1137 /* 1138 * Test the ability to read and write to the NIC memory. This has the 1139 * side affect of determining if this is an NE1000 or an NE2000. 1140 */ 1141 1142 /* 1143 * This prevents packets from being stored in the NIC memory when the 1144 * readmem routine turns on the start bit in the CR. 1145 */ 1146 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_MON); 1147 1148 /* Temporarily initialize DCR for byte operations */ 1149 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS); 1150 1151 outb(sc->nic_addr + ED_P0_PSTART, 8192 / ED_PAGE_SIZE); 1152 outb(sc->nic_addr + ED_P0_PSTOP, 16384 / ED_PAGE_SIZE); 1153 1154 sc->isa16bit = 0; 1155 1156 /* 1157 * Write a test pattern in byte mode. If this fails, then there 1158 * probably isn't any memory at 8k - which likely means that the board 1159 * is an NE2000. 1160 */ 1161 ed_pio_writemem(sc, test_pattern, 8192, sizeof(test_pattern)); 1162 ed_pio_readmem(sc, 8192, test_buffer, sizeof(test_pattern)); 1163 1164 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern))) { 1165 /* not an NE1000 - try NE2000 */ 1166 1167 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_WTS | ED_DCR_FT1 | ED_DCR_LS); 1168 outb(sc->nic_addr + ED_P0_PSTART, 16384 / ED_PAGE_SIZE); 1169 outb(sc->nic_addr + ED_P0_PSTOP, 32768 / ED_PAGE_SIZE); 1170 1171 sc->isa16bit = 1; 1172 1173 /* 1174 * Write a test pattern in word mode. If this also fails, then 1175 * we don't know what this board is. 1176 */ 1177 ed_pio_writemem(sc, test_pattern, 16384, sizeof(test_pattern)); 1178 ed_pio_readmem(sc, 16384, test_buffer, sizeof(test_pattern)); 1179 1180 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern))) 1181 return (0); /* not an NE2000 either */ 1182 1183 sc->type = ED_TYPE_NE2000; 1184 sc->type_str = "NE2000"; 1185 } else { 1186 sc->type = ED_TYPE_NE1000; 1187 sc->type_str = "NE1000"; 1188 } 1189 1190 /* 8k of memory plus an additional 8k if 16bit */ 1191 memsize = 8192 + sc->isa16bit * 8192; 1192 1193#if 0 /* probably not useful - NE boards only come two ways */ 1194 /* allow kernel config file overrides */ 1195 if (isa_dev->id_msize) 1196 memsize = isa_dev->id_msize; 1197#endif 1198 1199 sc->mem_size = memsize; 1200 1201 /* NIC memory doesn't start at zero on an NE board */ 1202 /* The start address is tied to the bus width */ 1203 sc->mem_start = (char *) 8192 + sc->isa16bit * 8192; 1204 sc->mem_end = sc->mem_start + memsize; 1205 sc->tx_page_start = memsize / ED_PAGE_SIZE; 1206 1207#ifdef GWETHER 1208 { 1209 int x, i, mstart = 0, msize = 0; 1210 char pbuf0[ED_PAGE_SIZE], pbuf[ED_PAGE_SIZE], tbuf[ED_PAGE_SIZE]; 1211 1212 for (i = 0; i < ED_PAGE_SIZE; i++) 1213 pbuf0[i] = 0; 1214 1215 /* Clear all the memory. */ 1216 for (x = 1; x < 256; x++) 1217 ed_pio_writemem(sc, pbuf0, x * 256, ED_PAGE_SIZE); 1218 1219 /* Search for the start of RAM. */ 1220 for (x = 1; x < 256; x++) { 1221 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE); 1222 if (bcmp(pbuf0, tbuf, ED_PAGE_SIZE) == 0) { 1223 for (i = 0; i < ED_PAGE_SIZE; i++) 1224 pbuf[i] = 255 - x; 1225 ed_pio_writemem(sc, pbuf, x * 256, ED_PAGE_SIZE); 1226 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE); 1227 if (bcmp(pbuf, tbuf, ED_PAGE_SIZE) == 0) { 1228 mstart = x * ED_PAGE_SIZE; 1229 msize = ED_PAGE_SIZE; 1230 break; 1231 } 1232 } 1233 } 1234 1235 if (mstart == 0) { 1236 printf("ed%d: Cannot find start of RAM.\n", unit); 1237 return 0; 1238 } 1239 /* Search for the start of RAM. */ 1240 for (x = (mstart / ED_PAGE_SIZE) + 1; x < 256; x++) { 1241 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE); 1242 if (bcmp(pbuf0, tbuf, ED_PAGE_SIZE) == 0) { 1243 for (i = 0; i < ED_PAGE_SIZE; i++) 1244 pbuf[i] = 255 - x; 1245 ed_pio_writemem(sc, pbuf, x * 256, ED_PAGE_SIZE); 1246 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE); 1247 if (bcmp(pbuf, tbuf, ED_PAGE_SIZE) == 0) 1248 msize += ED_PAGE_SIZE; 1249 else { 1250 break; 1251 } 1252 } else { 1253 break; 1254 } 1255 } 1256 1257 if (msize == 0) { 1258 printf("ed%d: Cannot find any RAM, start : %d, x = %d.\n", unit, mstart, x); 1259 return 0; 1260 } 1261 printf("ed%d: RAM start at %d, size : %d.\n", unit, mstart, msize); 1262 1263 sc->mem_size = msize; 1264 sc->mem_start = (char *) mstart; 1265 sc->mem_end = (char *) (msize + mstart); 1266 sc->tx_page_start = mstart / ED_PAGE_SIZE; 1267 } 1268#endif /* GWETHER */ 1269 1270 /* 1271 * Use one xmit buffer if < 16k, two buffers otherwise (if not told 1272 * otherwise). 1273 */ 1274 if ((memsize < 16384) || (flags & ED_FLAGS_NO_MULTI_BUFFERING)) 1275 sc->txb_cnt = 1; 1276 else 1277 sc->txb_cnt = 2; 1278 1279 sc->rec_page_start = sc->tx_page_start + sc->txb_cnt * ED_TXBUF_SIZE; 1280 sc->rec_page_stop = sc->tx_page_start + memsize / ED_PAGE_SIZE; 1281 1282 sc->mem_ring = sc->mem_start + sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE; 1283 1284 ed_pio_readmem(sc, 0, romdata, 16); 1285 for (n = 0; n < ETHER_ADDR_LEN; n++) 1286 sc->arpcom.ac_enaddr[n] = romdata[n * (sc->isa16bit + 1)]; 1287 1288#ifdef GWETHER 1289 if (sc->arpcom.ac_enaddr[2] == 0x86) { 1290 sc->type_str = "Gateway AT"; 1291 } 1292#endif /* GWETHER */ 1293 1294 /* clear any pending interrupts that might have occurred above */ 1295 outb(sc->nic_addr + ED_P0_ISR, 0xff); 1296 1297 return (ED_NOVELL_IO_PORTS); 1298} 1299 1300static int 1301ed_probe_Novell(isa_dev) 1302 struct isa_device *isa_dev; 1303{ 1304 struct ed_softc *sc = &ed_softc[isa_dev->id_unit]; 1305 1306 isa_dev->id_maddr = 0; 1307 return ed_probe_Novell_generic(sc, isa_dev->id_iobase, 1308 isa_dev->id_unit, isa_dev->id_flags); 1309} 1310 1311#if NCRD > 0 1312 1313/* 1314 * Probe framework for pccards. Replicates the standard framework, 1315 * minus the pccard driver registration and ignores the ether address 1316 * supplied (from the CIS), relying on the probe to find it instead. 1317 */ 1318static int 1319ed_probe_pccard(isa_dev, ether) 1320 struct isa_device *isa_dev; 1321 u_char *ether; 1322{ 1323 int nports; 1324 1325 nports = ed_probe_WD80x3(isa_dev); 1326 if (nports) 1327 return (nports); 1328 1329 nports = ed_probe_Novell(isa_dev); 1330 if (nports) 1331 return (nports); 1332 1333 return (0); 1334} 1335 1336#endif /* NCRD > 0 */ 1337 1338#define ED_HPP_TEST_SIZE 16 1339 1340/* 1341 * Probe and vendor specific initialization for the HP PC Lan+ Cards. 1342 * (HP Part nos: 27247B and 27252A). 1343 * 1344 * The card has an asic wrapper around a DS8390 core. The asic handles 1345 * host accesses and offers both standard register IO and memory mapped 1346 * IO. Memory mapped I/O allows better performance at the expense of greater 1347 * chance of an incompatibility with existing ISA cards. 1348 * 1349 * The card has a few caveats: it isn't tolerant of byte wide accesses, only 1350 * short (16 bit) or word (32 bit) accesses are allowed. Some card revisions 1351 * don't allow 32 bit accesses; these are indicated by a bit in the software 1352 * ID register (see if_edreg.h). 1353 * 1354 * Other caveats are: we should read the MAC address only when the card 1355 * is inactive. 1356 * 1357 * For more information; please consult the CRYNWR packet driver. 1358 * 1359 * The AUI port is turned on using the "link2" option on the ifconfig 1360 * command line. 1361 */ 1362static int 1363ed_probe_HP_pclanp(isa_dev) 1364 struct isa_device *isa_dev; 1365{ 1366 struct ed_softc *sc = &ed_softc[isa_dev->id_unit]; 1367 int n; /* temp var */ 1368 int memsize; /* mem on board */ 1369 u_char checksum; /* checksum of board address */ 1370 u_char irq; /* board configured IRQ */ 1371 char test_pattern[ED_HPP_TEST_SIZE]; /* read/write areas for */ 1372 char test_buffer[ED_HPP_TEST_SIZE]; /* probing card */ 1373 1374 1375 /* Fill in basic information */ 1376 sc->asic_addr = isa_dev->id_iobase + ED_HPP_ASIC_OFFSET; 1377 sc->nic_addr = isa_dev->id_iobase + ED_HPP_NIC_OFFSET; 1378 sc->is790 = 0; 1379 sc->isa16bit = 0; /* the 8390 core needs to be in byte mode */ 1380 1381 /* 1382 * Look for the HP PCLAN+ signature: "0x50,0x48,0x00,0x53" 1383 */ 1384 1385 if ((inb(sc->asic_addr + ED_HPP_ID) != 0x50) || 1386 (inb(sc->asic_addr + ED_HPP_ID + 1) != 0x48) || 1387 ((inb(sc->asic_addr + ED_HPP_ID + 2) & 0xF0) != 0) || 1388 (inb(sc->asic_addr + ED_HPP_ID + 3) != 0x53)) 1389 return 0; 1390 1391 /* 1392 * Read the MAC address and verify checksum on the address. 1393 */ 1394 1395 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_MAC); 1396 for (n = 0, checksum = 0; n < ETHER_ADDR_LEN; n++) 1397 checksum += (sc->arpcom.ac_enaddr[n] = 1398 inb(sc->asic_addr + ED_HPP_MAC_ADDR + n)); 1399 1400 checksum += inb(sc->asic_addr + ED_HPP_MAC_ADDR + ETHER_ADDR_LEN); 1401 1402 if (checksum != 0xFF) 1403 return 0; 1404 1405 /* 1406 * Verify that the software model number is 0. 1407 */ 1408 1409 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_ID); 1410 if (((sc->hpp_id = inw(sc->asic_addr + ED_HPP_PAGE_4)) & 1411 ED_HPP_ID_SOFT_MODEL_MASK) != 0x0000) 1412 return 0; 1413 1414 /* 1415 * Read in and save the current options configured on card. 1416 */ 1417 1418 sc->hpp_options = inw(sc->asic_addr + ED_HPP_OPTION); 1419 1420 sc->hpp_options |= (ED_HPP_OPTION_NIC_RESET | 1421 ED_HPP_OPTION_CHIP_RESET | 1422 ED_HPP_OPTION_ENABLE_IRQ); 1423 1424 /* 1425 * Reset the chip. This requires writing to the option register 1426 * so take care to preserve the other bits. 1427 */ 1428 1429 outw(sc->asic_addr + ED_HPP_OPTION, 1430 (sc->hpp_options & ~(ED_HPP_OPTION_NIC_RESET | 1431 ED_HPP_OPTION_CHIP_RESET))); 1432 1433 DELAY(5000); /* wait for chip reset to complete */ 1434 1435 outw(sc->asic_addr + ED_HPP_OPTION, 1436 (sc->hpp_options | (ED_HPP_OPTION_NIC_RESET | 1437 ED_HPP_OPTION_CHIP_RESET | 1438 ED_HPP_OPTION_ENABLE_IRQ))); 1439 1440 DELAY(5000); 1441 1442 if (!(inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RST)) 1443 return 0; /* reset did not complete */ 1444 1445 /* 1446 * Read out configuration information. 1447 */ 1448 1449 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_HW); 1450 1451 irq = inb(sc->asic_addr + ED_HPP_HW_IRQ); 1452 1453 /* 1454 * Check for impossible IRQ. 1455 */ 1456 1457 if (irq >= (sizeof(ed_hpp_intr_mask) / sizeof(ed_hpp_intr_mask[0]))) 1458 return 0; 1459 1460 /* 1461 * If the kernel IRQ was specified with a '?' use the cards idea 1462 * of the IRQ. If the kernel IRQ was explicitly specified, it 1463 * should match that of the hardware. 1464 */ 1465 1466 if (isa_dev->id_irq <= 0) 1467 isa_dev->id_irq = ed_hpp_intr_mask[irq]; 1468 else if (isa_dev->id_irq != ed_hpp_intr_mask[irq]) 1469 return 0; 1470 1471 /* 1472 * Fill in softconfig info. 1473 */ 1474 1475 sc->vendor = ED_VENDOR_HP; 1476 sc->type = ED_TYPE_HP_PCLANPLUS; 1477 sc->type_str = "HP-PCLAN+"; 1478 1479 sc->mem_shared = 0; /* we DON'T have dual ported RAM */ 1480 sc->mem_start = 0; /* we use offsets inside the card RAM */ 1481 1482 sc->hpp_mem_start = NULL;/* no memory mapped I/O by default */ 1483 1484 /* 1485 * Check if memory mapping of the I/O registers possible. 1486 */ 1487 1488 if (sc->hpp_options & ED_HPP_OPTION_MEM_ENABLE) 1489 { 1490 u_long mem_addr; 1491 1492 /* 1493 * determine the memory address from the board. 1494 */ 1495 1496 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_HW); 1497 mem_addr = (inw(sc->asic_addr + ED_HPP_HW_MEM_MAP) << 8); 1498 1499 /* 1500 * Check that the kernel specified start of memory and 1501 * hardware's idea of it match. 1502 */ 1503 1504 if (mem_addr != kvtop(isa_dev->id_maddr)) 1505 return 0; 1506 1507 sc->hpp_mem_start = isa_dev->id_maddr; 1508 } 1509 1510 /* 1511 * The board has 32KB of memory. Is there a way to determine 1512 * this programmatically? 1513 */ 1514 1515 memsize = 32768; 1516 1517 /* 1518 * Fill in the rest of the soft config structure. 1519 */ 1520 1521 /* 1522 * The transmit page index. 1523 */ 1524 1525 sc->tx_page_start = ED_HPP_TX_PAGE_OFFSET; 1526 1527 if (isa_dev->id_flags & ED_FLAGS_NO_MULTI_BUFFERING) 1528 sc->txb_cnt = 1; 1529 else 1530 sc->txb_cnt = 2; 1531 1532 /* 1533 * Memory description 1534 */ 1535 1536 sc->mem_size = memsize; 1537 sc->mem_ring = sc->mem_start + 1538 (sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE); 1539 sc->mem_end = sc->mem_start + sc->mem_size; 1540 1541 /* 1542 * Receive area starts after the transmit area and 1543 * continues till the end of memory. 1544 */ 1545 1546 sc->rec_page_start = sc->tx_page_start + 1547 (sc->txb_cnt * ED_TXBUF_SIZE); 1548 sc->rec_page_stop = (sc->mem_size / ED_PAGE_SIZE); 1549 1550 1551 sc->cr_proto = 0; /* value works */ 1552 1553 /* 1554 * Set the wrap registers for string I/O reads. 1555 */ 1556 1557 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_HW); 1558 outw(sc->asic_addr + ED_HPP_HW_WRAP, 1559 ((sc->rec_page_start / ED_PAGE_SIZE) | 1560 (((sc->rec_page_stop / ED_PAGE_SIZE) - 1) << 8))); 1561 1562 /* 1563 * Reset the register page to normal operation. 1564 */ 1565 1566 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_PERF); 1567 1568 /* 1569 * Verify that we can read/write from adapter memory. 1570 * Create test pattern. 1571 */ 1572 1573 for (n = 0; n < ED_HPP_TEST_SIZE; n++) 1574 { 1575 test_pattern[n] = (n*n) ^ ~n; 1576 } 1577 1578#undef ED_HPP_TEST_SIZE 1579 1580 /* 1581 * Check that the memory is accessible thru the I/O ports. 1582 * Write out the contents of "test_pattern", read back 1583 * into "test_buffer" and compare the two for any 1584 * mismatch. 1585 */ 1586 1587 for (n = 0; n < (32768 / ED_PAGE_SIZE); n ++) { 1588 1589 ed_pio_writemem(sc, test_pattern, (n * ED_PAGE_SIZE), 1590 sizeof(test_pattern)); 1591 ed_pio_readmem(sc, (n * ED_PAGE_SIZE), 1592 test_buffer, sizeof(test_pattern)); 1593 1594 if (bcmp(test_pattern, test_buffer, 1595 sizeof(test_pattern))) 1596 return 0; 1597 } 1598 1599 return (ED_HPP_IO_PORTS); 1600 1601} 1602 1603/* 1604 * HP PC Lan+ : Set the physical link to use AUI or TP/TL. 1605 */ 1606 1607void 1608ed_hpp_set_physical_link(struct ed_softc *sc) 1609{ 1610 struct ifnet *ifp = &sc->arpcom.ac_if; 1611 int lan_page; 1612 1613 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_LAN); 1614 lan_page = inw(sc->asic_addr + ED_HPP_PAGE_0); 1615 1616 if (ifp->if_flags & IFF_ALTPHYS) { 1617 1618 /* 1619 * Use the AUI port. 1620 */ 1621 1622 lan_page |= ED_HPP_LAN_AUI; 1623 1624 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_LAN); 1625 outw(sc->asic_addr + ED_HPP_PAGE_0, lan_page); 1626 1627 1628 } else { 1629 1630 /* 1631 * Use the ThinLan interface 1632 */ 1633 1634 lan_page &= ~ED_HPP_LAN_AUI; 1635 1636 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_LAN); 1637 outw(sc->asic_addr + ED_HPP_PAGE_0, lan_page); 1638 1639 } 1640 1641 /* 1642 * Wait for the lan card to re-initialize itself 1643 */ 1644 1645 DELAY(150000); /* wait 150 ms */ 1646 1647 /* 1648 * Restore normal pages. 1649 */ 1650 1651 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_PERF); 1652 1653} 1654 1655 1656/* 1657 * Install interface into kernel networking data structures 1658 */ 1659static int 1660ed_attach(sc, unit, flags) 1661 struct ed_softc *sc; 1662 int unit; 1663 int flags; 1664{ 1665 struct ifnet *ifp = &sc->arpcom.ac_if; 1666 1667 /* 1668 * Set interface to stopped condition (reset) 1669 */ 1670 ed_stop(sc); 1671 1672 if (!ifp->if_name) { 1673 /* 1674 * Initialize ifnet structure 1675 */ 1676 ifp->if_softc = sc; 1677 ifp->if_unit = unit; 1678 ifp->if_name = "ed"; 1679 ifp->if_output = ether_output; 1680 ifp->if_start = ed_start; 1681 ifp->if_ioctl = ed_ioctl; 1682 ifp->if_watchdog = ed_watchdog; 1683 ifp->if_init = ed_init; 1684 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 1685 ifp->if_linkmib = &sc->mibdata; 1686 ifp->if_linkmiblen = sizeof sc->mibdata; 1687 /* 1688 * XXX - should do a better job. 1689 */ 1690 if (sc->is790) 1691 sc->mibdata.dot3StatsEtherChipSet = 1692 DOT3CHIPSET(dot3VendorWesternDigital, 1693 dot3ChipSetWesternDigital83C790); 1694 else 1695 sc->mibdata.dot3StatsEtherChipSet = 1696 DOT3CHIPSET(dot3VendorNational, 1697 dot3ChipSetNational8390); 1698 sc->mibdata.dot3Compliance = DOT3COMPLIANCE_COLLS; 1699 1700 /* 1701 * Set default state for ALTPHYS flag (used to disable the 1702 * tranceiver for AUI operation), based on compile-time 1703 * config option. 1704 */ 1705 if (flags & ED_FLAGS_DISABLE_TRANCEIVER) 1706 ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX | 1707 IFF_MULTICAST | IFF_ALTPHYS); 1708 else 1709 ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX | 1710 IFF_MULTICAST); 1711 1712 /* 1713 * Attach the interface 1714 */ 1715 if_attach(ifp); 1716 ether_ifattach(ifp); 1717 } 1718 /* device attach does transition from UNCONFIGURED to IDLE state */ 1719 1720 /* 1721 * Print additional info when attached 1722 */ 1723 printf("%s%d: address %6D, ", ifp->if_name, ifp->if_unit, 1724 sc->arpcom.ac_enaddr, ":"); 1725 1726 if (sc->type_str && (*sc->type_str != 0)) 1727 printf("type %s ", sc->type_str); 1728 else 1729 printf("type unknown (0x%x) ", sc->type); 1730 1731 if (sc->vendor == ED_VENDOR_HP) 1732 printf("(%s %s IO)", (sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS) ? 1733 "16-bit" : "32-bit", 1734 sc->hpp_mem_start ? "memory mapped" : "regular"); 1735 else 1736 printf("%s ", sc->isa16bit ? "(16 bit)" : "(8 bit)"); 1737 1738 printf("%s\n", (((sc->vendor == ED_VENDOR_3COM) || 1739 (sc->vendor == ED_VENDOR_HP)) && 1740 (ifp->if_flags & IFF_ALTPHYS)) ? " tranceiver disabled" : ""); 1741 1742 /* 1743 * If BPF is in the kernel, call the attach for it 1744 */ 1745#if NBPFILTER > 0 1746 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header)); 1747#endif 1748 return 1; 1749} 1750 1751static int 1752ed_attach_isa(isa_dev) 1753 struct isa_device *isa_dev; 1754{ 1755 int unit = isa_dev->id_unit; 1756 struct ed_softc *sc = &ed_softc[unit]; 1757 int flags = isa_dev->id_flags; 1758 1759 return ed_attach(sc, unit, flags); 1760} 1761 1762#if NPCI > 0 1763void * 1764ed_attach_NE2000_pci(unit, port) 1765 int unit; 1766 int port; 1767{ 1768 struct ed_softc *sc = malloc(sizeof *sc, M_DEVBUF, M_NOWAIT); 1769 int isa_flags = 0; 1770 1771 if (!sc) 1772 return sc; 1773 1774 bzero(sc, sizeof *sc); 1775 if (ed_probe_Novell_generic(sc, port, unit, isa_flags) == 0 1776 || ed_attach(sc, unit, isa_flags) == 0) { 1777 free(sc, M_DEVBUF); 1778 return NULL; 1779 } 1780 return sc; 1781} 1782#endif 1783 1784/* 1785 * Reset interface. 1786 */ 1787static void 1788ed_reset(ifp) 1789 struct ifnet *ifp; 1790{ 1791 struct ed_softc *sc = ifp->if_softc; 1792 int s; 1793 1794 if (sc->gone) 1795 return; 1796 s = splimp(); 1797 1798 /* 1799 * Stop interface and re-initialize. 1800 */ 1801 ed_stop(sc); 1802 ed_init(sc); 1803 1804 (void) splx(s); 1805} 1806 1807/* 1808 * Take interface offline. 1809 */ 1810static void 1811ed_stop(sc) 1812 struct ed_softc *sc; 1813{ 1814 int n = 5000; 1815 1816 if (sc->gone) 1817 return; 1818 /* 1819 * Stop everything on the interface, and select page 0 registers. 1820 */ 1821 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP); 1822 1823 /* 1824 * Wait for interface to enter stopped state, but limit # of checks to 1825 * 'n' (about 5ms). It shouldn't even take 5us on modern DS8390's, but 1826 * just in case it's an old one. 1827 */ 1828 while (((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RST) == 0) && --n); 1829} 1830 1831/* 1832 * Device timeout/watchdog routine. Entered if the device neglects to 1833 * generate an interrupt after a transmit has been started on it. 1834 */ 1835static void 1836ed_watchdog(ifp) 1837 struct ifnet *ifp; 1838{ 1839 struct ed_softc *sc = ifp->if_softc; 1840 1841 if (sc->gone) 1842 return; 1843 log(LOG_ERR, "ed%d: device timeout\n", ifp->if_unit); 1844 ifp->if_oerrors++; 1845 1846 ed_reset(ifp); 1847} 1848 1849/* 1850 * Initialize device. 1851 */ 1852static void 1853ed_init(xsc) 1854 void *xsc; 1855{ 1856 struct ed_softc *sc = xsc; 1857 struct ifnet *ifp = &sc->arpcom.ac_if; 1858 int i, s; 1859 1860 if (sc->gone) 1861 return; 1862 1863 /* address not known */ 1864 if (TAILQ_EMPTY(&ifp->if_addrhead)) /* unlikely? XXX */ 1865 return; 1866 1867 /* 1868 * Initialize the NIC in the exact order outlined in the NS manual. 1869 * This init procedure is "mandatory"...don't change what or when 1870 * things happen. 1871 */ 1872 s = splimp(); 1873 1874 /* reset transmitter flags */ 1875 sc->xmit_busy = 0; 1876 ifp->if_timer = 0; 1877 1878 sc->txb_inuse = 0; 1879 sc->txb_new = 0; 1880 sc->txb_next_tx = 0; 1881 1882 /* This variable is used below - don't move this assignment */ 1883 sc->next_packet = sc->rec_page_start + 1; 1884 1885 /* 1886 * Set interface for page 0, Remote DMA complete, Stopped 1887 */ 1888 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP); 1889 1890 if (sc->isa16bit) { 1891 1892 /* 1893 * Set FIFO threshold to 8, No auto-init Remote DMA, byte 1894 * order=80x86, word-wide DMA xfers, 1895 */ 1896 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1 | ED_DCR_WTS | ED_DCR_LS); 1897 } else { 1898 1899 /* 1900 * Same as above, but byte-wide DMA xfers 1901 */ 1902 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS); 1903 } 1904 1905 /* 1906 * Clear Remote Byte Count Registers 1907 */ 1908 outb(sc->nic_addr + ED_P0_RBCR0, 0); 1909 outb(sc->nic_addr + ED_P0_RBCR1, 0); 1910 1911 /* 1912 * For the moment, don't store incoming packets in memory. 1913 */ 1914 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_MON); 1915 1916 /* 1917 * Place NIC in internal loopback mode 1918 */ 1919 outb(sc->nic_addr + ED_P0_TCR, ED_TCR_LB0); 1920 1921 /* 1922 * Initialize transmit/receive (ring-buffer) Page Start 1923 */ 1924 outb(sc->nic_addr + ED_P0_TPSR, sc->tx_page_start); 1925 outb(sc->nic_addr + ED_P0_PSTART, sc->rec_page_start); 1926 /* Set lower bits of byte addressable framing to 0 */ 1927 if (sc->is790) 1928 outb(sc->nic_addr + 0x09, 0); 1929 1930 /* 1931 * Initialize Receiver (ring-buffer) Page Stop and Boundry 1932 */ 1933 outb(sc->nic_addr + ED_P0_PSTOP, sc->rec_page_stop); 1934 outb(sc->nic_addr + ED_P0_BNRY, sc->rec_page_start); 1935 1936 /* 1937 * Clear all interrupts. A '1' in each bit position clears the 1938 * corresponding flag. 1939 */ 1940 outb(sc->nic_addr + ED_P0_ISR, 0xff); 1941 1942 /* 1943 * Enable the following interrupts: receive/transmit complete, 1944 * receive/transmit error, and Receiver OverWrite. 1945 * 1946 * Counter overflow and Remote DMA complete are *not* enabled. 1947 */ 1948 outb(sc->nic_addr + ED_P0_IMR, 1949 ED_IMR_PRXE | ED_IMR_PTXE | ED_IMR_RXEE | ED_IMR_TXEE | ED_IMR_OVWE); 1950 1951 /* 1952 * Program Command Register for page 1 1953 */ 1954 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP); 1955 1956 /* 1957 * Copy out our station address 1958 */ 1959 for (i = 0; i < ETHER_ADDR_LEN; ++i) 1960 outb(sc->nic_addr + ED_P1_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1961 1962 /* 1963 * Set Current Page pointer to next_packet (initialized above) 1964 */ 1965 outb(sc->nic_addr + ED_P1_CURR, sc->next_packet); 1966 1967 /* 1968 * Program Receiver Configuration Register and multicast filter. CR is 1969 * set to page 0 on return. 1970 */ 1971 ed_setrcr(sc); 1972 1973 /* 1974 * Take interface out of loopback 1975 */ 1976 outb(sc->nic_addr + ED_P0_TCR, 0); 1977 1978 /* 1979 * If this is a 3Com board, the tranceiver must be software enabled 1980 * (there is no settable hardware default). 1981 */ 1982 if (sc->vendor == ED_VENDOR_3COM) { 1983 if (ifp->if_flags & IFF_ALTPHYS) { 1984 outb(sc->asic_addr + ED_3COM_CR, 0); 1985 } else { 1986 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL); 1987 } 1988 } 1989 1990 /* 1991 * Set 'running' flag, and clear output active flag. 1992 */ 1993 ifp->if_flags |= IFF_RUNNING; 1994 ifp->if_flags &= ~IFF_OACTIVE; 1995 1996 /* 1997 * ...and attempt to start output 1998 */ 1999 ed_start(ifp); 2000 2001 (void) splx(s); 2002} 2003 2004/* 2005 * This routine actually starts the transmission on the interface 2006 */ 2007static inline void 2008ed_xmit(sc) 2009 struct ed_softc *sc; 2010{ 2011 struct ifnet *ifp = (struct ifnet *)sc; 2012 unsigned short len; 2013 2014 if (sc->gone) 2015 return; 2016 len = sc->txb_len[sc->txb_next_tx]; 2017 2018 /* 2019 * Set NIC for page 0 register access 2020 */ 2021 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA); 2022 2023 /* 2024 * Set TX buffer start page 2025 */ 2026 outb(sc->nic_addr + ED_P0_TPSR, sc->tx_page_start + 2027 sc->txb_next_tx * ED_TXBUF_SIZE); 2028 2029 /* 2030 * Set TX length 2031 */ 2032 outb(sc->nic_addr + ED_P0_TBCR0, len); 2033 outb(sc->nic_addr + ED_P0_TBCR1, len >> 8); 2034 2035 /* 2036 * Set page 0, Remote DMA complete, Transmit Packet, and *Start* 2037 */ 2038 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_TXP | ED_CR_STA); 2039 sc->xmit_busy = 1; 2040 2041 /* 2042 * Point to next transmit buffer slot and wrap if necessary. 2043 */ 2044 sc->txb_next_tx++; 2045 if (sc->txb_next_tx == sc->txb_cnt) 2046 sc->txb_next_tx = 0; 2047 2048 /* 2049 * Set a timer just in case we never hear from the board again 2050 */ 2051 ifp->if_timer = 2; 2052} 2053 2054/* 2055 * Start output on interface. 2056 * We make two assumptions here: 2057 * 1) that the current priority is set to splimp _before_ this code 2058 * is called *and* is returned to the appropriate priority after 2059 * return 2060 * 2) that the IFF_OACTIVE flag is checked before this code is called 2061 * (i.e. that the output part of the interface is idle) 2062 */ 2063static void 2064ed_start(ifp) 2065 struct ifnet *ifp; 2066{ 2067 struct ed_softc *sc = ifp->if_softc; 2068 struct mbuf *m0, *m; 2069 caddr_t buffer; 2070 int len; 2071 2072 if (sc->gone) { 2073 printf("ed_start(%p) GONE\n",ifp); 2074 return; 2075 } 2076outloop: 2077 2078 /* 2079 * First, see if there are buffered packets and an idle transmitter - 2080 * should never happen at this point. 2081 */ 2082 if (sc->txb_inuse && (sc->xmit_busy == 0)) { 2083 printf("ed: packets buffered, but transmitter idle\n"); 2084 ed_xmit(sc); 2085 } 2086 2087 /* 2088 * See if there is room to put another packet in the buffer. 2089 */ 2090 if (sc->txb_inuse == sc->txb_cnt) { 2091 2092 /* 2093 * No room. Indicate this to the outside world and exit. 2094 */ 2095 ifp->if_flags |= IFF_OACTIVE; 2096 return; 2097 } 2098 IF_DEQUEUE(&ifp->if_snd, m); 2099 if (m == 0) { 2100 2101 /* 2102 * We are using the !OACTIVE flag to indicate to the outside 2103 * world that we can accept an additional packet rather than 2104 * that the transmitter is _actually_ active. Indeed, the 2105 * transmitter may be active, but if we haven't filled all the 2106 * buffers with data then we still want to accept more. 2107 */ 2108 ifp->if_flags &= ~IFF_OACTIVE; 2109 return; 2110 } 2111 2112 /* 2113 * Copy the mbuf chain into the transmit buffer 2114 */ 2115 2116 m0 = m; 2117 2118 /* txb_new points to next open buffer slot */ 2119 buffer = sc->mem_start + (sc->txb_new * ED_TXBUF_SIZE * ED_PAGE_SIZE); 2120 2121 if (sc->mem_shared) { 2122 2123 /* 2124 * Special case setup for 16 bit boards... 2125 */ 2126 if (sc->isa16bit) { 2127 switch (sc->vendor) { 2128 2129 /* 2130 * For 16bit 3Com boards (which have 16k of 2131 * memory), we have the xmit buffers in a 2132 * different page of memory ('page 0') - so 2133 * change pages. 2134 */ 2135 case ED_VENDOR_3COM: 2136 outb(sc->asic_addr + ED_3COM_GACFR, 2137 ED_3COM_GACFR_RSEL); 2138 break; 2139 2140 /* 2141 * Enable 16bit access to shared memory on 2142 * WD/SMC boards. 2143 */ 2144 case ED_VENDOR_WD_SMC:{ 2145 outb(sc->asic_addr + ED_WD_LAAR, 2146 (sc->wd_laar_proto | ED_WD_LAAR_M16EN)); 2147 if (sc->is790) { 2148 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_MENB); 2149 } 2150 break; 2151 } 2152 } 2153 } 2154 for (len = 0; m != 0; m = m->m_next) { 2155 bcopy(mtod(m, caddr_t), buffer, m->m_len); 2156 buffer += m->m_len; 2157 len += m->m_len; 2158 } 2159 2160 /* 2161 * Restore previous shared memory access 2162 */ 2163 if (sc->isa16bit) { 2164 switch (sc->vendor) { 2165 case ED_VENDOR_3COM: 2166 outb(sc->asic_addr + ED_3COM_GACFR, 2167 ED_3COM_GACFR_RSEL | ED_3COM_GACFR_MBS0); 2168 break; 2169 case ED_VENDOR_WD_SMC:{ 2170 if (sc->is790) { 2171 outb(sc->asic_addr + ED_WD_MSR, 0x00); 2172 } 2173 outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto); 2174 break; 2175 } 2176 } 2177 } 2178 } else { 2179 len = ed_pio_write_mbufs(sc, m, (int)buffer); 2180 if (len == 0) 2181 goto outloop; 2182 } 2183 2184 sc->txb_len[sc->txb_new] = max(len, (ETHER_MIN_LEN-ETHER_CRC_LEN)); 2185 2186 sc->txb_inuse++; 2187 2188 /* 2189 * Point to next buffer slot and wrap if necessary. 2190 */ 2191 sc->txb_new++; 2192 if (sc->txb_new == sc->txb_cnt) 2193 sc->txb_new = 0; 2194 2195 if (sc->xmit_busy == 0) 2196 ed_xmit(sc); 2197 2198 /* 2199 * Tap off here if there is a bpf listener. 2200 */ 2201#if NBPFILTER > 0 2202 if (ifp->if_bpf) { 2203 bpf_mtap(ifp, m0); 2204 } 2205#endif 2206 2207 m_freem(m0); 2208 2209 /* 2210 * Loop back to the top to possibly buffer more packets 2211 */ 2212 goto outloop; 2213} 2214 2215/* 2216 * Ethernet interface receiver interrupt. 2217 */ 2218static inline void 2219ed_rint(sc) 2220 struct ed_softc *sc; 2221{ 2222 struct ifnet *ifp = &sc->arpcom.ac_if; 2223 u_char boundry; 2224 u_short len; 2225 struct ed_ring packet_hdr; 2226 char *packet_ptr; 2227 2228 if (sc->gone) 2229 return; 2230 2231 /* 2232 * Set NIC to page 1 registers to get 'current' pointer 2233 */ 2234 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA); 2235 2236 /* 2237 * 'sc->next_packet' is the logical beginning of the ring-buffer - 2238 * i.e. it points to where new data has been buffered. The 'CURR' 2239 * (current) register points to the logical end of the ring-buffer - 2240 * i.e. it points to where additional new data will be added. We loop 2241 * here until the logical beginning equals the logical end (or in 2242 * other words, until the ring-buffer is empty). 2243 */ 2244 while (sc->next_packet != inb(sc->nic_addr + ED_P1_CURR)) { 2245 2246 /* get pointer to this buffer's header structure */ 2247 packet_ptr = sc->mem_ring + 2248 (sc->next_packet - sc->rec_page_start) * ED_PAGE_SIZE; 2249 2250 /* 2251 * The byte count includes a 4 byte header that was added by 2252 * the NIC. 2253 */ 2254 if (sc->mem_shared) 2255 packet_hdr = *(struct ed_ring *) packet_ptr; 2256 else 2257 ed_pio_readmem(sc, (int)packet_ptr, (char *) &packet_hdr, 2258 sizeof(packet_hdr)); 2259 len = packet_hdr.count; 2260 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring)) || 2261 len < (ETHER_MIN_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring))) { 2262 /* 2263 * Length is a wild value. There's a good chance that 2264 * this was caused by the NIC being old and buggy. 2265 * The bug is that the length low byte is duplicated in 2266 * the high byte. Try to recalculate the length based on 2267 * the pointer to the next packet. 2268 */ 2269 /* 2270 * NOTE: sc->next_packet is pointing at the current packet. 2271 */ 2272 len &= ED_PAGE_SIZE - 1; /* preserve offset into page */ 2273 if (packet_hdr.next_packet >= sc->next_packet) { 2274 len += (packet_hdr.next_packet - sc->next_packet) * ED_PAGE_SIZE; 2275 } else { 2276 len += ((packet_hdr.next_packet - sc->rec_page_start) + 2277 (sc->rec_page_stop - sc->next_packet)) * ED_PAGE_SIZE; 2278 } 2279 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN 2280 + sizeof(struct ed_ring))) 2281 sc->mibdata.dot3StatsFrameTooLongs++; 2282 } 2283 /* 2284 * Be fairly liberal about what we allow as a "reasonable" length 2285 * so that a [crufty] packet will make it to BPF (and can thus 2286 * be analyzed). Note that all that is really important is that 2287 * we have a length that will fit into one mbuf cluster or less; 2288 * the upper layer protocols can then figure out the length from 2289 * their own length field(s). 2290 */ 2291 if ((len > sizeof(struct ed_ring)) && 2292 (len <= MCLBYTES) && 2293 (packet_hdr.next_packet >= sc->rec_page_start) && 2294 (packet_hdr.next_packet < sc->rec_page_stop)) { 2295 /* 2296 * Go get packet. 2297 */ 2298 ed_get_packet(sc, packet_ptr + sizeof(struct ed_ring), 2299 len - sizeof(struct ed_ring), packet_hdr.rsr & ED_RSR_PHY); 2300 ifp->if_ipackets++; 2301 } else { 2302 /* 2303 * Really BAD. The ring pointers are corrupted. 2304 */ 2305 log(LOG_ERR, 2306 "ed%d: NIC memory corrupt - invalid packet length %d\n", 2307 ifp->if_unit, len); 2308 ifp->if_ierrors++; 2309 ed_reset(ifp); 2310 return; 2311 } 2312 2313 /* 2314 * Update next packet pointer 2315 */ 2316 sc->next_packet = packet_hdr.next_packet; 2317 2318 /* 2319 * Update NIC boundry pointer - being careful to keep it one 2320 * buffer behind. (as recommended by NS databook) 2321 */ 2322 boundry = sc->next_packet - 1; 2323 if (boundry < sc->rec_page_start) 2324 boundry = sc->rec_page_stop - 1; 2325 2326 /* 2327 * Set NIC to page 0 registers to update boundry register 2328 */ 2329 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA); 2330 2331 outb(sc->nic_addr + ED_P0_BNRY, boundry); 2332 2333 /* 2334 * Set NIC to page 1 registers before looping to top (prepare 2335 * to get 'CURR' current pointer) 2336 */ 2337 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA); 2338 } 2339} 2340 2341/* 2342 * Ethernet interface interrupt processor 2343 */ 2344void 2345edintr_sc(sc) 2346 struct ed_softc *sc; 2347{ 2348 struct ifnet *ifp = (struct ifnet *)sc; 2349 u_char isr; 2350 2351 if (sc->gone) 2352 return; 2353 /* 2354 * Set NIC to page 0 registers 2355 */ 2356 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA); 2357 2358 /* 2359 * loop until there are no more new interrupts 2360 */ 2361 while ((isr = inb(sc->nic_addr + ED_P0_ISR)) != 0) { 2362 2363 /* 2364 * reset all the bits that we are 'acknowledging' by writing a 2365 * '1' to each bit position that was set (writing a '1' 2366 * *clears* the bit) 2367 */ 2368 outb(sc->nic_addr + ED_P0_ISR, isr); 2369 2370 /* 2371 * Handle transmitter interrupts. Handle these first because 2372 * the receiver will reset the board under some conditions. 2373 */ 2374 if (isr & (ED_ISR_PTX | ED_ISR_TXE)) { 2375 u_char collisions = inb(sc->nic_addr + ED_P0_NCR) & 0x0f; 2376 2377 /* 2378 * Check for transmit error. If a TX completed with an 2379 * error, we end up throwing the packet away. Really 2380 * the only error that is possible is excessive 2381 * collisions, and in this case it is best to allow 2382 * the automatic mechanisms of TCP to backoff the 2383 * flow. Of course, with UDP we're screwed, but this 2384 * is expected when a network is heavily loaded. 2385 */ 2386 (void) inb(sc->nic_addr + ED_P0_TSR); 2387 if (isr & ED_ISR_TXE) { 2388 u_char tsr; 2389 2390 /* 2391 * Excessive collisions (16) 2392 */ 2393 tsr = inb(sc->nic_addr + ED_P0_TSR); 2394 if ((tsr & ED_TSR_ABT) 2395 && (collisions == 0)) { 2396 2397 /* 2398 * When collisions total 16, the 2399 * P0_NCR will indicate 0, and the 2400 * TSR_ABT is set. 2401 */ 2402 collisions = 16; 2403 sc->mibdata.dot3StatsExcessiveCollisions++; 2404 sc->mibdata.dot3StatsCollFrequencies[15]++; 2405 } 2406 if (tsr & ED_TSR_OWC) 2407 sc->mibdata.dot3StatsLateCollisions++; 2408 if (tsr & ED_TSR_CDH) 2409 sc->mibdata.dot3StatsSQETestErrors++; 2410 if (tsr & ED_TSR_CRS) 2411 sc->mibdata.dot3StatsCarrierSenseErrors++; 2412 if (tsr & ED_TSR_FU) 2413 sc->mibdata.dot3StatsInternalMacTransmitErrors++; 2414 2415 /* 2416 * update output errors counter 2417 */ 2418 ifp->if_oerrors++; 2419 } else { 2420 2421 /* 2422 * Update total number of successfully 2423 * transmitted packets. 2424 */ 2425 ifp->if_opackets++; 2426 } 2427 2428 /* 2429 * reset tx busy and output active flags 2430 */ 2431 sc->xmit_busy = 0; 2432 ifp->if_flags &= ~IFF_OACTIVE; 2433 2434 /* 2435 * clear watchdog timer 2436 */ 2437 ifp->if_timer = 0; 2438 2439 /* 2440 * Add in total number of collisions on last 2441 * transmission. 2442 */ 2443 ifp->if_collisions += collisions; 2444 switch(collisions) { 2445 case 0: 2446 case 16: 2447 break; 2448 case 1: 2449 sc->mibdata.dot3StatsSingleCollisionFrames++; 2450 sc->mibdata.dot3StatsCollFrequencies[0]++; 2451 break; 2452 default: 2453 sc->mibdata.dot3StatsMultipleCollisionFrames++; 2454 sc->mibdata. 2455 dot3StatsCollFrequencies[collisions-1] 2456 ++; 2457 break; 2458 } 2459 2460 /* 2461 * Decrement buffer in-use count if not zero (can only 2462 * be zero if a transmitter interrupt occured while 2463 * not actually transmitting). If data is ready to 2464 * transmit, start it transmitting, otherwise defer 2465 * until after handling receiver 2466 */ 2467 if (sc->txb_inuse && --sc->txb_inuse) 2468 ed_xmit(sc); 2469 } 2470 2471 /* 2472 * Handle receiver interrupts 2473 */ 2474 if (isr & (ED_ISR_PRX | ED_ISR_RXE | ED_ISR_OVW)) { 2475 2476 /* 2477 * Overwrite warning. In order to make sure that a 2478 * lockup of the local DMA hasn't occurred, we reset 2479 * and re-init the NIC. The NSC manual suggests only a 2480 * partial reset/re-init is necessary - but some chips 2481 * seem to want more. The DMA lockup has been seen 2482 * only with early rev chips - Methinks this bug was 2483 * fixed in later revs. -DG 2484 */ 2485 if (isr & ED_ISR_OVW) { 2486 ifp->if_ierrors++; 2487#ifdef DIAGNOSTIC 2488 log(LOG_WARNING, 2489 "ed%d: warning - receiver ring buffer overrun\n", 2490 ifp->if_unit); 2491#endif 2492 2493 /* 2494 * Stop/reset/re-init NIC 2495 */ 2496 ed_reset(ifp); 2497 } else { 2498 2499 /* 2500 * Receiver Error. One or more of: CRC error, 2501 * frame alignment error FIFO overrun, or 2502 * missed packet. 2503 */ 2504 if (isr & ED_ISR_RXE) { 2505 u_char rsr; 2506 rsr = inb(sc->nic_addr + ED_P0_RSR); 2507 if (rsr & ED_RSR_CRC) 2508 sc->mibdata.dot3StatsFCSErrors++; 2509 if (rsr & ED_RSR_FAE) 2510 sc->mibdata.dot3StatsAlignmentErrors++; 2511 if (rsr & ED_RSR_FO) 2512 sc->mibdata.dot3StatsInternalMacReceiveErrors++; 2513 ifp->if_ierrors++; 2514#ifdef ED_DEBUG 2515 printf("ed%d: receive error %x\n", ifp->if_unit, 2516 inb(sc->nic_addr + ED_P0_RSR)); 2517#endif 2518 } 2519 2520 /* 2521 * Go get the packet(s) XXX - Doing this on an 2522 * error is dubious because there shouldn't be 2523 * any data to get (we've configured the 2524 * interface to not accept packets with 2525 * errors). 2526 */ 2527 2528 /* 2529 * Enable 16bit access to shared memory first 2530 * on WD/SMC boards. 2531 */ 2532 if (sc->isa16bit && 2533 (sc->vendor == ED_VENDOR_WD_SMC)) { 2534 2535 outb(sc->asic_addr + ED_WD_LAAR, 2536 (sc->wd_laar_proto |= 2537 ED_WD_LAAR_M16EN)); 2538 if (sc->is790) { 2539 outb(sc->asic_addr + ED_WD_MSR, 2540 ED_WD_MSR_MENB); 2541 } 2542 } 2543 ed_rint(sc); 2544 2545 /* disable 16bit access */ 2546 if (sc->isa16bit && 2547 (sc->vendor == ED_VENDOR_WD_SMC)) { 2548 2549 if (sc->is790) { 2550 outb(sc->asic_addr + ED_WD_MSR, 0x00); 2551 } 2552 outb(sc->asic_addr + ED_WD_LAAR, 2553 (sc->wd_laar_proto &= 2554 ~ED_WD_LAAR_M16EN)); 2555 } 2556 } 2557 } 2558 2559 /* 2560 * If it looks like the transmitter can take more data, 2561 * attempt to start output on the interface. This is done 2562 * after handling the receiver to give the receiver priority. 2563 */ 2564 if ((ifp->if_flags & IFF_OACTIVE) == 0) 2565 ed_start(ifp); 2566 2567 /* 2568 * return NIC CR to standard state: page 0, remote DMA 2569 * complete, start (toggling the TXP bit off, even if was just 2570 * set in the transmit routine, is *okay* - it is 'edge' 2571 * triggered from low to high) 2572 */ 2573 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA); 2574 2575 /* 2576 * If the Network Talley Counters overflow, read them to reset 2577 * them. It appears that old 8390's won't clear the ISR flag 2578 * otherwise - resulting in an infinite loop. 2579 */ 2580 if (isr & ED_ISR_CNT) { 2581 (void) inb(sc->nic_addr + ED_P0_CNTR0); 2582 (void) inb(sc->nic_addr + ED_P0_CNTR1); 2583 (void) inb(sc->nic_addr + ED_P0_CNTR2); 2584 } 2585 } 2586} 2587 2588void 2589edintr(unit) 2590 int unit; 2591{ 2592 edintr_sc (&ed_softc[unit]); 2593} 2594 2595/* 2596 * Process an ioctl request. This code needs some work - it looks 2597 * pretty ugly. 2598 */ 2599static int 2600ed_ioctl(ifp, command, data) 2601 register struct ifnet *ifp; 2602 int command; 2603 caddr_t data; 2604{ 2605 struct ed_softc *sc = ifp->if_softc; 2606 struct ifreq *ifr = (struct ifreq *) data; 2607 int s, error = 0; 2608 2609 if (sc->gone) { 2610 ifp->if_flags &= ~IFF_RUNNING; 2611 return ENXIO; 2612 } 2613 s = splimp(); 2614 2615 switch (command) { 2616 2617 case SIOCSIFADDR: 2618 case SIOCGIFADDR: 2619 case SIOCSIFMTU: 2620 error = ether_ioctl(ifp, command, data); 2621 break; 2622 2623 case SIOCSIFFLAGS: 2624 2625 /* 2626 * If the interface is marked up and stopped, then start it. 2627 * If it is marked down and running, then stop it. 2628 */ 2629 if (ifp->if_flags & IFF_UP) { 2630 if ((ifp->if_flags & IFF_RUNNING) == 0) 2631 ed_init(sc); 2632 } else { 2633 if (ifp->if_flags & IFF_RUNNING) { 2634 ed_stop(sc); 2635 ifp->if_flags &= ~IFF_RUNNING; 2636 } 2637 } 2638 2639#if NBPFILTER > 0 2640 2641 /* 2642 * Promiscuous flag may have changed, so reprogram the RCR. 2643 */ 2644 ed_setrcr(sc); 2645#endif 2646 2647 /* 2648 * An unfortunate hack to provide the (required) software 2649 * control of the tranceiver for 3Com boards. The ALTPHYS flag 2650 * disables the tranceiver if set. 2651 */ 2652 if (sc->vendor == ED_VENDOR_3COM) { 2653 if (ifp->if_flags & IFF_ALTPHYS) { 2654 outb(sc->asic_addr + ED_3COM_CR, 0); 2655 } else { 2656 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL); 2657 } 2658 } else if (sc->vendor == ED_VENDOR_HP) 2659 ed_hpp_set_physical_link(sc); 2660 break; 2661 2662 case SIOCADDMULTI: 2663 case SIOCDELMULTI: 2664 /* 2665 * Multicast list has changed; set the hardware filter 2666 * accordingly. 2667 */ 2668 ed_setrcr(sc); 2669 error = 0; 2670 break; 2671 2672 default: 2673 error = EINVAL; 2674 } 2675 (void) splx(s); 2676 return (error); 2677} 2678 2679/* 2680 * Given a source and destination address, copy 'amount' of a packet from 2681 * the ring buffer into a linear destination buffer. Takes into account 2682 * ring-wrap. 2683 */ 2684static inline char * 2685ed_ring_copy(sc, src, dst, amount) 2686 struct ed_softc *sc; 2687 char *src; 2688 char *dst; 2689 u_short amount; 2690{ 2691 u_short tmp_amount; 2692 2693 /* does copy wrap to lower addr in ring buffer? */ 2694 if (src + amount > sc->mem_end) { 2695 tmp_amount = sc->mem_end - src; 2696 2697 /* copy amount up to end of NIC memory */ 2698 if (sc->mem_shared) 2699 bcopy(src, dst, tmp_amount); 2700 else 2701 ed_pio_readmem(sc, (int)src, dst, tmp_amount); 2702 2703 amount -= tmp_amount; 2704 src = sc->mem_ring; 2705 dst += tmp_amount; 2706 } 2707 if (sc->mem_shared) 2708 bcopy(src, dst, amount); 2709 else 2710 ed_pio_readmem(sc, (int)src, dst, amount); 2711 2712 return (src + amount); 2713} 2714 2715/* 2716 * Retreive packet from shared memory and send to the next level up via 2717 * ether_input(). If there is a BPF listener, give a copy to BPF, too. 2718 */ 2719static void 2720ed_get_packet(sc, buf, len, multicast) 2721 struct ed_softc *sc; 2722 char *buf; 2723 u_short len; 2724 int multicast; 2725{ 2726 struct ether_header *eh; 2727 struct mbuf *m; 2728 2729 /* Allocate a header mbuf */ 2730 MGETHDR(m, M_DONTWAIT, MT_DATA); 2731 if (m == NULL) 2732 return; 2733 m->m_pkthdr.rcvif = &sc->arpcom.ac_if; 2734 m->m_pkthdr.len = m->m_len = len; 2735 2736 /* 2737 * We always put the received packet in a single buffer - 2738 * either with just an mbuf header or in a cluster attached 2739 * to the header. The +2 is to compensate for the alignment 2740 * fixup below. 2741 */ 2742 if ((len + 2) > MHLEN) { 2743 /* Attach an mbuf cluster */ 2744 MCLGET(m, M_DONTWAIT); 2745 2746 /* Insist on getting a cluster */ 2747 if ((m->m_flags & M_EXT) == 0) { 2748 m_freem(m); 2749 return; 2750 } 2751 } 2752 2753 /* 2754 * The +2 is to longword align the start of the real packet. 2755 * This is important for NFS. 2756 */ 2757 m->m_data += 2; 2758 eh = mtod(m, struct ether_header *); 2759 2760 /* 2761 * Get packet, including link layer address, from interface. 2762 */ 2763 ed_ring_copy(sc, buf, (char *)eh, len); 2764 2765#if NBPFILTER > 0 2766 2767 /* 2768 * Check if there's a BPF listener on this interface. If so, hand off 2769 * the raw packet to bpf. 2770 */ 2771 if (sc->arpcom.ac_if.if_bpf) { 2772 bpf_mtap(&sc->arpcom.ac_if, m); 2773 2774 /* 2775 * Note that the interface cannot be in promiscuous mode if 2776 * there are no BPF listeners. And if we are in promiscuous 2777 * mode, we have to check if this packet is really ours. 2778 */ 2779 if ((sc->arpcom.ac_if.if_flags & IFF_PROMISC) && 2780 bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr, 2781 sizeof(eh->ether_dhost)) != 0 && multicast == 0) { 2782 m_freem(m); 2783 return; 2784 } 2785 } 2786#endif 2787 2788 /* 2789 * Remove link layer address. 2790 */ 2791 m->m_pkthdr.len = m->m_len = len - sizeof(struct ether_header); 2792 m->m_data += sizeof(struct ether_header); 2793 2794 ether_input(&sc->arpcom.ac_if, eh, m); 2795 return; 2796} 2797 2798/* 2799 * Supporting routines 2800 */ 2801 2802/* 2803 * Given a NIC memory source address and a host memory destination 2804 * address, copy 'amount' from NIC to host using Programmed I/O. 2805 * The 'amount' is rounded up to a word - okay as long as mbufs 2806 * are word sized. 2807 * This routine is currently Novell-specific. 2808 */ 2809static void 2810ed_pio_readmem(sc, src, dst, amount) 2811 struct ed_softc *sc; 2812 int src; 2813 unsigned char *dst; 2814 unsigned short amount; 2815{ 2816 /* HP cards need special handling */ 2817 if (sc->vendor == ED_VENDOR_HP && sc->type == ED_TYPE_HP_PCLANPLUS) { 2818 ed_hpp_readmem(sc, src, dst, amount); 2819 return; 2820 } 2821 2822 /* Regular Novell cards */ 2823 /* select page 0 registers */ 2824 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STA); 2825 2826 /* round up to a word */ 2827 if (amount & 1) 2828 ++amount; 2829 2830 /* set up DMA byte count */ 2831 outb(sc->nic_addr + ED_P0_RBCR0, amount); 2832 outb(sc->nic_addr + ED_P0_RBCR1, amount >> 8); 2833 2834 /* set up source address in NIC mem */ 2835 outb(sc->nic_addr + ED_P0_RSAR0, src); 2836 outb(sc->nic_addr + ED_P0_RSAR1, src >> 8); 2837 2838 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD0 | ED_CR_STA); 2839 2840 if (sc->isa16bit) { 2841 insw(sc->asic_addr + ED_NOVELL_DATA, dst, amount / 2); 2842 } else 2843 insb(sc->asic_addr + ED_NOVELL_DATA, dst, amount); 2844 2845} 2846 2847/* 2848 * Stripped down routine for writing a linear buffer to NIC memory. 2849 * Only used in the probe routine to test the memory. 'len' must 2850 * be even. 2851 */ 2852static void 2853ed_pio_writemem(sc, src, dst, len) 2854 struct ed_softc *sc; 2855 char *src; 2856 unsigned short dst; 2857 unsigned short len; 2858{ 2859 int maxwait = 200; /* about 240us */ 2860 2861 if (sc->vendor == ED_VENDOR_NOVELL) { 2862 2863 /* select page 0 registers */ 2864 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STA); 2865 2866 /* reset remote DMA complete flag */ 2867 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC); 2868 2869 /* set up DMA byte count */ 2870 outb(sc->nic_addr + ED_P0_RBCR0, len); 2871 outb(sc->nic_addr + ED_P0_RBCR1, len >> 8); 2872 2873 /* set up destination address in NIC mem */ 2874 outb(sc->nic_addr + ED_P0_RSAR0, dst); 2875 outb(sc->nic_addr + ED_P0_RSAR1, dst >> 8); 2876 2877 /* set remote DMA write */ 2878 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD1 | ED_CR_STA); 2879 2880 if (sc->isa16bit) 2881 outsw(sc->asic_addr + ED_NOVELL_DATA, src, len / 2); 2882 else 2883 outsb(sc->asic_addr + ED_NOVELL_DATA, src, len); 2884 2885 /* 2886 * Wait for remote DMA complete. This is necessary because on the 2887 * transmit side, data is handled internally by the NIC in bursts and 2888 * we can't start another remote DMA until this one completes. Not 2889 * waiting causes really bad things to happen - like the NIC 2890 * irrecoverably jamming the ISA bus. 2891 */ 2892 while (((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait); 2893 2894 } else if ((sc->vendor == ED_VENDOR_HP) && 2895 (sc->type == ED_TYPE_HP_PCLANPLUS)) { 2896 2897 /* HP PCLAN+ */ 2898 2899 /* reset remote DMA complete flag */ 2900 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC); 2901 2902 /* program the write address in RAM */ 2903 outw(sc->asic_addr + ED_HPP_PAGE_0, dst); 2904 2905 if (sc->hpp_mem_start) { 2906 u_short *s = (u_short *) src; 2907 volatile u_short *d = (u_short *) sc->hpp_mem_start; 2908 u_short *const fence = s + (len >> 1); 2909 2910 /* 2911 * Enable memory mapped access. 2912 */ 2913 2914 outw(sc->asic_addr + ED_HPP_OPTION, 2915 sc->hpp_options & 2916 ~(ED_HPP_OPTION_MEM_DISABLE | 2917 ED_HPP_OPTION_BOOT_ROM_ENB)); 2918 2919 /* 2920 * Copy to NIC memory. 2921 */ 2922 2923 while (s < fence) 2924 *d = *s++; 2925 2926 /* 2927 * Restore Boot ROM access. 2928 */ 2929 2930 outw(sc->asic_addr + ED_HPP_OPTION, 2931 sc->hpp_options); 2932 2933 } else { 2934 /* write data using I/O writes */ 2935 outsw(sc->asic_addr + ED_HPP_PAGE_4, src, len / 2); 2936 } 2937 2938 } 2939} 2940 2941/* 2942 * Write an mbuf chain to the destination NIC memory address using 2943 * programmed I/O. 2944 */ 2945static u_short 2946ed_pio_write_mbufs(sc, m, dst) 2947 struct ed_softc *sc; 2948 struct mbuf *m; 2949 int dst; 2950{ 2951 struct ifnet *ifp = (struct ifnet *)sc; 2952 unsigned short total_len, dma_len; 2953 struct mbuf *mp; 2954 int maxwait = 200; /* about 240us */ 2955 2956 /* HP PC Lan+ cards need special handling */ 2957 if ((sc->vendor == ED_VENDOR_HP) && 2958 (sc->type == ED_TYPE_HP_PCLANPLUS)) { 2959 return ed_hpp_write_mbufs(sc, m, dst); 2960 } 2961 2962 /* First, count up the total number of bytes to copy */ 2963 for (total_len = 0, mp = m; mp; mp = mp->m_next) 2964 total_len += mp->m_len; 2965 2966 dma_len = total_len; 2967 if (sc->isa16bit && (dma_len & 1)) 2968 dma_len++; 2969 2970 /* select page 0 registers */ 2971 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STA); 2972 2973 /* reset remote DMA complete flag */ 2974 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC); 2975 2976 /* set up DMA byte count */ 2977 outb(sc->nic_addr + ED_P0_RBCR0, dma_len); 2978 outb(sc->nic_addr + ED_P0_RBCR1, dma_len >> 8); 2979 2980 /* set up destination address in NIC mem */ 2981 outb(sc->nic_addr + ED_P0_RSAR0, dst); 2982 outb(sc->nic_addr + ED_P0_RSAR1, dst >> 8); 2983 2984 /* set remote DMA write */ 2985 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD1 | ED_CR_STA); 2986 2987 /* 2988 * Transfer the mbuf chain to the NIC memory. 2989 * 16-bit cards require that data be transferred as words, and only words. 2990 * So that case requires some extra code to patch over odd-length mbufs. 2991 */ 2992 2993 if (!sc->isa16bit) { 2994 /* NE1000s are easy */ 2995 while (m) { 2996 if (m->m_len) { 2997 outsb(sc->asic_addr + ED_NOVELL_DATA, 2998 m->m_data, m->m_len); 2999 } 3000 m = m->m_next; 3001 } 3002 } else { 3003 /* NE2000s are a pain */ 3004 unsigned char *data; 3005 int len, wantbyte; 3006 unsigned char savebyte[2]; 3007 3008 wantbyte = 0; 3009 3010 while (m) { 3011 len = m->m_len; 3012 if (len) { 3013 data = mtod(m, caddr_t); 3014 /* finish the last word */ 3015 if (wantbyte) { 3016 savebyte[1] = *data; 3017 outw(sc->asic_addr + ED_NOVELL_DATA, *(u_short *)savebyte); 3018 data++; 3019 len--; 3020 wantbyte = 0; 3021 } 3022 /* output contiguous words */ 3023 if (len > 1) { 3024 outsw(sc->asic_addr + ED_NOVELL_DATA, 3025 data, len >> 1); 3026 data += len & ~1; 3027 len &= 1; 3028 } 3029 /* save last byte, if necessary */ 3030 if (len == 1) { 3031 savebyte[0] = *data; 3032 wantbyte = 1; 3033 } 3034 } 3035 m = m->m_next; 3036 } 3037 /* spit last byte */ 3038 if (wantbyte) { 3039 outw(sc->asic_addr + ED_NOVELL_DATA, *(u_short *)savebyte); 3040 } 3041 } 3042 3043 /* 3044 * Wait for remote DMA complete. This is necessary because on the 3045 * transmit side, data is handled internally by the NIC in bursts and 3046 * we can't start another remote DMA until this one completes. Not 3047 * waiting causes really bad things to happen - like the NIC 3048 * irrecoverably jamming the ISA bus. 3049 */ 3050 while (((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait); 3051 3052 if (!maxwait) { 3053 log(LOG_WARNING, "ed%d: remote transmit DMA failed to complete\n", 3054 ifp->if_unit); 3055 ed_reset(ifp); 3056 return(0); 3057 } 3058 return (total_len); 3059} 3060 3061/* 3062 * Support routines to handle the HP PC Lan+ card. 3063 */ 3064 3065/* 3066 * HP PC Lan+: Read from NIC memory, using either PIO or memory mapped 3067 * IO. 3068 */ 3069 3070static void 3071ed_hpp_readmem(sc, src, dst, amount) 3072 struct ed_softc *sc; 3073 unsigned short src; 3074 unsigned char *dst; 3075 unsigned short amount; 3076{ 3077 3078 int use_32bit_access = !(sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS); 3079 3080 3081 /* Program the source address in RAM */ 3082 outw(sc->asic_addr + ED_HPP_PAGE_2, src); 3083 3084 /* 3085 * The HP PC Lan+ card supports word reads as well as 3086 * a memory mapped i/o port that is aliased to every 3087 * even address on the board. 3088 */ 3089 3090 if (sc->hpp_mem_start) { 3091 3092 /* Enable memory mapped access. */ 3093 outw(sc->asic_addr + ED_HPP_OPTION, 3094 sc->hpp_options & 3095 ~(ED_HPP_OPTION_MEM_DISABLE | 3096 ED_HPP_OPTION_BOOT_ROM_ENB)); 3097 3098 if (use_32bit_access && (amount > 3)) { 3099 u_long *dl = (u_long *) dst; 3100 volatile u_long *const sl = 3101 (u_long *) sc->hpp_mem_start; 3102 u_long *const fence = dl + (amount >> 2); 3103 3104 /* Copy out NIC data. We could probably write this 3105 as a `movsl'. The currently generated code is lousy. 3106 */ 3107 3108 while (dl < fence) 3109 *dl++ = *sl; 3110 3111 dst += (amount & ~3); 3112 amount &= 3; 3113 3114 } 3115 3116 /* Finish off any words left, as a series of short reads */ 3117 if (amount > 1) { 3118 u_short *d = (u_short *) dst; 3119 volatile u_short *const s = 3120 (u_short *) sc->hpp_mem_start; 3121 u_short *const fence = d + (amount >> 1); 3122 3123 /* Copy out NIC data. */ 3124 3125 while (d < fence) 3126 *d++ = *s; 3127 3128 dst += (amount & ~1); 3129 amount &= 1; 3130 } 3131 3132 /* 3133 * read in a byte; however we need to always read 16 bits 3134 * at a time or the hardware gets into a funny state 3135 */ 3136 3137 if (amount == 1) { 3138 /* need to read in a short and copy LSB */ 3139 volatile u_short *const s = 3140 (volatile u_short *) sc->hpp_mem_start; 3141 3142 *dst = (*s) & 0xFF; 3143 } 3144 3145 /* Restore Boot ROM access. */ 3146 3147 outw(sc->asic_addr + ED_HPP_OPTION, 3148 sc->hpp_options); 3149 3150 3151 } else { 3152 /* Read in data using the I/O port */ 3153 if (use_32bit_access && (amount > 3)) { 3154 insl(sc->asic_addr + ED_HPP_PAGE_4, dst, amount >> 2); 3155 dst += (amount & ~3); 3156 amount &= 3; 3157 } 3158 if (amount > 1) { 3159 insw(sc->asic_addr + ED_HPP_PAGE_4, dst, amount >> 1); 3160 dst += (amount & ~1); 3161 amount &= 1; 3162 } 3163 if (amount == 1) { /* read in a short and keep the LSB */ 3164 *dst = inw(sc->asic_addr + ED_HPP_PAGE_4) & 0xFF; 3165 } 3166 } 3167} 3168 3169/* 3170 * Write to HP PC Lan+ NIC memory. Access to the NIC can be by using 3171 * outsw() or via the memory mapped interface to the same register. 3172 * Writes have to be in word units; byte accesses won't work and may cause 3173 * the NIC to behave wierdly. Long word accesses are permitted if the ASIC 3174 * allows it. 3175 */ 3176 3177static u_short 3178ed_hpp_write_mbufs(struct ed_softc *sc, struct mbuf *m, int dst) 3179{ 3180 int len, wantbyte; 3181 unsigned short total_len; 3182 unsigned char savebyte[2]; 3183 volatile u_short * const d = 3184 (volatile u_short *) sc->hpp_mem_start; 3185 int use_32bit_accesses = !(sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS); 3186 3187 /* select page 0 registers */ 3188 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA); 3189 3190 /* reset remote DMA complete flag */ 3191 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC); 3192 3193 /* program the write address in RAM */ 3194 outw(sc->asic_addr + ED_HPP_PAGE_0, dst); 3195 3196 if (sc->hpp_mem_start) /* enable memory mapped I/O */ 3197 outw(sc->asic_addr + ED_HPP_OPTION, sc->hpp_options & 3198 ~(ED_HPP_OPTION_MEM_DISABLE | 3199 ED_HPP_OPTION_BOOT_ROM_ENB)); 3200 3201 wantbyte = 0; 3202 total_len = 0; 3203 3204 if (sc->hpp_mem_start) { /* Memory mapped I/O port */ 3205 while (m) { 3206 total_len += (len = m->m_len); 3207 if (len) { 3208 caddr_t data = mtod(m, caddr_t); 3209 /* finish the last word of the previous mbuf */ 3210 if (wantbyte) { 3211 savebyte[1] = *data; 3212 *d = *((ushort *) savebyte); 3213 data++; len--; wantbyte = 0; 3214 } 3215 /* output contiguous words */ 3216 if ((len > 3) && (use_32bit_accesses)) { 3217 volatile u_long *const dl = 3218 (volatile u_long *) d; 3219 u_long *sl = (u_long *) data; 3220 u_long *fence = sl + (len >> 2); 3221 3222 while (sl < fence) 3223 *dl = *sl++; 3224 3225 data += (len & ~3); 3226 len &= 3; 3227 } 3228 /* finish off remain 16 bit writes */ 3229 if (len > 1) { 3230 u_short *s = (u_short *) data; 3231 u_short *fence = s + (len >> 1); 3232 3233 while (s < fence) 3234 *d = *s++; 3235 3236 data += (len & ~1); 3237 len &= 1; 3238 } 3239 /* save last byte if needed */ 3240 if (wantbyte = (len == 1)) 3241 savebyte[0] = *data; 3242 } 3243 m = m->m_next; /* to next mbuf */ 3244 } 3245 if (wantbyte) /* write last byte */ 3246 *d = *((u_short *) savebyte); 3247 } else { 3248 /* use programmed I/O */ 3249 while (m) { 3250 total_len += (len = m->m_len); 3251 if (len) { 3252 caddr_t data = mtod(m, caddr_t); 3253 /* finish the last word of the previous mbuf */ 3254 if (wantbyte) { 3255 savebyte[1] = *data; 3256 outw(sc->asic_addr + ED_HPP_PAGE_4, 3257 *((u_short *)savebyte)); 3258 data++; 3259 len--; 3260 wantbyte = 0; 3261 } 3262 /* output contiguous words */ 3263 if ((len > 3) && use_32bit_accesses) { 3264 outsl(sc->asic_addr + ED_HPP_PAGE_4, 3265 data, len >> 2); 3266 data += (len & ~3); 3267 len &= 3; 3268 } 3269 /* finish off remaining 16 bit accesses */ 3270 if (len > 1) { 3271 outsw(sc->asic_addr + ED_HPP_PAGE_4, 3272 data, len >> 1); 3273 data += (len & ~1); 3274 len &= 1; 3275 } 3276 if (wantbyte = (len == 1)) 3277 savebyte[0] = *data; 3278 3279 } /* if len != 0 */ 3280 m = m->m_next; 3281 } 3282 if (wantbyte) /* spit last byte */ 3283 outw(sc->asic_addr + ED_HPP_PAGE_4, 3284 *(u_short *)savebyte); 3285 3286 } 3287 3288 if (sc->hpp_mem_start) /* turn off memory mapped i/o */ 3289 outw(sc->asic_addr + ED_HPP_OPTION, 3290 sc->hpp_options); 3291 3292 return (total_len); 3293} 3294 3295static void 3296ed_setrcr(sc) 3297 struct ed_softc *sc; 3298{ 3299 struct ifnet *ifp = (struct ifnet *)sc; 3300 int i; 3301 3302 /* set page 1 registers */ 3303 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP); 3304 3305 if (ifp->if_flags & IFF_PROMISC) { 3306 3307 /* 3308 * Reconfigure the multicast filter. 3309 */ 3310 for (i = 0; i < 8; i++) 3311 outb(sc->nic_addr + ED_P1_MAR0 + i, 0xff); 3312 3313 /* 3314 * And turn on promiscuous mode. Also enable reception of 3315 * runts and packets with CRC & alignment errors. 3316 */ 3317 /* Set page 0 registers */ 3318 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP); 3319 3320 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_PRO | ED_RCR_AM | 3321 ED_RCR_AB | ED_RCR_AR | ED_RCR_SEP); 3322 } else { 3323 /* set up multicast addresses and filter modes */ 3324 if (ifp->if_flags & IFF_MULTICAST) { 3325 u_long mcaf[2]; 3326 3327 if (ifp->if_flags & IFF_ALLMULTI) { 3328 mcaf[0] = 0xffffffff; 3329 mcaf[1] = 0xffffffff; 3330 } else 3331 ds_getmcaf(sc, mcaf); 3332 3333 /* 3334 * Set multicast filter on chip. 3335 */ 3336 for (i = 0; i < 8; i++) 3337 outb(sc->nic_addr + ED_P1_MAR0 + i, ((u_char *) mcaf)[i]); 3338 3339 /* Set page 0 registers */ 3340 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP); 3341 3342 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_AM | ED_RCR_AB); 3343 } else { 3344 3345 /* 3346 * Initialize multicast address hashing registers to 3347 * not accept multicasts. 3348 */ 3349 for (i = 0; i < 8; ++i) 3350 outb(sc->nic_addr + ED_P1_MAR0 + i, 0x00); 3351 3352 /* Set page 0 registers */ 3353 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP); 3354 3355 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_AB); 3356 } 3357 } 3358 3359 /* 3360 * Start interface. 3361 */ 3362 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA); 3363} 3364 3365/* 3366 * Compute crc for ethernet address 3367 */ 3368static u_long 3369ds_crc(ep) 3370 u_char *ep; 3371{ 3372#define POLYNOMIAL 0x04c11db6 3373 register u_long crc = 0xffffffffL; 3374 register int carry, i, j; 3375 register u_char b; 3376 3377 for (i = 6; --i >= 0;) { 3378 b = *ep++; 3379 for (j = 8; --j >= 0;) { 3380 carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01); 3381 crc <<= 1; 3382 b >>= 1; 3383 if (carry) 3384 crc = ((crc ^ POLYNOMIAL) | carry); 3385 } 3386 } 3387 return crc; 3388#undef POLYNOMIAL 3389} 3390 3391/* 3392 * Compute the multicast address filter from the 3393 * list of multicast addresses we need to listen to. 3394 */ 3395static void 3396ds_getmcaf(sc, mcaf) 3397 struct ed_softc *sc; 3398 u_long *mcaf; 3399{ 3400 register u_int index; 3401 register u_char *af = (u_char *) mcaf; 3402 struct ifmultiaddr *ifma; 3403 3404 mcaf[0] = 0; 3405 mcaf[1] = 0; 3406 3407 for (ifma = sc->arpcom.ac_if.if_multiaddrs.lh_first; ifma; 3408 ifma = ifma->ifma_link.le_next) { 3409 if (ifma->ifma_addr->sa_family != AF_LINK) 3410 continue; 3411 index = ds_crc(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)) 3412 >> 26; 3413 af[index >> 3] |= 1 << (index & 7); 3414 } 3415} 3416