if_ed.c revision 190562
1/*- 2 * Copyright (c) 1995, David Greenman 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28#include <sys/cdefs.h> 29__FBSDID("$FreeBSD: head/sys/dev/ed/if_ed.c 190562 2009-03-30 17:25:56Z imp $"); 30 31/* 32 * Device driver for National Semiconductor DS8390/WD83C690 based ethernet 33 * adapters. By David Greenman, 29-April-1993 34 * 35 * Currently supports the Western Digital/SMC 8003 and 8013 series, 36 * the SMC Elite Ultra (8216), the 3Com 3c503, the NE1000 and NE2000, 37 * and a variety of similar clones. 38 * 39 */ 40 41#include "opt_ed.h" 42 43#include <sys/param.h> 44#include <sys/systm.h> 45#include <sys/sockio.h> 46#include <sys/mbuf.h> 47#include <sys/kernel.h> 48#include <sys/socket.h> 49#include <sys/sysctl.h> 50#include <sys/syslog.h> 51 52#include <sys/bus.h> 53 54#include <machine/bus.h> 55#include <sys/rman.h> 56#include <machine/resource.h> 57 58#include <net/ethernet.h> 59#include <net/if.h> 60#include <net/if_arp.h> 61#include <net/if_dl.h> 62#include <net/if_mib.h> 63#include <net/if_media.h> 64#include <net/if_types.h> 65 66#include <net/bpf.h> 67 68#include <dev/ed/if_edreg.h> 69#include <dev/ed/if_edvar.h> 70#include <sys/kdb.h> 71 72devclass_t ed_devclass; 73 74static void ed_init(void *); 75static void ed_init_locked(struct ed_softc *); 76static int ed_ioctl(struct ifnet *, u_long, caddr_t); 77static void ed_start(struct ifnet *); 78static void ed_start_locked(struct ifnet *); 79static void ed_reset(struct ifnet *); 80static void ed_watchdog(struct ifnet *); 81 82static void ed_ds_getmcaf(struct ed_softc *, uint32_t *); 83 84static void ed_get_packet(struct ed_softc *, bus_size_t, u_short); 85static void ed_stop_hw(struct ed_softc *sc); 86 87static __inline void ed_rint(struct ed_softc *); 88static __inline void ed_xmit(struct ed_softc *); 89static __inline void ed_ring_copy(struct ed_softc *, bus_size_t, char *, 90 u_short); 91 92static void ed_setrcr(struct ed_softc *); 93 94/* 95 * Generic probe routine for testing for the existance of a DS8390. 96 * Must be called after the NIC has just been reset. This routine 97 * works by looking at certain register values that are guaranteed 98 * to be initialized a certain way after power-up or reset. Seems 99 * not to currently work on the 83C690. 100 * 101 * Specifically: 102 * 103 * Register reset bits set bits 104 * Command Register (CR) TXP, STA RD2, STP 105 * Interrupt Status (ISR) RST 106 * Interrupt Mask (IMR) All bits 107 * Data Control (DCR) LAS 108 * Transmit Config. (TCR) LB1, LB0 109 * 110 * We only look at the CR and ISR registers, however, because looking at 111 * the others would require changing register pages (which would be 112 * intrusive if this isn't an 8390). 113 * 114 * Return 1 if 8390 was found, 0 if not. 115 */ 116 117int 118ed_probe_generic8390(struct ed_softc *sc) 119{ 120 if ((ed_nic_inb(sc, ED_P0_CR) & 121 (ED_CR_RD2 | ED_CR_TXP | ED_CR_STA | ED_CR_STP)) != 122 (ED_CR_RD2 | ED_CR_STP)) 123 return (0); 124 if ((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RST) != ED_ISR_RST) 125 return (0); 126 127 return (1); 128} 129 130void 131ed_disable_16bit_access(struct ed_softc *sc) 132{ 133 /* 134 * Disable 16 bit access to shared memory 135 */ 136 if (sc->isa16bit && sc->vendor == ED_VENDOR_WD_SMC) { 137 if (sc->chip_type == ED_CHIP_TYPE_WD790) 138 ed_asic_outb(sc, ED_WD_MSR, 0x00); 139 ed_asic_outb(sc, ED_WD_LAAR, 140 sc->wd_laar_proto & ~ED_WD_LAAR_M16EN); 141 } 142} 143 144void 145ed_enable_16bit_access(struct ed_softc *sc) 146{ 147 if (sc->isa16bit && sc->vendor == ED_VENDOR_WD_SMC) { 148 ed_asic_outb(sc, ED_WD_LAAR, 149 sc->wd_laar_proto | ED_WD_LAAR_M16EN); 150 if (sc->chip_type == ED_CHIP_TYPE_WD790) 151 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_MENB); 152 } 153} 154 155/* 156 * Allocate a port resource with the given resource id. 157 */ 158int 159ed_alloc_port(device_t dev, int rid, int size) 160{ 161 struct ed_softc *sc = device_get_softc(dev); 162 struct resource *res; 163 164 res = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 165 0ul, ~0ul, size, RF_ACTIVE); 166 if (res) { 167 sc->port_rid = rid; 168 sc->port_res = res; 169 sc->port_used = size; 170 sc->port_bst = rman_get_bustag(res); 171 sc->port_bsh = rman_get_bushandle(res); 172 return (0); 173 } 174 return (ENOENT); 175} 176 177/* 178 * Allocate a memory resource with the given resource id. 179 */ 180int 181ed_alloc_memory(device_t dev, int rid, int size) 182{ 183 struct ed_softc *sc = device_get_softc(dev); 184 struct resource *res; 185 186 res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 187 0ul, ~0ul, size, RF_ACTIVE); 188 if (res) { 189 sc->mem_rid = rid; 190 sc->mem_res = res; 191 sc->mem_used = size; 192 sc->mem_bst = rman_get_bustag(res); 193 sc->mem_bsh = rman_get_bushandle(res); 194 return (0); 195 } 196 return (ENOENT); 197} 198 199/* 200 * Allocate an irq resource with the given resource id. 201 */ 202int 203ed_alloc_irq(device_t dev, int rid, int flags) 204{ 205 struct ed_softc *sc = device_get_softc(dev); 206 struct resource *res; 207 208 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE | flags); 209 if (res) { 210 sc->irq_rid = rid; 211 sc->irq_res = res; 212 return (0); 213 } 214 return (ENOENT); 215} 216 217/* 218 * Release all resources 219 */ 220void 221ed_release_resources(device_t dev) 222{ 223 struct ed_softc *sc = device_get_softc(dev); 224 225 if (sc->port_res) { 226 bus_release_resource(dev, SYS_RES_IOPORT, 227 sc->port_rid, sc->port_res); 228 sc->port_res = 0; 229 } 230 if (sc->mem_res) { 231 bus_release_resource(dev, SYS_RES_MEMORY, 232 sc->mem_rid, sc->mem_res); 233 sc->mem_res = 0; 234 } 235 if (sc->irq_res) { 236 bus_release_resource(dev, SYS_RES_IRQ, 237 sc->irq_rid, sc->irq_res); 238 sc->irq_res = 0; 239 } 240 if (sc->ifp) 241 if_free(sc->ifp); 242} 243 244/* 245 * Install interface into kernel networking data structures 246 */ 247int 248ed_attach(device_t dev) 249{ 250 struct ed_softc *sc = device_get_softc(dev); 251 struct ifnet *ifp; 252 253 sc->dev = dev; 254 ED_LOCK_INIT(sc); 255 ifp = sc->ifp = if_alloc(IFT_ETHER); 256 if (ifp == NULL) { 257 device_printf(dev, "can not if_alloc()\n"); 258 ED_LOCK_DESTROY(sc); 259 return (ENOSPC); 260 } 261 262 if (sc->readmem == NULL) { 263 if (sc->mem_shared) { 264 if (sc->isa16bit) 265 sc->readmem = ed_shmem_readmem16; 266 else 267 sc->readmem = ed_shmem_readmem8; 268 } else { 269 sc->readmem = ed_pio_readmem; 270 } 271 } 272 if (sc->sc_write_mbufs == NULL) { 273 device_printf(dev, "No write mbufs routine set\n"); 274 return (ENXIO); 275 } 276 277 callout_init_mtx(&sc->tick_ch, ED_MUTEX(sc), 0); 278 /* 279 * Set interface to stopped condition (reset) 280 */ 281 ed_stop_hw(sc); 282 283 /* 284 * Initialize ifnet structure 285 */ 286 ifp->if_softc = sc; 287 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 288 ifp->if_start = ed_start; 289 ifp->if_ioctl = ed_ioctl; 290 ifp->if_watchdog = ed_watchdog; 291 ifp->if_init = ed_init; 292 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 293 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN; 294 IFQ_SET_READY(&ifp->if_snd); 295 ifp->if_linkmib = &sc->mibdata; 296 ifp->if_linkmiblen = sizeof sc->mibdata; 297 /* 298 * XXX - should do a better job. 299 */ 300 if (sc->chip_type == ED_CHIP_TYPE_WD790) 301 sc->mibdata.dot3StatsEtherChipSet = 302 DOT3CHIPSET(dot3VendorWesternDigital, 303 dot3ChipSetWesternDigital83C790); 304 else 305 sc->mibdata.dot3StatsEtherChipSet = 306 DOT3CHIPSET(dot3VendorNational, 307 dot3ChipSetNational8390); 308 sc->mibdata.dot3Compliance = DOT3COMPLIANCE_COLLS; 309 310 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 311 /* 312 * Set default state for LINK2 flag (used to disable the 313 * tranceiver for AUI operation), based on config option. 314 * We only set this flag before we attach the device, so there's 315 * no race. It is convenient to allow users to turn this off 316 * by default in the kernel config, but given our more advanced 317 * boot time configuration options, this might no longer be needed. 318 */ 319 if (device_get_flags(dev) & ED_FLAGS_DISABLE_TRANCEIVER) 320 ifp->if_flags |= IFF_LINK2; 321 322 /* 323 * Attach the interface 324 */ 325 ether_ifattach(ifp, sc->enaddr); 326 /* device attach does transition from UNCONFIGURED to IDLE state */ 327 328 sc->tx_mem = sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE; 329 sc->rx_mem = (sc->rec_page_stop - sc->rec_page_start) * ED_PAGE_SIZE; 330 SYSCTL_ADD_STRING(device_get_sysctl_ctx(dev), 331 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 332 0, "type", CTLTYPE_STRING | CTLFLAG_RD, sc->type_str, 0, 333 "Type of chip in card"); 334 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 335 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 336 1, "TxMem", CTLTYPE_STRING | CTLFLAG_RD, &sc->tx_mem, 0, 337 "Memory set aside for transmitting packets"); 338 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 339 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 340 2, "RxMem", CTLTYPE_STRING | CTLFLAG_RD, &sc->rx_mem, 0, 341 "Memory set aside for receiving packets"); 342 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 343 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 344 3, "Mem", CTLTYPE_STRING | CTLFLAG_RD, &sc->mem_size, 0, 345 "Total Card Memory"); 346 if (bootverbose) { 347 if (sc->type_str && (*sc->type_str != 0)) 348 device_printf(dev, "type %s ", sc->type_str); 349 else 350 device_printf(dev, "type unknown (0x%x) ", sc->type); 351 352#ifdef ED_HPP 353 if (sc->vendor == ED_VENDOR_HP) 354 printf("(%s %s IO)", 355 (sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS) ? 356 "16-bit" : "32-bit", 357 sc->hpp_mem_start ? "memory mapped" : "regular"); 358 else 359#endif 360 printf("%s", sc->isa16bit ? "(16 bit)" : "(8 bit)"); 361 362#if defined(ED_HPP) || defined(ED_3C503) 363 printf("%s", (((sc->vendor == ED_VENDOR_3COM) || 364 (sc->vendor == ED_VENDOR_HP)) && 365 (ifp->if_flags & IFF_LINK2)) ? 366 " tranceiver disabled" : ""); 367#endif 368 printf("\n"); 369 } 370 return (0); 371} 372 373/* 374 * Detach the driver from the hardware and other systems in the kernel. 375 */ 376int 377ed_detach(device_t dev) 378{ 379 struct ed_softc *sc = device_get_softc(dev); 380 struct ifnet *ifp = sc->ifp; 381 382 ED_ASSERT_UNLOCKED(sc); 383 if (ifp) { 384 ED_LOCK(sc); 385 if (bus_child_present(dev)) 386 ed_stop(sc); 387 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 388 ED_UNLOCK(sc); 389 callout_drain(&sc->tick_ch); 390 ether_ifdetach(ifp); 391 } 392 if (sc->irq_res != NULL && sc->irq_handle) 393 bus_teardown_intr(dev, sc->irq_res, sc->irq_handle); 394 ed_release_resources(dev); 395 if (sc->miibus) 396 device_delete_child(dev, sc->miibus); 397 ED_LOCK_DESTROY(sc); 398 bus_generic_detach(dev); 399 return (0); 400} 401 402/* 403 * Reset interface. 404 */ 405static void 406ed_reset(struct ifnet *ifp) 407{ 408 struct ed_softc *sc = ifp->if_softc; 409 410 ED_ASSERT_LOCKED(sc); 411 /* 412 * Stop interface and re-initialize. 413 */ 414 ed_stop(sc); 415 ed_init_locked(sc); 416} 417 418static void 419ed_stop_hw(struct ed_softc *sc) 420{ 421 int n = 5000; 422 423 /* 424 * Stop everything on the interface, and select page 0 registers. 425 */ 426 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP); 427 428 /* 429 * Wait for interface to enter stopped state, but limit # of checks to 430 * 'n' (about 5ms). It shouldn't even take 5us on modern DS8390's, but 431 * just in case it's an old one. 432 * 433 * The AX88x90 chips don't seem to implement this behavor. The 434 * datasheets say it is only turned on when the chip enters a RESET 435 * state and is silent about behavior for the stopped state we just 436 * entered. 437 */ 438 if (sc->chip_type == ED_CHIP_TYPE_AX88190 || 439 sc->chip_type == ED_CHIP_TYPE_AX88790) 440 return; 441 while (((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RST) == 0) && --n) 442 continue; 443 if (n <= 0) 444 device_printf(sc->dev, "ed_stop_hw RST never set\n"); 445} 446 447/* 448 * Take interface offline. 449 */ 450void 451ed_stop(struct ed_softc *sc) 452{ 453 ED_ASSERT_LOCKED(sc); 454 if (sc->sc_tick) 455 callout_stop(&sc->tick_ch); 456 ed_stop_hw(sc); 457} 458 459/* 460 * Device timeout/watchdog routine. Entered if the device neglects to 461 * generate an interrupt after a transmit has been started on it. 462 */ 463static void 464ed_watchdog(struct ifnet *ifp) 465{ 466 struct ed_softc *sc = ifp->if_softc; 467 468 log(LOG_ERR, "%s: device timeout\n", ifp->if_xname); 469 ifp->if_oerrors++; 470 471 ED_LOCK(sc); 472 ed_reset(ifp); 473 ED_UNLOCK(sc); 474} 475 476/* 477 * Initialize device. 478 */ 479static void 480ed_init(void *xsc) 481{ 482 struct ed_softc *sc = xsc; 483 484 ED_ASSERT_UNLOCKED(sc); 485 ED_LOCK(sc); 486 ed_init_locked(sc); 487 ED_UNLOCK(sc); 488} 489 490static void 491ed_init_locked(struct ed_softc *sc) 492{ 493 struct ifnet *ifp = sc->ifp; 494 int i; 495 496 ED_ASSERT_LOCKED(sc); 497 498 /* 499 * Initialize the NIC in the exact order outlined in the NS manual. 500 * This init procedure is "mandatory"...don't change what or when 501 * things happen. 502 */ 503 504 /* reset transmitter flags */ 505 sc->xmit_busy = 0; 506 ifp->if_timer = 0; 507 508 sc->txb_inuse = 0; 509 sc->txb_new = 0; 510 sc->txb_next_tx = 0; 511 512 /* This variable is used below - don't move this assignment */ 513 sc->next_packet = sc->rec_page_start + 1; 514 515 /* 516 * Set interface for page 0, Remote DMA complete, Stopped 517 */ 518 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP); 519 520 if (sc->isa16bit) 521 /* 522 * Set FIFO threshold to 8, No auto-init Remote DMA, byte 523 * order=80x86, word-wide DMA xfers, 524 */ 525 ed_nic_outb(sc, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_WTS | ED_DCR_LS); 526 else 527 /* 528 * Same as above, but byte-wide DMA xfers 529 */ 530 ed_nic_outb(sc, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS); 531 532 /* 533 * Clear Remote Byte Count Registers 534 */ 535 ed_nic_outb(sc, ED_P0_RBCR0, 0); 536 ed_nic_outb(sc, ED_P0_RBCR1, 0); 537 538 /* 539 * For the moment, don't store incoming packets in memory. 540 */ 541 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_MON); 542 543 /* 544 * Place NIC in internal loopback mode 545 */ 546 ed_nic_outb(sc, ED_P0_TCR, ED_TCR_LB0); 547 548 /* 549 * Initialize transmit/receive (ring-buffer) Page Start 550 */ 551 ed_nic_outb(sc, ED_P0_TPSR, sc->tx_page_start); 552 ed_nic_outb(sc, ED_P0_PSTART, sc->rec_page_start); 553 /* Set lower bits of byte addressable framing to 0 */ 554 if (sc->chip_type == ED_CHIP_TYPE_WD790) 555 ed_nic_outb(sc, 0x09, 0); 556 557 /* 558 * Initialize Receiver (ring-buffer) Page Stop and Boundry 559 */ 560 ed_nic_outb(sc, ED_P0_PSTOP, sc->rec_page_stop); 561 ed_nic_outb(sc, ED_P0_BNRY, sc->rec_page_start); 562 563 /* 564 * Clear all interrupts. A '1' in each bit position clears the 565 * corresponding flag. 566 */ 567 ed_nic_outb(sc, ED_P0_ISR, 0xff); 568 569 /* 570 * Enable the following interrupts: receive/transmit complete, 571 * receive/transmit error, and Receiver OverWrite. 572 * 573 * Counter overflow and Remote DMA complete are *not* enabled. 574 */ 575 ed_nic_outb(sc, ED_P0_IMR, 576 ED_IMR_PRXE | ED_IMR_PTXE | ED_IMR_RXEE | ED_IMR_TXEE | ED_IMR_OVWE); 577 578 /* 579 * Program Command Register for page 1 580 */ 581 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP); 582 583 /* 584 * Copy out our station address 585 */ 586 for (i = 0; i < ETHER_ADDR_LEN; ++i) 587 ed_nic_outb(sc, ED_P1_PAR(i), IF_LLADDR(sc->ifp)[i]); 588 589 /* 590 * Set Current Page pointer to next_packet (initialized above) 591 */ 592 ed_nic_outb(sc, ED_P1_CURR, sc->next_packet); 593 594 /* 595 * Program Receiver Configuration Register and multicast filter. CR is 596 * set to page 0 on return. 597 */ 598 ed_setrcr(sc); 599 600 /* 601 * Take interface out of loopback 602 */ 603 ed_nic_outb(sc, ED_P0_TCR, 0); 604 605 if (sc->sc_mediachg) 606 sc->sc_mediachg(sc); 607 608 /* 609 * Set 'running' flag, and clear output active flag. 610 */ 611 ifp->if_drv_flags |= IFF_DRV_RUNNING; 612 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 613 614 /* 615 * ...and attempt to start output 616 */ 617 ed_start_locked(ifp); 618 619 if (sc->sc_tick) 620 callout_reset(&sc->tick_ch, hz, sc->sc_tick, sc); 621} 622 623/* 624 * This routine actually starts the transmission on the interface 625 */ 626static __inline void 627ed_xmit(struct ed_softc *sc) 628{ 629 struct ifnet *ifp = sc->ifp; 630 unsigned short len; 631 632 len = sc->txb_len[sc->txb_next_tx]; 633 634 /* 635 * Set NIC for page 0 register access 636 */ 637 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA); 638 639 /* 640 * Set TX buffer start page 641 */ 642 ed_nic_outb(sc, ED_P0_TPSR, sc->tx_page_start + 643 sc->txb_next_tx * ED_TXBUF_SIZE); 644 645 /* 646 * Set TX length 647 */ 648 ed_nic_outb(sc, ED_P0_TBCR0, len); 649 ed_nic_outb(sc, ED_P0_TBCR1, len >> 8); 650 651 /* 652 * Set page 0, Remote DMA complete, Transmit Packet, and *Start* 653 */ 654 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_TXP | ED_CR_STA); 655 sc->xmit_busy = 1; 656 657 /* 658 * Point to next transmit buffer slot and wrap if necessary. 659 */ 660 sc->txb_next_tx++; 661 if (sc->txb_next_tx == sc->txb_cnt) 662 sc->txb_next_tx = 0; 663 664 /* 665 * Set a timer just in case we never hear from the board again 666 */ 667 ifp->if_timer = 2; 668} 669 670/* 671 * Start output on interface. 672 * We make two assumptions here: 673 * 1) that the current priority is set to splimp _before_ this code 674 * is called *and* is returned to the appropriate priority after 675 * return 676 * 2) that the IFF_DRV_OACTIVE flag is checked before this code is called 677 * (i.e. that the output part of the interface is idle) 678 */ 679static void 680ed_start(struct ifnet *ifp) 681{ 682 struct ed_softc *sc = ifp->if_softc; 683 684 ED_ASSERT_UNLOCKED(sc); 685 ED_LOCK(sc); 686 ed_start_locked(ifp); 687 ED_UNLOCK(sc); 688} 689 690static void 691ed_start_locked(struct ifnet *ifp) 692{ 693 struct ed_softc *sc = ifp->if_softc; 694 struct mbuf *m0, *m; 695 bus_size_t buffer; 696 int len; 697 698 ED_ASSERT_LOCKED(sc); 699outloop: 700 701 /* 702 * First, see if there are buffered packets and an idle transmitter - 703 * should never happen at this point. 704 */ 705 if (sc->txb_inuse && (sc->xmit_busy == 0)) { 706 printf("ed: packets buffered, but transmitter idle\n"); 707 ed_xmit(sc); 708 } 709 710 /* 711 * See if there is room to put another packet in the buffer. 712 */ 713 if (sc->txb_inuse == sc->txb_cnt) { 714 715 /* 716 * No room. Indicate this to the outside world and exit. 717 */ 718 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 719 return; 720 } 721 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 722 if (m == 0) { 723 724 /* 725 * We are using the !OACTIVE flag to indicate to the outside 726 * world that we can accept an additional packet rather than 727 * that the transmitter is _actually_ active. Indeed, the 728 * transmitter may be active, but if we haven't filled all the 729 * buffers with data then we still want to accept more. 730 */ 731 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 732 return; 733 } 734 735 /* 736 * Copy the mbuf chain into the transmit buffer 737 */ 738 m0 = m; 739 740 /* txb_new points to next open buffer slot */ 741 buffer = sc->mem_start + (sc->txb_new * ED_TXBUF_SIZE * ED_PAGE_SIZE); 742 743 len = sc->sc_write_mbufs(sc, m, buffer); 744 if (len == 0) { 745 m_freem(m0); 746 goto outloop; 747 } 748 749 sc->txb_len[sc->txb_new] = max(len, (ETHER_MIN_LEN-ETHER_CRC_LEN)); 750 751 sc->txb_inuse++; 752 753 /* 754 * Point to next buffer slot and wrap if necessary. 755 */ 756 sc->txb_new++; 757 if (sc->txb_new == sc->txb_cnt) 758 sc->txb_new = 0; 759 760 if (sc->xmit_busy == 0) 761 ed_xmit(sc); 762 763 /* 764 * Tap off here if there is a bpf listener. 765 */ 766 BPF_MTAP(ifp, m0); 767 768 m_freem(m0); 769 770 /* 771 * Loop back to the top to possibly buffer more packets 772 */ 773 goto outloop; 774} 775 776/* 777 * Ethernet interface receiver interrupt. 778 */ 779static __inline void 780ed_rint(struct ed_softc *sc) 781{ 782 struct ifnet *ifp = sc->ifp; 783 u_char boundry; 784 u_short len; 785 struct ed_ring packet_hdr; 786 bus_size_t packet_ptr; 787 788 ED_ASSERT_LOCKED(sc); 789 790 /* 791 * Set NIC to page 1 registers to get 'current' pointer 792 */ 793 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA); 794 795 /* 796 * 'sc->next_packet' is the logical beginning of the ring-buffer - 797 * i.e. it points to where new data has been buffered. The 'CURR' 798 * (current) register points to the logical end of the ring-buffer - 799 * i.e. it points to where additional new data will be added. We loop 800 * here until the logical beginning equals the logical end (or in 801 * other words, until the ring-buffer is empty). 802 */ 803 while (sc->next_packet != ed_nic_inb(sc, ED_P1_CURR)) { 804 805 /* get pointer to this buffer's header structure */ 806 packet_ptr = sc->mem_ring + 807 (sc->next_packet - sc->rec_page_start) * ED_PAGE_SIZE; 808 809 /* 810 * The byte count includes a 4 byte header that was added by 811 * the NIC. 812 */ 813 sc->readmem(sc, packet_ptr, (char *) &packet_hdr, 814 sizeof(packet_hdr)); 815 len = packet_hdr.count; 816 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring)) || 817 len < (ETHER_MIN_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring))) { 818 /* 819 * Length is a wild value. There's a good chance that 820 * this was caused by the NIC being old and buggy. 821 * The bug is that the length low byte is duplicated 822 * in the high byte. Try to recalculate the length 823 * based on the pointer to the next packet. Also, 824 * need ot preserve offset into page. 825 * 826 * NOTE: sc->next_packet is pointing at the current 827 * packet. 828 */ 829 len &= ED_PAGE_SIZE - 1; 830 if (packet_hdr.next_packet >= sc->next_packet) 831 len += (packet_hdr.next_packet - 832 sc->next_packet) * ED_PAGE_SIZE; 833 else 834 len += 835 ((packet_hdr.next_packet - sc->rec_page_start) + 836 (sc->rec_page_stop - sc->next_packet)) * ED_PAGE_SIZE; 837 /* 838 * because buffers are aligned on 256-byte boundary, 839 * the length computed above is off by 256 in almost 840 * all cases. Fix it... 841 */ 842 if (len & 0xff) 843 len -= 256; 844 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN 845 + sizeof(struct ed_ring))) 846 sc->mibdata.dot3StatsFrameTooLongs++; 847 } 848 849 /* 850 * Be fairly liberal about what we allow as a "reasonable" 851 * length so that a [crufty] packet will make it to BPF (and 852 * can thus be analyzed). Note that all that is really 853 * important is that we have a length that will fit into one 854 * mbuf cluster or less; the upper layer protocols can then 855 * figure out the length from their own length field(s). But 856 * make sure that we have at least a full ethernet header or 857 * we would be unable to call ether_input() later. 858 */ 859 if ((len >= sizeof(struct ed_ring) + ETHER_HDR_LEN) && 860 (len <= MCLBYTES) && 861 (packet_hdr.next_packet >= sc->rec_page_start) && 862 (packet_hdr.next_packet < sc->rec_page_stop)) { 863 /* 864 * Go get packet. 865 */ 866 ed_get_packet(sc, packet_ptr + sizeof(struct ed_ring), 867 len - sizeof(struct ed_ring)); 868 ifp->if_ipackets++; 869 } else { 870 /* 871 * Really BAD. The ring pointers are corrupted. 872 */ 873 log(LOG_ERR, 874 "%s: NIC memory corrupt - invalid packet length %d\n", 875 ifp->if_xname, len); 876 ifp->if_ierrors++; 877 ed_reset(ifp); 878 return; 879 } 880 881 /* 882 * Update next packet pointer 883 */ 884 sc->next_packet = packet_hdr.next_packet; 885 886 /* 887 * Update NIC boundry pointer - being careful to keep it one 888 * buffer behind. (as recommended by NS databook) 889 */ 890 boundry = sc->next_packet - 1; 891 if (boundry < sc->rec_page_start) 892 boundry = sc->rec_page_stop - 1; 893 894 /* 895 * Set NIC to page 0 registers to update boundry register 896 */ 897 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA); 898 ed_nic_outb(sc, ED_P0_BNRY, boundry); 899 900 /* 901 * Set NIC to page 1 registers before looping to top (prepare 902 * to get 'CURR' current pointer) 903 */ 904 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA); 905 } 906} 907 908/* 909 * Ethernet interface interrupt processor 910 */ 911void 912edintr(void *arg) 913{ 914 struct ed_softc *sc = (struct ed_softc*) arg; 915 struct ifnet *ifp = sc->ifp; 916 u_char isr; 917 int count; 918 919 ED_LOCK(sc); 920 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 921 ED_UNLOCK(sc); 922 return; 923 } 924 /* 925 * Set NIC to page 0 registers 926 */ 927 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA); 928 929 /* 930 * loop until there are no more new interrupts. When the card goes 931 * away, the hardware will read back 0xff. Looking at the interrupts, 932 * it would appear that 0xff is impossible, or at least extremely 933 * unlikely. 934 */ 935 while ((isr = ed_nic_inb(sc, ED_P0_ISR)) != 0 && isr != 0xff) { 936 937 /* 938 * reset all the bits that we are 'acknowledging' by writing a 939 * '1' to each bit position that was set (writing a '1' 940 * *clears* the bit) 941 */ 942 ed_nic_outb(sc, ED_P0_ISR, isr); 943 944 /* 945 * The AX88190 and AX88190A has problems acking an interrupt 946 * and having them clear. This interferes with top-level loop 947 * here. Wait for all the bits to clear. 948 * 949 * We limit this to 5000 iterations. At 1us per inb/outb, 950 * this translates to about 15ms, which should be plenty of 951 * time, and also gives protection in the card eject case. 952 */ 953 if (sc->chip_type == ED_CHIP_TYPE_AX88190) { 954 count = 5000; /* 15ms */ 955 while (count-- && (ed_nic_inb(sc, ED_P0_ISR) & isr)) { 956 ed_nic_outb(sc, ED_P0_ISR,0); 957 ed_nic_outb(sc, ED_P0_ISR,isr); 958 } 959 if (count == 0) 960 break; 961 } 962 963 /* 964 * Handle transmitter interrupts. Handle these first because 965 * the receiver will reset the board under some conditions. 966 */ 967 if (isr & (ED_ISR_PTX | ED_ISR_TXE)) { 968 u_char collisions = ed_nic_inb(sc, ED_P0_NCR) & 0x0f; 969 970 /* 971 * Check for transmit error. If a TX completed with an 972 * error, we end up throwing the packet away. Really 973 * the only error that is possible is excessive 974 * collisions, and in this case it is best to allow 975 * the automatic mechanisms of TCP to backoff the 976 * flow. Of course, with UDP we're screwed, but this 977 * is expected when a network is heavily loaded. 978 */ 979 (void) ed_nic_inb(sc, ED_P0_TSR); 980 if (isr & ED_ISR_TXE) { 981 u_char tsr; 982 983 /* 984 * Excessive collisions (16) 985 */ 986 tsr = ed_nic_inb(sc, ED_P0_TSR); 987 if ((tsr & ED_TSR_ABT) 988 && (collisions == 0)) { 989 990 /* 991 * When collisions total 16, the 992 * P0_NCR will indicate 0, and the 993 * TSR_ABT is set. 994 */ 995 collisions = 16; 996 sc->mibdata.dot3StatsExcessiveCollisions++; 997 sc->mibdata.dot3StatsCollFrequencies[15]++; 998 } 999 if (tsr & ED_TSR_OWC) 1000 sc->mibdata.dot3StatsLateCollisions++; 1001 if (tsr & ED_TSR_CDH) 1002 sc->mibdata.dot3StatsSQETestErrors++; 1003 if (tsr & ED_TSR_CRS) 1004 sc->mibdata.dot3StatsCarrierSenseErrors++; 1005 if (tsr & ED_TSR_FU) 1006 sc->mibdata.dot3StatsInternalMacTransmitErrors++; 1007 1008 /* 1009 * update output errors counter 1010 */ 1011 ifp->if_oerrors++; 1012 } else { 1013 1014 /* 1015 * Update total number of successfully 1016 * transmitted packets. 1017 */ 1018 ifp->if_opackets++; 1019 } 1020 1021 /* 1022 * reset tx busy and output active flags 1023 */ 1024 sc->xmit_busy = 0; 1025 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1026 1027 /* 1028 * clear watchdog timer 1029 */ 1030 ifp->if_timer = 0; 1031 1032 /* 1033 * Add in total number of collisions on last 1034 * transmission. 1035 */ 1036 ifp->if_collisions += collisions; 1037 switch(collisions) { 1038 case 0: 1039 case 16: 1040 break; 1041 case 1: 1042 sc->mibdata.dot3StatsSingleCollisionFrames++; 1043 sc->mibdata.dot3StatsCollFrequencies[0]++; 1044 break; 1045 default: 1046 sc->mibdata.dot3StatsMultipleCollisionFrames++; 1047 sc->mibdata. 1048 dot3StatsCollFrequencies[collisions-1] 1049 ++; 1050 break; 1051 } 1052 1053 /* 1054 * Decrement buffer in-use count if not zero (can only 1055 * be zero if a transmitter interrupt occured while 1056 * not actually transmitting). If data is ready to 1057 * transmit, start it transmitting, otherwise defer 1058 * until after handling receiver 1059 */ 1060 if (sc->txb_inuse && --sc->txb_inuse) 1061 ed_xmit(sc); 1062 } 1063 1064 /* 1065 * Handle receiver interrupts 1066 */ 1067 if (isr & (ED_ISR_PRX | ED_ISR_RXE | ED_ISR_OVW)) { 1068 1069 /* 1070 * Overwrite warning. In order to make sure that a 1071 * lockup of the local DMA hasn't occurred, we reset 1072 * and re-init the NIC. The NSC manual suggests only a 1073 * partial reset/re-init is necessary - but some chips 1074 * seem to want more. The DMA lockup has been seen 1075 * only with early rev chips - Methinks this bug was 1076 * fixed in later revs. -DG 1077 */ 1078 if (isr & ED_ISR_OVW) { 1079 ifp->if_ierrors++; 1080#ifdef DIAGNOSTIC 1081 log(LOG_WARNING, 1082 "%s: warning - receiver ring buffer overrun\n", 1083 ifp->if_xname); 1084#endif 1085 1086 /* 1087 * Stop/reset/re-init NIC 1088 */ 1089 ed_reset(ifp); 1090 } else { 1091 1092 /* 1093 * Receiver Error. One or more of: CRC error, 1094 * frame alignment error FIFO overrun, or 1095 * missed packet. 1096 */ 1097 if (isr & ED_ISR_RXE) { 1098 u_char rsr; 1099 rsr = ed_nic_inb(sc, ED_P0_RSR); 1100 if (rsr & ED_RSR_CRC) 1101 sc->mibdata.dot3StatsFCSErrors++; 1102 if (rsr & ED_RSR_FAE) 1103 sc->mibdata.dot3StatsAlignmentErrors++; 1104 if (rsr & ED_RSR_FO) 1105 sc->mibdata.dot3StatsInternalMacReceiveErrors++; 1106 ifp->if_ierrors++; 1107#ifdef ED_DEBUG 1108 if_printf(ifp, "receive error %x\n", 1109 ed_nic_inb(sc, ED_P0_RSR)); 1110#endif 1111 } 1112 1113 /* 1114 * Go get the packet(s) XXX - Doing this on an 1115 * error is dubious because there shouldn't be 1116 * any data to get (we've configured the 1117 * interface to not accept packets with 1118 * errors). 1119 */ 1120 1121 /* 1122 * Enable 16bit access to shared memory first 1123 * on WD/SMC boards. 1124 */ 1125 ed_enable_16bit_access(sc); 1126 ed_rint(sc); 1127 ed_disable_16bit_access(sc); 1128 } 1129 } 1130 1131 /* 1132 * If it looks like the transmitter can take more data, 1133 * attempt to start output on the interface. This is done 1134 * after handling the receiver to give the receiver priority. 1135 */ 1136 if ((ifp->if_drv_flags & IFF_DRV_OACTIVE) == 0) 1137 ed_start_locked(ifp); 1138 1139 /* 1140 * return NIC CR to standard state: page 0, remote DMA 1141 * complete, start (toggling the TXP bit off, even if was just 1142 * set in the transmit routine, is *okay* - it is 'edge' 1143 * triggered from low to high) 1144 */ 1145 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA); 1146 1147 /* 1148 * If the Network Talley Counters overflow, read them to reset 1149 * them. It appears that old 8390's won't clear the ISR flag 1150 * otherwise - resulting in an infinite loop. 1151 */ 1152 if (isr & ED_ISR_CNT) { 1153 (void) ed_nic_inb(sc, ED_P0_CNTR0); 1154 (void) ed_nic_inb(sc, ED_P0_CNTR1); 1155 (void) ed_nic_inb(sc, ED_P0_CNTR2); 1156 } 1157 } 1158 ED_UNLOCK(sc); 1159} 1160 1161/* 1162 * Process an ioctl request. 1163 */ 1164static int 1165ed_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1166{ 1167 struct ed_softc *sc = ifp->if_softc; 1168 struct ifreq *ifr = (struct ifreq *)data; 1169 int error = 0; 1170 1171 /* 1172 * XXX really needed? 1173 */ 1174 if (sc == NULL) { 1175 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1176 return (ENXIO); 1177 } 1178 1179 switch (command) { 1180 case SIOCSIFFLAGS: 1181 /* 1182 * If the interface is marked up and stopped, then start it. 1183 * If we're up and already running, then it may be a mediachg. 1184 * If it is marked down and running, then stop it. 1185 */ 1186 ED_LOCK(sc); 1187 if (ifp->if_flags & IFF_UP) { 1188 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1189 ed_init_locked(sc); 1190 else if (sc->sc_mediachg) 1191 sc->sc_mediachg(sc); 1192 } else { 1193 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1194 ed_stop(sc); 1195 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1196 } 1197 } 1198 1199 /* 1200 * Promiscuous flag may have changed, so reprogram the RCR. 1201 */ 1202 ed_setrcr(sc); 1203 1204 ED_UNLOCK(sc); 1205 break; 1206 1207 case SIOCADDMULTI: 1208 case SIOCDELMULTI: 1209 /* 1210 * Multicast list has changed; set the hardware filter 1211 * accordingly. 1212 */ 1213 ED_LOCK(sc); 1214 ed_setrcr(sc); 1215 ED_UNLOCK(sc); 1216 error = 0; 1217 break; 1218 1219 case SIOCGIFMEDIA: 1220 case SIOCSIFMEDIA: 1221 if (sc->sc_media_ioctl == NULL) { 1222 error = EINVAL; 1223 break; 1224 } 1225 sc->sc_media_ioctl(sc, ifr, command); 1226 break; 1227 1228 default: 1229 error = ether_ioctl(ifp, command, data); 1230 break; 1231 } 1232 return (error); 1233} 1234 1235/* 1236 * Given a source and destination address, copy 'amount' of a packet from 1237 * the ring buffer into a linear destination buffer. Takes into account 1238 * ring-wrap. 1239 */ 1240static __inline void 1241ed_ring_copy(struct ed_softc *sc, bus_size_t src, char *dst, u_short amount) 1242{ 1243 u_short tmp_amount; 1244 1245 /* does copy wrap to lower addr in ring buffer? */ 1246 if (src + amount > sc->mem_end) { 1247 tmp_amount = sc->mem_end - src; 1248 /* copy amount up to end of NIC memory */ 1249 sc->readmem(sc, src, dst, tmp_amount); 1250 amount -= tmp_amount; 1251 src = sc->mem_ring; 1252 dst += tmp_amount; 1253 } 1254 sc->readmem(sc, src, dst, amount); 1255} 1256 1257/* 1258 * Retreive packet from shared memory and send to the next level up via 1259 * ether_input(). 1260 */ 1261static void 1262ed_get_packet(struct ed_softc *sc, bus_size_t buf, u_short len) 1263{ 1264 struct ifnet *ifp = sc->ifp; 1265 struct ether_header *eh; 1266 struct mbuf *m; 1267 1268 /* Allocate a header mbuf */ 1269 MGETHDR(m, M_DONTWAIT, MT_DATA); 1270 if (m == NULL) 1271 return; 1272 m->m_pkthdr.rcvif = ifp; 1273 m->m_pkthdr.len = m->m_len = len; 1274 1275 /* 1276 * We always put the received packet in a single buffer - 1277 * either with just an mbuf header or in a cluster attached 1278 * to the header. The +2 is to compensate for the alignment 1279 * fixup below. 1280 */ 1281 if ((len + 2) > MHLEN) { 1282 /* Attach an mbuf cluster */ 1283 MCLGET(m, M_DONTWAIT); 1284 1285 /* Insist on getting a cluster */ 1286 if ((m->m_flags & M_EXT) == 0) { 1287 m_freem(m); 1288 return; 1289 } 1290 } 1291 1292 /* 1293 * The +2 is to longword align the start of the real packet. 1294 * This is important for NFS. 1295 */ 1296 m->m_data += 2; 1297 eh = mtod(m, struct ether_header *); 1298 1299 /* 1300 * Get packet, including link layer address, from interface. 1301 */ 1302 ed_ring_copy(sc, buf, (char *)eh, len); 1303 1304 m->m_pkthdr.len = m->m_len = len; 1305 1306 ED_UNLOCK(sc); 1307 (*ifp->if_input)(ifp, m); 1308 ED_LOCK(sc); 1309} 1310 1311/* 1312 * Supporting routines 1313 */ 1314 1315/* 1316 * Given a NIC memory source address and a host memory destination 1317 * address, copy 'amount' from NIC to host using shared memory. 1318 * The 'amount' is rounded up to a word - okay as long as mbufs 1319 * are word sized. That's what the +1 is below. 1320 * This routine accesses things as 16 bit quantities. 1321 */ 1322void 1323ed_shmem_readmem16(struct ed_softc *sc, bus_size_t src, uint8_t *dst, 1324 uint16_t amount) 1325{ 1326 bus_space_read_region_2(sc->mem_bst, sc->mem_bsh, src, (uint16_t *)dst, 1327 (amount + 1) / 2); 1328} 1329 1330/* 1331 * Given a NIC memory source address and a host memory destination 1332 * address, copy 'amount' from NIC to host using shared memory. 1333 * This routine accesses things as 8 bit quantities. 1334 */ 1335void 1336ed_shmem_readmem8(struct ed_softc *sc, bus_size_t src, uint8_t *dst, 1337 uint16_t amount) 1338{ 1339 bus_space_read_region_1(sc->mem_bst, sc->mem_bsh, src, dst, amount); 1340} 1341 1342/* 1343 * Given a NIC memory source address and a host memory destination 1344 * address, copy 'amount' from NIC to host using Programmed I/O. 1345 * The 'amount' is rounded up to a word - okay as long as mbufs 1346 * are word sized. 1347 * This routine is currently Novell-specific. 1348 */ 1349void 1350ed_pio_readmem(struct ed_softc *sc, bus_size_t src, uint8_t *dst, 1351 uint16_t amount) 1352{ 1353 /* Regular Novell cards */ 1354 /* select page 0 registers */ 1355 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STA); 1356 1357 /* round up to a word */ 1358 if (amount & 1) 1359 ++amount; 1360 1361 /* set up DMA byte count */ 1362 ed_nic_outb(sc, ED_P0_RBCR0, amount); 1363 ed_nic_outb(sc, ED_P0_RBCR1, amount >> 8); 1364 1365 /* set up source address in NIC mem */ 1366 ed_nic_outb(sc, ED_P0_RSAR0, src); 1367 ed_nic_outb(sc, ED_P0_RSAR1, src >> 8); 1368 1369 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD0 | ED_CR_STA); 1370 1371 if (sc->isa16bit) 1372 ed_asic_insw(sc, ED_NOVELL_DATA, dst, amount / 2); 1373 else 1374 ed_asic_insb(sc, ED_NOVELL_DATA, dst, amount); 1375} 1376 1377/* 1378 * Stripped down routine for writing a linear buffer to NIC memory. 1379 * Only used in the probe routine to test the memory. 'len' must 1380 * be even. 1381 */ 1382void 1383ed_pio_writemem(struct ed_softc *sc, uint8_t *src, uint16_t dst, uint16_t len) 1384{ 1385 int maxwait = 200; /* about 240us */ 1386 1387 /* select page 0 registers */ 1388 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STA); 1389 1390 /* reset remote DMA complete flag */ 1391 ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC); 1392 1393 /* set up DMA byte count */ 1394 ed_nic_outb(sc, ED_P0_RBCR0, len); 1395 ed_nic_outb(sc, ED_P0_RBCR1, len >> 8); 1396 1397 /* set up destination address in NIC mem */ 1398 ed_nic_outb(sc, ED_P0_RSAR0, dst); 1399 ed_nic_outb(sc, ED_P0_RSAR1, dst >> 8); 1400 1401 /* set remote DMA write */ 1402 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD1 | ED_CR_STA); 1403 1404 if (sc->isa16bit) 1405 ed_asic_outsw(sc, ED_NOVELL_DATA, src, len / 2); 1406 else 1407 ed_asic_outsb(sc, ED_NOVELL_DATA, src, len); 1408 1409 /* 1410 * Wait for remote DMA complete. This is necessary because on the 1411 * transmit side, data is handled internally by the NIC in bursts and 1412 * we can't start another remote DMA until this one completes. Not 1413 * waiting causes really bad things to happen - like the NIC 1414 * irrecoverably jamming the ISA bus. 1415 */ 1416 while (((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && 1417 --maxwait) 1418 continue; 1419} 1420 1421/* 1422 * Write an mbuf chain to the destination NIC memory address using 1423 * programmed I/O. 1424 */ 1425u_short 1426ed_pio_write_mbufs(struct ed_softc *sc, struct mbuf *m, bus_size_t dst) 1427{ 1428 struct ifnet *ifp = sc->ifp; 1429 unsigned short total_len, dma_len; 1430 struct mbuf *mp; 1431 int maxwait = 200; /* about 240us */ 1432 1433 ED_ASSERT_LOCKED(sc); 1434 1435 /* Regular Novell cards */ 1436 /* First, count up the total number of bytes to copy */ 1437 for (total_len = 0, mp = m; mp; mp = mp->m_next) 1438 total_len += mp->m_len; 1439 1440 dma_len = total_len; 1441 if (sc->isa16bit && (dma_len & 1)) 1442 dma_len++; 1443 1444 /* select page 0 registers */ 1445 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STA); 1446 1447 /* reset remote DMA complete flag */ 1448 ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC); 1449 1450 /* set up DMA byte count */ 1451 ed_nic_outb(sc, ED_P0_RBCR0, dma_len); 1452 ed_nic_outb(sc, ED_P0_RBCR1, dma_len >> 8); 1453 1454 /* set up destination address in NIC mem */ 1455 ed_nic_outb(sc, ED_P0_RSAR0, dst); 1456 ed_nic_outb(sc, ED_P0_RSAR1, dst >> 8); 1457 1458 /* set remote DMA write */ 1459 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD1 | ED_CR_STA); 1460 1461 /* 1462 * Transfer the mbuf chain to the NIC memory. 1463 * 16-bit cards require that data be transferred as words, and only words. 1464 * So that case requires some extra code to patch over odd-length mbufs. 1465 */ 1466 1467 if (!sc->isa16bit) { 1468 /* NE1000s are easy */ 1469 while (m) { 1470 if (m->m_len) 1471 ed_asic_outsb(sc, ED_NOVELL_DATA, 1472 m->m_data, m->m_len); 1473 m = m->m_next; 1474 } 1475 } else { 1476 /* NE2000s are a pain */ 1477 unsigned char *data; 1478 int len, wantbyte; 1479 unsigned char savebyte[2]; 1480 1481 wantbyte = 0; 1482 1483 while (m) { 1484 len = m->m_len; 1485 if (len) { 1486 data = mtod(m, caddr_t); 1487 /* finish the last word */ 1488 if (wantbyte) { 1489 savebyte[1] = *data; 1490 ed_asic_outw(sc, ED_NOVELL_DATA, 1491 *(u_short *)savebyte); 1492 data++; 1493 len--; 1494 wantbyte = 0; 1495 } 1496 /* output contiguous words */ 1497 if (len > 1) { 1498 ed_asic_outsw(sc, ED_NOVELL_DATA, 1499 data, len >> 1); 1500 data += len & ~1; 1501 len &= 1; 1502 } 1503 /* save last byte, if necessary */ 1504 if (len == 1) { 1505 savebyte[0] = *data; 1506 wantbyte = 1; 1507 } 1508 } 1509 m = m->m_next; 1510 } 1511 /* spit last byte */ 1512 if (wantbyte) 1513 ed_asic_outw(sc, ED_NOVELL_DATA, *(u_short *)savebyte); 1514 } 1515 1516 /* 1517 * Wait for remote DMA complete. This is necessary because on the 1518 * transmit side, data is handled internally by the NIC in bursts and 1519 * we can't start another remote DMA until this one completes. Not 1520 * waiting causes really bad things to happen - like the NIC 1521 * irrecoverably jamming the ISA bus. 1522 */ 1523 while (((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && 1524 --maxwait) 1525 continue; 1526 1527 if (!maxwait) { 1528 log(LOG_WARNING, "%s: remote transmit DMA failed to complete\n", 1529 ifp->if_xname); 1530 ed_reset(ifp); 1531 return(0); 1532 } 1533 return (total_len); 1534} 1535 1536static void 1537ed_setrcr(struct ed_softc *sc) 1538{ 1539 struct ifnet *ifp = sc->ifp; 1540 int i; 1541 u_char reg1; 1542 1543 ED_ASSERT_LOCKED(sc); 1544 1545 /* Bit 6 in AX88190 RCR register must be set. */ 1546 if (sc->chip_type == ED_CHIP_TYPE_AX88190 || 1547 sc->chip_type == ED_CHIP_TYPE_AX88790) 1548 reg1 = ED_RCR_INTT; 1549 else 1550 reg1 = 0x00; 1551 1552 /* set page 1 registers */ 1553 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP); 1554 1555 if (ifp->if_flags & IFF_PROMISC) { 1556 1557 /* 1558 * Reconfigure the multicast filter. 1559 */ 1560 for (i = 0; i < 8; i++) 1561 ed_nic_outb(sc, ED_P1_MAR(i), 0xff); 1562 1563 /* 1564 * And turn on promiscuous mode. Also enable reception of 1565 * runts and packets with CRC & alignment errors. 1566 */ 1567 /* Set page 0 registers */ 1568 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP); 1569 1570 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_PRO | ED_RCR_AM | 1571 ED_RCR_AB | ED_RCR_AR | ED_RCR_SEP | reg1); 1572 } else { 1573 /* set up multicast addresses and filter modes */ 1574 if (ifp->if_flags & IFF_MULTICAST) { 1575 uint32_t mcaf[2]; 1576 1577 if (ifp->if_flags & IFF_ALLMULTI) { 1578 mcaf[0] = 0xffffffff; 1579 mcaf[1] = 0xffffffff; 1580 } else 1581 ed_ds_getmcaf(sc, mcaf); 1582 1583 /* 1584 * Set multicast filter on chip. 1585 */ 1586 for (i = 0; i < 8; i++) 1587 ed_nic_outb(sc, ED_P1_MAR(i), ((u_char *) mcaf)[i]); 1588 1589 /* Set page 0 registers */ 1590 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP); 1591 1592 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_AM | ED_RCR_AB | reg1); 1593 } else { 1594 1595 /* 1596 * Initialize multicast address hashing registers to 1597 * not accept multicasts. 1598 */ 1599 for (i = 0; i < 8; ++i) 1600 ed_nic_outb(sc, ED_P1_MAR(i), 0x00); 1601 1602 /* Set page 0 registers */ 1603 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP); 1604 1605 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_AB | reg1); 1606 } 1607 } 1608 1609 /* 1610 * Start interface. 1611 */ 1612 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA); 1613} 1614 1615/* 1616 * Compute the multicast address filter from the 1617 * list of multicast addresses we need to listen to. 1618 */ 1619static void 1620ed_ds_getmcaf(struct ed_softc *sc, uint32_t *mcaf) 1621{ 1622 uint32_t index; 1623 u_char *af = (u_char *) mcaf; 1624 struct ifmultiaddr *ifma; 1625 1626 mcaf[0] = 0; 1627 mcaf[1] = 0; 1628 1629 IF_ADDR_LOCK(sc->ifp); 1630 TAILQ_FOREACH(ifma, &sc->ifp->if_multiaddrs, ifma_link) { 1631 if (ifma->ifma_addr->sa_family != AF_LINK) 1632 continue; 1633 index = ether_crc32_be(LLADDR((struct sockaddr_dl *) 1634 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 1635 af[index >> 3] |= 1 << (index & 7); 1636 } 1637 IF_ADDR_UNLOCK(sc->ifp); 1638} 1639 1640int 1641ed_isa_mem_ok(device_t dev, u_long pmem, u_int memsize) 1642{ 1643 if (pmem < 0xa0000 || pmem + memsize > 0x1000000) { 1644 device_printf(dev, "Invalid ISA memory address range " 1645 "configured: 0x%lx - 0x%lx\n", pmem, pmem + memsize); 1646 return (ENXIO); 1647 } 1648 return (0); 1649} 1650 1651int 1652ed_clear_memory(device_t dev) 1653{ 1654 struct ed_softc *sc = device_get_softc(dev); 1655 bus_size_t i; 1656 1657 bus_space_set_region_1(sc->mem_bst, sc->mem_bsh, sc->mem_start, 1658 0, sc->mem_size); 1659 1660 for (i = 0; i < sc->mem_size; i++) { 1661 if (bus_space_read_1(sc->mem_bst, sc->mem_bsh, 1662 sc->mem_start + i)) { 1663 device_printf(dev, "failed to clear shared memory at " 1664 "0x%jx - check configuration\n", 1665 (uintmax_t)rman_get_start(sc->mem_res) + i); 1666 return (ENXIO); 1667 } 1668 } 1669 return (0); 1670} 1671 1672u_short 1673ed_shmem_write_mbufs(struct ed_softc *sc, struct mbuf *m, bus_size_t dst) 1674{ 1675 u_short len; 1676 1677 /* 1678 * Special case setup for 16 bit boards... 1679 */ 1680 if (sc->isa16bit) { 1681 switch (sc->vendor) { 1682#ifdef ED_3C503 1683 /* 1684 * For 16bit 3Com boards (which have 16k of 1685 * memory), we have the xmit buffers in a 1686 * different page of memory ('page 0') - so 1687 * change pages. 1688 */ 1689 case ED_VENDOR_3COM: 1690 ed_asic_outb(sc, ED_3COM_GACFR, ED_3COM_GACFR_RSEL); 1691 break; 1692#endif 1693 /* 1694 * Enable 16bit access to shared memory on 1695 * WD/SMC boards. 1696 * 1697 * XXX - same as ed_enable_16bit_access() 1698 */ 1699 case ED_VENDOR_WD_SMC: 1700 ed_asic_outb(sc, ED_WD_LAAR, 1701 sc->wd_laar_proto | ED_WD_LAAR_M16EN); 1702 if (sc->chip_type == ED_CHIP_TYPE_WD790) 1703 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_MENB); 1704 break; 1705 } 1706 } 1707 for (len = 0; m != 0; m = m->m_next) { 1708 if (sc->isa16bit) 1709 bus_space_write_region_2(sc->mem_bst, 1710 sc->mem_bsh, dst, 1711 mtod(m, uint16_t *), (m->m_len + 1)/ 2); 1712 else 1713 bus_space_write_region_1(sc->mem_bst, 1714 sc->mem_bsh, dst, 1715 mtod(m, uint8_t *), m->m_len); 1716 dst += m->m_len; 1717 len += m->m_len; 1718 } 1719 1720 /* 1721 * Restore previous shared memory access 1722 */ 1723 if (sc->isa16bit) { 1724 switch (sc->vendor) { 1725#ifdef ED_3C503 1726 case ED_VENDOR_3COM: 1727 ed_asic_outb(sc, ED_3COM_GACFR, 1728 ED_3COM_GACFR_RSEL | ED_3COM_GACFR_MBS0); 1729 break; 1730#endif 1731 case ED_VENDOR_WD_SMC: 1732 /* XXX - same as ed_disable_16bit_access() */ 1733 if (sc->chip_type == ED_CHIP_TYPE_WD790) 1734 ed_asic_outb(sc, ED_WD_MSR, 0x00); 1735 ed_asic_outb(sc, ED_WD_LAAR, 1736 sc->wd_laar_proto & ~ED_WD_LAAR_M16EN); 1737 break; 1738 } 1739 } 1740 return (len); 1741} 1742