if_ed.c revision 150300
1/*- 2 * Copyright (c) 1995, David Greenman 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28#include <sys/cdefs.h> 29__FBSDID("$FreeBSD: head/sys/dev/ed/if_ed.c 150300 2005-09-18 20:51:34Z imp $"); 30 31/* 32 * Device driver for National Semiconductor DS8390/WD83C690 based ethernet 33 * adapters. By David Greenman, 29-April-1993 34 * 35 * Currently supports the Western Digital/SMC 8003 and 8013 series, 36 * the SMC Elite Ultra (8216), the 3Com 3c503, the NE1000 and NE2000, 37 * and a variety of similar clones. 38 * 39 */ 40 41#include "opt_ed.h" 42 43#include <sys/param.h> 44#include <sys/systm.h> 45#include <sys/sockio.h> 46#include <sys/mbuf.h> 47#include <sys/kernel.h> 48#include <sys/socket.h> 49#include <sys/syslog.h> 50 51#include <sys/bus.h> 52 53#include <machine/bus.h> 54#include <sys/rman.h> 55#include <machine/resource.h> 56 57#include <net/ethernet.h> 58#include <net/if.h> 59#include <net/if_arp.h> 60#include <net/if_dl.h> 61#include <net/if_mib.h> 62#include <net/if_media.h> 63#include <net/if_types.h> 64 65#include <net/bpf.h> 66 67#include <dev/ed/if_edreg.h> 68#include <dev/ed/if_edvar.h> 69#include <sys/kdb.h> 70 71devclass_t ed_devclass; 72 73static void ed_init(void *); 74static void ed_init_locked(struct ed_softc *); 75static int ed_ioctl(struct ifnet *, u_long, caddr_t); 76static void ed_start(struct ifnet *); 77static void ed_start_locked(struct ifnet *); 78static void ed_reset(struct ifnet *); 79static void ed_watchdog(struct ifnet *); 80 81static void ed_ds_getmcaf(struct ed_softc *, uint32_t *); 82 83static void ed_get_packet(struct ed_softc *, bus_size_t, u_short); 84static void ed_stop_hw(struct ed_softc *sc); 85 86static __inline void ed_rint(struct ed_softc *); 87static __inline void ed_xmit(struct ed_softc *); 88static __inline void ed_ring_copy(struct ed_softc *, bus_size_t, char *, 89 u_short); 90static u_short ed_pio_write_mbufs(struct ed_softc *, struct mbuf *, 91 bus_size_t); 92 93static void ed_setrcr(struct ed_softc *); 94 95/* 96 * Generic probe routine for testing for the existance of a DS8390. 97 * Must be called after the NIC has just been reset. This routine 98 * works by looking at certain register values that are guaranteed 99 * to be initialized a certain way after power-up or reset. Seems 100 * not to currently work on the 83C690. 101 * 102 * Specifically: 103 * 104 * Register reset bits set bits 105 * Command Register (CR) TXP, STA RD2, STP 106 * Interrupt Status (ISR) RST 107 * Interrupt Mask (IMR) All bits 108 * Data Control (DCR) LAS 109 * Transmit Config. (TCR) LB1, LB0 110 * 111 * We only look at the CR and ISR registers, however, because looking at 112 * the others would require changing register pages (which would be 113 * intrusive if this isn't an 8390). 114 * 115 * Return 1 if 8390 was found, 0 if not. 116 */ 117 118int 119ed_probe_generic8390(struct ed_softc *sc) 120{ 121 if ((ed_nic_inb(sc, ED_P0_CR) & 122 (ED_CR_RD2 | ED_CR_TXP | ED_CR_STA | ED_CR_STP)) != 123 (ED_CR_RD2 | ED_CR_STP)) 124 return (0); 125 if ((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RST) != ED_ISR_RST) 126 return (0); 127 128 return (1); 129} 130 131void 132ed_disable_16bit_access(struct ed_softc *sc) 133{ 134 /* 135 * Disable 16 bit access to shared memory 136 */ 137 if (sc->isa16bit && sc->vendor == ED_VENDOR_WD_SMC) { 138 if (sc->chip_type == ED_CHIP_TYPE_WD790) 139 ed_asic_outb(sc, ED_WD_MSR, 0x00); 140 ed_asic_outb(sc, ED_WD_LAAR, 141 sc->wd_laar_proto & ~ED_WD_LAAR_M16EN); 142 } 143} 144 145void 146ed_enable_16bit_access(struct ed_softc *sc) 147{ 148 if (sc->isa16bit && sc->vendor == ED_VENDOR_WD_SMC) { 149 ed_asic_outb(sc, ED_WD_LAAR, 150 sc->wd_laar_proto | ED_WD_LAAR_M16EN); 151 if (sc->chip_type == ED_CHIP_TYPE_WD790) 152 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_MENB); 153 } 154} 155 156/* 157 * Allocate a port resource with the given resource id. 158 */ 159int 160ed_alloc_port(device_t dev, int rid, int size) 161{ 162 struct ed_softc *sc = device_get_softc(dev); 163 struct resource *res; 164 165 res = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 166 0ul, ~0ul, size, RF_ACTIVE); 167 if (res) { 168 sc->port_rid = rid; 169 sc->port_res = res; 170 sc->port_used = size; 171 sc->port_bst = rman_get_bustag(res); 172 sc->port_bsh = rman_get_bushandle(res); 173 return (0); 174 } 175 return (ENOENT); 176} 177 178/* 179 * Allocate a memory resource with the given resource id. 180 */ 181int 182ed_alloc_memory(device_t dev, int rid, int size) 183{ 184 struct ed_softc *sc = device_get_softc(dev); 185 struct resource *res; 186 187 res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 188 0ul, ~0ul, size, RF_ACTIVE); 189 if (res) { 190 sc->mem_rid = rid; 191 sc->mem_res = res; 192 sc->mem_used = size; 193 sc->mem_bst = rman_get_bustag(res); 194 sc->mem_bsh = rman_get_bushandle(res); 195 return (0); 196 } 197 return (ENOENT); 198} 199 200/* 201 * Allocate an irq resource with the given resource id. 202 */ 203int 204ed_alloc_irq(device_t dev, int rid, int flags) 205{ 206 struct ed_softc *sc = device_get_softc(dev); 207 struct resource *res; 208 209 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE | flags); 210 if (res) { 211 sc->irq_rid = rid; 212 sc->irq_res = res; 213 return (0); 214 } 215 return (ENOENT); 216} 217 218/* 219 * Release all resources 220 */ 221void 222ed_release_resources(device_t dev) 223{ 224 struct ed_softc *sc = device_get_softc(dev); 225 226 if (sc->port_res) { 227 bus_deactivate_resource(dev, SYS_RES_IOPORT, 228 sc->port_rid, sc->port_res); 229 bus_release_resource(dev, SYS_RES_IOPORT, 230 sc->port_rid, sc->port_res); 231 sc->port_res = 0; 232 } 233 if (sc->mem_res) { 234 bus_deactivate_resource(dev, SYS_RES_MEMORY, 235 sc->mem_rid, sc->mem_res); 236 bus_release_resource(dev, SYS_RES_MEMORY, 237 sc->mem_rid, sc->mem_res); 238 sc->mem_res = 0; 239 } 240 if (sc->irq_res) { 241 bus_deactivate_resource(dev, SYS_RES_IRQ, 242 sc->irq_rid, sc->irq_res); 243 bus_release_resource(dev, SYS_RES_IRQ, 244 sc->irq_rid, sc->irq_res); 245 sc->irq_res = 0; 246 } 247 if (sc->ifp) 248 if_free(sc->ifp); 249} 250 251/* 252 * Install interface into kernel networking data structures 253 */ 254int 255ed_attach(device_t dev) 256{ 257 struct ed_softc *sc = device_get_softc(dev); 258 struct ifnet *ifp; 259 260 sc->dev = dev; 261 ED_LOCK_INIT(sc); 262 ifp = sc->ifp = if_alloc(IFT_ETHER); 263 if (ifp == NULL) { 264 device_printf(dev, "can not if_alloc()\n"); 265 ED_LOCK_DESTROY(sc); 266 return (ENOSPC); 267 } 268 269 if (sc->readmem == NULL) { 270 if (sc->mem_shared) { 271 if (sc->isa16bit) 272 sc->readmem = ed_shmem_readmem16; 273 else 274 sc->readmem = ed_shmem_readmem8; 275 } else { 276 sc->readmem = ed_pio_readmem; 277 } 278 } 279 280 callout_init_mtx(&sc->tick_ch, ED_MUTEX(sc), 0); 281 /* 282 * Set interface to stopped condition (reset) 283 */ 284 ed_stop_hw(sc); 285 286 /* 287 * Initialize ifnet structure 288 */ 289 ifp->if_softc = sc; 290 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 291 ifp->if_start = ed_start; 292 ifp->if_ioctl = ed_ioctl; 293 ifp->if_watchdog = ed_watchdog; 294 ifp->if_init = ed_init; 295 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 296 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN; 297 IFQ_SET_READY(&ifp->if_snd); 298 ifp->if_linkmib = &sc->mibdata; 299 ifp->if_linkmiblen = sizeof sc->mibdata; 300 /* 301 * XXX - should do a better job. 302 */ 303 if (sc->chip_type == ED_CHIP_TYPE_WD790) 304 sc->mibdata.dot3StatsEtherChipSet = 305 DOT3CHIPSET(dot3VendorWesternDigital, 306 dot3ChipSetWesternDigital83C790); 307 else 308 sc->mibdata.dot3StatsEtherChipSet = 309 DOT3CHIPSET(dot3VendorNational, 310 dot3ChipSetNational8390); 311 sc->mibdata.dot3Compliance = DOT3COMPLIANCE_COLLS; 312 313 /* 314 * Set default state for ALTPHYS flag (used to disable the 315 * tranceiver for AUI operation), based on config option. 316 */ 317 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 318 if (device_get_flags(dev) & ED_FLAGS_DISABLE_TRANCEIVER) 319 ifp->if_flags |= IFF_ALTPHYS; 320 321 /* 322 * Attach the interface 323 */ 324 ether_ifattach(ifp, sc->enaddr); 325 /* device attach does transition from UNCONFIGURED to IDLE state */ 326 327 if (bootverbose || 1) { 328 if (sc->type_str && (*sc->type_str != 0)) 329 device_printf(dev, "type %s ", sc->type_str); 330 else 331 device_printf(dev, "type unknown (0x%x) ", sc->type); 332 333#ifdef ED_HPP 334 if (sc->vendor == ED_VENDOR_HP) 335 printf("(%s %s IO)", 336 (sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS) ? 337 "16-bit" : "32-bit", 338 sc->hpp_mem_start ? "memory mapped" : "regular"); 339 else 340#endif 341 printf("%s ", sc->isa16bit ? "(16 bit)" : "(8 bit)"); 342 343#if defined(ED_HPP) || defined(ED_3C503) 344 printf("%s", (((sc->vendor == ED_VENDOR_3COM) || 345 (sc->vendor == ED_VENDOR_HP)) && 346 (ifp->if_flags & IFF_ALTPHYS)) ? 347 " tranceiver disabled" : ""); 348#endif 349 printf("\n"); 350 } 351 return (0); 352} 353 354/* 355 * Detach the driver from the hardware and other systems in the kernel. 356 */ 357int 358ed_detach(device_t dev) 359{ 360 struct ed_softc *sc = device_get_softc(dev); 361 struct ifnet *ifp = sc->ifp; 362 363 ED_ASSERT_UNLOCKED(sc); 364 ED_LOCK(sc); 365 if (bus_child_present(dev)) 366 ed_stop(sc); 367 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 368 ED_UNLOCK(sc); 369 callout_drain(&sc->tick_ch); 370 ether_ifdetach(ifp); 371 bus_teardown_intr(dev, sc->irq_res, sc->irq_handle); 372 if_free(ifp); 373 ed_release_resources(dev); 374 ED_LOCK_DESTROY(sc); 375 return (0); 376} 377 378/* 379 * Reset interface. 380 */ 381static void 382ed_reset(struct ifnet *ifp) 383{ 384 struct ed_softc *sc = ifp->if_softc; 385 386 ED_ASSERT_LOCKED(sc); 387 /* 388 * Stop interface and re-initialize. 389 */ 390 ed_stop(sc); 391 ed_init_locked(sc); 392} 393 394static void 395ed_stop_hw(struct ed_softc *sc) 396{ 397 int n = 5000; 398 399 /* 400 * Stop everything on the interface, and select page 0 registers. 401 */ 402 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP); 403 404 /* 405 * Wait for interface to enter stopped state, but limit # of checks to 406 * 'n' (about 5ms). It shouldn't even take 5us on modern DS8390's, but 407 * just in case it's an old one. 408 */ 409 if (sc->chip_type != ED_CHIP_TYPE_AX88190) 410 while (((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RST) == 0) && --n) 411 continue; 412} 413 414/* 415 * Take interface offline. 416 */ 417void 418ed_stop(struct ed_softc *sc) 419{ 420 ED_ASSERT_LOCKED(sc); 421 if (sc->sc_tick) 422 callout_stop(&sc->tick_ch); 423 ed_stop_hw(sc); 424} 425 426/* 427 * Device timeout/watchdog routine. Entered if the device neglects to 428 * generate an interrupt after a transmit has been started on it. 429 */ 430static void 431ed_watchdog(struct ifnet *ifp) 432{ 433 struct ed_softc *sc = ifp->if_softc; 434 435 log(LOG_ERR, "%s: device timeout\n", ifp->if_xname); 436 ifp->if_oerrors++; 437 438 ED_LOCK(sc); 439 ed_reset(ifp); 440 ED_UNLOCK(sc); 441} 442 443/* 444 * Initialize device. 445 */ 446static void 447ed_init(void *xsc) 448{ 449 struct ed_softc *sc = xsc; 450 451 ED_ASSERT_UNLOCKED(sc); 452 ED_LOCK(sc); 453 ed_init_locked(sc); 454 ED_UNLOCK(sc); 455} 456 457static void 458ed_init_locked(struct ed_softc *sc) 459{ 460 struct ifnet *ifp = sc->ifp; 461 int i; 462 463 ED_ASSERT_LOCKED(sc); 464 465 /* 466 * Initialize the NIC in the exact order outlined in the NS manual. 467 * This init procedure is "mandatory"...don't change what or when 468 * things happen. 469 */ 470 471 /* reset transmitter flags */ 472 sc->xmit_busy = 0; 473 ifp->if_timer = 0; 474 475 sc->txb_inuse = 0; 476 sc->txb_new = 0; 477 sc->txb_next_tx = 0; 478 479 /* This variable is used below - don't move this assignment */ 480 sc->next_packet = sc->rec_page_start + 1; 481 482 /* 483 * Set interface for page 0, Remote DMA complete, Stopped 484 */ 485 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP); 486 487 if (sc->isa16bit) 488 /* 489 * Set FIFO threshold to 8, No auto-init Remote DMA, byte 490 * order=80x86, word-wide DMA xfers, 491 */ 492 ed_nic_outb(sc, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_WTS | ED_DCR_LS); 493 else 494 /* 495 * Same as above, but byte-wide DMA xfers 496 */ 497 ed_nic_outb(sc, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS); 498 499 /* 500 * Clear Remote Byte Count Registers 501 */ 502 ed_nic_outb(sc, ED_P0_RBCR0, 0); 503 ed_nic_outb(sc, ED_P0_RBCR1, 0); 504 505 /* 506 * For the moment, don't store incoming packets in memory. 507 */ 508 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_MON); 509 510 /* 511 * Place NIC in internal loopback mode 512 */ 513 ed_nic_outb(sc, ED_P0_TCR, ED_TCR_LB0); 514 515 /* 516 * Initialize transmit/receive (ring-buffer) Page Start 517 */ 518 ed_nic_outb(sc, ED_P0_TPSR, sc->tx_page_start); 519 ed_nic_outb(sc, ED_P0_PSTART, sc->rec_page_start); 520 /* Set lower bits of byte addressable framing to 0 */ 521 if (sc->chip_type == ED_CHIP_TYPE_WD790) 522 ed_nic_outb(sc, 0x09, 0); 523 524 /* 525 * Initialize Receiver (ring-buffer) Page Stop and Boundry 526 */ 527 ed_nic_outb(sc, ED_P0_PSTOP, sc->rec_page_stop); 528 ed_nic_outb(sc, ED_P0_BNRY, sc->rec_page_start); 529 530 /* 531 * Clear all interrupts. A '1' in each bit position clears the 532 * corresponding flag. 533 */ 534 ed_nic_outb(sc, ED_P0_ISR, 0xff); 535 536 /* 537 * Enable the following interrupts: receive/transmit complete, 538 * receive/transmit error, and Receiver OverWrite. 539 * 540 * Counter overflow and Remote DMA complete are *not* enabled. 541 */ 542 ed_nic_outb(sc, ED_P0_IMR, 543 ED_IMR_PRXE | ED_IMR_PTXE | ED_IMR_RXEE | ED_IMR_TXEE | ED_IMR_OVWE); 544 545 /* 546 * Program Command Register for page 1 547 */ 548 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP); 549 550 /* 551 * Copy out our station address 552 */ 553 for (i = 0; i < ETHER_ADDR_LEN; ++i) 554 ed_nic_outb(sc, ED_P1_PAR(i), IFP2ENADDR(sc->ifp)[i]); 555 556 /* 557 * Set Current Page pointer to next_packet (initialized above) 558 */ 559 ed_nic_outb(sc, ED_P1_CURR, sc->next_packet); 560 561 /* 562 * Program Receiver Configuration Register and multicast filter. CR is 563 * set to page 0 on return. 564 */ 565 ed_setrcr(sc); 566 567 /* 568 * Take interface out of loopback 569 */ 570 ed_nic_outb(sc, ED_P0_TCR, 0); 571 572#ifdef ED_3C503 573 /* 574 * If this is a 3Com board, the tranceiver must be software enabled 575 * (there is no settable hardware default). 576 */ 577 if (sc->vendor == ED_VENDOR_3COM) { 578 if (ifp->if_flags & IFF_ALTPHYS) 579 ed_asic_outb(sc, ED_3COM_CR, 0); 580 else 581 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_XSEL); 582 } 583#endif 584 if (sc->sc_mediachg) 585 sc->sc_mediachg(sc); 586 587 /* 588 * Set 'running' flag, and clear output active flag. 589 */ 590 ifp->if_drv_flags |= IFF_DRV_RUNNING; 591 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 592 593 /* 594 * ...and attempt to start output 595 */ 596 ed_start_locked(ifp); 597 598 if (sc->sc_tick) 599 callout_reset(&sc->tick_ch, hz, sc->sc_tick, sc); 600} 601 602/* 603 * This routine actually starts the transmission on the interface 604 */ 605static __inline void 606ed_xmit(struct ed_softc *sc) 607{ 608 struct ifnet *ifp = sc->ifp; 609 unsigned short len; 610 611 len = sc->txb_len[sc->txb_next_tx]; 612 613 /* 614 * Set NIC for page 0 register access 615 */ 616 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA); 617 618 /* 619 * Set TX buffer start page 620 */ 621 ed_nic_outb(sc, ED_P0_TPSR, sc->tx_page_start + 622 sc->txb_next_tx * ED_TXBUF_SIZE); 623 624 /* 625 * Set TX length 626 */ 627 ed_nic_outb(sc, ED_P0_TBCR0, len); 628 ed_nic_outb(sc, ED_P0_TBCR1, len >> 8); 629 630 /* 631 * Set page 0, Remote DMA complete, Transmit Packet, and *Start* 632 */ 633 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_TXP | ED_CR_STA); 634 sc->xmit_busy = 1; 635 636 /* 637 * Point to next transmit buffer slot and wrap if necessary. 638 */ 639 sc->txb_next_tx++; 640 if (sc->txb_next_tx == sc->txb_cnt) 641 sc->txb_next_tx = 0; 642 643 /* 644 * Set a timer just in case we never hear from the board again 645 */ 646 ifp->if_timer = 2; 647} 648 649/* 650 * Start output on interface. 651 * We make two assumptions here: 652 * 1) that the current priority is set to splimp _before_ this code 653 * is called *and* is returned to the appropriate priority after 654 * return 655 * 2) that the IFF_DRV_OACTIVE flag is checked before this code is called 656 * (i.e. that the output part of the interface is idle) 657 */ 658static void 659ed_start(struct ifnet *ifp) 660{ 661 struct ed_softc *sc = ifp->if_softc; 662 663 ED_ASSERT_UNLOCKED(sc); 664 ED_LOCK(sc); 665 ed_start_locked(ifp); 666 ED_UNLOCK(sc); 667} 668 669static void 670ed_start_locked(struct ifnet *ifp) 671{ 672 struct ed_softc *sc = ifp->if_softc; 673 struct mbuf *m0, *m; 674 bus_size_t buffer; 675 int len; 676 677 ED_ASSERT_LOCKED(sc); 678outloop: 679 680 /* 681 * First, see if there are buffered packets and an idle transmitter - 682 * should never happen at this point. 683 */ 684 if (sc->txb_inuse && (sc->xmit_busy == 0)) { 685 printf("ed: packets buffered, but transmitter idle\n"); 686 ed_xmit(sc); 687 } 688 689 /* 690 * See if there is room to put another packet in the buffer. 691 */ 692 if (sc->txb_inuse == sc->txb_cnt) { 693 694 /* 695 * No room. Indicate this to the outside world and exit. 696 */ 697 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 698 return; 699 } 700 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 701 if (m == 0) { 702 703 /* 704 * We are using the !OACTIVE flag to indicate to the outside 705 * world that we can accept an additional packet rather than 706 * that the transmitter is _actually_ active. Indeed, the 707 * transmitter may be active, but if we haven't filled all the 708 * buffers with data then we still want to accept more. 709 */ 710 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 711 return; 712 } 713 714 /* 715 * Copy the mbuf chain into the transmit buffer 716 */ 717 m0 = m; 718 719 /* txb_new points to next open buffer slot */ 720 buffer = sc->mem_start + (sc->txb_new * ED_TXBUF_SIZE * ED_PAGE_SIZE); 721 722 if (sc->mem_shared) { 723 /* 724 * Special case setup for 16 bit boards... 725 */ 726 if (sc->isa16bit) { 727 switch (sc->vendor) { 728#ifdef ED_3C503 729 /* 730 * For 16bit 3Com boards (which have 16k of 731 * memory), we have the xmit buffers in a 732 * different page of memory ('page 0') - so 733 * change pages. 734 */ 735 case ED_VENDOR_3COM: 736 ed_asic_outb(sc, ED_3COM_GACFR, 737 ED_3COM_GACFR_RSEL); 738 break; 739#endif 740 /* 741 * Enable 16bit access to shared memory on 742 * WD/SMC boards. 743 * 744 * XXX - same as ed_enable_16bit_access() 745 */ 746 case ED_VENDOR_WD_SMC: 747 ed_asic_outb(sc, ED_WD_LAAR, 748 sc->wd_laar_proto | ED_WD_LAAR_M16EN); 749 if (sc->chip_type == ED_CHIP_TYPE_WD790) 750 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_MENB); 751 break; 752 } 753 } 754 for (len = 0; m != 0; m = m->m_next) { 755 if (sc->isa16bit) 756 bus_space_write_region_2(sc->mem_bst, 757 sc->mem_bsh, buffer, 758 mtod(m, uint16_t *), (m->m_len + 1)/ 2); 759 else 760 bus_space_write_region_1(sc->mem_bst, 761 sc->mem_bsh, buffer, 762 mtod(m, uint8_t *), m->m_len); 763 buffer += m->m_len; 764 len += m->m_len; 765 } 766 767 /* 768 * Restore previous shared memory access 769 */ 770 if (sc->isa16bit) { 771 switch (sc->vendor) { 772#ifdef ED_3C503 773 case ED_VENDOR_3COM: 774 ed_asic_outb(sc, ED_3COM_GACFR, 775 ED_3COM_GACFR_RSEL | ED_3COM_GACFR_MBS0); 776 break; 777#endif 778 case ED_VENDOR_WD_SMC: 779 /* XXX - same as ed_disable_16bit_access() */ 780 if (sc->chip_type == ED_CHIP_TYPE_WD790) 781 ed_asic_outb(sc, ED_WD_MSR, 0x00); 782 ed_asic_outb(sc, ED_WD_LAAR, 783 sc->wd_laar_proto & ~ED_WD_LAAR_M16EN); 784 break; 785 } 786 } 787 } else { 788 len = ed_pio_write_mbufs(sc, m, buffer); 789 if (len == 0) { 790 m_freem(m0); 791 goto outloop; 792 } 793 } 794 795 sc->txb_len[sc->txb_new] = max(len, (ETHER_MIN_LEN-ETHER_CRC_LEN)); 796 797 sc->txb_inuse++; 798 799 /* 800 * Point to next buffer slot and wrap if necessary. 801 */ 802 sc->txb_new++; 803 if (sc->txb_new == sc->txb_cnt) 804 sc->txb_new = 0; 805 806 if (sc->xmit_busy == 0) 807 ed_xmit(sc); 808 809 /* 810 * Tap off here if there is a bpf listener. 811 */ 812 BPF_MTAP(ifp, m0); 813 814 m_freem(m0); 815 816 /* 817 * Loop back to the top to possibly buffer more packets 818 */ 819 goto outloop; 820} 821 822/* 823 * Ethernet interface receiver interrupt. 824 */ 825static __inline void 826ed_rint(struct ed_softc *sc) 827{ 828 struct ifnet *ifp = sc->ifp; 829 u_char boundry; 830 u_short len; 831 struct ed_ring packet_hdr; 832 bus_size_t packet_ptr; 833 834 ED_ASSERT_LOCKED(sc); 835 836 /* 837 * Set NIC to page 1 registers to get 'current' pointer 838 */ 839 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA); 840 841 /* 842 * 'sc->next_packet' is the logical beginning of the ring-buffer - 843 * i.e. it points to where new data has been buffered. The 'CURR' 844 * (current) register points to the logical end of the ring-buffer - 845 * i.e. it points to where additional new data will be added. We loop 846 * here until the logical beginning equals the logical end (or in 847 * other words, until the ring-buffer is empty). 848 */ 849 while (sc->next_packet != ed_nic_inb(sc, ED_P1_CURR)) { 850 851 /* get pointer to this buffer's header structure */ 852 packet_ptr = sc->mem_ring + 853 (sc->next_packet - sc->rec_page_start) * ED_PAGE_SIZE; 854 855 /* 856 * The byte count includes a 4 byte header that was added by 857 * the NIC. 858 */ 859 sc->readmem(sc, packet_ptr, (char *) &packet_hdr, 860 sizeof(packet_hdr)); 861 len = packet_hdr.count; 862 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring)) || 863 len < (ETHER_MIN_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring))) { 864 /* 865 * Length is a wild value. There's a good chance that 866 * this was caused by the NIC being old and buggy. 867 * The bug is that the length low byte is duplicated in 868 * the high byte. Try to recalculate the length based on 869 * the pointer to the next packet. 870 */ 871 /* 872 * NOTE: sc->next_packet is pointing at the current packet. 873 */ 874 len &= ED_PAGE_SIZE - 1; /* preserve offset into page */ 875 if (packet_hdr.next_packet >= sc->next_packet) 876 len += (packet_hdr.next_packet - 877 sc->next_packet) * ED_PAGE_SIZE; 878 else 879 len += 880 ((packet_hdr.next_packet - sc->rec_page_start) + 881 (sc->rec_page_stop - sc->next_packet)) * ED_PAGE_SIZE; 882 /* 883 * because buffers are aligned on 256-byte boundary, 884 * the length computed above is off by 256 in almost 885 * all cases. Fix it... 886 */ 887 if (len & 0xff) 888 len -= 256; 889 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN 890 + sizeof(struct ed_ring))) 891 sc->mibdata.dot3StatsFrameTooLongs++; 892 } 893 894 /* 895 * Be fairly liberal about what we allow as a "reasonable" length 896 * so that a [crufty] packet will make it to BPF (and can thus 897 * be analyzed). Note that all that is really important is that 898 * we have a length that will fit into one mbuf cluster or less; 899 * the upper layer protocols can then figure out the length from 900 * their own length field(s). 901 * But make sure that we have at least a full ethernet header 902 * or we would be unable to call ether_input() later. 903 */ 904 if ((len >= sizeof(struct ed_ring) + ETHER_HDR_LEN) && 905 (len <= MCLBYTES) && 906 (packet_hdr.next_packet >= sc->rec_page_start) && 907 (packet_hdr.next_packet < sc->rec_page_stop)) { 908 /* 909 * Go get packet. 910 */ 911 ed_get_packet(sc, packet_ptr + sizeof(struct ed_ring), 912 len - sizeof(struct ed_ring)); 913 ifp->if_ipackets++; 914 } else { 915 /* 916 * Really BAD. The ring pointers are corrupted. 917 */ 918 log(LOG_ERR, 919 "%s: NIC memory corrupt - invalid packet length %d\n", 920 ifp->if_xname, len); 921 ifp->if_ierrors++; 922 ed_reset(ifp); 923 return; 924 } 925 926 /* 927 * Update next packet pointer 928 */ 929 sc->next_packet = packet_hdr.next_packet; 930 931 /* 932 * Update NIC boundry pointer - being careful to keep it one 933 * buffer behind. (as recommended by NS databook) 934 */ 935 boundry = sc->next_packet - 1; 936 if (boundry < sc->rec_page_start) 937 boundry = sc->rec_page_stop - 1; 938 939 /* 940 * Set NIC to page 0 registers to update boundry register 941 */ 942 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA); 943 ed_nic_outb(sc, ED_P0_BNRY, boundry); 944 945 /* 946 * Set NIC to page 1 registers before looping to top (prepare 947 * to get 'CURR' current pointer) 948 */ 949 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA); 950 } 951} 952 953/* 954 * Ethernet interface interrupt processor 955 */ 956void 957edintr(void *arg) 958{ 959 struct ed_softc *sc = (struct ed_softc*) arg; 960 struct ifnet *ifp = sc->ifp; 961 u_char isr; 962 int count; 963 964 ED_LOCK(sc); 965 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 966 ED_UNLOCK(sc); 967 return; 968 } 969 /* 970 * Set NIC to page 0 registers 971 */ 972 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA); 973 974 /* 975 * loop until there are no more new interrupts. When the card 976 * goes away, the hardware will read back 0xff. Looking at 977 * the interrupts, it would appear that 0xff is impossible, 978 * or at least extremely unlikely. 979 */ 980 while ((isr = ed_nic_inb(sc, ED_P0_ISR)) != 0 && isr != 0xff) { 981 982 /* 983 * reset all the bits that we are 'acknowledging' by writing a 984 * '1' to each bit position that was set (writing a '1' 985 * *clears* the bit) 986 */ 987 ed_nic_outb(sc, ED_P0_ISR, isr); 988 989 /* 990 * XXX workaround for AX88190 991 * We limit this to 5000 iterations. At 1us per inb/outb, 992 * this translates to about 15ms, which should be plenty 993 * of time, and also gives protection in the card eject 994 * case. 995 */ 996 if (sc->chip_type == ED_CHIP_TYPE_AX88190) { 997 count = 5000; /* 15ms */ 998 while (count-- && (ed_nic_inb(sc, ED_P0_ISR) & isr)) { 999 ed_nic_outb(sc, ED_P0_ISR,0); 1000 ed_nic_outb(sc, ED_P0_ISR,isr); 1001 } 1002 if (count == 0) 1003 break; 1004 } 1005 1006 /* 1007 * Handle transmitter interrupts. Handle these first because 1008 * the receiver will reset the board under some conditions. 1009 */ 1010 if (isr & (ED_ISR_PTX | ED_ISR_TXE)) { 1011 u_char collisions = ed_nic_inb(sc, ED_P0_NCR) & 0x0f; 1012 1013 /* 1014 * Check for transmit error. If a TX completed with an 1015 * error, we end up throwing the packet away. Really 1016 * the only error that is possible is excessive 1017 * collisions, and in this case it is best to allow 1018 * the automatic mechanisms of TCP to backoff the 1019 * flow. Of course, with UDP we're screwed, but this 1020 * is expected when a network is heavily loaded. 1021 */ 1022 (void) ed_nic_inb(sc, ED_P0_TSR); 1023 if (isr & ED_ISR_TXE) { 1024 u_char tsr; 1025 1026 /* 1027 * Excessive collisions (16) 1028 */ 1029 tsr = ed_nic_inb(sc, ED_P0_TSR); 1030 if ((tsr & ED_TSR_ABT) 1031 && (collisions == 0)) { 1032 1033 /* 1034 * When collisions total 16, the 1035 * P0_NCR will indicate 0, and the 1036 * TSR_ABT is set. 1037 */ 1038 collisions = 16; 1039 sc->mibdata.dot3StatsExcessiveCollisions++; 1040 sc->mibdata.dot3StatsCollFrequencies[15]++; 1041 } 1042 if (tsr & ED_TSR_OWC) 1043 sc->mibdata.dot3StatsLateCollisions++; 1044 if (tsr & ED_TSR_CDH) 1045 sc->mibdata.dot3StatsSQETestErrors++; 1046 if (tsr & ED_TSR_CRS) 1047 sc->mibdata.dot3StatsCarrierSenseErrors++; 1048 if (tsr & ED_TSR_FU) 1049 sc->mibdata.dot3StatsInternalMacTransmitErrors++; 1050 1051 /* 1052 * update output errors counter 1053 */ 1054 ifp->if_oerrors++; 1055 } else { 1056 1057 /* 1058 * Update total number of successfully 1059 * transmitted packets. 1060 */ 1061 ifp->if_opackets++; 1062 } 1063 1064 /* 1065 * reset tx busy and output active flags 1066 */ 1067 sc->xmit_busy = 0; 1068 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1069 1070 /* 1071 * clear watchdog timer 1072 */ 1073 ifp->if_timer = 0; 1074 1075 /* 1076 * Add in total number of collisions on last 1077 * transmission. 1078 */ 1079 ifp->if_collisions += collisions; 1080 switch(collisions) { 1081 case 0: 1082 case 16: 1083 break; 1084 case 1: 1085 sc->mibdata.dot3StatsSingleCollisionFrames++; 1086 sc->mibdata.dot3StatsCollFrequencies[0]++; 1087 break; 1088 default: 1089 sc->mibdata.dot3StatsMultipleCollisionFrames++; 1090 sc->mibdata. 1091 dot3StatsCollFrequencies[collisions-1] 1092 ++; 1093 break; 1094 } 1095 1096 /* 1097 * Decrement buffer in-use count if not zero (can only 1098 * be zero if a transmitter interrupt occured while 1099 * not actually transmitting). If data is ready to 1100 * transmit, start it transmitting, otherwise defer 1101 * until after handling receiver 1102 */ 1103 if (sc->txb_inuse && --sc->txb_inuse) 1104 ed_xmit(sc); 1105 } 1106 1107 /* 1108 * Handle receiver interrupts 1109 */ 1110 if (isr & (ED_ISR_PRX | ED_ISR_RXE | ED_ISR_OVW)) { 1111 1112 /* 1113 * Overwrite warning. In order to make sure that a 1114 * lockup of the local DMA hasn't occurred, we reset 1115 * and re-init the NIC. The NSC manual suggests only a 1116 * partial reset/re-init is necessary - but some chips 1117 * seem to want more. The DMA lockup has been seen 1118 * only with early rev chips - Methinks this bug was 1119 * fixed in later revs. -DG 1120 */ 1121 if (isr & ED_ISR_OVW) { 1122 ifp->if_ierrors++; 1123#ifdef DIAGNOSTIC 1124 log(LOG_WARNING, 1125 "%s: warning - receiver ring buffer overrun\n", 1126 ifp->if_xname); 1127#endif 1128 1129 /* 1130 * Stop/reset/re-init NIC 1131 */ 1132 ed_reset(ifp); 1133 } else { 1134 1135 /* 1136 * Receiver Error. One or more of: CRC error, 1137 * frame alignment error FIFO overrun, or 1138 * missed packet. 1139 */ 1140 if (isr & ED_ISR_RXE) { 1141 u_char rsr; 1142 rsr = ed_nic_inb(sc, ED_P0_RSR); 1143 if (rsr & ED_RSR_CRC) 1144 sc->mibdata.dot3StatsFCSErrors++; 1145 if (rsr & ED_RSR_FAE) 1146 sc->mibdata.dot3StatsAlignmentErrors++; 1147 if (rsr & ED_RSR_FO) 1148 sc->mibdata.dot3StatsInternalMacReceiveErrors++; 1149 ifp->if_ierrors++; 1150#ifdef ED_DEBUG 1151 if_printf(ifp, "receive error %x\n", 1152 ed_nic_inb(sc, ED_P0_RSR)); 1153#endif 1154 } 1155 1156 /* 1157 * Go get the packet(s) XXX - Doing this on an 1158 * error is dubious because there shouldn't be 1159 * any data to get (we've configured the 1160 * interface to not accept packets with 1161 * errors). 1162 */ 1163 1164 /* 1165 * Enable 16bit access to shared memory first 1166 * on WD/SMC boards. 1167 */ 1168 ed_enable_16bit_access(sc); 1169 ed_rint(sc); 1170 ed_disable_16bit_access(sc); 1171 } 1172 } 1173 1174 /* 1175 * If it looks like the transmitter can take more data, 1176 * attempt to start output on the interface. This is done 1177 * after handling the receiver to give the receiver priority. 1178 */ 1179 if ((ifp->if_drv_flags & IFF_DRV_OACTIVE) == 0) 1180 ed_start_locked(ifp); 1181 1182 /* 1183 * return NIC CR to standard state: page 0, remote DMA 1184 * complete, start (toggling the TXP bit off, even if was just 1185 * set in the transmit routine, is *okay* - it is 'edge' 1186 * triggered from low to high) 1187 */ 1188 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA); 1189 1190 /* 1191 * If the Network Talley Counters overflow, read them to reset 1192 * them. It appears that old 8390's won't clear the ISR flag 1193 * otherwise - resulting in an infinite loop. 1194 */ 1195 if (isr & ED_ISR_CNT) { 1196 (void) ed_nic_inb(sc, ED_P0_CNTR0); 1197 (void) ed_nic_inb(sc, ED_P0_CNTR1); 1198 (void) ed_nic_inb(sc, ED_P0_CNTR2); 1199 } 1200 } 1201 ED_UNLOCK(sc); 1202} 1203 1204/* 1205 * Process an ioctl request. 1206 */ 1207static int 1208ed_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1209{ 1210 struct ed_softc *sc = ifp->if_softc; 1211 struct ifreq *ifr = (struct ifreq *)data; 1212 int error = 0; 1213 1214 /* 1215 * XXX really needed? 1216 */ 1217 if (sc == NULL) { 1218 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1219 return (ENXIO); 1220 } 1221 1222 switch (command) { 1223 case SIOCSIFFLAGS: 1224 /* 1225 * If the interface is marked up and stopped, then start it. 1226 * If it is marked down and running, then stop it. 1227 */ 1228 ED_LOCK(sc); 1229 if (ifp->if_flags & IFF_UP) { 1230 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1231 ed_init_locked(sc); 1232 } else { 1233 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1234 ed_stop(sc); 1235 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1236 } 1237 } 1238 1239 /* 1240 * Promiscuous flag may have changed, so reprogram the RCR. 1241 */ 1242 ed_setrcr(sc); 1243 1244 /* 1245 * An unfortunate hack to provide the (required) software 1246 * control of the tranceiver for 3Com/HP boards. 1247 * The ALTPHYS flag disables the tranceiver if set. 1248 */ 1249#ifdef ED_3C503 1250 if (sc->vendor == ED_VENDOR_3COM) { 1251 if (ifp->if_flags & IFF_ALTPHYS) 1252 ed_asic_outb(sc, ED_3COM_CR, 0); 1253 else 1254 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_XSEL); 1255 } 1256#endif 1257#ifdef ED_HPP 1258 if (sc->vendor == ED_VENDOR_HP) 1259 ed_hpp_set_physical_link(sc); 1260#endif 1261 ED_UNLOCK(sc); 1262 break; 1263 1264 case SIOCADDMULTI: 1265 case SIOCDELMULTI: 1266 /* 1267 * Multicast list has changed; set the hardware filter 1268 * accordingly. 1269 */ 1270 ED_LOCK(sc); 1271 ed_setrcr(sc); 1272 ED_UNLOCK(sc); 1273 error = 0; 1274 break; 1275 1276 case SIOCGIFMEDIA: 1277 case SIOCSIFMEDIA: 1278 if (sc->sc_media_ioctl == NULL) { 1279 error = EINVAL; 1280 break; 1281 } 1282 sc->sc_media_ioctl(sc, ifr, command); 1283 break; 1284 1285 default: 1286 error = ether_ioctl(ifp, command, data); 1287 break; 1288 } 1289 return (error); 1290} 1291 1292/* 1293 * Given a source and destination address, copy 'amount' of a packet from 1294 * the ring buffer into a linear destination buffer. Takes into account 1295 * ring-wrap. 1296 */ 1297static __inline void 1298ed_ring_copy(struct ed_softc *sc, bus_size_t src, char *dst, u_short amount) 1299{ 1300 u_short tmp_amount; 1301 1302 /* does copy wrap to lower addr in ring buffer? */ 1303 if (src + amount > sc->mem_end) { 1304 tmp_amount = sc->mem_end - src; 1305 /* copy amount up to end of NIC memory */ 1306 sc->readmem(sc, src, dst, tmp_amount); 1307 amount -= tmp_amount; 1308 src = sc->mem_ring; 1309 dst += tmp_amount; 1310 } 1311 sc->readmem(sc, src, dst, amount); 1312} 1313 1314/* 1315 * Retreive packet from shared memory and send to the next level up via 1316 * ether_input(). 1317 */ 1318static void 1319ed_get_packet(struct ed_softc *sc, bus_size_t buf, u_short len) 1320{ 1321 struct ifnet *ifp = sc->ifp; 1322 struct ether_header *eh; 1323 struct mbuf *m; 1324 1325 /* Allocate a header mbuf */ 1326 MGETHDR(m, M_DONTWAIT, MT_DATA); 1327 if (m == NULL) 1328 return; 1329 m->m_pkthdr.rcvif = ifp; 1330 m->m_pkthdr.len = m->m_len = len; 1331 1332 /* 1333 * We always put the received packet in a single buffer - 1334 * either with just an mbuf header or in a cluster attached 1335 * to the header. The +2 is to compensate for the alignment 1336 * fixup below. 1337 */ 1338 if ((len + 2) > MHLEN) { 1339 /* Attach an mbuf cluster */ 1340 MCLGET(m, M_DONTWAIT); 1341 1342 /* Insist on getting a cluster */ 1343 if ((m->m_flags & M_EXT) == 0) { 1344 m_freem(m); 1345 return; 1346 } 1347 } 1348 1349 /* 1350 * The +2 is to longword align the start of the real packet. 1351 * This is important for NFS. 1352 */ 1353 m->m_data += 2; 1354 eh = mtod(m, struct ether_header *); 1355 1356 /* 1357 * Get packet, including link layer address, from interface. 1358 */ 1359 ed_ring_copy(sc, buf, (char *)eh, len); 1360 1361 m->m_pkthdr.len = m->m_len = len; 1362 1363 ED_UNLOCK(sc); 1364 (*ifp->if_input)(ifp, m); 1365 ED_LOCK(sc); 1366} 1367 1368/* 1369 * Supporting routines 1370 */ 1371 1372/* 1373 * Given a NIC memory source address and a host memory destination 1374 * address, copy 'amount' from NIC to host using shared memory. 1375 * The 'amount' is rounded up to a word - okay as long as mbufs 1376 * are word sized. That's what the +1 is below. 1377 * This routine accesses things as 16 bit quantities. 1378 */ 1379void 1380ed_shmem_readmem16(struct ed_softc *sc, bus_size_t src, uint8_t *dst, 1381 uint16_t amount) 1382{ 1383 bus_space_read_region_2(sc->mem_bst, sc->mem_bsh, src, (uint16_t *)dst, 1384 amount + 1 / 2); 1385} 1386 1387/* 1388 * Given a NIC memory source address and a host memory destination 1389 * address, copy 'amount' from NIC to host using shared memory. 1390 * This routine accesses things as 8 bit quantities. 1391 */ 1392void 1393ed_shmem_readmem8(struct ed_softc *sc, bus_size_t src, uint8_t *dst, 1394 uint16_t amount) 1395{ 1396 bus_space_read_region_1(sc->mem_bst, sc->mem_bsh, src, dst, amount); 1397} 1398 1399/* 1400 * Given a NIC memory source address and a host memory destination 1401 * address, copy 'amount' from NIC to host using Programmed I/O. 1402 * The 'amount' is rounded up to a word - okay as long as mbufs 1403 * are word sized. 1404 * This routine is currently Novell-specific. 1405 */ 1406void 1407ed_pio_readmem(struct ed_softc *sc, bus_size_t src, uint8_t *dst, 1408 uint16_t amount) 1409{ 1410 /* Regular Novell cards */ 1411 /* select page 0 registers */ 1412 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STA); 1413 1414 /* round up to a word */ 1415 if (amount & 1) 1416 ++amount; 1417 1418 /* set up DMA byte count */ 1419 ed_nic_outb(sc, ED_P0_RBCR0, amount); 1420 ed_nic_outb(sc, ED_P0_RBCR1, amount >> 8); 1421 1422 /* set up source address in NIC mem */ 1423 ed_nic_outb(sc, ED_P0_RSAR0, src); 1424 ed_nic_outb(sc, ED_P0_RSAR1, src >> 8); 1425 1426 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD0 | ED_CR_STA); 1427 1428 if (sc->isa16bit) 1429 ed_asic_insw(sc, ED_NOVELL_DATA, dst, amount / 2); 1430 else 1431 ed_asic_insb(sc, ED_NOVELL_DATA, dst, amount); 1432} 1433 1434/* 1435 * Stripped down routine for writing a linear buffer to NIC memory. 1436 * Only used in the probe routine to test the memory. 'len' must 1437 * be even. 1438 */ 1439void 1440ed_pio_writemem(struct ed_softc *sc, uint8_t *src, uint16_t dst, uint16_t len) 1441{ 1442 int maxwait = 200; /* about 240us */ 1443 1444 /* select page 0 registers */ 1445 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STA); 1446 1447 /* reset remote DMA complete flag */ 1448 ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC); 1449 1450 /* set up DMA byte count */ 1451 ed_nic_outb(sc, ED_P0_RBCR0, len); 1452 ed_nic_outb(sc, ED_P0_RBCR1, len >> 8); 1453 1454 /* set up destination address in NIC mem */ 1455 ed_nic_outb(sc, ED_P0_RSAR0, dst); 1456 ed_nic_outb(sc, ED_P0_RSAR1, dst >> 8); 1457 1458 /* set remote DMA write */ 1459 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD1 | ED_CR_STA); 1460 1461 if (sc->isa16bit) 1462 ed_asic_outsw(sc, ED_NOVELL_DATA, src, len / 2); 1463 else 1464 ed_asic_outsb(sc, ED_NOVELL_DATA, src, len); 1465 1466 /* 1467 * Wait for remote DMA complete. This is necessary because on the 1468 * transmit side, data is handled internally by the NIC in bursts and 1469 * we can't start another remote DMA until this one completes. Not 1470 * waiting causes really bad things to happen - like the NIC 1471 * irrecoverably jamming the ISA bus. 1472 */ 1473 while (((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && 1474 --maxwait) 1475 continue; 1476} 1477 1478/* 1479 * Write an mbuf chain to the destination NIC memory address using 1480 * programmed I/O. 1481 */ 1482static u_short 1483ed_pio_write_mbufs(struct ed_softc *sc, struct mbuf *m, bus_size_t dst) 1484{ 1485 struct ifnet *ifp = sc->ifp; 1486 unsigned short total_len, dma_len; 1487 struct mbuf *mp; 1488 int maxwait = 200; /* about 240us */ 1489 1490 ED_ASSERT_LOCKED(sc); 1491 1492#ifdef ED_HPP 1493 /* HP PC Lan+ cards need special handling */ 1494 if (sc->vendor == ED_VENDOR_HP && sc->type == ED_TYPE_HP_PCLANPLUS) 1495 return ed_hpp_write_mbufs(sc, m, dst); 1496#endif 1497 1498 /* Regular Novell cards */ 1499 /* First, count up the total number of bytes to copy */ 1500 for (total_len = 0, mp = m; mp; mp = mp->m_next) 1501 total_len += mp->m_len; 1502 1503 dma_len = total_len; 1504 if (sc->isa16bit && (dma_len & 1)) 1505 dma_len++; 1506 1507 /* select page 0 registers */ 1508 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STA); 1509 1510 /* reset remote DMA complete flag */ 1511 ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC); 1512 1513 /* set up DMA byte count */ 1514 ed_nic_outb(sc, ED_P0_RBCR0, dma_len); 1515 ed_nic_outb(sc, ED_P0_RBCR1, dma_len >> 8); 1516 1517 /* set up destination address in NIC mem */ 1518 ed_nic_outb(sc, ED_P0_RSAR0, dst); 1519 ed_nic_outb(sc, ED_P0_RSAR1, dst >> 8); 1520 1521 /* set remote DMA write */ 1522 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD1 | ED_CR_STA); 1523 1524 /* 1525 * Transfer the mbuf chain to the NIC memory. 1526 * 16-bit cards require that data be transferred as words, and only words. 1527 * So that case requires some extra code to patch over odd-length mbufs. 1528 */ 1529 1530 if (!sc->isa16bit) { 1531 /* NE1000s are easy */ 1532 while (m) { 1533 if (m->m_len) 1534 ed_asic_outsb(sc, ED_NOVELL_DATA, 1535 m->m_data, m->m_len); 1536 m = m->m_next; 1537 } 1538 } else { 1539 /* NE2000s are a pain */ 1540 unsigned char *data; 1541 int len, wantbyte; 1542 unsigned char savebyte[2]; 1543 1544 wantbyte = 0; 1545 1546 while (m) { 1547 len = m->m_len; 1548 if (len) { 1549 data = mtod(m, caddr_t); 1550 /* finish the last word */ 1551 if (wantbyte) { 1552 savebyte[1] = *data; 1553 ed_asic_outw(sc, ED_NOVELL_DATA, 1554 *(u_short *)savebyte); 1555 data++; 1556 len--; 1557 wantbyte = 0; 1558 } 1559 /* output contiguous words */ 1560 if (len > 1) { 1561 ed_asic_outsw(sc, ED_NOVELL_DATA, 1562 data, len >> 1); 1563 data += len & ~1; 1564 len &= 1; 1565 } 1566 /* save last byte, if necessary */ 1567 if (len == 1) { 1568 savebyte[0] = *data; 1569 wantbyte = 1; 1570 } 1571 } 1572 m = m->m_next; 1573 } 1574 /* spit last byte */ 1575 if (wantbyte) 1576 ed_asic_outw(sc, ED_NOVELL_DATA, *(u_short *)savebyte); 1577 } 1578 1579 /* 1580 * Wait for remote DMA complete. This is necessary because on the 1581 * transmit side, data is handled internally by the NIC in bursts and 1582 * we can't start another remote DMA until this one completes. Not 1583 * waiting causes really bad things to happen - like the NIC 1584 * irrecoverably jamming the ISA bus. 1585 */ 1586 while (((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && 1587 --maxwait) 1588 continue; 1589 1590 if (!maxwait) { 1591 log(LOG_WARNING, "%s: remote transmit DMA failed to complete\n", 1592 ifp->if_xname); 1593 ed_reset(ifp); 1594 return(0); 1595 } 1596 return (total_len); 1597} 1598 1599static void 1600ed_setrcr(struct ed_softc *sc) 1601{ 1602 struct ifnet *ifp = sc->ifp; 1603 int i; 1604 u_char reg1; 1605 1606 ED_ASSERT_LOCKED(sc); 1607 1608 /* Bit 6 in AX88190 RCR register must be set. */ 1609 if (sc->chip_type == ED_CHIP_TYPE_AX88190) 1610 reg1 = ED_RCR_INTT; 1611 else 1612 reg1 = 0x00; 1613 1614 /* set page 1 registers */ 1615 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP); 1616 1617 if (ifp->if_flags & IFF_PROMISC) { 1618 1619 /* 1620 * Reconfigure the multicast filter. 1621 */ 1622 for (i = 0; i < 8; i++) 1623 ed_nic_outb(sc, ED_P1_MAR(i), 0xff); 1624 1625 /* 1626 * And turn on promiscuous mode. Also enable reception of 1627 * runts and packets with CRC & alignment errors. 1628 */ 1629 /* Set page 0 registers */ 1630 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP); 1631 1632 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_PRO | ED_RCR_AM | 1633 ED_RCR_AB | ED_RCR_AR | ED_RCR_SEP | reg1); 1634 } else { 1635 /* set up multicast addresses and filter modes */ 1636 if (ifp->if_flags & IFF_MULTICAST) { 1637 uint32_t mcaf[2]; 1638 1639 if (ifp->if_flags & IFF_ALLMULTI) { 1640 mcaf[0] = 0xffffffff; 1641 mcaf[1] = 0xffffffff; 1642 } else 1643 ed_ds_getmcaf(sc, mcaf); 1644 1645 /* 1646 * Set multicast filter on chip. 1647 */ 1648 for (i = 0; i < 8; i++) 1649 ed_nic_outb(sc, ED_P1_MAR(i), ((u_char *) mcaf)[i]); 1650 1651 /* Set page 0 registers */ 1652 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP); 1653 1654 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_AM | ED_RCR_AB | reg1); 1655 } else { 1656 1657 /* 1658 * Initialize multicast address hashing registers to 1659 * not accept multicasts. 1660 */ 1661 for (i = 0; i < 8; ++i) 1662 ed_nic_outb(sc, ED_P1_MAR(i), 0x00); 1663 1664 /* Set page 0 registers */ 1665 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP); 1666 1667 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_AB | reg1); 1668 } 1669 } 1670 1671 /* 1672 * Start interface. 1673 */ 1674 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA); 1675} 1676 1677/* 1678 * Compute the multicast address filter from the 1679 * list of multicast addresses we need to listen to. 1680 */ 1681static void 1682ed_ds_getmcaf(struct ed_softc *sc, uint32_t *mcaf) 1683{ 1684 uint32_t index; 1685 u_char *af = (u_char *) mcaf; 1686 struct ifmultiaddr *ifma; 1687 1688 mcaf[0] = 0; 1689 mcaf[1] = 0; 1690 1691 IF_ADDR_LOCK(sc->ifp); 1692 TAILQ_FOREACH(ifma, &sc->ifp->if_multiaddrs, ifma_link) { 1693 if (ifma->ifma_addr->sa_family != AF_LINK) 1694 continue; 1695 index = ether_crc32_be(LLADDR((struct sockaddr_dl *) 1696 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 1697 af[index >> 3] |= 1 << (index & 7); 1698 } 1699 IF_ADDR_UNLOCK(sc->ifp); 1700} 1701 1702int 1703ed_isa_mem_ok(device_t dev, u_long pmem, u_int memsize) 1704{ 1705 if (pmem < 0xa0000 || pmem + memsize > 0x1000000) { 1706 device_printf(dev, "Invalid ISA memory address range " 1707 "configured: 0x%lx - 0x%lx\n", pmem, pmem + memsize); 1708 return (ENXIO); 1709 } 1710 return (0); 1711} 1712 1713int 1714ed_clear_memory(device_t dev) 1715{ 1716 struct ed_softc *sc = device_get_softc(dev); 1717 bus_size_t i; 1718 1719 bus_space_set_region_1(sc->mem_bst, sc->mem_bsh, sc->mem_start, 1720 0, sc->mem_size); 1721 1722 for (i = 0; i < sc->mem_size; i++) { 1723 if (bus_space_read_1(sc->mem_bst, sc->mem_bsh, 1724 sc->mem_start + i)) { 1725 device_printf(dev, "failed to clear shared memory at " 1726 "0x%jx - check configuration\n", 1727 (uintmax_t)rman_get_start(sc->mem_res) + i); 1728 return (ENXIO); 1729 } 1730 } 1731 return (0); 1732} 1733