if_ed.c revision 142259
1/*- 2 * Copyright (c) 1995, David Greenman 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28#include <sys/cdefs.h> 29__FBSDID("$FreeBSD: head/sys/dev/ed/if_ed.c 142259 2005-02-22 22:03:52Z imp $"); 30 31/* 32 * Device driver for National Semiconductor DS8390/WD83C690 based ethernet 33 * adapters. By David Greenman, 29-April-1993 34 * 35 * Currently supports the Western Digital/SMC 8003 and 8013 series, 36 * the SMC Elite Ultra (8216), the 3Com 3c503, the NE1000 and NE2000, 37 * and a variety of similar clones. 38 * 39 */ 40 41#include "opt_ed.h" 42 43#include <sys/param.h> 44#include <sys/systm.h> 45#include <sys/sockio.h> 46#include <sys/mbuf.h> 47#include <sys/kernel.h> 48#include <sys/socket.h> 49#include <sys/syslog.h> 50 51#include <sys/bus.h> 52 53#include <machine/bus.h> 54#include <sys/rman.h> 55#include <machine/resource.h> 56 57#include <net/ethernet.h> 58#include <net/if.h> 59#include <net/if_arp.h> 60#include <net/if_dl.h> 61#include <net/if_mib.h> 62#include <net/if_media.h> 63 64#ifndef ED_NO_MIIBUS 65#include <dev/mii/mii.h> 66#include <dev/mii/miivar.h> 67#endif 68 69#include <net/bpf.h> 70 71#include <dev/ed/if_edreg.h> 72#include <dev/ed/if_edvar.h> 73 74devclass_t ed_devclass; 75 76static void ed_init(void *); 77static int ed_ioctl(struct ifnet *, u_long, caddr_t); 78static void ed_start(struct ifnet *); 79static void ed_reset(struct ifnet *); 80static void ed_watchdog(struct ifnet *); 81#ifndef ED_NO_MIIBUS 82static void ed_tick(void *); 83#endif 84 85static void ed_ds_getmcaf(struct ed_softc *, uint32_t *); 86 87static void ed_get_packet(struct ed_softc *, char *, u_short); 88 89static __inline void ed_rint(struct ed_softc *); 90static __inline void ed_xmit(struct ed_softc *); 91static __inline char *ed_ring_copy(struct ed_softc *, char *, char *, u_short); 92static u_short ed_pio_write_mbufs(struct ed_softc *, struct mbuf *, long); 93 94static void ed_setrcr(struct ed_softc *); 95 96/* 97 * Generic probe routine for testing for the existance of a DS8390. 98 * Must be called after the NIC has just been reset. This routine 99 * works by looking at certain register values that are guaranteed 100 * to be initialized a certain way after power-up or reset. Seems 101 * not to currently work on the 83C690. 102 * 103 * Specifically: 104 * 105 * Register reset bits set bits 106 * Command Register (CR) TXP, STA RD2, STP 107 * Interrupt Status (ISR) RST 108 * Interrupt Mask (IMR) All bits 109 * Data Control (DCR) LAS 110 * Transmit Config. (TCR) LB1, LB0 111 * 112 * We only look at the CR and ISR registers, however, because looking at 113 * the others would require changing register pages (which would be 114 * intrusive if this isn't an 8390). 115 * 116 * Return 1 if 8390 was found, 0 if not. 117 */ 118 119int 120ed_probe_generic8390(struct ed_softc *sc) 121{ 122 if ((ed_nic_inb(sc, ED_P0_CR) & 123 (ED_CR_RD2 | ED_CR_TXP | ED_CR_STA | ED_CR_STP)) != 124 (ED_CR_RD2 | ED_CR_STP)) 125 return (0); 126 if ((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RST) != ED_ISR_RST) 127 return (0); 128 129 return (1); 130} 131 132void 133ed_disable_16bit_access(struct ed_softc *sc) 134{ 135 /* 136 * Disable 16 bit access to shared memory 137 */ 138 if (sc->isa16bit && sc->vendor == ED_VENDOR_WD_SMC) { 139 if (sc->chip_type == ED_CHIP_TYPE_WD790) 140 ed_asic_outb(sc, ED_WD_MSR, 0x00); 141 ed_asic_outb(sc, ED_WD_LAAR, 142 sc->wd_laar_proto & ~ED_WD_LAAR_M16EN); 143 } 144} 145 146void 147ed_enable_16bit_access(struct ed_softc *sc) 148{ 149 if (sc->isa16bit && sc->vendor == ED_VENDOR_WD_SMC) { 150 ed_asic_outb(sc, ED_WD_LAAR, 151 sc->wd_laar_proto | ED_WD_LAAR_M16EN); 152 if (sc->chip_type == ED_CHIP_TYPE_WD790) 153 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_MENB); 154 } 155} 156 157/* 158 * Allocate a port resource with the given resource id. 159 */ 160int 161ed_alloc_port(device_t dev, int rid, int size) 162{ 163 struct ed_softc *sc = device_get_softc(dev); 164 struct resource *res; 165 166 res = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 167 0ul, ~0ul, size, RF_ACTIVE); 168 if (res) { 169 sc->port_rid = rid; 170 sc->port_res = res; 171 sc->port_used = size; 172 sc->port_bst = rman_get_bustag(res); 173 sc->port_bsh = rman_get_bushandle(res); 174 return (0); 175 } 176 return (ENOENT); 177} 178 179/* 180 * Allocate a memory resource with the given resource id. 181 */ 182int 183ed_alloc_memory(device_t dev, int rid, int size) 184{ 185 struct ed_softc *sc = device_get_softc(dev); 186 struct resource *res; 187 188 res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 189 0ul, ~0ul, size, RF_ACTIVE); 190 if (res) { 191 sc->mem_rid = rid; 192 sc->mem_res = res; 193 sc->mem_used = size; 194 sc->mem_bst = rman_get_bustag(res); 195 sc->mem_bsh = rman_get_bushandle(res); 196 return (0); 197 } 198 return (ENOENT); 199} 200 201/* 202 * Allocate an irq resource with the given resource id. 203 */ 204int 205ed_alloc_irq(device_t dev, int rid, int flags) 206{ 207 struct ed_softc *sc = device_get_softc(dev); 208 struct resource *res; 209 210 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE | flags); 211 if (res) { 212 sc->irq_rid = rid; 213 sc->irq_res = res; 214 return (0); 215 } 216 return (ENOENT); 217} 218 219/* 220 * Release all resources 221 */ 222void 223ed_release_resources(device_t dev) 224{ 225 struct ed_softc *sc = device_get_softc(dev); 226 227 if (sc->port_res) { 228 bus_deactivate_resource(dev, SYS_RES_IOPORT, 229 sc->port_rid, sc->port_res); 230 bus_release_resource(dev, SYS_RES_IOPORT, 231 sc->port_rid, sc->port_res); 232 sc->port_res = 0; 233 } 234 if (sc->mem_res) { 235 bus_deactivate_resource(dev, SYS_RES_MEMORY, 236 sc->mem_rid, sc->mem_res); 237 bus_release_resource(dev, SYS_RES_MEMORY, 238 sc->mem_rid, sc->mem_res); 239 sc->mem_res = 0; 240 } 241 if (sc->irq_res) { 242 bus_deactivate_resource(dev, SYS_RES_IRQ, 243 sc->irq_rid, sc->irq_res); 244 bus_release_resource(dev, SYS_RES_IRQ, 245 sc->irq_rid, sc->irq_res); 246 sc->irq_res = 0; 247 } 248} 249 250/* 251 * Install interface into kernel networking data structures 252 */ 253int 254ed_attach(device_t dev) 255{ 256 struct ed_softc *sc = device_get_softc(dev); 257 struct ifnet *ifp = &sc->arpcom.ac_if; 258 259 callout_handle_init(&sc->tick_ch); 260 /* 261 * Set interface to stopped condition (reset) 262 */ 263 ed_stop(sc); 264 265 /* 266 * Initialize ifnet structure 267 */ 268 ifp->if_softc = sc; 269 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 270 ifp->if_start = ed_start; 271 ifp->if_ioctl = ed_ioctl; 272 ifp->if_watchdog = ed_watchdog; 273 ifp->if_init = ed_init; 274 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 275 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN; 276 IFQ_SET_READY(&ifp->if_snd); 277 ifp->if_linkmib = &sc->mibdata; 278 ifp->if_linkmiblen = sizeof sc->mibdata; 279 /* 280 * XXX - should do a better job. 281 */ 282 if (sc->chip_type == ED_CHIP_TYPE_WD790) 283 sc->mibdata.dot3StatsEtherChipSet = 284 DOT3CHIPSET(dot3VendorWesternDigital, 285 dot3ChipSetWesternDigital83C790); 286 else 287 sc->mibdata.dot3StatsEtherChipSet = 288 DOT3CHIPSET(dot3VendorNational, 289 dot3ChipSetNational8390); 290 sc->mibdata.dot3Compliance = DOT3COMPLIANCE_COLLS; 291 292 /* 293 * Set default state for ALTPHYS flag (used to disable the 294 * tranceiver for AUI operation), based on compile-time 295 * config option. 296 */ 297 if (device_get_flags(dev) & ED_FLAGS_DISABLE_TRANCEIVER) 298 ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX | 299 IFF_MULTICAST | IFF_ALTPHYS | IFF_NEEDSGIANT); 300 else 301 ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX | 302 IFF_MULTICAST | IFF_NEEDSGIANT); 303 304 /* 305 * Attach the interface 306 */ 307 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 308 /* device attach does transition from UNCONFIGURED to IDLE state */ 309 310 if (bootverbose || 1) { 311 if (sc->type_str && (*sc->type_str != 0)) 312 device_printf(dev, "type %s ", sc->type_str); 313 else 314 device_printf(dev, "type unknown (0x%x) ", sc->type); 315 316#ifdef ED_HPP 317 if (sc->vendor == ED_VENDOR_HP) 318 printf("(%s %s IO)", 319 (sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS) ? 320 "16-bit" : "32-bit", 321 sc->hpp_mem_start ? "memory mapped" : "regular"); 322 else 323#endif 324 printf("%s ", sc->isa16bit ? "(16 bit)" : "(8 bit)"); 325 326#if defined(ED_HPP) || defined(ED_3C503) 327 printf("%s\n", (((sc->vendor == ED_VENDOR_3COM) || 328 (sc->vendor == ED_VENDOR_HP)) && 329 (ifp->if_flags & IFF_ALTPHYS)) ? 330 " tranceiver disabled" : ""); 331#endif 332 printf("\n"); 333 } 334 return (0); 335} 336 337/* 338 * Detach the driver from the hardware and other systems in the kernel. 339 */ 340int 341ed_detach(device_t dev) 342{ 343 struct ed_softc *sc = device_get_softc(dev); 344 struct ifnet *ifp = &sc->arpcom.ac_if; 345 346 if (sc->gone) 347 return (0); 348 ed_stop(sc); 349 ifp->if_flags &= ~IFF_RUNNING; 350 ether_ifdetach(ifp); 351 sc->gone = 1; 352 bus_teardown_intr(dev, sc->irq_res, sc->irq_handle); 353 ed_release_resources(dev); 354 return (0); 355} 356 357/* 358 * Reset interface. 359 */ 360static void 361ed_reset(struct ifnet *ifp) 362{ 363 struct ed_softc *sc = ifp->if_softc; 364 int s; 365 366 if (sc->gone) 367 return; 368 s = splimp(); 369 370 /* 371 * Stop interface and re-initialize. 372 */ 373 ed_stop(sc); 374 ed_init(sc); 375 376 (void) splx(s); 377} 378 379/* 380 * Take interface offline. 381 */ 382void 383ed_stop(struct ed_softc *sc) 384{ 385 int n = 5000; 386 387#ifndef ED_NO_MIIBUS 388 untimeout(ed_tick, sc, sc->tick_ch); 389 callout_handle_init(&sc->tick_ch); 390#endif 391 if (sc->gone) 392 return; 393 /* 394 * Stop everything on the interface, and select page 0 registers. 395 */ 396 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP); 397 398 /* 399 * Wait for interface to enter stopped state, but limit # of checks to 400 * 'n' (about 5ms). It shouldn't even take 5us on modern DS8390's, but 401 * just in case it's an old one. 402 */ 403 if (sc->chip_type != ED_CHIP_TYPE_AX88190) 404 while (((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RST) == 0) && --n) 405 continue; 406} 407 408/* 409 * Device timeout/watchdog routine. Entered if the device neglects to 410 * generate an interrupt after a transmit has been started on it. 411 */ 412static void 413ed_watchdog(struct ifnet *ifp) 414{ 415 struct ed_softc *sc = ifp->if_softc; 416 417 if (sc->gone) 418 return; 419 log(LOG_ERR, "%s: device timeout\n", ifp->if_xname); 420 ifp->if_oerrors++; 421 422 ed_reset(ifp); 423} 424 425#ifndef ED_NO_MIIBUS 426static void 427ed_tick(void *arg) 428{ 429 struct ed_softc *sc = arg; 430 struct mii_data *mii; 431 int s; 432 433 if (sc->gone) { 434 callout_handle_init(&sc->tick_ch); 435 return; 436 } 437 s = splimp(); 438 if (sc->miibus != NULL) { 439 mii = device_get_softc(sc->miibus); 440 mii_tick(mii); 441 } 442 sc->tick_ch = timeout(ed_tick, sc, hz); 443 splx(s); 444} 445#endif 446 447/* 448 * Initialize device. 449 */ 450static void 451ed_init(void *xsc) 452{ 453 struct ed_softc *sc = xsc; 454 struct ifnet *ifp = &sc->arpcom.ac_if; 455 int i, s; 456 457 if (sc->gone) 458 return; 459 460 /* 461 * Initialize the NIC in the exact order outlined in the NS manual. 462 * This init procedure is "mandatory"...don't change what or when 463 * things happen. 464 */ 465 s = splimp(); 466 467 /* reset transmitter flags */ 468 sc->xmit_busy = 0; 469 ifp->if_timer = 0; 470 471 sc->txb_inuse = 0; 472 sc->txb_new = 0; 473 sc->txb_next_tx = 0; 474 475 /* This variable is used below - don't move this assignment */ 476 sc->next_packet = sc->rec_page_start + 1; 477 478 /* 479 * Set interface for page 0, Remote DMA complete, Stopped 480 */ 481 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP); 482 483 if (sc->isa16bit) 484 /* 485 * Set FIFO threshold to 8, No auto-init Remote DMA, byte 486 * order=80x86, word-wide DMA xfers, 487 */ 488 ed_nic_outb(sc, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_WTS | ED_DCR_LS); 489 else 490 /* 491 * Same as above, but byte-wide DMA xfers 492 */ 493 ed_nic_outb(sc, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS); 494 495 /* 496 * Clear Remote Byte Count Registers 497 */ 498 ed_nic_outb(sc, ED_P0_RBCR0, 0); 499 ed_nic_outb(sc, ED_P0_RBCR1, 0); 500 501 /* 502 * For the moment, don't store incoming packets in memory. 503 */ 504 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_MON); 505 506 /* 507 * Place NIC in internal loopback mode 508 */ 509 ed_nic_outb(sc, ED_P0_TCR, ED_TCR_LB0); 510 511 /* 512 * Initialize transmit/receive (ring-buffer) Page Start 513 */ 514 ed_nic_outb(sc, ED_P0_TPSR, sc->tx_page_start); 515 ed_nic_outb(sc, ED_P0_PSTART, sc->rec_page_start); 516 /* Set lower bits of byte addressable framing to 0 */ 517 if (sc->chip_type == ED_CHIP_TYPE_WD790) 518 ed_nic_outb(sc, 0x09, 0); 519 520 /* 521 * Initialize Receiver (ring-buffer) Page Stop and Boundry 522 */ 523 ed_nic_outb(sc, ED_P0_PSTOP, sc->rec_page_stop); 524 ed_nic_outb(sc, ED_P0_BNRY, sc->rec_page_start); 525 526 /* 527 * Clear all interrupts. A '1' in each bit position clears the 528 * corresponding flag. 529 */ 530 ed_nic_outb(sc, ED_P0_ISR, 0xff); 531 532 /* 533 * Enable the following interrupts: receive/transmit complete, 534 * receive/transmit error, and Receiver OverWrite. 535 * 536 * Counter overflow and Remote DMA complete are *not* enabled. 537 */ 538 ed_nic_outb(sc, ED_P0_IMR, 539 ED_IMR_PRXE | ED_IMR_PTXE | ED_IMR_RXEE | ED_IMR_TXEE | ED_IMR_OVWE); 540 541 /* 542 * Program Command Register for page 1 543 */ 544 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP); 545 546 /* 547 * Copy out our station address 548 */ 549 for (i = 0; i < ETHER_ADDR_LEN; ++i) 550 ed_nic_outb(sc, ED_P1_PAR(i), sc->arpcom.ac_enaddr[i]); 551 552 /* 553 * Set Current Page pointer to next_packet (initialized above) 554 */ 555 ed_nic_outb(sc, ED_P1_CURR, sc->next_packet); 556 557 /* 558 * Program Receiver Configuration Register and multicast filter. CR is 559 * set to page 0 on return. 560 */ 561 ed_setrcr(sc); 562 563 /* 564 * Take interface out of loopback 565 */ 566 ed_nic_outb(sc, ED_P0_TCR, 0); 567 568#ifdef ED_3C503 569 /* 570 * If this is a 3Com board, the tranceiver must be software enabled 571 * (there is no settable hardware default). 572 */ 573 if (sc->vendor == ED_VENDOR_3COM) { 574 if (ifp->if_flags & IFF_ALTPHYS) 575 ed_asic_outb(sc, ED_3COM_CR, 0); 576 else 577 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_XSEL); 578 } 579#endif 580#ifndef ED_NO_MIIBUS 581 if (sc->miibus != NULL) { 582 struct mii_data *mii; 583 mii = device_get_softc(sc->miibus); 584 mii_mediachg(mii); 585 } 586#endif 587 /* 588 * Set 'running' flag, and clear output active flag. 589 */ 590 ifp->if_flags |= IFF_RUNNING; 591 ifp->if_flags &= ~IFF_OACTIVE; 592 593 /* 594 * ...and attempt to start output 595 */ 596 ed_start(ifp); 597 598#ifndef ED_NO_MIIBUS 599 untimeout(ed_tick, sc, sc->tick_ch); 600 sc->tick_ch = timeout(ed_tick, sc, hz); 601#endif 602 (void) splx(s); 603} 604 605/* 606 * This routine actually starts the transmission on the interface 607 */ 608static __inline void 609ed_xmit(struct ed_softc *sc) 610{ 611 struct ifnet *ifp = (struct ifnet *)sc; 612 unsigned short len; 613 614 if (sc->gone) 615 return; 616 len = sc->txb_len[sc->txb_next_tx]; 617 618 /* 619 * Set NIC for page 0 register access 620 */ 621 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA); 622 623 /* 624 * Set TX buffer start page 625 */ 626 ed_nic_outb(sc, ED_P0_TPSR, sc->tx_page_start + 627 sc->txb_next_tx * ED_TXBUF_SIZE); 628 629 /* 630 * Set TX length 631 */ 632 ed_nic_outb(sc, ED_P0_TBCR0, len); 633 ed_nic_outb(sc, ED_P0_TBCR1, len >> 8); 634 635 /* 636 * Set page 0, Remote DMA complete, Transmit Packet, and *Start* 637 */ 638 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_TXP | ED_CR_STA); 639 sc->xmit_busy = 1; 640 641 /* 642 * Point to next transmit buffer slot and wrap if necessary. 643 */ 644 sc->txb_next_tx++; 645 if (sc->txb_next_tx == sc->txb_cnt) 646 sc->txb_next_tx = 0; 647 648 /* 649 * Set a timer just in case we never hear from the board again 650 */ 651 ifp->if_timer = 2; 652} 653 654/* 655 * Start output on interface. 656 * We make two assumptions here: 657 * 1) that the current priority is set to splimp _before_ this code 658 * is called *and* is returned to the appropriate priority after 659 * return 660 * 2) that the IFF_OACTIVE flag is checked before this code is called 661 * (i.e. that the output part of the interface is idle) 662 */ 663static void 664ed_start(struct ifnet *ifp) 665{ 666 struct ed_softc *sc = ifp->if_softc; 667 struct mbuf *m0, *m; 668 caddr_t buffer; 669 int len; 670 671 if (sc->gone) { 672 printf("ed_start(%p) GONE\n",ifp); 673 return; 674 } 675outloop: 676 677 /* 678 * First, see if there are buffered packets and an idle transmitter - 679 * should never happen at this point. 680 */ 681 if (sc->txb_inuse && (sc->xmit_busy == 0)) { 682 printf("ed: packets buffered, but transmitter idle\n"); 683 ed_xmit(sc); 684 } 685 686 /* 687 * See if there is room to put another packet in the buffer. 688 */ 689 if (sc->txb_inuse == sc->txb_cnt) { 690 691 /* 692 * No room. Indicate this to the outside world and exit. 693 */ 694 ifp->if_flags |= IFF_OACTIVE; 695 return; 696 } 697 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 698 if (m == 0) { 699 700 /* 701 * We are using the !OACTIVE flag to indicate to the outside 702 * world that we can accept an additional packet rather than 703 * that the transmitter is _actually_ active. Indeed, the 704 * transmitter may be active, but if we haven't filled all the 705 * buffers with data then we still want to accept more. 706 */ 707 ifp->if_flags &= ~IFF_OACTIVE; 708 return; 709 } 710 711 /* 712 * Copy the mbuf chain into the transmit buffer 713 */ 714 715 m0 = m; 716 717 /* txb_new points to next open buffer slot */ 718 buffer = sc->mem_start + (sc->txb_new * ED_TXBUF_SIZE * ED_PAGE_SIZE); 719 720 if (sc->mem_shared) { 721 /* 722 * Special case setup for 16 bit boards... 723 */ 724 if (sc->isa16bit) { 725 switch (sc->vendor) { 726#ifdef ED_3C503 727 /* 728 * For 16bit 3Com boards (which have 16k of 729 * memory), we have the xmit buffers in a 730 * different page of memory ('page 0') - so 731 * change pages. 732 */ 733 case ED_VENDOR_3COM: 734 ed_asic_outb(sc, ED_3COM_GACFR, 735 ED_3COM_GACFR_RSEL); 736 break; 737#endif 738 /* 739 * Enable 16bit access to shared memory on 740 * WD/SMC boards. 741 * 742 * XXX - same as ed_enable_16bit_access() 743 */ 744 case ED_VENDOR_WD_SMC: 745 ed_asic_outb(sc, ED_WD_LAAR, 746 sc->wd_laar_proto | ED_WD_LAAR_M16EN); 747 if (sc->chip_type == ED_CHIP_TYPE_WD790) 748 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_MENB); 749 break; 750 } 751 } 752 for (len = 0; m != 0; m = m->m_next) { 753 /* XXX 754 * I'm not sure that this bcopy does only 16bit 755 * access 756 */ 757 bcopy(mtod(m, caddr_t), buffer, m->m_len); 758 buffer += m->m_len; 759 len += m->m_len; 760 } 761 762 /* 763 * Restore previous shared memory access 764 */ 765 if (sc->isa16bit) { 766 switch (sc->vendor) { 767#ifdef ED_3C503 768 case ED_VENDOR_3COM: 769 ed_asic_outb(sc, ED_3COM_GACFR, 770 ED_3COM_GACFR_RSEL | ED_3COM_GACFR_MBS0); 771 break; 772#endif 773 case ED_VENDOR_WD_SMC: 774 /* XXX - same as ed_disable_16bit_access() */ 775 if (sc->chip_type == ED_CHIP_TYPE_WD790) 776 ed_asic_outb(sc, ED_WD_MSR, 0x00); 777 ed_asic_outb(sc, ED_WD_LAAR, 778 sc->wd_laar_proto & ~ED_WD_LAAR_M16EN); 779 break; 780 } 781 } 782 } else { 783 len = ed_pio_write_mbufs(sc, m, (uintptr_t)buffer); 784 if (len == 0) { 785 m_freem(m0); 786 goto outloop; 787 } 788 } 789 790 sc->txb_len[sc->txb_new] = max(len, (ETHER_MIN_LEN-ETHER_CRC_LEN)); 791 792 sc->txb_inuse++; 793 794 /* 795 * Point to next buffer slot and wrap if necessary. 796 */ 797 sc->txb_new++; 798 if (sc->txb_new == sc->txb_cnt) 799 sc->txb_new = 0; 800 801 if (sc->xmit_busy == 0) 802 ed_xmit(sc); 803 804 /* 805 * Tap off here if there is a bpf listener. 806 */ 807 BPF_MTAP(ifp, m0); 808 809 m_freem(m0); 810 811 /* 812 * Loop back to the top to possibly buffer more packets 813 */ 814 goto outloop; 815} 816 817/* 818 * Ethernet interface receiver interrupt. 819 */ 820static __inline void 821ed_rint(struct ed_softc *sc) 822{ 823 struct ifnet *ifp = &sc->arpcom.ac_if; 824 u_char boundry; 825 u_short len; 826 struct ed_ring packet_hdr; 827 char *packet_ptr; 828 829 if (sc->gone) 830 return; 831 832 /* 833 * Set NIC to page 1 registers to get 'current' pointer 834 */ 835 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA); 836 837 /* 838 * 'sc->next_packet' is the logical beginning of the ring-buffer - 839 * i.e. it points to where new data has been buffered. The 'CURR' 840 * (current) register points to the logical end of the ring-buffer - 841 * i.e. it points to where additional new data will be added. We loop 842 * here until the logical beginning equals the logical end (or in 843 * other words, until the ring-buffer is empty). 844 */ 845 while (sc->next_packet != ed_nic_inb(sc, ED_P1_CURR)) { 846 847 /* get pointer to this buffer's header structure */ 848 packet_ptr = sc->mem_ring + 849 (sc->next_packet - sc->rec_page_start) * ED_PAGE_SIZE; 850 851 /* 852 * The byte count includes a 4 byte header that was added by 853 * the NIC. 854 */ 855 if (sc->mem_shared) 856 packet_hdr = *(struct ed_ring *) packet_ptr; 857 else 858 ed_pio_readmem(sc, (uintptr_t)packet_ptr, 859 (char *) &packet_hdr, sizeof(packet_hdr)); 860 len = packet_hdr.count; 861 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring)) || 862 len < (ETHER_MIN_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring))) { 863 /* 864 * Length is a wild value. There's a good chance that 865 * this was caused by the NIC being old and buggy. 866 * The bug is that the length low byte is duplicated in 867 * the high byte. Try to recalculate the length based on 868 * the pointer to the next packet. 869 */ 870 /* 871 * NOTE: sc->next_packet is pointing at the current packet. 872 */ 873 len &= ED_PAGE_SIZE - 1; /* preserve offset into page */ 874 if (packet_hdr.next_packet >= sc->next_packet) 875 len += (packet_hdr.next_packet - 876 sc->next_packet) * ED_PAGE_SIZE; 877 else 878 len += 879 ((packet_hdr.next_packet - sc->rec_page_start) + 880 (sc->rec_page_stop - sc->next_packet)) * ED_PAGE_SIZE; 881 /* 882 * because buffers are aligned on 256-byte boundary, 883 * the length computed above is off by 256 in almost 884 * all cases. Fix it... 885 */ 886 if (len & 0xff) 887 len -= 256; 888 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN 889 + sizeof(struct ed_ring))) 890 sc->mibdata.dot3StatsFrameTooLongs++; 891 } 892 893 /* 894 * Be fairly liberal about what we allow as a "reasonable" length 895 * so that a [crufty] packet will make it to BPF (and can thus 896 * be analyzed). Note that all that is really important is that 897 * we have a length that will fit into one mbuf cluster or less; 898 * the upper layer protocols can then figure out the length from 899 * their own length field(s). 900 * But make sure that we have at least a full ethernet header 901 * or we would be unable to call ether_input() later. 902 */ 903 if ((len >= sizeof(struct ed_ring) + ETHER_HDR_LEN) && 904 (len <= MCLBYTES) && 905 (packet_hdr.next_packet >= sc->rec_page_start) && 906 (packet_hdr.next_packet < sc->rec_page_stop)) { 907 /* 908 * Go get packet. 909 */ 910 ed_get_packet(sc, packet_ptr + sizeof(struct ed_ring), 911 len - sizeof(struct ed_ring)); 912 ifp->if_ipackets++; 913 } else { 914 /* 915 * Really BAD. The ring pointers are corrupted. 916 */ 917 log(LOG_ERR, 918 "%s: NIC memory corrupt - invalid packet length %d\n", 919 ifp->if_xname, len); 920 ifp->if_ierrors++; 921 ed_reset(ifp); 922 return; 923 } 924 925 /* 926 * Update next packet pointer 927 */ 928 sc->next_packet = packet_hdr.next_packet; 929 930 /* 931 * Update NIC boundry pointer - being careful to keep it one 932 * buffer behind. (as recommended by NS databook) 933 */ 934 boundry = sc->next_packet - 1; 935 if (boundry < sc->rec_page_start) 936 boundry = sc->rec_page_stop - 1; 937 938 /* 939 * Set NIC to page 0 registers to update boundry register 940 */ 941 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA); 942 ed_nic_outb(sc, ED_P0_BNRY, boundry); 943 944 /* 945 * Set NIC to page 1 registers before looping to top (prepare 946 * to get 'CURR' current pointer) 947 */ 948 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA); 949 } 950} 951 952/* 953 * Ethernet interface interrupt processor 954 */ 955void 956edintr(void *arg) 957{ 958 struct ed_softc *sc = (struct ed_softc*) arg; 959 struct ifnet *ifp = (struct ifnet *)sc; 960 u_char isr; 961 int count; 962 963 if (sc->gone) 964 return; 965 /* 966 * Set NIC to page 0 registers 967 */ 968 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA); 969 970 /* 971 * loop until there are no more new interrupts. When the card 972 * goes away, the hardware will read back 0xff. Looking at 973 * the interrupts, it would appear that 0xff is impossible, 974 * or at least extremely unlikely. 975 */ 976 while ((isr = ed_nic_inb(sc, ED_P0_ISR)) != 0 && isr != 0xff) { 977 978 /* 979 * reset all the bits that we are 'acknowledging' by writing a 980 * '1' to each bit position that was set (writing a '1' 981 * *clears* the bit) 982 */ 983 ed_nic_outb(sc, ED_P0_ISR, isr); 984 985 /* 986 * XXX workaround for AX88190 987 * We limit this to 5000 iterations. At 1us per inb/outb, 988 * this translates to about 15ms, which should be plenty 989 * of time, and also gives protection in the card eject 990 * case. 991 */ 992 if (sc->chip_type == ED_CHIP_TYPE_AX88190) { 993 count = 5000; /* 15ms */ 994 while (count-- && (ed_nic_inb(sc, ED_P0_ISR) & isr)) { 995 ed_nic_outb(sc, ED_P0_ISR,0); 996 ed_nic_outb(sc, ED_P0_ISR,isr); 997 } 998 if (count == 0) 999 break; 1000 } 1001 1002 /* 1003 * Handle transmitter interrupts. Handle these first because 1004 * the receiver will reset the board under some conditions. 1005 */ 1006 if (isr & (ED_ISR_PTX | ED_ISR_TXE)) { 1007 u_char collisions = ed_nic_inb(sc, ED_P0_NCR) & 0x0f; 1008 1009 /* 1010 * Check for transmit error. If a TX completed with an 1011 * error, we end up throwing the packet away. Really 1012 * the only error that is possible is excessive 1013 * collisions, and in this case it is best to allow 1014 * the automatic mechanisms of TCP to backoff the 1015 * flow. Of course, with UDP we're screwed, but this 1016 * is expected when a network is heavily loaded. 1017 */ 1018 (void) ed_nic_inb(sc, ED_P0_TSR); 1019 if (isr & ED_ISR_TXE) { 1020 u_char tsr; 1021 1022 /* 1023 * Excessive collisions (16) 1024 */ 1025 tsr = ed_nic_inb(sc, ED_P0_TSR); 1026 if ((tsr & ED_TSR_ABT) 1027 && (collisions == 0)) { 1028 1029 /* 1030 * When collisions total 16, the 1031 * P0_NCR will indicate 0, and the 1032 * TSR_ABT is set. 1033 */ 1034 collisions = 16; 1035 sc->mibdata.dot3StatsExcessiveCollisions++; 1036 sc->mibdata.dot3StatsCollFrequencies[15]++; 1037 } 1038 if (tsr & ED_TSR_OWC) 1039 sc->mibdata.dot3StatsLateCollisions++; 1040 if (tsr & ED_TSR_CDH) 1041 sc->mibdata.dot3StatsSQETestErrors++; 1042 if (tsr & ED_TSR_CRS) 1043 sc->mibdata.dot3StatsCarrierSenseErrors++; 1044 if (tsr & ED_TSR_FU) 1045 sc->mibdata.dot3StatsInternalMacTransmitErrors++; 1046 1047 /* 1048 * update output errors counter 1049 */ 1050 ifp->if_oerrors++; 1051 } else { 1052 1053 /* 1054 * Update total number of successfully 1055 * transmitted packets. 1056 */ 1057 ifp->if_opackets++; 1058 } 1059 1060 /* 1061 * reset tx busy and output active flags 1062 */ 1063 sc->xmit_busy = 0; 1064 ifp->if_flags &= ~IFF_OACTIVE; 1065 1066 /* 1067 * clear watchdog timer 1068 */ 1069 ifp->if_timer = 0; 1070 1071 /* 1072 * Add in total number of collisions on last 1073 * transmission. 1074 */ 1075 ifp->if_collisions += collisions; 1076 switch(collisions) { 1077 case 0: 1078 case 16: 1079 break; 1080 case 1: 1081 sc->mibdata.dot3StatsSingleCollisionFrames++; 1082 sc->mibdata.dot3StatsCollFrequencies[0]++; 1083 break; 1084 default: 1085 sc->mibdata.dot3StatsMultipleCollisionFrames++; 1086 sc->mibdata. 1087 dot3StatsCollFrequencies[collisions-1] 1088 ++; 1089 break; 1090 } 1091 1092 /* 1093 * Decrement buffer in-use count if not zero (can only 1094 * be zero if a transmitter interrupt occured while 1095 * not actually transmitting). If data is ready to 1096 * transmit, start it transmitting, otherwise defer 1097 * until after handling receiver 1098 */ 1099 if (sc->txb_inuse && --sc->txb_inuse) 1100 ed_xmit(sc); 1101 } 1102 1103 /* 1104 * Handle receiver interrupts 1105 */ 1106 if (isr & (ED_ISR_PRX | ED_ISR_RXE | ED_ISR_OVW)) { 1107 1108 /* 1109 * Overwrite warning. In order to make sure that a 1110 * lockup of the local DMA hasn't occurred, we reset 1111 * and re-init the NIC. The NSC manual suggests only a 1112 * partial reset/re-init is necessary - but some chips 1113 * seem to want more. The DMA lockup has been seen 1114 * only with early rev chips - Methinks this bug was 1115 * fixed in later revs. -DG 1116 */ 1117 if (isr & ED_ISR_OVW) { 1118 ifp->if_ierrors++; 1119#ifdef DIAGNOSTIC 1120 log(LOG_WARNING, 1121 "%s: warning - receiver ring buffer overrun\n", 1122 ifp->if_xname); 1123#endif 1124 1125 /* 1126 * Stop/reset/re-init NIC 1127 */ 1128 ed_reset(ifp); 1129 } else { 1130 1131 /* 1132 * Receiver Error. One or more of: CRC error, 1133 * frame alignment error FIFO overrun, or 1134 * missed packet. 1135 */ 1136 if (isr & ED_ISR_RXE) { 1137 u_char rsr; 1138 rsr = ed_nic_inb(sc, ED_P0_RSR); 1139 if (rsr & ED_RSR_CRC) 1140 sc->mibdata.dot3StatsFCSErrors++; 1141 if (rsr & ED_RSR_FAE) 1142 sc->mibdata.dot3StatsAlignmentErrors++; 1143 if (rsr & ED_RSR_FO) 1144 sc->mibdata.dot3StatsInternalMacReceiveErrors++; 1145 ifp->if_ierrors++; 1146#ifdef ED_DEBUG 1147 if_printf(ifp, "receive error %x\n", 1148 ed_nic_inb(sc, ED_P0_RSR)); 1149#endif 1150 } 1151 1152 /* 1153 * Go get the packet(s) XXX - Doing this on an 1154 * error is dubious because there shouldn't be 1155 * any data to get (we've configured the 1156 * interface to not accept packets with 1157 * errors). 1158 */ 1159 1160 /* 1161 * Enable 16bit access to shared memory first 1162 * on WD/SMC boards. 1163 */ 1164 ed_enable_16bit_access(sc); 1165 ed_rint(sc); 1166 ed_disable_16bit_access(sc); 1167 } 1168 } 1169 1170 /* 1171 * If it looks like the transmitter can take more data, 1172 * attempt to start output on the interface. This is done 1173 * after handling the receiver to give the receiver priority. 1174 */ 1175 if ((ifp->if_flags & IFF_OACTIVE) == 0) 1176 ed_start(ifp); 1177 1178 /* 1179 * return NIC CR to standard state: page 0, remote DMA 1180 * complete, start (toggling the TXP bit off, even if was just 1181 * set in the transmit routine, is *okay* - it is 'edge' 1182 * triggered from low to high) 1183 */ 1184 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA); 1185 1186 /* 1187 * If the Network Talley Counters overflow, read them to reset 1188 * them. It appears that old 8390's won't clear the ISR flag 1189 * otherwise - resulting in an infinite loop. 1190 */ 1191 if (isr & ED_ISR_CNT) { 1192 (void) ed_nic_inb(sc, ED_P0_CNTR0); 1193 (void) ed_nic_inb(sc, ED_P0_CNTR1); 1194 (void) ed_nic_inb(sc, ED_P0_CNTR2); 1195 } 1196 } 1197} 1198 1199/* 1200 * Process an ioctl request. 1201 */ 1202static int 1203ed_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1204{ 1205 struct ed_softc *sc = ifp->if_softc; 1206#ifndef ED_NO_MIIBUS 1207 struct ifreq *ifr = (struct ifreq *)data; 1208 struct mii_data *mii; 1209#endif 1210 int s, error = 0; 1211 1212 if (sc == NULL || sc->gone) { 1213 ifp->if_flags &= ~IFF_RUNNING; 1214 return ENXIO; 1215 } 1216 s = splimp(); 1217 1218 switch (command) { 1219 case SIOCSIFFLAGS: 1220 1221 /* 1222 * If the interface is marked up and stopped, then start it. 1223 * If it is marked down and running, then stop it. 1224 */ 1225 if (ifp->if_flags & IFF_UP) { 1226 if ((ifp->if_flags & IFF_RUNNING) == 0) 1227 ed_init(sc); 1228 } else { 1229 if (ifp->if_flags & IFF_RUNNING) { 1230 ed_stop(sc); 1231 ifp->if_flags &= ~IFF_RUNNING; 1232 } 1233 } 1234 1235 /* 1236 * Promiscuous flag may have changed, so reprogram the RCR. 1237 */ 1238 ed_setrcr(sc); 1239 1240 /* 1241 * An unfortunate hack to provide the (required) software 1242 * control of the tranceiver for 3Com/HP boards. 1243 * The ALTPHYS flag disables the tranceiver if set. 1244 * 1245 * XXX - should use ifmedia. 1246 */ 1247#ifdef ED_3C503 1248 if (sc->vendor == ED_VENDOR_3COM) { 1249 if (ifp->if_flags & IFF_ALTPHYS) 1250 ed_asic_outb(sc, ED_3COM_CR, 0); 1251 else 1252 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_XSEL); 1253 } 1254#endif 1255#ifdef ED_HPP 1256 if (sc->vendor == ED_VENDOR_HP) 1257 ed_hpp_set_physical_link(sc); 1258#endif 1259 break; 1260 1261 case SIOCADDMULTI: 1262 case SIOCDELMULTI: 1263 /* 1264 * Multicast list has changed; set the hardware filter 1265 * accordingly. 1266 */ 1267 ed_setrcr(sc); 1268 error = 0; 1269 break; 1270 1271 case SIOCGIFMEDIA: 1272 case SIOCSIFMEDIA: 1273 if (sc->miibus == NULL) { 1274 error = EINVAL; 1275 break; 1276 } 1277#ifndef ED_NO_MIIBUS 1278 mii = device_get_softc(sc->miibus); 1279 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1280 break; 1281#endif 1282 1283 default: 1284 error = ether_ioctl(ifp, command, data); 1285 } 1286 (void) splx(s); 1287 return (error); 1288} 1289 1290/* 1291 * Given a source and destination address, copy 'amount' of a packet from 1292 * the ring buffer into a linear destination buffer. Takes into account 1293 * ring-wrap. 1294 */ 1295static __inline char * 1296ed_ring_copy(struct ed_softc *sc, char *src, char *dst, u_short amount) 1297{ 1298 u_short tmp_amount; 1299 1300 /* does copy wrap to lower addr in ring buffer? */ 1301 if (src + amount > sc->mem_end) { 1302 tmp_amount = sc->mem_end - src; 1303 1304 /* XXX 1305 * I'm not sure that this bcopy does only 16bit access 1306 */ 1307 /* copy amount up to end of NIC memory */ 1308 if (sc->mem_shared) 1309 bcopy(src, dst, tmp_amount); 1310 else 1311 ed_pio_readmem(sc, (uintptr_t)src, dst, tmp_amount); 1312 1313 amount -= tmp_amount; 1314 src = sc->mem_ring; 1315 dst += tmp_amount; 1316 } 1317 if (sc->mem_shared) 1318 bcopy(src, dst, amount); 1319 else 1320 ed_pio_readmem(sc, (uintptr_t)src, dst, amount); 1321 1322 return (src + amount); 1323} 1324 1325/* 1326 * Retreive packet from shared memory and send to the next level up via 1327 * ether_input(). 1328 */ 1329static void 1330ed_get_packet(struct ed_softc *sc, char *buf, u_short len) 1331{ 1332 struct ifnet *ifp = &sc->arpcom.ac_if; 1333 struct ether_header *eh; 1334 struct mbuf *m; 1335 1336 /* Allocate a header mbuf */ 1337 MGETHDR(m, M_DONTWAIT, MT_DATA); 1338 if (m == NULL) 1339 return; 1340 m->m_pkthdr.rcvif = ifp; 1341 m->m_pkthdr.len = m->m_len = len; 1342 1343 /* 1344 * We always put the received packet in a single buffer - 1345 * either with just an mbuf header or in a cluster attached 1346 * to the header. The +2 is to compensate for the alignment 1347 * fixup below. 1348 */ 1349 if ((len + 2) > MHLEN) { 1350 /* Attach an mbuf cluster */ 1351 MCLGET(m, M_DONTWAIT); 1352 1353 /* Insist on getting a cluster */ 1354 if ((m->m_flags & M_EXT) == 0) { 1355 m_freem(m); 1356 return; 1357 } 1358 } 1359 1360 /* 1361 * The +2 is to longword align the start of the real packet. 1362 * This is important for NFS. 1363 */ 1364 m->m_data += 2; 1365 eh = mtod(m, struct ether_header *); 1366 1367 /* 1368 * Get packet, including link layer address, from interface. 1369 */ 1370 ed_ring_copy(sc, buf, (char *)eh, len); 1371 1372 m->m_pkthdr.len = m->m_len = len; 1373 1374 (*ifp->if_input)(ifp, m); 1375} 1376 1377/* 1378 * Supporting routines 1379 */ 1380 1381/* 1382 * Given a NIC memory source address and a host memory destination 1383 * address, copy 'amount' from NIC to host using Programmed I/O. 1384 * The 'amount' is rounded up to a word - okay as long as mbufs 1385 * are word sized. 1386 * This routine is currently Novell-specific. 1387 */ 1388void 1389ed_pio_readmem(struct ed_softc *sc, long src, uint8_t *dst, uint16_t amount) 1390{ 1391#ifdef ED_HPP 1392 /* HP PC Lan+ cards need special handling */ 1393 if (sc->vendor == ED_VENDOR_HP && sc->type == ED_TYPE_HP_PCLANPLUS) { 1394 ed_hpp_readmem(sc, src, dst, amount); 1395 return; 1396 } 1397#endif 1398 1399 /* Regular Novell cards */ 1400 /* select page 0 registers */ 1401 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STA); 1402 1403 /* round up to a word */ 1404 if (amount & 1) 1405 ++amount; 1406 1407 /* set up DMA byte count */ 1408 ed_nic_outb(sc, ED_P0_RBCR0, amount); 1409 ed_nic_outb(sc, ED_P0_RBCR1, amount >> 8); 1410 1411 /* set up source address in NIC mem */ 1412 ed_nic_outb(sc, ED_P0_RSAR0, src); 1413 ed_nic_outb(sc, ED_P0_RSAR1, src >> 8); 1414 1415 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD0 | ED_CR_STA); 1416 1417 if (sc->isa16bit) 1418 ed_asic_insw(sc, ED_NOVELL_DATA, dst, amount / 2); 1419 else 1420 ed_asic_insb(sc, ED_NOVELL_DATA, dst, amount); 1421} 1422 1423/* 1424 * Stripped down routine for writing a linear buffer to NIC memory. 1425 * Only used in the probe routine to test the memory. 'len' must 1426 * be even. 1427 */ 1428void 1429ed_pio_writemem(struct ed_softc *sc, uint8_t *src, uint16_t dst, uint16_t len) 1430{ 1431 int maxwait = 200; /* about 240us */ 1432 1433 /* select page 0 registers */ 1434 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STA); 1435 1436 /* reset remote DMA complete flag */ 1437 ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC); 1438 1439 /* set up DMA byte count */ 1440 ed_nic_outb(sc, ED_P0_RBCR0, len); 1441 ed_nic_outb(sc, ED_P0_RBCR1, len >> 8); 1442 1443 /* set up destination address in NIC mem */ 1444 ed_nic_outb(sc, ED_P0_RSAR0, dst); 1445 ed_nic_outb(sc, ED_P0_RSAR1, dst >> 8); 1446 1447 /* set remote DMA write */ 1448 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD1 | ED_CR_STA); 1449 1450 if (sc->isa16bit) 1451 ed_asic_outsw(sc, ED_NOVELL_DATA, src, len / 2); 1452 else 1453 ed_asic_outsb(sc, ED_NOVELL_DATA, src, len); 1454 1455 /* 1456 * Wait for remote DMA complete. This is necessary because on the 1457 * transmit side, data is handled internally by the NIC in bursts and 1458 * we can't start another remote DMA until this one completes. Not 1459 * waiting causes really bad things to happen - like the NIC 1460 * irrecoverably jamming the ISA bus. 1461 */ 1462 while (((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && 1463 --maxwait) 1464 continue; 1465} 1466 1467/* 1468 * Write an mbuf chain to the destination NIC memory address using 1469 * programmed I/O. 1470 */ 1471static u_short 1472ed_pio_write_mbufs(struct ed_softc *sc, struct mbuf *m, long dst) 1473{ 1474 struct ifnet *ifp = (struct ifnet *)sc; 1475 unsigned short total_len, dma_len; 1476 struct mbuf *mp; 1477 int maxwait = 200; /* about 240us */ 1478 1479#ifdef ED_HPP 1480 /* HP PC Lan+ cards need special handling */ 1481 if (sc->vendor == ED_VENDOR_HP && sc->type == ED_TYPE_HP_PCLANPLUS) 1482 return ed_hpp_write_mbufs(sc, m, dst); 1483#endif 1484 1485 /* Regular Novell cards */ 1486 /* First, count up the total number of bytes to copy */ 1487 for (total_len = 0, mp = m; mp; mp = mp->m_next) 1488 total_len += mp->m_len; 1489 1490 dma_len = total_len; 1491 if (sc->isa16bit && (dma_len & 1)) 1492 dma_len++; 1493 1494 /* select page 0 registers */ 1495 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STA); 1496 1497 /* reset remote DMA complete flag */ 1498 ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC); 1499 1500 /* set up DMA byte count */ 1501 ed_nic_outb(sc, ED_P0_RBCR0, dma_len); 1502 ed_nic_outb(sc, ED_P0_RBCR1, dma_len >> 8); 1503 1504 /* set up destination address in NIC mem */ 1505 ed_nic_outb(sc, ED_P0_RSAR0, dst); 1506 ed_nic_outb(sc, ED_P0_RSAR1, dst >> 8); 1507 1508 /* set remote DMA write */ 1509 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD1 | ED_CR_STA); 1510 1511 /* 1512 * Transfer the mbuf chain to the NIC memory. 1513 * 16-bit cards require that data be transferred as words, and only words. 1514 * So that case requires some extra code to patch over odd-length mbufs. 1515 */ 1516 1517 if (!sc->isa16bit) { 1518 /* NE1000s are easy */ 1519 while (m) { 1520 if (m->m_len) 1521 ed_asic_outsb(sc, ED_NOVELL_DATA, 1522 m->m_data, m->m_len); 1523 m = m->m_next; 1524 } 1525 } else { 1526 /* NE2000s are a pain */ 1527 unsigned char *data; 1528 int len, wantbyte; 1529 unsigned char savebyte[2]; 1530 1531 wantbyte = 0; 1532 1533 while (m) { 1534 len = m->m_len; 1535 if (len) { 1536 data = mtod(m, caddr_t); 1537 /* finish the last word */ 1538 if (wantbyte) { 1539 savebyte[1] = *data; 1540 ed_asic_outw(sc, ED_NOVELL_DATA, 1541 *(u_short *)savebyte); 1542 data++; 1543 len--; 1544 wantbyte = 0; 1545 } 1546 /* output contiguous words */ 1547 if (len > 1) { 1548 ed_asic_outsw(sc, ED_NOVELL_DATA, 1549 data, len >> 1); 1550 data += len & ~1; 1551 len &= 1; 1552 } 1553 /* save last byte, if necessary */ 1554 if (len == 1) { 1555 savebyte[0] = *data; 1556 wantbyte = 1; 1557 } 1558 } 1559 m = m->m_next; 1560 } 1561 /* spit last byte */ 1562 if (wantbyte) 1563 ed_asic_outw(sc, ED_NOVELL_DATA, *(u_short *)savebyte); 1564 } 1565 1566 /* 1567 * Wait for remote DMA complete. This is necessary because on the 1568 * transmit side, data is handled internally by the NIC in bursts and 1569 * we can't start another remote DMA until this one completes. Not 1570 * waiting causes really bad things to happen - like the NIC 1571 * irrecoverably jamming the ISA bus. 1572 */ 1573 while (((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && 1574 --maxwait) 1575 continue; 1576 1577 if (!maxwait) { 1578 log(LOG_WARNING, "%s: remote transmit DMA failed to complete\n", 1579 ifp->if_xname); 1580 ed_reset(ifp); 1581 return(0); 1582 } 1583 return (total_len); 1584} 1585 1586#ifndef ED_NO_MIIBUS 1587/* 1588 * MII bus support routines. 1589 */ 1590int 1591ed_miibus_readreg(device_t dev, int phy, int reg) 1592{ 1593 struct ed_softc *sc; 1594 int failed, s, val; 1595 1596 s = splimp(); 1597 sc = device_get_softc(dev); 1598 if (sc->gone) { 1599 splx(s); 1600 return (0); 1601 } 1602 1603 (*sc->mii_writebits)(sc, 0xffffffff, 32); 1604 (*sc->mii_writebits)(sc, ED_MII_STARTDELIM, ED_MII_STARTDELIM_BITS); 1605 (*sc->mii_writebits)(sc, ED_MII_READOP, ED_MII_OP_BITS); 1606 (*sc->mii_writebits)(sc, phy, ED_MII_PHY_BITS); 1607 (*sc->mii_writebits)(sc, reg, ED_MII_REG_BITS); 1608 1609 failed = (*sc->mii_readbits)(sc, ED_MII_ACK_BITS); 1610 val = (*sc->mii_readbits)(sc, ED_MII_DATA_BITS); 1611 (*sc->mii_writebits)(sc, ED_MII_IDLE, ED_MII_IDLE_BITS); 1612 1613 splx(s); 1614 return (failed ? 0 : val); 1615} 1616 1617void 1618ed_miibus_writereg(device_t dev, int phy, int reg, int data) 1619{ 1620 struct ed_softc *sc; 1621 int s; 1622 1623 s = splimp(); 1624 sc = device_get_softc(dev); 1625 if (sc->gone) { 1626 splx(s); 1627 return; 1628 } 1629 1630 (*sc->mii_writebits)(sc, 0xffffffff, 32); 1631 (*sc->mii_writebits)(sc, ED_MII_STARTDELIM, ED_MII_STARTDELIM_BITS); 1632 (*sc->mii_writebits)(sc, ED_MII_WRITEOP, ED_MII_OP_BITS); 1633 (*sc->mii_writebits)(sc, phy, ED_MII_PHY_BITS); 1634 (*sc->mii_writebits)(sc, reg, ED_MII_REG_BITS); 1635 (*sc->mii_writebits)(sc, ED_MII_TURNAROUND, ED_MII_TURNAROUND_BITS); 1636 (*sc->mii_writebits)(sc, data, ED_MII_DATA_BITS); 1637 (*sc->mii_writebits)(sc, ED_MII_IDLE, ED_MII_IDLE_BITS); 1638 1639 splx(s); 1640} 1641 1642int 1643ed_ifmedia_upd(struct ifnet *ifp) 1644{ 1645 struct ed_softc *sc; 1646 struct mii_data *mii; 1647 1648 sc = ifp->if_softc; 1649 if (sc->gone || sc->miibus == NULL) 1650 return (ENXIO); 1651 1652 mii = device_get_softc(sc->miibus); 1653 return mii_mediachg(mii); 1654} 1655 1656void 1657ed_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1658{ 1659 struct ed_softc *sc; 1660 struct mii_data *mii; 1661 1662 sc = ifp->if_softc; 1663 if (sc->gone || sc->miibus == NULL) 1664 return; 1665 1666 mii = device_get_softc(sc->miibus); 1667 mii_pollstat(mii); 1668 ifmr->ifm_active = mii->mii_media_active; 1669 ifmr->ifm_status = mii->mii_media_status; 1670} 1671 1672void 1673ed_child_detached(device_t dev, device_t child) 1674{ 1675 struct ed_softc *sc; 1676 1677 sc = device_get_softc(dev); 1678 if (child == sc->miibus) 1679 sc->miibus = NULL; 1680} 1681#endif 1682 1683static void 1684ed_setrcr(struct ed_softc *sc) 1685{ 1686 struct ifnet *ifp = (struct ifnet *)sc; 1687 int i; 1688 u_char reg1; 1689 1690 /* Bit 6 in AX88190 RCR register must be set. */ 1691 if (sc->chip_type == ED_CHIP_TYPE_AX88190) 1692 reg1 = ED_RCR_INTT; 1693 else 1694 reg1 = 0x00; 1695 1696 /* set page 1 registers */ 1697 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP); 1698 1699 if (ifp->if_flags & IFF_PROMISC) { 1700 1701 /* 1702 * Reconfigure the multicast filter. 1703 */ 1704 for (i = 0; i < 8; i++) 1705 ed_nic_outb(sc, ED_P1_MAR(i), 0xff); 1706 1707 /* 1708 * And turn on promiscuous mode. Also enable reception of 1709 * runts and packets with CRC & alignment errors. 1710 */ 1711 /* Set page 0 registers */ 1712 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP); 1713 1714 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_PRO | ED_RCR_AM | 1715 ED_RCR_AB | ED_RCR_AR | ED_RCR_SEP | reg1); 1716 } else { 1717 /* set up multicast addresses and filter modes */ 1718 if (ifp->if_flags & IFF_MULTICAST) { 1719 uint32_t mcaf[2]; 1720 1721 if (ifp->if_flags & IFF_ALLMULTI) { 1722 mcaf[0] = 0xffffffff; 1723 mcaf[1] = 0xffffffff; 1724 } else 1725 ed_ds_getmcaf(sc, mcaf); 1726 1727 /* 1728 * Set multicast filter on chip. 1729 */ 1730 for (i = 0; i < 8; i++) 1731 ed_nic_outb(sc, ED_P1_MAR(i), ((u_char *) mcaf)[i]); 1732 1733 /* Set page 0 registers */ 1734 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP); 1735 1736 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_AM | ED_RCR_AB | reg1); 1737 } else { 1738 1739 /* 1740 * Initialize multicast address hashing registers to 1741 * not accept multicasts. 1742 */ 1743 for (i = 0; i < 8; ++i) 1744 ed_nic_outb(sc, ED_P1_MAR(i), 0x00); 1745 1746 /* Set page 0 registers */ 1747 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP); 1748 1749 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_AB | reg1); 1750 } 1751 } 1752 1753 /* 1754 * Start interface. 1755 */ 1756 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA); 1757} 1758 1759/* 1760 * Compute the multicast address filter from the 1761 * list of multicast addresses we need to listen to. 1762 */ 1763static void 1764ed_ds_getmcaf(struct ed_softc *sc, uint32_t *mcaf) 1765{ 1766 uint32_t index; 1767 u_char *af = (u_char *) mcaf; 1768 struct ifmultiaddr *ifma; 1769 1770 mcaf[0] = 0; 1771 mcaf[1] = 0; 1772 1773 TAILQ_FOREACH(ifma, &sc->arpcom.ac_if.if_multiaddrs, ifma_link) { 1774 if (ifma->ifma_addr->sa_family != AF_LINK) 1775 continue; 1776 index = ether_crc32_be(LLADDR((struct sockaddr_dl *) 1777 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 1778 af[index >> 3] |= 1 << (index & 7); 1779 } 1780} 1781 1782int 1783ed_isa_mem_ok(device_t dev, u_long pmem, u_int memsize) 1784{ 1785 if (pmem < 0xa0000 || pmem + memsize > 0x1000000) { 1786 device_printf(dev, "Invalid ISA memory address range " 1787 "configured: 0x%lx - 0x%lx\n", pmem, pmem + memsize); 1788 return (ENXIO); 1789 } 1790 return (0); 1791} 1792 1793int 1794ed_clear_memory(device_t dev) 1795{ 1796 struct ed_softc *sc = device_get_softc(dev); 1797 int i; 1798 1799 /* 1800 * Now zero memory and verify that it is clear 1801 * XXX restricted to 16-bit writes? Do we need to 1802 * XXX enable 16-bit access? 1803 */ 1804 bzero(sc->mem_start, sc->mem_size); 1805 1806 for (i = 0; i < sc->mem_size; ++i) { 1807 if (sc->mem_start[i]) { 1808 device_printf(dev, "failed to clear shared memory at " 1809 "0x%jx - check configuration\n", 1810 (uintmax_t)rman_get_start(sc->mem_res) + i); 1811 return (ENXIO); 1812 } 1813 } 1814 return (0); 1815} 1816