if_ed.c revision 141672
1/*- 2 * Copyright (c) 1995, David Greenman 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28#include <sys/cdefs.h> 29__FBSDID("$FreeBSD: head/sys/dev/ed/if_ed.c 141672 2005-02-10 23:31:27Z imp $"); 30 31/* 32 * Device driver for National Semiconductor DS8390/WD83C690 based ethernet 33 * adapters. By David Greenman, 29-April-1993 34 * 35 * Currently supports the Western Digital/SMC 8003 and 8013 series, 36 * the SMC Elite Ultra (8216), the 3Com 3c503, the NE1000 and NE2000, 37 * and a variety of similar clones. 38 * 39 */ 40 41#include "opt_ed.h" 42 43#include <sys/param.h> 44#include <sys/systm.h> 45#include <sys/sockio.h> 46#include <sys/mbuf.h> 47#include <sys/kernel.h> 48#include <sys/socket.h> 49#include <sys/syslog.h> 50 51#include <sys/bus.h> 52 53#include <machine/bus.h> 54#include <sys/rman.h> 55#include <machine/resource.h> 56 57#include <net/ethernet.h> 58#include <net/if.h> 59#include <net/if_arp.h> 60#include <net/if_dl.h> 61#include <net/if_mib.h> 62#include <net/if_media.h> 63 64#ifndef ED_NO_MIIBUS 65#include <dev/mii/mii.h> 66#include <dev/mii/miivar.h> 67#endif 68 69#include <net/bpf.h> 70 71#include <dev/ed/if_edreg.h> 72#include <dev/ed/if_edvar.h> 73 74devclass_t ed_devclass; 75 76static void ed_init(void *); 77static int ed_ioctl(struct ifnet *, u_long, caddr_t); 78static void ed_start(struct ifnet *); 79static void ed_reset(struct ifnet *); 80static void ed_watchdog(struct ifnet *); 81#ifndef ED_NO_MIIBUS 82static void ed_tick(void *); 83#endif 84 85static void ed_ds_getmcaf(struct ed_softc *, uint32_t *); 86 87static void ed_get_packet(struct ed_softc *, char *, u_short); 88 89static __inline void ed_rint(struct ed_softc *); 90static __inline void ed_xmit(struct ed_softc *); 91static __inline char *ed_ring_copy(struct ed_softc *, char *, char *, u_short); 92static u_short ed_pio_write_mbufs(struct ed_softc *, struct mbuf *, long); 93 94static void ed_setrcr(struct ed_softc *); 95 96/* 97 * Generic probe routine for testing for the existance of a DS8390. 98 * Must be called after the NIC has just been reset. This routine 99 * works by looking at certain register values that are guaranteed 100 * to be initialized a certain way after power-up or reset. Seems 101 * not to currently work on the 83C690. 102 * 103 * Specifically: 104 * 105 * Register reset bits set bits 106 * Command Register (CR) TXP, STA RD2, STP 107 * Interrupt Status (ISR) RST 108 * Interrupt Mask (IMR) All bits 109 * Data Control (DCR) LAS 110 * Transmit Config. (TCR) LB1, LB0 111 * 112 * We only look at the CR and ISR registers, however, because looking at 113 * the others would require changing register pages (which would be 114 * intrusive if this isn't an 8390). 115 * 116 * Return 1 if 8390 was found, 0 if not. 117 */ 118 119int 120ed_probe_generic8390(struct ed_softc *sc) 121{ 122 if ((ed_nic_inb(sc, ED_P0_CR) & 123 (ED_CR_RD2 | ED_CR_TXP | ED_CR_STA | ED_CR_STP)) != 124 (ED_CR_RD2 | ED_CR_STP)) 125 return (0); 126 if ((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RST) != ED_ISR_RST) 127 return (0); 128 129 return (1); 130} 131 132/* 133 * Allocate a port resource with the given resource id. 134 */ 135int 136ed_alloc_port(device_t dev, int rid, int size) 137{ 138 struct ed_softc *sc = device_get_softc(dev); 139 struct resource *res; 140 141 res = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 142 0ul, ~0ul, size, RF_ACTIVE); 143 if (res) { 144 sc->port_rid = rid; 145 sc->port_res = res; 146 sc->port_used = size; 147 return (0); 148 } else { 149 return (ENOENT); 150 } 151} 152 153/* 154 * Allocate a memory resource with the given resource id. 155 */ 156int 157ed_alloc_memory(device_t dev, int rid, int size) 158{ 159 struct ed_softc *sc = device_get_softc(dev); 160 struct resource *res; 161 162 res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 163 0ul, ~0ul, size, RF_ACTIVE); 164 if (res) { 165 sc->mem_rid = rid; 166 sc->mem_res = res; 167 sc->mem_used = size; 168 return (0); 169 } else { 170 return (ENOENT); 171 } 172} 173 174/* 175 * Allocate an irq resource with the given resource id. 176 */ 177int 178ed_alloc_irq(device_t dev, int rid, int flags) 179{ 180 struct ed_softc *sc = device_get_softc(dev); 181 struct resource *res; 182 183 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE | flags); 184 if (res) { 185 sc->irq_rid = rid; 186 sc->irq_res = res; 187 return (0); 188 } else { 189 return (ENOENT); 190 } 191} 192 193/* 194 * Release all resources 195 */ 196void 197ed_release_resources(device_t dev) 198{ 199 struct ed_softc *sc = device_get_softc(dev); 200 201 if (sc->port_res) { 202 bus_deactivate_resource(dev, SYS_RES_IOPORT, 203 sc->port_rid, sc->port_res); 204 bus_release_resource(dev, SYS_RES_IOPORT, 205 sc->port_rid, sc->port_res); 206 sc->port_res = 0; 207 } 208 if (sc->mem_res) { 209 bus_deactivate_resource(dev, SYS_RES_MEMORY, 210 sc->mem_rid, sc->mem_res); 211 bus_release_resource(dev, SYS_RES_MEMORY, 212 sc->mem_rid, sc->mem_res); 213 sc->mem_res = 0; 214 } 215 if (sc->irq_res) { 216 bus_deactivate_resource(dev, SYS_RES_IRQ, 217 sc->irq_rid, sc->irq_res); 218 bus_release_resource(dev, SYS_RES_IRQ, 219 sc->irq_rid, sc->irq_res); 220 sc->irq_res = 0; 221 } 222} 223 224/* 225 * Install interface into kernel networking data structures 226 */ 227int 228ed_attach(device_t dev) 229{ 230 struct ed_softc *sc = device_get_softc(dev); 231 struct ifnet *ifp = &sc->arpcom.ac_if; 232 233 callout_handle_init(&sc->tick_ch); 234 /* 235 * Set interface to stopped condition (reset) 236 */ 237 ed_stop(sc); 238 239 /* 240 * Initialize ifnet structure 241 */ 242 ifp->if_softc = sc; 243 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 244 ifp->if_start = ed_start; 245 ifp->if_ioctl = ed_ioctl; 246 ifp->if_watchdog = ed_watchdog; 247 ifp->if_init = ed_init; 248 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 249 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN; 250 IFQ_SET_READY(&ifp->if_snd); 251 ifp->if_linkmib = &sc->mibdata; 252 ifp->if_linkmiblen = sizeof sc->mibdata; 253 /* 254 * XXX - should do a better job. 255 */ 256 if (sc->chip_type == ED_CHIP_TYPE_WD790) 257 sc->mibdata.dot3StatsEtherChipSet = 258 DOT3CHIPSET(dot3VendorWesternDigital, 259 dot3ChipSetWesternDigital83C790); 260 else 261 sc->mibdata.dot3StatsEtherChipSet = 262 DOT3CHIPSET(dot3VendorNational, 263 dot3ChipSetNational8390); 264 sc->mibdata.dot3Compliance = DOT3COMPLIANCE_COLLS; 265 266 /* 267 * Set default state for ALTPHYS flag (used to disable the 268 * tranceiver for AUI operation), based on compile-time 269 * config option. 270 */ 271 if (device_get_flags(dev) & ED_FLAGS_DISABLE_TRANCEIVER) 272 ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX | 273 IFF_MULTICAST | IFF_ALTPHYS | IFF_NEEDSGIANT); 274 else 275 ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX | 276 IFF_MULTICAST | IFF_NEEDSGIANT); 277 278 /* 279 * Attach the interface 280 */ 281 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 282 /* device attach does transition from UNCONFIGURED to IDLE state */ 283 284 if (bootverbose || 1) { 285 if (sc->type_str && (*sc->type_str != 0)) 286 device_printf(dev, "type %s ", sc->type_str); 287 else 288 device_printf(dev, "type unknown (0x%x) ", sc->type); 289 290#ifdef ED_HPP 291 if (sc->vendor == ED_VENDOR_HP) 292 printf("(%s %s IO)", 293 (sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS) ? 294 "16-bit" : "32-bit", 295 sc->hpp_mem_start ? "memory mapped" : "regular"); 296 else 297#endif 298 printf("%s ", sc->isa16bit ? "(16 bit)" : "(8 bit)"); 299 300 printf("%s\n", (((sc->vendor == ED_VENDOR_3COM) || 301 (sc->vendor == ED_VENDOR_HP)) && 302 (ifp->if_flags & IFF_ALTPHYS)) ? 303 " tranceiver disabled" : ""); 304 } 305 return (0); 306} 307 308/* 309 * Detach the driver from the hardware and other systems in the kernel. 310 */ 311int 312ed_detach(device_t dev) 313{ 314 struct ed_softc *sc = device_get_softc(dev); 315 struct ifnet *ifp = &sc->arpcom.ac_if; 316 317 if (sc->gone) 318 return (0); 319 ed_stop(sc); 320 ifp->if_flags &= ~IFF_RUNNING; 321 ether_ifdetach(ifp); 322 sc->gone = 1; 323 bus_teardown_intr(dev, sc->irq_res, sc->irq_handle); 324 ed_release_resources(dev); 325 return (0); 326} 327 328/* 329 * Reset interface. 330 */ 331static void 332ed_reset(struct ifnet *ifp) 333{ 334 struct ed_softc *sc = ifp->if_softc; 335 int s; 336 337 if (sc->gone) 338 return; 339 s = splimp(); 340 341 /* 342 * Stop interface and re-initialize. 343 */ 344 ed_stop(sc); 345 ed_init(sc); 346 347 (void) splx(s); 348} 349 350/* 351 * Take interface offline. 352 */ 353void 354ed_stop(struct ed_softc *sc) 355{ 356 int n = 5000; 357 358#ifndef ED_NO_MIIBUS 359 untimeout(ed_tick, sc, sc->tick_ch); 360 callout_handle_init(&sc->tick_ch); 361#endif 362 if (sc->gone) 363 return; 364 /* 365 * Stop everything on the interface, and select page 0 registers. 366 */ 367 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP); 368 369 /* 370 * Wait for interface to enter stopped state, but limit # of checks to 371 * 'n' (about 5ms). It shouldn't even take 5us on modern DS8390's, but 372 * just in case it's an old one. 373 */ 374 if (sc->chip_type != ED_CHIP_TYPE_AX88190) 375 while (((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RST) == 0) && --n) 376 continue; 377} 378 379/* 380 * Device timeout/watchdog routine. Entered if the device neglects to 381 * generate an interrupt after a transmit has been started on it. 382 */ 383static void 384ed_watchdog(struct ifnet *ifp) 385{ 386 struct ed_softc *sc = ifp->if_softc; 387 388 if (sc->gone) 389 return; 390 log(LOG_ERR, "%s: device timeout\n", ifp->if_xname); 391 ifp->if_oerrors++; 392 393 ed_reset(ifp); 394} 395 396#ifndef ED_NO_MIIBUS 397static void 398ed_tick(void *arg) 399{ 400 struct ed_softc *sc = arg; 401 struct mii_data *mii; 402 int s; 403 404 if (sc->gone) { 405 callout_handle_init(&sc->tick_ch); 406 return; 407 } 408 s = splimp(); 409 if (sc->miibus != NULL) { 410 mii = device_get_softc(sc->miibus); 411 mii_tick(mii); 412 } 413 sc->tick_ch = timeout(ed_tick, sc, hz); 414 splx(s); 415} 416#endif 417 418/* 419 * Initialize device. 420 */ 421static void 422ed_init(void *xsc) 423{ 424 struct ed_softc *sc = xsc; 425 struct ifnet *ifp = &sc->arpcom.ac_if; 426 int i, s; 427 428 if (sc->gone) 429 return; 430 431 /* 432 * Initialize the NIC in the exact order outlined in the NS manual. 433 * This init procedure is "mandatory"...don't change what or when 434 * things happen. 435 */ 436 s = splimp(); 437 438 /* reset transmitter flags */ 439 sc->xmit_busy = 0; 440 ifp->if_timer = 0; 441 442 sc->txb_inuse = 0; 443 sc->txb_new = 0; 444 sc->txb_next_tx = 0; 445 446 /* This variable is used below - don't move this assignment */ 447 sc->next_packet = sc->rec_page_start + 1; 448 449 /* 450 * Set interface for page 0, Remote DMA complete, Stopped 451 */ 452 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP); 453 454 if (sc->isa16bit) { 455 456 /* 457 * Set FIFO threshold to 8, No auto-init Remote DMA, byte 458 * order=80x86, word-wide DMA xfers, 459 */ 460 ed_nic_outb(sc, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_WTS | ED_DCR_LS); 461 } else { 462 463 /* 464 * Same as above, but byte-wide DMA xfers 465 */ 466 ed_nic_outb(sc, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS); 467 } 468 469 /* 470 * Clear Remote Byte Count Registers 471 */ 472 ed_nic_outb(sc, ED_P0_RBCR0, 0); 473 ed_nic_outb(sc, ED_P0_RBCR1, 0); 474 475 /* 476 * For the moment, don't store incoming packets in memory. 477 */ 478 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_MON); 479 480 /* 481 * Place NIC in internal loopback mode 482 */ 483 ed_nic_outb(sc, ED_P0_TCR, ED_TCR_LB0); 484 485 /* 486 * Initialize transmit/receive (ring-buffer) Page Start 487 */ 488 ed_nic_outb(sc, ED_P0_TPSR, sc->tx_page_start); 489 ed_nic_outb(sc, ED_P0_PSTART, sc->rec_page_start); 490 /* Set lower bits of byte addressable framing to 0 */ 491 if (sc->chip_type == ED_CHIP_TYPE_WD790) 492 ed_nic_outb(sc, 0x09, 0); 493 494 /* 495 * Initialize Receiver (ring-buffer) Page Stop and Boundry 496 */ 497 ed_nic_outb(sc, ED_P0_PSTOP, sc->rec_page_stop); 498 ed_nic_outb(sc, ED_P0_BNRY, sc->rec_page_start); 499 500 /* 501 * Clear all interrupts. A '1' in each bit position clears the 502 * corresponding flag. 503 */ 504 ed_nic_outb(sc, ED_P0_ISR, 0xff); 505 506 /* 507 * Enable the following interrupts: receive/transmit complete, 508 * receive/transmit error, and Receiver OverWrite. 509 * 510 * Counter overflow and Remote DMA complete are *not* enabled. 511 */ 512 ed_nic_outb(sc, ED_P0_IMR, 513 ED_IMR_PRXE | ED_IMR_PTXE | ED_IMR_RXEE | ED_IMR_TXEE | ED_IMR_OVWE); 514 515 /* 516 * Program Command Register for page 1 517 */ 518 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP); 519 520 /* 521 * Copy out our station address 522 */ 523 for (i = 0; i < ETHER_ADDR_LEN; ++i) 524 ed_nic_outb(sc, ED_P1_PAR(i), sc->arpcom.ac_enaddr[i]); 525 526 /* 527 * Set Current Page pointer to next_packet (initialized above) 528 */ 529 ed_nic_outb(sc, ED_P1_CURR, sc->next_packet); 530 531 /* 532 * Program Receiver Configuration Register and multicast filter. CR is 533 * set to page 0 on return. 534 */ 535 ed_setrcr(sc); 536 537 /* 538 * Take interface out of loopback 539 */ 540 ed_nic_outb(sc, ED_P0_TCR, 0); 541 542 /* 543 * If this is a 3Com board, the tranceiver must be software enabled 544 * (there is no settable hardware default). 545 */ 546 if (sc->vendor == ED_VENDOR_3COM) { 547 if (ifp->if_flags & IFF_ALTPHYS) { 548 ed_asic_outb(sc, ED_3COM_CR, 0); 549 } else { 550 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_XSEL); 551 } 552 } 553 554#ifndef ED_NO_MIIBUS 555 if (sc->miibus != NULL) { 556 struct mii_data *mii; 557 mii = device_get_softc(sc->miibus); 558 mii_mediachg(mii); 559 } 560#endif 561 /* 562 * Set 'running' flag, and clear output active flag. 563 */ 564 ifp->if_flags |= IFF_RUNNING; 565 ifp->if_flags &= ~IFF_OACTIVE; 566 567 /* 568 * ...and attempt to start output 569 */ 570 ed_start(ifp); 571 572#ifndef ED_NO_MIIBUS 573 untimeout(ed_tick, sc, sc->tick_ch); 574 sc->tick_ch = timeout(ed_tick, sc, hz); 575#endif 576 (void) splx(s); 577} 578 579/* 580 * This routine actually starts the transmission on the interface 581 */ 582static __inline void 583ed_xmit(struct ed_softc *sc) 584{ 585 struct ifnet *ifp = (struct ifnet *)sc; 586 unsigned short len; 587 588 if (sc->gone) 589 return; 590 len = sc->txb_len[sc->txb_next_tx]; 591 592 /* 593 * Set NIC for page 0 register access 594 */ 595 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA); 596 597 /* 598 * Set TX buffer start page 599 */ 600 ed_nic_outb(sc, ED_P0_TPSR, sc->tx_page_start + 601 sc->txb_next_tx * ED_TXBUF_SIZE); 602 603 /* 604 * Set TX length 605 */ 606 ed_nic_outb(sc, ED_P0_TBCR0, len); 607 ed_nic_outb(sc, ED_P0_TBCR1, len >> 8); 608 609 /* 610 * Set page 0, Remote DMA complete, Transmit Packet, and *Start* 611 */ 612 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_TXP | ED_CR_STA); 613 sc->xmit_busy = 1; 614 615 /* 616 * Point to next transmit buffer slot and wrap if necessary. 617 */ 618 sc->txb_next_tx++; 619 if (sc->txb_next_tx == sc->txb_cnt) 620 sc->txb_next_tx = 0; 621 622 /* 623 * Set a timer just in case we never hear from the board again 624 */ 625 ifp->if_timer = 2; 626} 627 628/* 629 * Start output on interface. 630 * We make two assumptions here: 631 * 1) that the current priority is set to splimp _before_ this code 632 * is called *and* is returned to the appropriate priority after 633 * return 634 * 2) that the IFF_OACTIVE flag is checked before this code is called 635 * (i.e. that the output part of the interface is idle) 636 */ 637static void 638ed_start(struct ifnet *ifp) 639{ 640 struct ed_softc *sc = ifp->if_softc; 641 struct mbuf *m0, *m; 642 caddr_t buffer; 643 int len; 644 645 if (sc->gone) { 646 printf("ed_start(%p) GONE\n",ifp); 647 return; 648 } 649outloop: 650 651 /* 652 * First, see if there are buffered packets and an idle transmitter - 653 * should never happen at this point. 654 */ 655 if (sc->txb_inuse && (sc->xmit_busy == 0)) { 656 printf("ed: packets buffered, but transmitter idle\n"); 657 ed_xmit(sc); 658 } 659 660 /* 661 * See if there is room to put another packet in the buffer. 662 */ 663 if (sc->txb_inuse == sc->txb_cnt) { 664 665 /* 666 * No room. Indicate this to the outside world and exit. 667 */ 668 ifp->if_flags |= IFF_OACTIVE; 669 return; 670 } 671 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 672 if (m == 0) { 673 674 /* 675 * We are using the !OACTIVE flag to indicate to the outside 676 * world that we can accept an additional packet rather than 677 * that the transmitter is _actually_ active. Indeed, the 678 * transmitter may be active, but if we haven't filled all the 679 * buffers with data then we still want to accept more. 680 */ 681 ifp->if_flags &= ~IFF_OACTIVE; 682 return; 683 } 684 685 /* 686 * Copy the mbuf chain into the transmit buffer 687 */ 688 689 m0 = m; 690 691 /* txb_new points to next open buffer slot */ 692 buffer = sc->mem_start + (sc->txb_new * ED_TXBUF_SIZE * ED_PAGE_SIZE); 693 694 if (sc->mem_shared) { 695 696 /* 697 * Special case setup for 16 bit boards... 698 */ 699 if (sc->isa16bit) { 700 switch (sc->vendor) { 701 702 /* 703 * For 16bit 3Com boards (which have 16k of 704 * memory), we have the xmit buffers in a 705 * different page of memory ('page 0') - so 706 * change pages. 707 */ 708 case ED_VENDOR_3COM: 709 ed_asic_outb(sc, ED_3COM_GACFR, 710 ED_3COM_GACFR_RSEL); 711 break; 712 713 /* 714 * Enable 16bit access to shared memory on 715 * WD/SMC boards. 716 */ 717 case ED_VENDOR_WD_SMC: 718 ed_asic_outb(sc, ED_WD_LAAR, 719 sc->wd_laar_proto | ED_WD_LAAR_M16EN); 720 if (sc->chip_type == ED_CHIP_TYPE_WD790) { 721 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_MENB); 722 } 723 break; 724 } 725 } 726 for (len = 0; m != 0; m = m->m_next) { 727 bcopy(mtod(m, caddr_t), buffer, m->m_len); 728 buffer += m->m_len; 729 len += m->m_len; 730 } 731 732 /* 733 * Restore previous shared memory access 734 */ 735 if (sc->isa16bit) { 736 switch (sc->vendor) { 737 case ED_VENDOR_3COM: 738 ed_asic_outb(sc, ED_3COM_GACFR, 739 ED_3COM_GACFR_RSEL | ED_3COM_GACFR_MBS0); 740 break; 741 case ED_VENDOR_WD_SMC: 742 if (sc->chip_type == ED_CHIP_TYPE_WD790) { 743 ed_asic_outb(sc, ED_WD_MSR, 0x00); 744 } 745 ed_asic_outb(sc, ED_WD_LAAR, 746 sc->wd_laar_proto & ~ED_WD_LAAR_M16EN); 747 break; 748 } 749 } 750 } else { 751 len = ed_pio_write_mbufs(sc, m, (uintptr_t)buffer); 752 if (len == 0) { 753 m_freem(m0); 754 goto outloop; 755 } 756 } 757 758 sc->txb_len[sc->txb_new] = max(len, (ETHER_MIN_LEN-ETHER_CRC_LEN)); 759 760 sc->txb_inuse++; 761 762 /* 763 * Point to next buffer slot and wrap if necessary. 764 */ 765 sc->txb_new++; 766 if (sc->txb_new == sc->txb_cnt) 767 sc->txb_new = 0; 768 769 if (sc->xmit_busy == 0) 770 ed_xmit(sc); 771 772 /* 773 * Tap off here if there is a bpf listener. 774 */ 775 BPF_MTAP(ifp, m0); 776 777 m_freem(m0); 778 779 /* 780 * Loop back to the top to possibly buffer more packets 781 */ 782 goto outloop; 783} 784 785/* 786 * Ethernet interface receiver interrupt. 787 */ 788static __inline void 789ed_rint(struct ed_softc *sc) 790{ 791 struct ifnet *ifp = &sc->arpcom.ac_if; 792 u_char boundry; 793 u_short len; 794 struct ed_ring packet_hdr; 795 char *packet_ptr; 796 797 if (sc->gone) 798 return; 799 800 /* 801 * Set NIC to page 1 registers to get 'current' pointer 802 */ 803 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA); 804 805 /* 806 * 'sc->next_packet' is the logical beginning of the ring-buffer - 807 * i.e. it points to where new data has been buffered. The 'CURR' 808 * (current) register points to the logical end of the ring-buffer - 809 * i.e. it points to where additional new data will be added. We loop 810 * here until the logical beginning equals the logical end (or in 811 * other words, until the ring-buffer is empty). 812 */ 813 while (sc->next_packet != ed_nic_inb(sc, ED_P1_CURR)) { 814 815 /* get pointer to this buffer's header structure */ 816 packet_ptr = sc->mem_ring + 817 (sc->next_packet - sc->rec_page_start) * ED_PAGE_SIZE; 818 819 /* 820 * The byte count includes a 4 byte header that was added by 821 * the NIC. 822 */ 823 if (sc->mem_shared) 824 packet_hdr = *(struct ed_ring *) packet_ptr; 825 else 826 ed_pio_readmem(sc, (uintptr_t)packet_ptr, 827 (char *) &packet_hdr, sizeof(packet_hdr)); 828 len = packet_hdr.count; 829 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring)) || 830 len < (ETHER_MIN_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring))) { 831 /* 832 * Length is a wild value. There's a good chance that 833 * this was caused by the NIC being old and buggy. 834 * The bug is that the length low byte is duplicated in 835 * the high byte. Try to recalculate the length based on 836 * the pointer to the next packet. 837 */ 838 /* 839 * NOTE: sc->next_packet is pointing at the current packet. 840 */ 841 len &= ED_PAGE_SIZE - 1; /* preserve offset into page */ 842 if (packet_hdr.next_packet >= sc->next_packet) { 843 len += (packet_hdr.next_packet - sc->next_packet) * ED_PAGE_SIZE; 844 } else { 845 len += ((packet_hdr.next_packet - sc->rec_page_start) + 846 (sc->rec_page_stop - sc->next_packet)) * ED_PAGE_SIZE; 847 } 848 /* 849 * because buffers are aligned on 256-byte boundary, 850 * the length computed above is off by 256 in almost 851 * all cases. Fix it... 852 */ 853 if (len & 0xff) 854 len -= 256 ; 855 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN 856 + sizeof(struct ed_ring))) 857 sc->mibdata.dot3StatsFrameTooLongs++; 858 } 859 /* 860 * Be fairly liberal about what we allow as a "reasonable" length 861 * so that a [crufty] packet will make it to BPF (and can thus 862 * be analyzed). Note that all that is really important is that 863 * we have a length that will fit into one mbuf cluster or less; 864 * the upper layer protocols can then figure out the length from 865 * their own length field(s). 866 * But make sure that we have at least a full ethernet header 867 * or we would be unable to call ether_input() later. 868 */ 869 if ((len >= sizeof(struct ed_ring) + ETHER_HDR_LEN) && 870 (len <= MCLBYTES) && 871 (packet_hdr.next_packet >= sc->rec_page_start) && 872 (packet_hdr.next_packet < sc->rec_page_stop)) { 873 /* 874 * Go get packet. 875 */ 876 ed_get_packet(sc, packet_ptr + sizeof(struct ed_ring), 877 len - sizeof(struct ed_ring)); 878 ifp->if_ipackets++; 879 } else { 880 /* 881 * Really BAD. The ring pointers are corrupted. 882 */ 883 log(LOG_ERR, 884 "%s: NIC memory corrupt - invalid packet length %d\n", 885 ifp->if_xname, len); 886 ifp->if_ierrors++; 887 ed_reset(ifp); 888 return; 889 } 890 891 /* 892 * Update next packet pointer 893 */ 894 sc->next_packet = packet_hdr.next_packet; 895 896 /* 897 * Update NIC boundry pointer - being careful to keep it one 898 * buffer behind. (as recommended by NS databook) 899 */ 900 boundry = sc->next_packet - 1; 901 if (boundry < sc->rec_page_start) 902 boundry = sc->rec_page_stop - 1; 903 904 /* 905 * Set NIC to page 0 registers to update boundry register 906 */ 907 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA); 908 909 ed_nic_outb(sc, ED_P0_BNRY, boundry); 910 911 /* 912 * Set NIC to page 1 registers before looping to top (prepare 913 * to get 'CURR' current pointer) 914 */ 915 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA); 916 } 917} 918 919/* 920 * Ethernet interface interrupt processor 921 */ 922void 923edintr(void *arg) 924{ 925 struct ed_softc *sc = (struct ed_softc*) arg; 926 struct ifnet *ifp = (struct ifnet *)sc; 927 u_char isr; 928 int count; 929 930 if (sc->gone) 931 return; 932 /* 933 * Set NIC to page 0 registers 934 */ 935 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA); 936 937 /* 938 * loop until there are no more new interrupts. When the card 939 * goes away, the hardware will read back 0xff. Looking at 940 * the interrupts, it would appear that 0xff is impossible, 941 * or at least extremely unlikely. 942 */ 943 while ((isr = ed_nic_inb(sc, ED_P0_ISR)) != 0 && isr != 0xff) { 944 945 /* 946 * reset all the bits that we are 'acknowledging' by writing a 947 * '1' to each bit position that was set (writing a '1' 948 * *clears* the bit) 949 */ 950 ed_nic_outb(sc, ED_P0_ISR, isr); 951 952 /* 953 * XXX workaround for AX88190 954 * We limit this to 5000 iterations. At 1us per inb/outb, 955 * this translates to about 15ms, which should be plenty 956 * of time, and also gives protection in the card eject 957 * case. 958 */ 959 if (sc->chip_type == ED_CHIP_TYPE_AX88190) { 960 count = 5000; /* 15ms */ 961 while (count-- && (ed_nic_inb(sc, ED_P0_ISR) & isr)) { 962 ed_nic_outb(sc, ED_P0_ISR,0); 963 ed_nic_outb(sc, ED_P0_ISR,isr); 964 } 965 if (count == 0) 966 break; 967 } 968 969 /* 970 * Handle transmitter interrupts. Handle these first because 971 * the receiver will reset the board under some conditions. 972 */ 973 if (isr & (ED_ISR_PTX | ED_ISR_TXE)) { 974 u_char collisions = ed_nic_inb(sc, ED_P0_NCR) & 0x0f; 975 976 /* 977 * Check for transmit error. If a TX completed with an 978 * error, we end up throwing the packet away. Really 979 * the only error that is possible is excessive 980 * collisions, and in this case it is best to allow 981 * the automatic mechanisms of TCP to backoff the 982 * flow. Of course, with UDP we're screwed, but this 983 * is expected when a network is heavily loaded. 984 */ 985 (void) ed_nic_inb(sc, ED_P0_TSR); 986 if (isr & ED_ISR_TXE) { 987 u_char tsr; 988 989 /* 990 * Excessive collisions (16) 991 */ 992 tsr = ed_nic_inb(sc, ED_P0_TSR); 993 if ((tsr & ED_TSR_ABT) 994 && (collisions == 0)) { 995 996 /* 997 * When collisions total 16, the 998 * P0_NCR will indicate 0, and the 999 * TSR_ABT is set. 1000 */ 1001 collisions = 16; 1002 sc->mibdata.dot3StatsExcessiveCollisions++; 1003 sc->mibdata.dot3StatsCollFrequencies[15]++; 1004 } 1005 if (tsr & ED_TSR_OWC) 1006 sc->mibdata.dot3StatsLateCollisions++; 1007 if (tsr & ED_TSR_CDH) 1008 sc->mibdata.dot3StatsSQETestErrors++; 1009 if (tsr & ED_TSR_CRS) 1010 sc->mibdata.dot3StatsCarrierSenseErrors++; 1011 if (tsr & ED_TSR_FU) 1012 sc->mibdata.dot3StatsInternalMacTransmitErrors++; 1013 1014 /* 1015 * update output errors counter 1016 */ 1017 ifp->if_oerrors++; 1018 } else { 1019 1020 /* 1021 * Update total number of successfully 1022 * transmitted packets. 1023 */ 1024 ifp->if_opackets++; 1025 } 1026 1027 /* 1028 * reset tx busy and output active flags 1029 */ 1030 sc->xmit_busy = 0; 1031 ifp->if_flags &= ~IFF_OACTIVE; 1032 1033 /* 1034 * clear watchdog timer 1035 */ 1036 ifp->if_timer = 0; 1037 1038 /* 1039 * Add in total number of collisions on last 1040 * transmission. 1041 */ 1042 ifp->if_collisions += collisions; 1043 switch(collisions) { 1044 case 0: 1045 case 16: 1046 break; 1047 case 1: 1048 sc->mibdata.dot3StatsSingleCollisionFrames++; 1049 sc->mibdata.dot3StatsCollFrequencies[0]++; 1050 break; 1051 default: 1052 sc->mibdata.dot3StatsMultipleCollisionFrames++; 1053 sc->mibdata. 1054 dot3StatsCollFrequencies[collisions-1] 1055 ++; 1056 break; 1057 } 1058 1059 /* 1060 * Decrement buffer in-use count if not zero (can only 1061 * be zero if a transmitter interrupt occured while 1062 * not actually transmitting). If data is ready to 1063 * transmit, start it transmitting, otherwise defer 1064 * until after handling receiver 1065 */ 1066 if (sc->txb_inuse && --sc->txb_inuse) 1067 ed_xmit(sc); 1068 } 1069 1070 /* 1071 * Handle receiver interrupts 1072 */ 1073 if (isr & (ED_ISR_PRX | ED_ISR_RXE | ED_ISR_OVW)) { 1074 1075 /* 1076 * Overwrite warning. In order to make sure that a 1077 * lockup of the local DMA hasn't occurred, we reset 1078 * and re-init the NIC. The NSC manual suggests only a 1079 * partial reset/re-init is necessary - but some chips 1080 * seem to want more. The DMA lockup has been seen 1081 * only with early rev chips - Methinks this bug was 1082 * fixed in later revs. -DG 1083 */ 1084 if (isr & ED_ISR_OVW) { 1085 ifp->if_ierrors++; 1086#ifdef DIAGNOSTIC 1087 log(LOG_WARNING, 1088 "%s: warning - receiver ring buffer overrun\n", 1089 ifp->if_xname); 1090#endif 1091 1092 /* 1093 * Stop/reset/re-init NIC 1094 */ 1095 ed_reset(ifp); 1096 } else { 1097 1098 /* 1099 * Receiver Error. One or more of: CRC error, 1100 * frame alignment error FIFO overrun, or 1101 * missed packet. 1102 */ 1103 if (isr & ED_ISR_RXE) { 1104 u_char rsr; 1105 rsr = ed_nic_inb(sc, ED_P0_RSR); 1106 if (rsr & ED_RSR_CRC) 1107 sc->mibdata.dot3StatsFCSErrors++; 1108 if (rsr & ED_RSR_FAE) 1109 sc->mibdata.dot3StatsAlignmentErrors++; 1110 if (rsr & ED_RSR_FO) 1111 sc->mibdata.dot3StatsInternalMacReceiveErrors++; 1112 ifp->if_ierrors++; 1113#ifdef ED_DEBUG 1114 if_printf(ifp, "receive error %x\n", 1115 ed_nic_inb(sc, ED_P0_RSR)); 1116#endif 1117 } 1118 1119 /* 1120 * Go get the packet(s) XXX - Doing this on an 1121 * error is dubious because there shouldn't be 1122 * any data to get (we've configured the 1123 * interface to not accept packets with 1124 * errors). 1125 */ 1126 1127 /* 1128 * Enable 16bit access to shared memory first 1129 * on WD/SMC boards. 1130 */ 1131 if (sc->isa16bit && 1132 (sc->vendor == ED_VENDOR_WD_SMC)) { 1133 1134 ed_asic_outb(sc, ED_WD_LAAR, 1135 sc->wd_laar_proto | ED_WD_LAAR_M16EN); 1136 if (sc->chip_type == ED_CHIP_TYPE_WD790) { 1137 ed_asic_outb(sc, ED_WD_MSR, 1138 ED_WD_MSR_MENB); 1139 } 1140 } 1141 ed_rint(sc); 1142 1143 /* disable 16bit access */ 1144 if (sc->isa16bit && 1145 (sc->vendor == ED_VENDOR_WD_SMC)) { 1146 1147 if (sc->chip_type == ED_CHIP_TYPE_WD790) { 1148 ed_asic_outb(sc, ED_WD_MSR, 0x00); 1149 } 1150 ed_asic_outb(sc, ED_WD_LAAR, 1151 sc->wd_laar_proto & ~ED_WD_LAAR_M16EN); 1152 } 1153 } 1154 } 1155 1156 /* 1157 * If it looks like the transmitter can take more data, 1158 * attempt to start output on the interface. This is done 1159 * after handling the receiver to give the receiver priority. 1160 */ 1161 if ((ifp->if_flags & IFF_OACTIVE) == 0) 1162 ed_start(ifp); 1163 1164 /* 1165 * return NIC CR to standard state: page 0, remote DMA 1166 * complete, start (toggling the TXP bit off, even if was just 1167 * set in the transmit routine, is *okay* - it is 'edge' 1168 * triggered from low to high) 1169 */ 1170 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA); 1171 1172 /* 1173 * If the Network Talley Counters overflow, read them to reset 1174 * them. It appears that old 8390's won't clear the ISR flag 1175 * otherwise - resulting in an infinite loop. 1176 */ 1177 if (isr & ED_ISR_CNT) { 1178 (void) ed_nic_inb(sc, ED_P0_CNTR0); 1179 (void) ed_nic_inb(sc, ED_P0_CNTR1); 1180 (void) ed_nic_inb(sc, ED_P0_CNTR2); 1181 } 1182 } 1183} 1184 1185/* 1186 * Process an ioctl request. 1187 */ 1188static int 1189ed_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1190{ 1191 struct ed_softc *sc = ifp->if_softc; 1192#ifndef ED_NO_MIIBUS 1193 struct ifreq *ifr = (struct ifreq *)data; 1194 struct mii_data *mii; 1195#endif 1196 int s, error = 0; 1197 1198 if (sc == NULL || sc->gone) { 1199 ifp->if_flags &= ~IFF_RUNNING; 1200 return ENXIO; 1201 } 1202 s = splimp(); 1203 1204 switch (command) { 1205 case SIOCSIFFLAGS: 1206 1207 /* 1208 * If the interface is marked up and stopped, then start it. 1209 * If it is marked down and running, then stop it. 1210 */ 1211 if (ifp->if_flags & IFF_UP) { 1212 if ((ifp->if_flags & IFF_RUNNING) == 0) 1213 ed_init(sc); 1214 } else { 1215 if (ifp->if_flags & IFF_RUNNING) { 1216 ed_stop(sc); 1217 ifp->if_flags &= ~IFF_RUNNING; 1218 } 1219 } 1220 1221 /* 1222 * Promiscuous flag may have changed, so reprogram the RCR. 1223 */ 1224 ed_setrcr(sc); 1225 1226 /* 1227 * An unfortunate hack to provide the (required) software 1228 * control of the tranceiver for 3Com boards. The ALTPHYS flag 1229 * disables the tranceiver if set. 1230 */ 1231 if (sc->vendor == ED_VENDOR_3COM) { 1232 if (ifp->if_flags & IFF_ALTPHYS) { 1233 ed_asic_outb(sc, ED_3COM_CR, 0); 1234 } else { 1235 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_XSEL); 1236 } 1237 } 1238#ifdef ED_HPP 1239 else if (sc->vendor == ED_VENDOR_HP) 1240 ed_hpp_set_physical_link(sc); 1241#endif 1242 break; 1243 1244 case SIOCADDMULTI: 1245 case SIOCDELMULTI: 1246 /* 1247 * Multicast list has changed; set the hardware filter 1248 * accordingly. 1249 */ 1250 ed_setrcr(sc); 1251 error = 0; 1252 break; 1253 1254#ifndef ED_NO_MIIBUS 1255 case SIOCGIFMEDIA: 1256 case SIOCSIFMEDIA: 1257 if (sc->miibus == NULL) { 1258 error = EINVAL; 1259 break; 1260 } 1261 mii = device_get_softc(sc->miibus); 1262 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1263 break; 1264#endif 1265 1266 default: 1267 error = ether_ioctl(ifp, command, data); 1268 } 1269 (void) splx(s); 1270 return (error); 1271} 1272 1273/* 1274 * Given a source and destination address, copy 'amount' of a packet from 1275 * the ring buffer into a linear destination buffer. Takes into account 1276 * ring-wrap. 1277 */ 1278static __inline char * 1279ed_ring_copy(struct ed_softc *sc, char *src, char *dst, u_short amount) 1280{ 1281 u_short tmp_amount; 1282 1283 /* does copy wrap to lower addr in ring buffer? */ 1284 if (src + amount > sc->mem_end) { 1285 tmp_amount = sc->mem_end - src; 1286 1287 /* copy amount up to end of NIC memory */ 1288 if (sc->mem_shared) 1289 bcopy(src, dst, tmp_amount); 1290 else 1291 ed_pio_readmem(sc, (uintptr_t)src, dst, tmp_amount); 1292 1293 amount -= tmp_amount; 1294 src = sc->mem_ring; 1295 dst += tmp_amount; 1296 } 1297 if (sc->mem_shared) 1298 bcopy(src, dst, amount); 1299 else 1300 ed_pio_readmem(sc, (uintptr_t)src, dst, amount); 1301 1302 return (src + amount); 1303} 1304 1305/* 1306 * Retreive packet from shared memory and send to the next level up via 1307 * ether_input(). 1308 */ 1309static void 1310ed_get_packet(struct ed_softc *sc, char *buf, u_short len) 1311{ 1312 struct ifnet *ifp = &sc->arpcom.ac_if; 1313 struct ether_header *eh; 1314 struct mbuf *m; 1315 1316 /* Allocate a header mbuf */ 1317 MGETHDR(m, M_DONTWAIT, MT_DATA); 1318 if (m == NULL) 1319 return; 1320 m->m_pkthdr.rcvif = ifp; 1321 m->m_pkthdr.len = m->m_len = len; 1322 1323 /* 1324 * We always put the received packet in a single buffer - 1325 * either with just an mbuf header or in a cluster attached 1326 * to the header. The +2 is to compensate for the alignment 1327 * fixup below. 1328 */ 1329 if ((len + 2) > MHLEN) { 1330 /* Attach an mbuf cluster */ 1331 MCLGET(m, M_DONTWAIT); 1332 1333 /* Insist on getting a cluster */ 1334 if ((m->m_flags & M_EXT) == 0) { 1335 m_freem(m); 1336 return; 1337 } 1338 } 1339 1340 /* 1341 * The +2 is to longword align the start of the real packet. 1342 * This is important for NFS. 1343 */ 1344 m->m_data += 2; 1345 eh = mtod(m, struct ether_header *); 1346 1347 /* 1348 * Get packet, including link layer address, from interface. 1349 */ 1350 ed_ring_copy(sc, buf, (char *)eh, len); 1351 1352 m->m_pkthdr.len = m->m_len = len; 1353 1354 (*ifp->if_input)(ifp, m); 1355} 1356 1357/* 1358 * Supporting routines 1359 */ 1360 1361/* 1362 * Given a NIC memory source address and a host memory destination 1363 * address, copy 'amount' from NIC to host using Programmed I/O. 1364 * The 'amount' is rounded up to a word - okay as long as mbufs 1365 * are word sized. 1366 * This routine is currently Novell-specific. 1367 */ 1368void 1369ed_pio_readmem(struct ed_softc *sc, long src, uint8_t *dst, uint16_t amount) 1370{ 1371#ifdef ED_HPP 1372 /* HP PC Lan+ cards need special handling */ 1373 if (sc->vendor == ED_VENDOR_HP && sc->type == ED_TYPE_HP_PCLANPLUS) { 1374 ed_hpp_readmem(sc, src, dst, amount); 1375 return; 1376 } 1377#endif 1378 1379 /* Regular Novell cards */ 1380 /* select page 0 registers */ 1381 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STA); 1382 1383 /* round up to a word */ 1384 if (amount & 1) 1385 ++amount; 1386 1387 /* set up DMA byte count */ 1388 ed_nic_outb(sc, ED_P0_RBCR0, amount); 1389 ed_nic_outb(sc, ED_P0_RBCR1, amount >> 8); 1390 1391 /* set up source address in NIC mem */ 1392 ed_nic_outb(sc, ED_P0_RSAR0, src); 1393 ed_nic_outb(sc, ED_P0_RSAR1, src >> 8); 1394 1395 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD0 | ED_CR_STA); 1396 1397 if (sc->isa16bit) { 1398 ed_asic_insw(sc, ED_NOVELL_DATA, dst, amount / 2); 1399 } else { 1400 ed_asic_insb(sc, ED_NOVELL_DATA, dst, amount); 1401 } 1402} 1403 1404/* 1405 * Stripped down routine for writing a linear buffer to NIC memory. 1406 * Only used in the probe routine to test the memory. 'len' must 1407 * be even. 1408 */ 1409void 1410ed_pio_writemem(struct ed_softc *sc, uint8_t *src, uint16_t dst, uint16_t len) 1411{ 1412 int maxwait = 200; /* about 240us */ 1413 1414 /* select page 0 registers */ 1415 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STA); 1416 1417 /* reset remote DMA complete flag */ 1418 ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC); 1419 1420 /* set up DMA byte count */ 1421 ed_nic_outb(sc, ED_P0_RBCR0, len); 1422 ed_nic_outb(sc, ED_P0_RBCR1, len >> 8); 1423 1424 /* set up destination address in NIC mem */ 1425 ed_nic_outb(sc, ED_P0_RSAR0, dst); 1426 ed_nic_outb(sc, ED_P0_RSAR1, dst >> 8); 1427 1428 /* set remote DMA write */ 1429 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD1 | ED_CR_STA); 1430 1431 if (sc->isa16bit) { 1432 ed_asic_outsw(sc, ED_NOVELL_DATA, src, len / 2); 1433 } else { 1434 ed_asic_outsb(sc, ED_NOVELL_DATA, src, len); 1435 } 1436 1437 /* 1438 * Wait for remote DMA complete. This is necessary because on the 1439 * transmit side, data is handled internally by the NIC in bursts and 1440 * we can't start another remote DMA until this one completes. Not 1441 * waiting causes really bad things to happen - like the NIC 1442 * irrecoverably jamming the ISA bus. 1443 */ 1444 while (((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && 1445 --maxwait) 1446 continue; 1447} 1448 1449/* 1450 * Write an mbuf chain to the destination NIC memory address using 1451 * programmed I/O. 1452 */ 1453static u_short 1454ed_pio_write_mbufs(struct ed_softc *sc, struct mbuf *m, long dst) 1455{ 1456 struct ifnet *ifp = (struct ifnet *)sc; 1457 unsigned short total_len, dma_len; 1458 struct mbuf *mp; 1459 int maxwait = 200; /* about 240us */ 1460 1461#ifdef ED_HPP 1462 /* HP PC Lan+ cards need special handling */ 1463 if (sc->vendor == ED_VENDOR_HP && sc->type == ED_TYPE_HP_PCLANPLUS) 1464 return ed_hpp_write_mbufs(sc, m, dst); 1465#endif 1466 1467 /* Regular Novell cards */ 1468 /* First, count up the total number of bytes to copy */ 1469 for (total_len = 0, mp = m; mp; mp = mp->m_next) 1470 total_len += mp->m_len; 1471 1472 dma_len = total_len; 1473 if (sc->isa16bit && (dma_len & 1)) 1474 dma_len++; 1475 1476 /* select page 0 registers */ 1477 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STA); 1478 1479 /* reset remote DMA complete flag */ 1480 ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC); 1481 1482 /* set up DMA byte count */ 1483 ed_nic_outb(sc, ED_P0_RBCR0, dma_len); 1484 ed_nic_outb(sc, ED_P0_RBCR1, dma_len >> 8); 1485 1486 /* set up destination address in NIC mem */ 1487 ed_nic_outb(sc, ED_P0_RSAR0, dst); 1488 ed_nic_outb(sc, ED_P0_RSAR1, dst >> 8); 1489 1490 /* set remote DMA write */ 1491 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD1 | ED_CR_STA); 1492 1493 /* 1494 * Transfer the mbuf chain to the NIC memory. 1495 * 16-bit cards require that data be transferred as words, and only words. 1496 * So that case requires some extra code to patch over odd-length mbufs. 1497 */ 1498 1499 if (!sc->isa16bit) { 1500 /* NE1000s are easy */ 1501 while (m) { 1502 if (m->m_len) { 1503 ed_asic_outsb(sc, ED_NOVELL_DATA, 1504 m->m_data, m->m_len); 1505 } 1506 m = m->m_next; 1507 } 1508 } else { 1509 /* NE2000s are a pain */ 1510 unsigned char *data; 1511 int len, wantbyte; 1512 unsigned char savebyte[2]; 1513 1514 wantbyte = 0; 1515 1516 while (m) { 1517 len = m->m_len; 1518 if (len) { 1519 data = mtod(m, caddr_t); 1520 /* finish the last word */ 1521 if (wantbyte) { 1522 savebyte[1] = *data; 1523 ed_asic_outw(sc, ED_NOVELL_DATA, 1524 *(u_short *)savebyte); 1525 data++; 1526 len--; 1527 wantbyte = 0; 1528 } 1529 /* output contiguous words */ 1530 if (len > 1) { 1531 ed_asic_outsw(sc, ED_NOVELL_DATA, 1532 data, len >> 1); 1533 data += len & ~1; 1534 len &= 1; 1535 } 1536 /* save last byte, if necessary */ 1537 if (len == 1) { 1538 savebyte[0] = *data; 1539 wantbyte = 1; 1540 } 1541 } 1542 m = m->m_next; 1543 } 1544 /* spit last byte */ 1545 if (wantbyte) { 1546 ed_asic_outw(sc, ED_NOVELL_DATA, *(u_short *)savebyte); 1547 } 1548 } 1549 1550 /* 1551 * Wait for remote DMA complete. This is necessary because on the 1552 * transmit side, data is handled internally by the NIC in bursts and 1553 * we can't start another remote DMA until this one completes. Not 1554 * waiting causes really bad things to happen - like the NIC 1555 * irrecoverably jamming the ISA bus. 1556 */ 1557 while (((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && 1558 --maxwait) 1559 continue; 1560 1561 if (!maxwait) { 1562 log(LOG_WARNING, "%s: remote transmit DMA failed to complete\n", 1563 ifp->if_xname); 1564 ed_reset(ifp); 1565 return(0); 1566 } 1567 return (total_len); 1568} 1569 1570#ifndef ED_NO_MIIBUS 1571/* 1572 * MII bus support routines. 1573 */ 1574int 1575ed_miibus_readreg(device_t dev, int phy, int reg) 1576{ 1577 struct ed_softc *sc; 1578 int failed, s, val; 1579 1580 s = splimp(); 1581 sc = device_get_softc(dev); 1582 if (sc->gone) { 1583 splx(s); 1584 return (0); 1585 } 1586 1587 (*sc->mii_writebits)(sc, 0xffffffff, 32); 1588 (*sc->mii_writebits)(sc, ED_MII_STARTDELIM, ED_MII_STARTDELIM_BITS); 1589 (*sc->mii_writebits)(sc, ED_MII_READOP, ED_MII_OP_BITS); 1590 (*sc->mii_writebits)(sc, phy, ED_MII_PHY_BITS); 1591 (*sc->mii_writebits)(sc, reg, ED_MII_REG_BITS); 1592 1593 failed = (*sc->mii_readbits)(sc, ED_MII_ACK_BITS); 1594 val = (*sc->mii_readbits)(sc, ED_MII_DATA_BITS); 1595 (*sc->mii_writebits)(sc, ED_MII_IDLE, ED_MII_IDLE_BITS); 1596 1597 splx(s); 1598 return (failed ? 0 : val); 1599} 1600 1601void 1602ed_miibus_writereg(device_t dev, int phy, int reg, int data) 1603{ 1604 struct ed_softc *sc; 1605 int s; 1606 1607 s = splimp(); 1608 sc = device_get_softc(dev); 1609 if (sc->gone) { 1610 splx(s); 1611 return; 1612 } 1613 1614 (*sc->mii_writebits)(sc, 0xffffffff, 32); 1615 (*sc->mii_writebits)(sc, ED_MII_STARTDELIM, ED_MII_STARTDELIM_BITS); 1616 (*sc->mii_writebits)(sc, ED_MII_WRITEOP, ED_MII_OP_BITS); 1617 (*sc->mii_writebits)(sc, phy, ED_MII_PHY_BITS); 1618 (*sc->mii_writebits)(sc, reg, ED_MII_REG_BITS); 1619 (*sc->mii_writebits)(sc, ED_MII_TURNAROUND, ED_MII_TURNAROUND_BITS); 1620 (*sc->mii_writebits)(sc, data, ED_MII_DATA_BITS); 1621 (*sc->mii_writebits)(sc, ED_MII_IDLE, ED_MII_IDLE_BITS); 1622 1623 splx(s); 1624} 1625 1626int 1627ed_ifmedia_upd(struct ifnet *ifp) 1628{ 1629 struct ed_softc *sc; 1630 struct mii_data *mii; 1631 1632 sc = ifp->if_softc; 1633 if (sc->gone || sc->miibus == NULL) 1634 return (ENXIO); 1635 1636 mii = device_get_softc(sc->miibus); 1637 return mii_mediachg(mii); 1638} 1639 1640void 1641ed_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1642{ 1643 struct ed_softc *sc; 1644 struct mii_data *mii; 1645 1646 sc = ifp->if_softc; 1647 if (sc->gone || sc->miibus == NULL) 1648 return; 1649 1650 mii = device_get_softc(sc->miibus); 1651 mii_pollstat(mii); 1652 ifmr->ifm_active = mii->mii_media_active; 1653 ifmr->ifm_status = mii->mii_media_status; 1654} 1655 1656void 1657ed_child_detached(device_t dev, device_t child) 1658{ 1659 struct ed_softc *sc; 1660 1661 sc = device_get_softc(dev); 1662 if (child == sc->miibus) 1663 sc->miibus = NULL; 1664} 1665#endif 1666 1667static void 1668ed_setrcr(struct ed_softc *sc) 1669{ 1670 struct ifnet *ifp = (struct ifnet *)sc; 1671 int i; 1672 u_char reg1; 1673 1674 /* Bit 6 in AX88190 RCR register must be set. */ 1675 if (sc->chip_type == ED_CHIP_TYPE_AX88190) 1676 reg1 = ED_RCR_INTT; 1677 else 1678 reg1 = 0x00; 1679 1680 /* set page 1 registers */ 1681 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP); 1682 1683 if (ifp->if_flags & IFF_PROMISC) { 1684 1685 /* 1686 * Reconfigure the multicast filter. 1687 */ 1688 for (i = 0; i < 8; i++) 1689 ed_nic_outb(sc, ED_P1_MAR(i), 0xff); 1690 1691 /* 1692 * And turn on promiscuous mode. Also enable reception of 1693 * runts and packets with CRC & alignment errors. 1694 */ 1695 /* Set page 0 registers */ 1696 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP); 1697 1698 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_PRO | ED_RCR_AM | 1699 ED_RCR_AB | ED_RCR_AR | ED_RCR_SEP | reg1); 1700 } else { 1701 /* set up multicast addresses and filter modes */ 1702 if (ifp->if_flags & IFF_MULTICAST) { 1703 uint32_t mcaf[2]; 1704 1705 if (ifp->if_flags & IFF_ALLMULTI) { 1706 mcaf[0] = 0xffffffff; 1707 mcaf[1] = 0xffffffff; 1708 } else 1709 ed_ds_getmcaf(sc, mcaf); 1710 1711 /* 1712 * Set multicast filter on chip. 1713 */ 1714 for (i = 0; i < 8; i++) 1715 ed_nic_outb(sc, ED_P1_MAR(i), ((u_char *) mcaf)[i]); 1716 1717 /* Set page 0 registers */ 1718 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP); 1719 1720 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_AM | ED_RCR_AB | reg1); 1721 } else { 1722 1723 /* 1724 * Initialize multicast address hashing registers to 1725 * not accept multicasts. 1726 */ 1727 for (i = 0; i < 8; ++i) 1728 ed_nic_outb(sc, ED_P1_MAR(i), 0x00); 1729 1730 /* Set page 0 registers */ 1731 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP); 1732 1733 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_AB | reg1); 1734 } 1735 } 1736 1737 /* 1738 * Start interface. 1739 */ 1740 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA); 1741} 1742 1743/* 1744 * Compute the multicast address filter from the 1745 * list of multicast addresses we need to listen to. 1746 */ 1747static void 1748ed_ds_getmcaf(struct ed_softc *sc, uint32_t *mcaf) 1749{ 1750 uint32_t index; 1751 u_char *af = (u_char *) mcaf; 1752 struct ifmultiaddr *ifma; 1753 1754 mcaf[0] = 0; 1755 mcaf[1] = 0; 1756 1757 TAILQ_FOREACH(ifma, &sc->arpcom.ac_if.if_multiaddrs, ifma_link) { 1758 if (ifma->ifma_addr->sa_family != AF_LINK) 1759 continue; 1760 index = ether_crc32_be(LLADDR((struct sockaddr_dl *) 1761 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 1762 af[index >> 3] |= 1 << (index & 7); 1763 } 1764} 1765 1766int 1767ed_isa_mem_ok(device_t dev, u_long pmem, u_int memsize) 1768{ 1769 if (pmem < 0xa0000 || pmem + memsize > 0x1000000) { 1770 device_printf(dev, "Invalid ISA memory address range " 1771 "configured: 0x%lx - 0x%lx\n", pmem, pmem + memsize); 1772 return (ENXIO); 1773 } 1774 return (0); 1775} 1776 1777int 1778ed_clear_memory(device_t dev) 1779{ 1780 struct ed_softc *sc = device_get_softc(dev); 1781 int i; 1782 1783 /* 1784 * Now zero memory and verify that it is clear 1785 */ 1786 bzero(sc->mem_start, sc->mem_size); 1787 1788 for (i = 0; i < sc->mem_size; ++i) { 1789 if (sc->mem_start[i]) { 1790 device_printf(dev, "failed to clear shared memory at " 1791 "0x%jx - check configuration\n", 1792 (uintmax_t)rman_get_start(sc->mem_res) + i); 1793 return (ENXIO); 1794 } 1795 } 1796 return (0); 1797} 1798