if_ed.c revision 126526
1/* 2 * Copyright (c) 1995, David Greenman 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28#include <sys/cdefs.h> 29__FBSDID("$FreeBSD: head/sys/dev/ed/if_ed.c 126526 2004-03-03 06:48:42Z obrien $"); 30 31/* 32 * Device driver for National Semiconductor DS8390/WD83C690 based ethernet 33 * adapters. By David Greenman, 29-April-1993 34 * 35 * Currently supports the Western Digital/SMC 8003 and 8013 series, 36 * the SMC Elite Ultra (8216), the 3Com 3c503, the NE1000 and NE2000, 37 * and a variety of similar clones. 38 * 39 */ 40 41#include "opt_ed.h" 42 43#include <sys/param.h> 44#include <sys/systm.h> 45#include <sys/sockio.h> 46#include <sys/mbuf.h> 47#include <sys/kernel.h> 48#include <sys/socket.h> 49#include <sys/syslog.h> 50 51#include <sys/bus.h> 52 53#include <machine/bus.h> 54#include <sys/rman.h> 55#include <machine/resource.h> 56 57#include <net/ethernet.h> 58#include <net/if.h> 59#include <net/if_arp.h> 60#include <net/if_dl.h> 61#include <net/if_mib.h> 62#include <net/if_media.h> 63 64#ifndef ED_NO_MIIBUS 65#include <dev/mii/mii.h> 66#include <dev/mii/miivar.h> 67#endif 68 69#include <net/bpf.h> 70#include <net/bridge.h> 71 72#include <machine/md_var.h> 73 74#include <dev/ed/if_edreg.h> 75#include <dev/ed/if_edvar.h> 76 77devclass_t ed_devclass; 78 79static void ed_init (void *); 80static int ed_ioctl (struct ifnet *, u_long, caddr_t); 81static void ed_start (struct ifnet *); 82static void ed_reset (struct ifnet *); 83static void ed_watchdog (struct ifnet *); 84#ifndef ED_NO_MIIBUS 85static void ed_tick (void *); 86#endif 87 88static void ds_getmcaf (struct ed_softc *, u_int32_t *); 89 90static void ed_get_packet (struct ed_softc *, char *, /* u_short */ int); 91 92static __inline void ed_rint (struct ed_softc *); 93static __inline void ed_xmit (struct ed_softc *); 94static __inline char * ed_ring_copy(struct ed_softc *, char *, char *, 95 /* u_short */ int); 96static void ed_hpp_set_physical_link(struct ed_softc *); 97static void ed_hpp_readmem (struct ed_softc *, int, unsigned char *, 98 /* u_short */ int); 99static void ed_hpp_writemem (struct ed_softc *, unsigned char *, 100 /* u_short */ int, /* u_short */ int); 101static u_short ed_hpp_write_mbufs(struct ed_softc *, struct mbuf *, int); 102 103static u_short ed_pio_write_mbufs(struct ed_softc *, struct mbuf *, long); 104 105static void ed_setrcr (struct ed_softc *); 106 107static uint32_t ds_mchash (const uint8_t *); 108 109/* 110 * Interrupt conversion table for WD/SMC ASIC/83C584 111 */ 112static unsigned short ed_intr_val[] = { 113 9, 114 3, 115 5, 116 7, 117 10, 118 11, 119 15, 120 4 121}; 122 123/* 124 * Interrupt conversion table for 83C790 125 */ 126static unsigned short ed_790_intr_val[] = { 127 0, 128 9, 129 3, 130 5, 131 7, 132 10, 133 11, 134 15 135}; 136 137/* 138 * Interrupt conversion table for the HP PC LAN+ 139 */ 140 141static unsigned short ed_hpp_intr_val[] = { 142 0, /* 0 */ 143 0, /* 1 */ 144 0, /* 2 */ 145 3, /* 3 */ 146 4, /* 4 */ 147 5, /* 5 */ 148 6, /* 6 */ 149 7, /* 7 */ 150 0, /* 8 */ 151 9, /* 9 */ 152 10, /* 10 */ 153 11, /* 11 */ 154 12, /* 12 */ 155 0, /* 13 */ 156 0, /* 14 */ 157 15 /* 15 */ 158}; 159 160/* 161 * Generic probe routine for testing for the existance of a DS8390. 162 * Must be called after the NIC has just been reset. This routine 163 * works by looking at certain register values that are guaranteed 164 * to be initialized a certain way after power-up or reset. Seems 165 * not to currently work on the 83C690. 166 * 167 * Specifically: 168 * 169 * Register reset bits set bits 170 * Command Register (CR) TXP, STA RD2, STP 171 * Interrupt Status (ISR) RST 172 * Interrupt Mask (IMR) All bits 173 * Data Control (DCR) LAS 174 * Transmit Config. (TCR) LB1, LB0 175 * 176 * We only look at the CR and ISR registers, however, because looking at 177 * the others would require changing register pages (which would be 178 * intrusive if this isn't an 8390). 179 * 180 * Return 1 if 8390 was found, 0 if not. 181 */ 182 183int 184ed_probe_generic8390(sc) 185 struct ed_softc *sc; 186{ 187 if ((ed_nic_inb(sc, ED_P0_CR) & 188 (ED_CR_RD2 | ED_CR_TXP | ED_CR_STA | ED_CR_STP)) != 189 (ED_CR_RD2 | ED_CR_STP)) 190 return (0); 191 if ((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RST) != ED_ISR_RST) 192 return (0); 193 194 return (1); 195} 196 197/* 198 * Probe and vendor-specific initialization routine for SMC/WD80x3 boards 199 */ 200int 201ed_probe_WD80x3_generic(dev, flags, intr_vals) 202 device_t dev; 203 int flags; 204 unsigned short *intr_vals[]; 205{ 206 struct ed_softc *sc = device_get_softc(dev); 207 int error; 208 int i; 209 u_int memsize, maddr; 210 u_char iptr, isa16bit, sum, totalsum; 211 u_long conf_maddr, conf_msize, irq, junk; 212 213 sc->chip_type = ED_CHIP_TYPE_DP8390; 214 215 if (ED_FLAGS_GETTYPE(flags) == ED_FLAGS_TOSH_ETHER) { 216 totalsum = ED_WD_ROM_CHECKSUM_TOTAL_TOSH_ETHER; 217 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_POW); 218 DELAY(10000); 219 } 220 else 221 totalsum = ED_WD_ROM_CHECKSUM_TOTAL; 222 223 /* 224 * Attempt to do a checksum over the station address PROM. If it 225 * fails, it's probably not a SMC/WD board. There is a problem with 226 * this, though: some clone WD boards don't pass the checksum test. 227 * Danpex boards for one. 228 */ 229 for (sum = 0, i = 0; i < 8; ++i) 230 sum += ed_asic_inb(sc, ED_WD_PROM + i); 231 232 if (sum != totalsum) { 233 234 /* 235 * Checksum is invalid. This often happens with cheap WD8003E 236 * clones. In this case, the checksum byte (the eighth byte) 237 * seems to always be zero. 238 */ 239 if (ed_asic_inb(sc, ED_WD_CARD_ID) != ED_TYPE_WD8003E || 240 ed_asic_inb(sc, ED_WD_PROM + 7) != 0) 241 return (ENXIO); 242 } 243 /* reset card to force it into a known state. */ 244 if (ED_FLAGS_GETTYPE(flags) == ED_FLAGS_TOSH_ETHER) 245 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_RST | ED_WD_MSR_POW); 246 else 247 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_RST); 248 249 DELAY(100); 250 ed_asic_outb(sc, ED_WD_MSR, ed_asic_inb(sc, ED_WD_MSR) & ~ED_WD_MSR_RST); 251 /* wait in the case this card is reading its EEROM */ 252 DELAY(5000); 253 254 sc->vendor = ED_VENDOR_WD_SMC; 255 sc->type = ed_asic_inb(sc, ED_WD_CARD_ID); 256 257 /* 258 * Set initial values for width/size. 259 */ 260 memsize = 8192; 261 isa16bit = 0; 262 switch (sc->type) { 263 case ED_TYPE_WD8003S: 264 sc->type_str = "WD8003S"; 265 break; 266 case ED_TYPE_WD8003E: 267 sc->type_str = "WD8003E"; 268 break; 269 case ED_TYPE_WD8003EB: 270 sc->type_str = "WD8003EB"; 271 break; 272 case ED_TYPE_WD8003W: 273 sc->type_str = "WD8003W"; 274 break; 275 case ED_TYPE_WD8013EBT: 276 sc->type_str = "WD8013EBT"; 277 memsize = 16384; 278 isa16bit = 1; 279 break; 280 case ED_TYPE_WD8013W: 281 sc->type_str = "WD8013W"; 282 memsize = 16384; 283 isa16bit = 1; 284 break; 285 case ED_TYPE_WD8013EP: /* also WD8003EP */ 286 if (ed_asic_inb(sc, ED_WD_ICR) & ED_WD_ICR_16BIT) { 287 isa16bit = 1; 288 memsize = 16384; 289 sc->type_str = "WD8013EP"; 290 } else { 291 sc->type_str = "WD8003EP"; 292 } 293 break; 294 case ED_TYPE_WD8013WC: 295 sc->type_str = "WD8013WC"; 296 memsize = 16384; 297 isa16bit = 1; 298 break; 299 case ED_TYPE_WD8013EBP: 300 sc->type_str = "WD8013EBP"; 301 memsize = 16384; 302 isa16bit = 1; 303 break; 304 case ED_TYPE_WD8013EPC: 305 sc->type_str = "WD8013EPC"; 306 memsize = 16384; 307 isa16bit = 1; 308 break; 309 case ED_TYPE_SMC8216C: /* 8216 has 16K shared mem -- 8416 has 8K */ 310 case ED_TYPE_SMC8216T: 311 if (sc->type == ED_TYPE_SMC8216C) { 312 sc->type_str = "SMC8216/SMC8216C"; 313 } else { 314 sc->type_str = "SMC8216T"; 315 } 316 317 ed_asic_outb(sc, ED_WD790_HWR, 318 ed_asic_inb(sc, ED_WD790_HWR) | ED_WD790_HWR_SWH); 319 switch (ed_asic_inb(sc, ED_WD790_RAR) & ED_WD790_RAR_SZ64) { 320 case ED_WD790_RAR_SZ64: 321 memsize = 65536; 322 break; 323 case ED_WD790_RAR_SZ32: 324 memsize = 32768; 325 break; 326 case ED_WD790_RAR_SZ16: 327 memsize = 16384; 328 break; 329 case ED_WD790_RAR_SZ8: 330 /* 8216 has 16K shared mem -- 8416 has 8K */ 331 if (sc->type == ED_TYPE_SMC8216C) { 332 sc->type_str = "SMC8416C/SMC8416BT"; 333 } else { 334 sc->type_str = "SMC8416T"; 335 } 336 memsize = 8192; 337 break; 338 } 339 ed_asic_outb(sc, ED_WD790_HWR, 340 ed_asic_inb(sc, ED_WD790_HWR) & ~ED_WD790_HWR_SWH); 341 342 isa16bit = 1; 343 sc->chip_type = ED_CHIP_TYPE_WD790; 344 break; 345 case ED_TYPE_TOSHIBA1: 346 sc->type_str = "Toshiba1"; 347 memsize = 32768; 348 isa16bit = 1; 349 break; 350 case ED_TYPE_TOSHIBA4: 351 sc->type_str = "Toshiba4"; 352 memsize = 32768; 353 isa16bit = 1; 354 break; 355 default: 356 sc->type_str = ""; 357 break; 358 } 359 360 /* 361 * Make some adjustments to initial values depending on what is found 362 * in the ICR. 363 */ 364 if (isa16bit && (sc->type != ED_TYPE_WD8013EBT) 365 && (sc->type != ED_TYPE_TOSHIBA1) && (sc->type != ED_TYPE_TOSHIBA4) 366 && ((ed_asic_inb(sc, ED_WD_ICR) & ED_WD_ICR_16BIT) == 0)) { 367 isa16bit = 0; 368 memsize = 8192; 369 } 370 371 error = bus_get_resource(dev, SYS_RES_MEMORY, 0, 372 &conf_maddr, &conf_msize); 373 if (error) 374 return (error); 375 376#if ED_DEBUG 377 printf("type = %x type_str=%s isa16bit=%d memsize=%d id_msize=%d\n", 378 sc->type, sc->type_str, isa16bit, memsize, conf_msize); 379 for (i = 0; i < 8; i++) 380 printf("%x -> %x\n", i, ed_asic_inb(sc, i)); 381#endif 382 383 /* 384 * Allow the user to override the autoconfiguration 385 */ 386 if (conf_msize > 1) 387 memsize = conf_msize; 388 389 maddr = conf_maddr; 390 if (maddr < 0xa0000 || maddr + memsize > 0x1000000) { 391 device_printf(dev, "Invalid ISA memory address range configured: 0x%x - 0x%x\n", 392 maddr, maddr + memsize); 393 return (ENXIO); 394 } 395 396 /* 397 * (note that if the user specifies both of the following flags that 398 * '8bit' mode intentionally has precedence) 399 */ 400 if (flags & ED_FLAGS_FORCE_16BIT_MODE) 401 isa16bit = 1; 402 if (flags & ED_FLAGS_FORCE_8BIT_MODE) 403 isa16bit = 0; 404 405 /* 406 * If possible, get the assigned interrupt number from the card and 407 * use it. 408 */ 409 if ((sc->type & ED_WD_SOFTCONFIG) && 410 (sc->chip_type != ED_CHIP_TYPE_WD790)) { 411 412 /* 413 * Assemble together the encoded interrupt number. 414 */ 415 iptr = (ed_asic_inb(sc, ED_WD_ICR) & ED_WD_ICR_IR2) | 416 ((ed_asic_inb(sc, ED_WD_IRR) & 417 (ED_WD_IRR_IR0 | ED_WD_IRR_IR1)) >> 5); 418 419 /* 420 * If no interrupt specified (or "?"), use what the board tells us. 421 */ 422 error = bus_get_resource(dev, SYS_RES_IRQ, 0, 423 &irq, &junk); 424 if (error && intr_vals[0] != NULL) { 425 error = bus_set_resource(dev, SYS_RES_IRQ, 0, 426 intr_vals[0][iptr], 1); 427 } 428 if (error) 429 return (error); 430 431 /* 432 * Enable the interrupt. 433 */ 434 ed_asic_outb(sc, ED_WD_IRR, 435 ed_asic_inb(sc, ED_WD_IRR) | ED_WD_IRR_IEN); 436 } 437 if (sc->chip_type == ED_CHIP_TYPE_WD790) { 438 ed_asic_outb(sc, ED_WD790_HWR, 439 ed_asic_inb(sc, ED_WD790_HWR) | ED_WD790_HWR_SWH); 440 iptr = (((ed_asic_inb(sc, ED_WD790_GCR) & ED_WD790_GCR_IR2) >> 4) | 441 (ed_asic_inb(sc, ED_WD790_GCR) & 442 (ED_WD790_GCR_IR1 | ED_WD790_GCR_IR0)) >> 2); 443 ed_asic_outb(sc, ED_WD790_HWR, 444 ed_asic_inb(sc, ED_WD790_HWR) & ~ED_WD790_HWR_SWH); 445 446 /* 447 * If no interrupt specified (or "?"), use what the board tells us. 448 */ 449 error = bus_get_resource(dev, SYS_RES_IRQ, 0, 450 &irq, &junk); 451 if (error && intr_vals[1] != NULL) { 452 error = bus_set_resource(dev, SYS_RES_IRQ, 0, 453 intr_vals[1][iptr], 1); 454 } 455 if (error) 456 return (error); 457 458 /* 459 * Enable interrupts. 460 */ 461 ed_asic_outb(sc, ED_WD790_ICR, 462 ed_asic_inb(sc, ED_WD790_ICR) | ED_WD790_ICR_EIL); 463 } 464 error = bus_get_resource(dev, SYS_RES_IRQ, 0, 465 &irq, &junk); 466 if (error) { 467 device_printf(dev, "%s cards don't support auto-detected/assigned interrupts.\n", 468 sc->type_str); 469 return (ENXIO); 470 } 471 sc->isa16bit = isa16bit; 472 sc->mem_shared = 1; 473 474 error = ed_alloc_memory(dev, 0, memsize); 475 if (error) { 476 printf("*** ed_alloc_memory() failed! (%d)\n", error); 477 return (error); 478 } 479 sc->mem_start = (caddr_t) rman_get_virtual(sc->mem_res); 480 481 /* 482 * allocate one xmit buffer if < 16k, two buffers otherwise 483 */ 484 if ((memsize < 16384) || 485 (flags & ED_FLAGS_NO_MULTI_BUFFERING)) { 486 sc->txb_cnt = 1; 487 } else { 488 sc->txb_cnt = 2; 489 } 490 sc->tx_page_start = ED_WD_PAGE_OFFSET; 491 sc->rec_page_start = ED_WD_PAGE_OFFSET + ED_TXBUF_SIZE * sc->txb_cnt; 492 sc->rec_page_stop = ED_WD_PAGE_OFFSET + memsize / ED_PAGE_SIZE; 493 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * sc->rec_page_start); 494 sc->mem_size = memsize; 495 sc->mem_end = sc->mem_start + memsize; 496 497 /* 498 * Get station address from on-board ROM 499 */ 500 for (i = 0; i < ETHER_ADDR_LEN; ++i) 501 sc->arpcom.ac_enaddr[i] = ed_asic_inb(sc, ED_WD_PROM + i); 502 503 /* 504 * Set upper address bits and 8/16 bit access to shared memory. 505 */ 506 if (isa16bit) { 507 if (sc->chip_type == ED_CHIP_TYPE_WD790) { 508 sc->wd_laar_proto = ed_asic_inb(sc, ED_WD_LAAR); 509 } else { 510 sc->wd_laar_proto = ED_WD_LAAR_L16EN | 511 ((kvtop(sc->mem_start) >> 19) & ED_WD_LAAR_ADDRHI); 512 } 513 /* 514 * Enable 16bit access 515 */ 516 ed_asic_outb(sc, ED_WD_LAAR, sc->wd_laar_proto | 517 ED_WD_LAAR_M16EN); 518 } else { 519 if (((sc->type & ED_WD_SOFTCONFIG) || 520 (sc->type == ED_TYPE_TOSHIBA1) || 521 (sc->type == ED_TYPE_TOSHIBA4) || 522 (sc->type == ED_TYPE_WD8013EBT)) && 523 (sc->chip_type != ED_CHIP_TYPE_WD790)) { 524 sc->wd_laar_proto = (kvtop(sc->mem_start) >> 19) & 525 ED_WD_LAAR_ADDRHI; 526 ed_asic_outb(sc, ED_WD_LAAR, sc->wd_laar_proto); 527 } 528 } 529 530 /* 531 * Set address and enable interface shared memory. 532 */ 533 if (sc->chip_type != ED_CHIP_TYPE_WD790) { 534 if (ED_FLAGS_GETTYPE(flags) == ED_FLAGS_TOSH_ETHER) { 535 ed_asic_outb(sc, ED_WD_MSR + 1, 536 ((kvtop(sc->mem_start) >> 8) & 0xe0) | 4); 537 ed_asic_outb(sc, ED_WD_MSR + 2, 538 ((kvtop(sc->mem_start) >> 16) & 0x0f)); 539 ed_asic_outb(sc, ED_WD_MSR, 540 ED_WD_MSR_MENB | ED_WD_MSR_POW); 541 } else { 542 ed_asic_outb(sc, ED_WD_MSR, 543 ((kvtop(sc->mem_start) >> 13) & 544 ED_WD_MSR_ADDR) | ED_WD_MSR_MENB); 545 } 546 sc->cr_proto = ED_CR_RD2; 547 } else { 548 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_MENB); 549 ed_asic_outb(sc, ED_WD790_HWR, (ed_asic_inb(sc, ED_WD790_HWR) | ED_WD790_HWR_SWH)); 550 ed_asic_outb(sc, ED_WD790_RAR, ((kvtop(sc->mem_start) >> 13) & 0x0f) | 551 ((kvtop(sc->mem_start) >> 11) & 0x40) | 552 (ed_asic_inb(sc, ED_WD790_RAR) & 0xb0)); 553 ed_asic_outb(sc, ED_WD790_HWR, (ed_asic_inb(sc, ED_WD790_HWR) & ~ED_WD790_HWR_SWH)); 554 sc->cr_proto = 0; 555 } 556 557#if 0 558 printf("starting memory performance test at 0x%x, size %d...\n", 559 sc->mem_start, memsize*16384); 560 for (i = 0; i < 16384; i++) 561 bzero(sc->mem_start, memsize); 562 printf("***DONE***\n"); 563#endif 564 565 /* 566 * Now zero memory and verify that it is clear 567 */ 568 bzero(sc->mem_start, memsize); 569 570 for (i = 0; i < memsize; ++i) { 571 if (sc->mem_start[i]) { 572 device_printf(dev, "failed to clear shared memory at %jx - check configuration\n", 573 (uintmax_t)kvtop(sc->mem_start + i)); 574 575 /* 576 * Disable 16 bit access to shared memory 577 */ 578 if (isa16bit) { 579 if (sc->chip_type == ED_CHIP_TYPE_WD790) { 580 ed_asic_outb(sc, ED_WD_MSR, 0x00); 581 } 582 ed_asic_outb(sc, ED_WD_LAAR, sc->wd_laar_proto & 583 ~ED_WD_LAAR_M16EN); 584 } 585 return (ENXIO); 586 } 587 } 588 589 /* 590 * Disable 16bit access to shared memory - we leave it 591 * disabled so that 1) machines reboot properly when the board 592 * is set 16 bit mode and there are conflicting 8bit 593 * devices/ROMS in the same 128k address space as this boards 594 * shared memory. and 2) so that other 8 bit devices with 595 * shared memory can be used in this 128k region, too. 596 */ 597 if (isa16bit) { 598 if (sc->chip_type == ED_CHIP_TYPE_WD790) { 599 ed_asic_outb(sc, ED_WD_MSR, 0x00); 600 } 601 ed_asic_outb(sc, ED_WD_LAAR, sc->wd_laar_proto & 602 ~ED_WD_LAAR_M16EN); 603 } 604 return (0); 605} 606 607int 608ed_probe_WD80x3(dev, port_rid, flags) 609 device_t dev; 610 int port_rid; 611 int flags; 612{ 613 struct ed_softc *sc = device_get_softc(dev); 614 int error; 615 static unsigned short *intr_vals[] = {ed_intr_val, ed_790_intr_val}; 616 617 error = ed_alloc_port(dev, port_rid, ED_WD_IO_PORTS); 618 if (error) 619 return (error); 620 621 sc->asic_offset = ED_WD_ASIC_OFFSET; 622 sc->nic_offset = ED_WD_NIC_OFFSET; 623 624 return ed_probe_WD80x3_generic(dev, flags, intr_vals); 625} 626 627/* 628 * Probe and vendor-specific initialization routine for 3Com 3c503 boards 629 */ 630int 631ed_probe_3Com(dev, port_rid, flags) 632 device_t dev; 633 int port_rid; 634 int flags; 635{ 636 struct ed_softc *sc = device_get_softc(dev); 637 int error; 638 int i; 639 u_int memsize; 640 u_char isa16bit; 641 u_long conf_maddr, conf_msize, irq, junk; 642 643 error = ed_alloc_port(dev, 0, ED_3COM_IO_PORTS); 644 if (error) 645 return (error); 646 647 sc->asic_offset = ED_3COM_ASIC_OFFSET; 648 sc->nic_offset = ED_3COM_NIC_OFFSET; 649 650 /* 651 * Verify that the kernel configured I/O address matches the board 652 * configured address 653 */ 654 switch (ed_asic_inb(sc, ED_3COM_BCFR)) { 655 case ED_3COM_BCFR_300: 656 if (rman_get_start(sc->port_res) != 0x300) 657 return (ENXIO); 658 break; 659 case ED_3COM_BCFR_310: 660 if (rman_get_start(sc->port_res) != 0x310) 661 return (ENXIO); 662 break; 663 case ED_3COM_BCFR_330: 664 if (rman_get_start(sc->port_res) != 0x330) 665 return (ENXIO); 666 break; 667 case ED_3COM_BCFR_350: 668 if (rman_get_start(sc->port_res) != 0x350) 669 return (ENXIO); 670 break; 671 case ED_3COM_BCFR_250: 672 if (rman_get_start(sc->port_res) != 0x250) 673 return (ENXIO); 674 break; 675 case ED_3COM_BCFR_280: 676 if (rman_get_start(sc->port_res) != 0x280) 677 return (ENXIO); 678 break; 679 case ED_3COM_BCFR_2A0: 680 if (rman_get_start(sc->port_res) != 0x2a0) 681 return (ENXIO); 682 break; 683 case ED_3COM_BCFR_2E0: 684 if (rman_get_start(sc->port_res) != 0x2e0) 685 return (ENXIO); 686 break; 687 default: 688 return (ENXIO); 689 } 690 691 error = bus_get_resource(dev, SYS_RES_MEMORY, 0, 692 &conf_maddr, &conf_msize); 693 if (error) 694 return (error); 695 696 /* 697 * Verify that the kernel shared memory address matches the board 698 * configured address. 699 */ 700 switch (ed_asic_inb(sc, ED_3COM_PCFR)) { 701 case ED_3COM_PCFR_DC000: 702 if (conf_maddr != 0xdc000) 703 return (ENXIO); 704 break; 705 case ED_3COM_PCFR_D8000: 706 if (conf_maddr != 0xd8000) 707 return (ENXIO); 708 break; 709 case ED_3COM_PCFR_CC000: 710 if (conf_maddr != 0xcc000) 711 return (ENXIO); 712 break; 713 case ED_3COM_PCFR_C8000: 714 if (conf_maddr != 0xc8000) 715 return (ENXIO); 716 break; 717 default: 718 return (ENXIO); 719 } 720 721 722 /* 723 * Reset NIC and ASIC. Enable on-board transceiver throughout reset 724 * sequence because it'll lock up if the cable isn't connected if we 725 * don't. 726 */ 727 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_RST | ED_3COM_CR_XSEL); 728 729 /* 730 * Wait for a while, then un-reset it 731 */ 732 DELAY(50); 733 734 /* 735 * The 3Com ASIC defaults to rather strange settings for the CR after 736 * a reset - it's important to set it again after the following outb 737 * (this is done when we map the PROM below). 738 */ 739 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_XSEL); 740 741 /* 742 * Wait a bit for the NIC to recover from the reset 743 */ 744 DELAY(5000); 745 746 sc->vendor = ED_VENDOR_3COM; 747 sc->type_str = "3c503"; 748 sc->mem_shared = 1; 749 sc->cr_proto = ED_CR_RD2; 750 751 /* 752 * Hmmm...a 16bit 3Com board has 16k of memory, but only an 8k window 753 * to it. 754 */ 755 memsize = 8192; 756 757 /* 758 * Get station address from on-board ROM 759 */ 760 761 /* 762 * First, map ethernet address PROM over the top of where the NIC 763 * registers normally appear. 764 */ 765 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_EALO | ED_3COM_CR_XSEL); 766 767 for (i = 0; i < ETHER_ADDR_LEN; ++i) 768 sc->arpcom.ac_enaddr[i] = ed_nic_inb(sc, i); 769 770 /* 771 * Unmap PROM - select NIC registers. The proper setting of the 772 * tranceiver is set in ed_init so that the attach code is given a 773 * chance to set the default based on a compile-time config option 774 */ 775 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_XSEL); 776 777 /* 778 * Determine if this is an 8bit or 16bit board 779 */ 780 781 /* 782 * select page 0 registers 783 */ 784 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STP); 785 786 /* 787 * Attempt to clear WTS bit. If it doesn't clear, then this is a 16bit 788 * board. 789 */ 790 ed_nic_outb(sc, ED_P0_DCR, 0); 791 792 /* 793 * select page 2 registers 794 */ 795 ed_nic_outb(sc, ED_P0_CR, ED_CR_PAGE_2 | ED_CR_RD2 | ED_CR_STP); 796 797 /* 798 * The 3c503 forces the WTS bit to a one if this is a 16bit board 799 */ 800 if (ed_nic_inb(sc, ED_P2_DCR) & ED_DCR_WTS) 801 isa16bit = 1; 802 else 803 isa16bit = 0; 804 805 /* 806 * select page 0 registers 807 */ 808 ed_nic_outb(sc, ED_P2_CR, ED_CR_RD2 | ED_CR_STP); 809 810 error = ed_alloc_memory(dev, 0, memsize); 811 if (error) 812 return (error); 813 814 sc->mem_start = (caddr_t) rman_get_virtual(sc->mem_res); 815 sc->mem_size = memsize; 816 sc->mem_end = sc->mem_start + memsize; 817 818 /* 819 * We have an entire 8k window to put the transmit buffers on the 820 * 16bit boards. But since the 16bit 3c503's shared memory is only 821 * fast enough to overlap the loading of one full-size packet, trying 822 * to load more than 2 buffers can actually leave the transmitter idle 823 * during the load. So 2 seems the best value. (Although a mix of 824 * variable-sized packets might change this assumption. Nonetheless, 825 * we optimize for linear transfers of same-size packets.) 826 */ 827 if (isa16bit) { 828 if (flags & ED_FLAGS_NO_MULTI_BUFFERING) 829 sc->txb_cnt = 1; 830 else 831 sc->txb_cnt = 2; 832 833 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_16BIT; 834 sc->rec_page_start = ED_3COM_RX_PAGE_OFFSET_16BIT; 835 sc->rec_page_stop = memsize / ED_PAGE_SIZE + 836 ED_3COM_RX_PAGE_OFFSET_16BIT; 837 sc->mem_ring = sc->mem_start; 838 } else { 839 sc->txb_cnt = 1; 840 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_8BIT; 841 sc->rec_page_start = ED_TXBUF_SIZE + ED_3COM_TX_PAGE_OFFSET_8BIT; 842 sc->rec_page_stop = memsize / ED_PAGE_SIZE + 843 ED_3COM_TX_PAGE_OFFSET_8BIT; 844 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * ED_TXBUF_SIZE); 845 } 846 847 sc->isa16bit = isa16bit; 848 849 /* 850 * Initialize GA page start/stop registers. Probably only needed if 851 * doing DMA, but what the hell. 852 */ 853 ed_asic_outb(sc, ED_3COM_PSTR, sc->rec_page_start); 854 ed_asic_outb(sc, ED_3COM_PSPR, sc->rec_page_stop); 855 856 /* 857 * Set IRQ. 3c503 only allows a choice of irq 2-5. 858 */ 859 error = bus_get_resource(dev, SYS_RES_IRQ, 0, &irq, &junk); 860 if (error) 861 return (error); 862 863 switch (irq) { 864 case 2: 865 case 9: 866 ed_asic_outb(sc, ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ2); 867 break; 868 case 3: 869 ed_asic_outb(sc, ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ3); 870 break; 871 case 4: 872 ed_asic_outb(sc, ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ4); 873 break; 874 case 5: 875 ed_asic_outb(sc, ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ5); 876 break; 877 default: 878 device_printf(dev, "Invalid irq configuration (%ld) must be 3-5,9 for 3c503\n", 879 irq); 880 return (ENXIO); 881 } 882 883 /* 884 * Initialize GA configuration register. Set bank and enable shared 885 * mem. 886 */ 887 ed_asic_outb(sc, ED_3COM_GACFR, ED_3COM_GACFR_RSEL | 888 ED_3COM_GACFR_MBS0); 889 890 /* 891 * Initialize "Vector Pointer" registers. These gawd-awful things are 892 * compared to 20 bits of the address on ISA, and if they match, the 893 * shared memory is disabled. We set them to 0xffff0...allegedly the 894 * reset vector. 895 */ 896 ed_asic_outb(sc, ED_3COM_VPTR2, 0xff); 897 ed_asic_outb(sc, ED_3COM_VPTR1, 0xff); 898 ed_asic_outb(sc, ED_3COM_VPTR0, 0x00); 899 900 /* 901 * Zero memory and verify that it is clear 902 */ 903 bzero(sc->mem_start, memsize); 904 905 for (i = 0; i < memsize; ++i) 906 if (sc->mem_start[i]) { 907 device_printf(dev, "failed to clear shared memory at %jx - check configuration\n", 908 (uintmax_t)kvtop(sc->mem_start + i)); 909 return (ENXIO); 910 } 911 return (0); 912} 913 914/* 915 * Probe and vendor-specific initialization routine for SIC boards 916 */ 917int 918ed_probe_SIC(dev, port_rid, flags) 919 device_t dev; 920 int port_rid; 921 int flags; 922{ 923 struct ed_softc *sc = device_get_softc(dev); 924 int error; 925 int i; 926 u_int memsize; 927 u_long conf_maddr, conf_msize; 928 u_char sum; 929 930 error = ed_alloc_port(dev, 0, ED_SIC_IO_PORTS); 931 if (error) 932 return (error); 933 934 sc->asic_offset = ED_SIC_ASIC_OFFSET; 935 sc->nic_offset = ED_SIC_NIC_OFFSET; 936 937 error = bus_get_resource(dev, SYS_RES_MEMORY, 0, 938 &conf_maddr, &conf_msize); 939 if (error) 940 return (error); 941 942 memsize = 16384; 943 if (conf_msize > 1) 944 memsize = conf_msize; 945 946 error = ed_alloc_memory(dev, 0, memsize); 947 if (error) 948 return (error); 949 950 sc->mem_start = (caddr_t) rman_get_virtual(sc->mem_res); 951 sc->mem_size = memsize; 952 953 /* Reset card to force it into a known state. */ 954 ed_asic_outb(sc, 0, 0x00); 955 DELAY(100); 956 957 /* 958 * Here we check the card ROM, if the checksum passes, and the 959 * type code and ethernet address check out, then we know we have 960 * an SIC card. 961 */ 962 ed_asic_outb(sc, 0, 0x81); 963 DELAY(100); 964 965 sum = sc->mem_start[6]; 966 for (i = 0; i < ETHER_ADDR_LEN; i++) { 967 sum ^= (sc->arpcom.ac_enaddr[i] = sc->mem_start[i]); 968 } 969#ifdef ED_DEBUG 970 device_printf(dev, "ed_probe_sic: got address %6D\n", 971 sc->arpcom.ac_enaddr, ":"); 972#endif 973 if (sum != 0) { 974 return (ENXIO); 975 } 976 if ((sc->arpcom.ac_enaddr[0] | sc->arpcom.ac_enaddr[1] | 977 sc->arpcom.ac_enaddr[2]) == 0) { 978 return (ENXIO); 979 } 980 981 sc->vendor = ED_VENDOR_SIC; 982 sc->type_str = "SIC"; 983 sc->isa16bit = 0; 984 sc->cr_proto = 0; 985 986 /* 987 * SIC RAM page 0x0000-0x3fff(or 0x7fff) 988 */ 989 ed_asic_outb(sc, 0, 0x80); 990 DELAY(100); 991 992 /* 993 * Now zero memory and verify that it is clear 994 */ 995 bzero(sc->mem_start, sc->mem_size); 996 997 for (i = 0; i < sc->mem_size; i++) { 998 if (sc->mem_start[i]) { 999 device_printf(dev, "failed to clear shared memory " 1000 "at %jx - check configuration\n", 1001 (uintmax_t)kvtop(sc->mem_start + i)); 1002 1003 return (ENXIO); 1004 } 1005 } 1006 1007 sc->mem_shared = 1; 1008 sc->mem_end = sc->mem_start + sc->mem_size; 1009 1010 /* 1011 * allocate one xmit buffer if < 16k, two buffers otherwise 1012 */ 1013 if ((sc->mem_size < 16384) || (flags & ED_FLAGS_NO_MULTI_BUFFERING)) { 1014 sc->txb_cnt = 1; 1015 } else { 1016 sc->txb_cnt = 2; 1017 } 1018 sc->tx_page_start = 0; 1019 1020 sc->rec_page_start = sc->tx_page_start + ED_TXBUF_SIZE * sc->txb_cnt; 1021 sc->rec_page_stop = sc->tx_page_start + sc->mem_size / ED_PAGE_SIZE; 1022 1023 sc->mem_ring = sc->mem_start + sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE; 1024 1025 return (0); 1026} 1027 1028/* 1029 * Probe and vendor-specific initialization routine for NE1000/2000 boards 1030 */ 1031int 1032ed_probe_Novell_generic(dev, flags) 1033 device_t dev; 1034 int flags; 1035{ 1036 struct ed_softc *sc = device_get_softc(dev); 1037 u_int memsize, n; 1038 u_char romdata[16], tmp; 1039 static char test_pattern[32] = "THIS is A memory TEST pattern"; 1040 char test_buffer[32]; 1041 1042 /* XXX - do Novell-specific probe here */ 1043 1044 /* Reset the board */ 1045 if (ED_FLAGS_GETTYPE(flags) == ED_FLAGS_GWETHER) { 1046 ed_asic_outb(sc, ED_NOVELL_RESET, 0); 1047 DELAY(200); 1048 } 1049 tmp = ed_asic_inb(sc, ED_NOVELL_RESET); 1050 1051 /* 1052 * I don't know if this is necessary; probably cruft leftover from 1053 * Clarkson packet driver code. Doesn't do a thing on the boards I've 1054 * tested. -DG [note that an outb(0x84, 0) seems to work here, and is 1055 * non-invasive...but some boards don't seem to reset and I don't have 1056 * complete documentation on what the 'right' thing to do is...so we 1057 * do the invasive thing for now. Yuck.] 1058 */ 1059 ed_asic_outb(sc, ED_NOVELL_RESET, tmp); 1060 DELAY(5000); 1061 1062 /* 1063 * This is needed because some NE clones apparently don't reset the 1064 * NIC properly (or the NIC chip doesn't reset fully on power-up) XXX 1065 * - this makes the probe invasive! ...Done against my better 1066 * judgement. -DLG 1067 */ 1068 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STP); 1069 1070 DELAY(5000); 1071 1072 /* Make sure that we really have an 8390 based board */ 1073 if (!ed_probe_generic8390(sc)) 1074 return (ENXIO); 1075 1076 sc->vendor = ED_VENDOR_NOVELL; 1077 sc->mem_shared = 0; 1078 sc->cr_proto = ED_CR_RD2; 1079 1080 /* 1081 * Test the ability to read and write to the NIC memory. This has the 1082 * side affect of determining if this is an NE1000 or an NE2000. 1083 */ 1084 1085 /* 1086 * This prevents packets from being stored in the NIC memory when the 1087 * readmem routine turns on the start bit in the CR. 1088 */ 1089 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_MON); 1090 1091 /* Temporarily initialize DCR for byte operations */ 1092 ed_nic_outb(sc, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS); 1093 1094 ed_nic_outb(sc, ED_P0_PSTART, 8192 / ED_PAGE_SIZE); 1095 ed_nic_outb(sc, ED_P0_PSTOP, 16384 / ED_PAGE_SIZE); 1096 1097 sc->isa16bit = 0; 1098 1099 /* 1100 * Write a test pattern in byte mode. If this fails, then there 1101 * probably isn't any memory at 8k - which likely means that the board 1102 * is an NE2000. 1103 */ 1104 ed_pio_writemem(sc, test_pattern, 8192, sizeof(test_pattern)); 1105 ed_pio_readmem(sc, 8192, test_buffer, sizeof(test_pattern)); 1106 1107 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern)) == 0) { 1108 sc->type = ED_TYPE_NE1000; 1109 sc->type_str = "NE1000"; 1110 } else { 1111 1112 /* neither an NE1000 nor a Linksys - try NE2000 */ 1113 ed_nic_outb(sc, ED_P0_DCR, ED_DCR_WTS | ED_DCR_FT1 | ED_DCR_LS); 1114 ed_nic_outb(sc, ED_P0_PSTART, 16384 / ED_PAGE_SIZE); 1115 ed_nic_outb(sc, ED_P0_PSTOP, 32768 / ED_PAGE_SIZE); 1116 1117 sc->isa16bit = 1; 1118 1119 /* 1120 * Write a test pattern in word mode. If this also fails, then 1121 * we don't know what this board is. 1122 */ 1123 ed_pio_writemem(sc, test_pattern, 16384, sizeof(test_pattern)); 1124 ed_pio_readmem(sc, 16384, test_buffer, sizeof(test_pattern)); 1125 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern)) == 0) { 1126 sc->type = ED_TYPE_NE2000; 1127 sc->type_str = "NE2000"; 1128 } else { 1129 return (ENXIO); 1130 } 1131 } 1132 1133 1134 /* 8k of memory plus an additional 8k if 16bit */ 1135 memsize = 8192 + sc->isa16bit * 8192; 1136 1137#if 0 /* probably not useful - NE boards only come two ways */ 1138 /* allow kernel config file overrides */ 1139 if (isa_dev->id_msize) 1140 memsize = isa_dev->id_msize; 1141#endif 1142 1143 sc->mem_size = memsize; 1144 1145 /* NIC memory doesn't start at zero on an NE board */ 1146 /* The start address is tied to the bus width */ 1147 sc->mem_start = (char *) 8192 + sc->isa16bit * 8192; 1148 sc->mem_end = sc->mem_start + memsize; 1149 sc->tx_page_start = memsize / ED_PAGE_SIZE; 1150 1151 if (ED_FLAGS_GETTYPE(flags) == ED_FLAGS_GWETHER) { 1152 int x, i, msize = 0; 1153 long mstart = 0; 1154 char pbuf0[ED_PAGE_SIZE], pbuf[ED_PAGE_SIZE], tbuf[ED_PAGE_SIZE]; 1155 1156 for (i = 0; i < ED_PAGE_SIZE; i++) 1157 pbuf0[i] = 0; 1158 1159 /* Clear all the memory. */ 1160 for (x = 1; x < 256; x++) 1161 ed_pio_writemem(sc, pbuf0, x * 256, ED_PAGE_SIZE); 1162 1163 /* Search for the start of RAM. */ 1164 for (x = 1; x < 256; x++) { 1165 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE); 1166 if (bcmp(pbuf0, tbuf, ED_PAGE_SIZE) == 0) { 1167 for (i = 0; i < ED_PAGE_SIZE; i++) 1168 pbuf[i] = 255 - x; 1169 ed_pio_writemem(sc, pbuf, x * 256, ED_PAGE_SIZE); 1170 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE); 1171 if (bcmp(pbuf, tbuf, ED_PAGE_SIZE) == 0) { 1172 mstart = x * ED_PAGE_SIZE; 1173 msize = ED_PAGE_SIZE; 1174 break; 1175 } 1176 } 1177 } 1178 1179 if (mstart == 0) { 1180 device_printf(dev, "Cannot find start of RAM.\n"); 1181 return (ENXIO); 1182 } 1183 /* Search for the start of RAM. */ 1184 for (x = (mstart / ED_PAGE_SIZE) + 1; x < 256; x++) { 1185 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE); 1186 if (bcmp(pbuf0, tbuf, ED_PAGE_SIZE) == 0) { 1187 for (i = 0; i < ED_PAGE_SIZE; i++) 1188 pbuf[i] = 255 - x; 1189 ed_pio_writemem(sc, pbuf, x * 256, ED_PAGE_SIZE); 1190 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE); 1191 if (bcmp(pbuf, tbuf, ED_PAGE_SIZE) == 0) 1192 msize += ED_PAGE_SIZE; 1193 else { 1194 break; 1195 } 1196 } else { 1197 break; 1198 } 1199 } 1200 1201 if (msize == 0) { 1202 device_printf(dev, "Cannot find any RAM, start : %ld, x = %d.\n", mstart, x); 1203 return (ENXIO); 1204 } 1205 device_printf(dev, "RAM start at %ld, size : %d.\n", mstart, msize); 1206 1207 sc->mem_size = msize; 1208 sc->mem_start = (caddr_t) mstart; 1209 sc->mem_end = (caddr_t) (msize + mstart); 1210 sc->tx_page_start = mstart / ED_PAGE_SIZE; 1211 } 1212 1213 /* 1214 * Use one xmit buffer if < 16k, two buffers otherwise (if not told 1215 * otherwise). 1216 */ 1217 if ((memsize < 16384) || (flags & ED_FLAGS_NO_MULTI_BUFFERING)) 1218 sc->txb_cnt = 1; 1219 else 1220 sc->txb_cnt = 2; 1221 1222 sc->rec_page_start = sc->tx_page_start + sc->txb_cnt * ED_TXBUF_SIZE; 1223 sc->rec_page_stop = sc->tx_page_start + memsize / ED_PAGE_SIZE; 1224 1225 sc->mem_ring = sc->mem_start + sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE; 1226 1227 ed_pio_readmem(sc, 0, romdata, 16); 1228 for (n = 0; n < ETHER_ADDR_LEN; n++) 1229 sc->arpcom.ac_enaddr[n] = romdata[n * (sc->isa16bit + 1)]; 1230 1231 if ((ED_FLAGS_GETTYPE(flags) == ED_FLAGS_GWETHER) && 1232 (sc->arpcom.ac_enaddr[2] == 0x86)) { 1233 sc->type_str = "Gateway AT"; 1234 } 1235 1236 /* clear any pending interrupts that might have occurred above */ 1237 ed_nic_outb(sc, ED_P0_ISR, 0xff); 1238 1239 return (0); 1240} 1241 1242int 1243ed_probe_Novell(dev, port_rid, flags) 1244 device_t dev; 1245 int port_rid; 1246 int flags; 1247{ 1248 struct ed_softc *sc = device_get_softc(dev); 1249 int error; 1250 1251 error = ed_alloc_port(dev, port_rid, ED_NOVELL_IO_PORTS); 1252 if (error) 1253 return (error); 1254 1255 sc->asic_offset = ED_NOVELL_ASIC_OFFSET; 1256 sc->nic_offset = ED_NOVELL_NIC_OFFSET; 1257 1258 return ed_probe_Novell_generic(dev, flags); 1259} 1260 1261#define ED_HPP_TEST_SIZE 16 1262 1263/* 1264 * Probe and vendor specific initialization for the HP PC Lan+ Cards. 1265 * (HP Part nos: 27247B and 27252A). 1266 * 1267 * The card has an asic wrapper around a DS8390 core. The asic handles 1268 * host accesses and offers both standard register IO and memory mapped 1269 * IO. Memory mapped I/O allows better performance at the expense of greater 1270 * chance of an incompatibility with existing ISA cards. 1271 * 1272 * The card has a few caveats: it isn't tolerant of byte wide accesses, only 1273 * short (16 bit) or word (32 bit) accesses are allowed. Some card revisions 1274 * don't allow 32 bit accesses; these are indicated by a bit in the software 1275 * ID register (see if_edreg.h). 1276 * 1277 * Other caveats are: we should read the MAC address only when the card 1278 * is inactive. 1279 * 1280 * For more information; please consult the CRYNWR packet driver. 1281 * 1282 * The AUI port is turned on using the "link2" option on the ifconfig 1283 * command line. 1284 */ 1285int 1286ed_probe_HP_pclanp(dev, port_rid, flags) 1287 device_t dev; 1288 int port_rid; 1289 int flags; 1290{ 1291 struct ed_softc *sc = device_get_softc(dev); 1292 int error; 1293 int n; /* temp var */ 1294 int memsize; /* mem on board */ 1295 u_char checksum; /* checksum of board address */ 1296 u_char irq; /* board configured IRQ */ 1297 char test_pattern[ED_HPP_TEST_SIZE]; /* read/write areas for */ 1298 char test_buffer[ED_HPP_TEST_SIZE]; /* probing card */ 1299 u_long conf_maddr, conf_msize, conf_irq, junk; 1300 1301 error = ed_alloc_port(dev, 0, ED_HPP_IO_PORTS); 1302 if (error) 1303 return (error); 1304 1305 /* Fill in basic information */ 1306 sc->asic_offset = ED_HPP_ASIC_OFFSET; 1307 sc->nic_offset = ED_HPP_NIC_OFFSET; 1308 1309 sc->chip_type = ED_CHIP_TYPE_DP8390; 1310 sc->isa16bit = 0; /* the 8390 core needs to be in byte mode */ 1311 1312 /* 1313 * Look for the HP PCLAN+ signature: "0x50,0x48,0x00,0x53" 1314 */ 1315 1316 if ((ed_asic_inb(sc, ED_HPP_ID) != 0x50) || 1317 (ed_asic_inb(sc, ED_HPP_ID + 1) != 0x48) || 1318 ((ed_asic_inb(sc, ED_HPP_ID + 2) & 0xF0) != 0) || 1319 (ed_asic_inb(sc, ED_HPP_ID + 3) != 0x53)) 1320 return ENXIO; 1321 1322 /* 1323 * Read the MAC address and verify checksum on the address. 1324 */ 1325 1326 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_MAC); 1327 for (n = 0, checksum = 0; n < ETHER_ADDR_LEN; n++) 1328 checksum += (sc->arpcom.ac_enaddr[n] = 1329 ed_asic_inb(sc, ED_HPP_MAC_ADDR + n)); 1330 1331 checksum += ed_asic_inb(sc, ED_HPP_MAC_ADDR + ETHER_ADDR_LEN); 1332 1333 if (checksum != 0xFF) 1334 return ENXIO; 1335 1336 /* 1337 * Verify that the software model number is 0. 1338 */ 1339 1340 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_ID); 1341 if (((sc->hpp_id = ed_asic_inw(sc, ED_HPP_PAGE_4)) & 1342 ED_HPP_ID_SOFT_MODEL_MASK) != 0x0000) 1343 return ENXIO; 1344 1345 /* 1346 * Read in and save the current options configured on card. 1347 */ 1348 1349 sc->hpp_options = ed_asic_inw(sc, ED_HPP_OPTION); 1350 1351 sc->hpp_options |= (ED_HPP_OPTION_NIC_RESET | 1352 ED_HPP_OPTION_CHIP_RESET | 1353 ED_HPP_OPTION_ENABLE_IRQ); 1354 1355 /* 1356 * Reset the chip. This requires writing to the option register 1357 * so take care to preserve the other bits. 1358 */ 1359 1360 ed_asic_outw(sc, ED_HPP_OPTION, 1361 (sc->hpp_options & ~(ED_HPP_OPTION_NIC_RESET | 1362 ED_HPP_OPTION_CHIP_RESET))); 1363 1364 DELAY(5000); /* wait for chip reset to complete */ 1365 1366 ed_asic_outw(sc, ED_HPP_OPTION, 1367 (sc->hpp_options | (ED_HPP_OPTION_NIC_RESET | 1368 ED_HPP_OPTION_CHIP_RESET | 1369 ED_HPP_OPTION_ENABLE_IRQ))); 1370 1371 DELAY(5000); 1372 1373 if (!(ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RST)) 1374 return ENXIO; /* reset did not complete */ 1375 1376 /* 1377 * Read out configuration information. 1378 */ 1379 1380 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_HW); 1381 1382 irq = ed_asic_inb(sc, ED_HPP_HW_IRQ); 1383 1384 /* 1385 * Check for impossible IRQ. 1386 */ 1387 1388 if (irq >= (sizeof(ed_hpp_intr_val) / sizeof(ed_hpp_intr_val[0]))) 1389 return ENXIO; 1390 1391 /* 1392 * If the kernel IRQ was specified with a '?' use the cards idea 1393 * of the IRQ. If the kernel IRQ was explicitly specified, it 1394 * should match that of the hardware. 1395 */ 1396 error = bus_get_resource(dev, SYS_RES_IRQ, 0, 1397 &conf_irq, &junk); 1398 if (error) { 1399 bus_set_resource(dev, SYS_RES_IRQ, 0, 1400 ed_hpp_intr_val[irq], 1); 1401 } else { 1402 if (conf_irq != ed_hpp_intr_val[irq]) 1403 return (ENXIO); 1404 } 1405 1406 /* 1407 * Fill in softconfig info. 1408 */ 1409 1410 sc->vendor = ED_VENDOR_HP; 1411 sc->type = ED_TYPE_HP_PCLANPLUS; 1412 sc->type_str = "HP-PCLAN+"; 1413 1414 sc->mem_shared = 0; /* we DON'T have dual ported RAM */ 1415 sc->mem_start = 0; /* we use offsets inside the card RAM */ 1416 1417 sc->hpp_mem_start = NULL;/* no memory mapped I/O by default */ 1418 1419 /* 1420 * The board has 32KB of memory. Is there a way to determine 1421 * this programmatically? 1422 */ 1423 1424 memsize = 32768; 1425 1426 /* 1427 * Check if memory mapping of the I/O registers possible. 1428 */ 1429 1430 if (sc->hpp_options & ED_HPP_OPTION_MEM_ENABLE) 1431 { 1432 u_long mem_addr; 1433 1434 /* 1435 * determine the memory address from the board. 1436 */ 1437 1438 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_HW); 1439 mem_addr = (ed_asic_inw(sc, ED_HPP_HW_MEM_MAP) << 8); 1440 1441 /* 1442 * Check that the kernel specified start of memory and 1443 * hardware's idea of it match. 1444 */ 1445 error = bus_get_resource(dev, SYS_RES_MEMORY, 0, 1446 &conf_maddr, &conf_msize); 1447 if (error) 1448 return (error); 1449 1450 if (mem_addr != conf_maddr) 1451 return ENXIO; 1452 1453 error = ed_alloc_memory(dev, 0, memsize); 1454 if (error) 1455 return (error); 1456 1457 sc->hpp_mem_start = rman_get_virtual(sc->mem_res); 1458 } 1459 1460 /* 1461 * Fill in the rest of the soft config structure. 1462 */ 1463 1464 /* 1465 * The transmit page index. 1466 */ 1467 1468 sc->tx_page_start = ED_HPP_TX_PAGE_OFFSET; 1469 1470 if (device_get_flags(dev) & ED_FLAGS_NO_MULTI_BUFFERING) 1471 sc->txb_cnt = 1; 1472 else 1473 sc->txb_cnt = 2; 1474 1475 /* 1476 * Memory description 1477 */ 1478 1479 sc->mem_size = memsize; 1480 sc->mem_ring = sc->mem_start + 1481 (sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE); 1482 sc->mem_end = sc->mem_start + sc->mem_size; 1483 1484 /* 1485 * Receive area starts after the transmit area and 1486 * continues till the end of memory. 1487 */ 1488 1489 sc->rec_page_start = sc->tx_page_start + 1490 (sc->txb_cnt * ED_TXBUF_SIZE); 1491 sc->rec_page_stop = (sc->mem_size / ED_PAGE_SIZE); 1492 1493 1494 sc->cr_proto = 0; /* value works */ 1495 1496 /* 1497 * Set the wrap registers for string I/O reads. 1498 */ 1499 1500 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_HW); 1501 ed_asic_outw(sc, ED_HPP_HW_WRAP, 1502 ((sc->rec_page_start / ED_PAGE_SIZE) | 1503 (((sc->rec_page_stop / ED_PAGE_SIZE) - 1) << 8))); 1504 1505 /* 1506 * Reset the register page to normal operation. 1507 */ 1508 1509 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_PERF); 1510 1511 /* 1512 * Verify that we can read/write from adapter memory. 1513 * Create test pattern. 1514 */ 1515 1516 for (n = 0; n < ED_HPP_TEST_SIZE; n++) 1517 { 1518 test_pattern[n] = (n*n) ^ ~n; 1519 } 1520 1521#undef ED_HPP_TEST_SIZE 1522 1523 /* 1524 * Check that the memory is accessible thru the I/O ports. 1525 * Write out the contents of "test_pattern", read back 1526 * into "test_buffer" and compare the two for any 1527 * mismatch. 1528 */ 1529 1530 for (n = 0; n < (32768 / ED_PAGE_SIZE); n ++) { 1531 1532 ed_hpp_writemem(sc, test_pattern, (n * ED_PAGE_SIZE), 1533 sizeof(test_pattern)); 1534 ed_hpp_readmem(sc, (n * ED_PAGE_SIZE), 1535 test_buffer, sizeof(test_pattern)); 1536 1537 if (bcmp(test_pattern, test_buffer, 1538 sizeof(test_pattern))) 1539 return ENXIO; 1540 } 1541 1542 return (0); 1543 1544} 1545 1546/* 1547 * HP PC Lan+ : Set the physical link to use AUI or TP/TL. 1548 */ 1549 1550static void 1551ed_hpp_set_physical_link(struct ed_softc *sc) 1552{ 1553 struct ifnet *ifp = &sc->arpcom.ac_if; 1554 int lan_page; 1555 1556 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_LAN); 1557 lan_page = ed_asic_inw(sc, ED_HPP_PAGE_0); 1558 1559 if (ifp->if_flags & IFF_ALTPHYS) { 1560 1561 /* 1562 * Use the AUI port. 1563 */ 1564 1565 lan_page |= ED_HPP_LAN_AUI; 1566 1567 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_LAN); 1568 ed_asic_outw(sc, ED_HPP_PAGE_0, lan_page); 1569 1570 1571 } else { 1572 1573 /* 1574 * Use the ThinLan interface 1575 */ 1576 1577 lan_page &= ~ED_HPP_LAN_AUI; 1578 1579 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_LAN); 1580 ed_asic_outw(sc, ED_HPP_PAGE_0, lan_page); 1581 1582 } 1583 1584 /* 1585 * Wait for the lan card to re-initialize itself 1586 */ 1587 1588 DELAY(150000); /* wait 150 ms */ 1589 1590 /* 1591 * Restore normal pages. 1592 */ 1593 1594 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_PERF); 1595 1596} 1597 1598/* 1599 * Allocate a port resource with the given resource id. 1600 */ 1601int 1602ed_alloc_port(dev, rid, size) 1603 device_t dev; 1604 int rid; 1605 int size; 1606{ 1607 struct ed_softc *sc = device_get_softc(dev); 1608 struct resource *res; 1609 1610 res = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 1611 0ul, ~0ul, size, RF_ACTIVE); 1612 if (res) { 1613 sc->port_rid = rid; 1614 sc->port_res = res; 1615 sc->port_used = size; 1616 return (0); 1617 } else { 1618 return (ENOENT); 1619 } 1620} 1621 1622/* 1623 * Allocate a memory resource with the given resource id. 1624 */ 1625int 1626ed_alloc_memory(dev, rid, size) 1627 device_t dev; 1628 int rid; 1629 int size; 1630{ 1631 struct ed_softc *sc = device_get_softc(dev); 1632 struct resource *res; 1633 1634 res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 1635 0ul, ~0ul, size, RF_ACTIVE); 1636 if (res) { 1637 sc->mem_rid = rid; 1638 sc->mem_res = res; 1639 sc->mem_used = size; 1640 return (0); 1641 } else { 1642 return (ENOENT); 1643 } 1644} 1645 1646/* 1647 * Allocate an irq resource with the given resource id. 1648 */ 1649int 1650ed_alloc_irq(dev, rid, flags) 1651 device_t dev; 1652 int rid; 1653 int flags; 1654{ 1655 struct ed_softc *sc = device_get_softc(dev); 1656 struct resource *res; 1657 1658 res = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 1659 0ul, ~0ul, 1, (RF_ACTIVE | flags)); 1660 if (res) { 1661 sc->irq_rid = rid; 1662 sc->irq_res = res; 1663 return (0); 1664 } else { 1665 return (ENOENT); 1666 } 1667} 1668 1669/* 1670 * Release all resources 1671 */ 1672void 1673ed_release_resources(dev) 1674 device_t dev; 1675{ 1676 struct ed_softc *sc = device_get_softc(dev); 1677 1678 if (sc->port_res) { 1679 bus_deactivate_resource(dev, SYS_RES_IOPORT, 1680 sc->port_rid, sc->port_res); 1681 bus_release_resource(dev, SYS_RES_IOPORT, 1682 sc->port_rid, sc->port_res); 1683 sc->port_res = 0; 1684 } 1685 if (sc->mem_res) { 1686 bus_deactivate_resource(dev, SYS_RES_MEMORY, 1687 sc->mem_rid, sc->mem_res); 1688 bus_release_resource(dev, SYS_RES_MEMORY, 1689 sc->mem_rid, sc->mem_res); 1690 sc->mem_res = 0; 1691 } 1692 if (sc->irq_res) { 1693 bus_deactivate_resource(dev, SYS_RES_IRQ, 1694 sc->irq_rid, sc->irq_res); 1695 bus_release_resource(dev, SYS_RES_IRQ, 1696 sc->irq_rid, sc->irq_res); 1697 sc->irq_res = 0; 1698 } 1699} 1700 1701/* 1702 * Install interface into kernel networking data structures 1703 */ 1704int 1705ed_attach(dev) 1706 device_t dev; 1707{ 1708 struct ed_softc *sc = device_get_softc(dev); 1709 struct ifnet *ifp = &sc->arpcom.ac_if; 1710 1711 callout_handle_init(&sc->tick_ch); 1712 /* 1713 * Set interface to stopped condition (reset) 1714 */ 1715 ed_stop(sc); 1716 1717 /* 1718 * Initialize ifnet structure 1719 */ 1720 ifp->if_softc = sc; 1721 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1722 ifp->if_output = ether_output; 1723 ifp->if_start = ed_start; 1724 ifp->if_ioctl = ed_ioctl; 1725 ifp->if_watchdog = ed_watchdog; 1726 ifp->if_init = ed_init; 1727 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 1728 ifp->if_linkmib = &sc->mibdata; 1729 ifp->if_linkmiblen = sizeof sc->mibdata; 1730 /* 1731 * XXX - should do a better job. 1732 */ 1733 if (sc->chip_type == ED_CHIP_TYPE_WD790) 1734 sc->mibdata.dot3StatsEtherChipSet = 1735 DOT3CHIPSET(dot3VendorWesternDigital, 1736 dot3ChipSetWesternDigital83C790); 1737 else 1738 sc->mibdata.dot3StatsEtherChipSet = 1739 DOT3CHIPSET(dot3VendorNational, 1740 dot3ChipSetNational8390); 1741 sc->mibdata.dot3Compliance = DOT3COMPLIANCE_COLLS; 1742 1743 /* 1744 * Set default state for ALTPHYS flag (used to disable the 1745 * tranceiver for AUI operation), based on compile-time 1746 * config option. 1747 */ 1748 if (device_get_flags(dev) & ED_FLAGS_DISABLE_TRANCEIVER) 1749 ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX | 1750 IFF_MULTICAST | IFF_ALTPHYS); 1751 else 1752 ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX | 1753 IFF_MULTICAST); 1754 1755 /* 1756 * Attach the interface 1757 */ 1758 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 1759 /* device attach does transition from UNCONFIGURED to IDLE state */ 1760 1761 /* 1762 * Print additional info when attached 1763 */ 1764 if_printf(ifp, "address %6D, ", sc->arpcom.ac_enaddr, ":"); 1765 1766 if (sc->type_str && (*sc->type_str != 0)) 1767 printf("type %s ", sc->type_str); 1768 else 1769 printf("type unknown (0x%x) ", sc->type); 1770 1771 if (sc->vendor == ED_VENDOR_HP) 1772 printf("(%s %s IO)", (sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS) ? 1773 "16-bit" : "32-bit", 1774 sc->hpp_mem_start ? "memory mapped" : "regular"); 1775 else 1776 printf("%s ", sc->isa16bit ? "(16 bit)" : "(8 bit)"); 1777 1778 printf("%s\n", (((sc->vendor == ED_VENDOR_3COM) || 1779 (sc->vendor == ED_VENDOR_HP)) && 1780 (ifp->if_flags & IFF_ALTPHYS)) ? " tranceiver disabled" : ""); 1781 1782 return (0); 1783} 1784 1785/* 1786 * Reset interface. 1787 */ 1788static void 1789ed_reset(ifp) 1790 struct ifnet *ifp; 1791{ 1792 struct ed_softc *sc = ifp->if_softc; 1793 int s; 1794 1795 if (sc->gone) 1796 return; 1797 s = splimp(); 1798 1799 /* 1800 * Stop interface and re-initialize. 1801 */ 1802 ed_stop(sc); 1803 ed_init(sc); 1804 1805 (void) splx(s); 1806} 1807 1808/* 1809 * Take interface offline. 1810 */ 1811void 1812ed_stop(sc) 1813 struct ed_softc *sc; 1814{ 1815 int n = 5000; 1816 1817#ifndef ED_NO_MIIBUS 1818 untimeout(ed_tick, sc, sc->tick_ch); 1819 callout_handle_init(&sc->tick_ch); 1820#endif 1821 if (sc->gone) 1822 return; 1823 /* 1824 * Stop everything on the interface, and select page 0 registers. 1825 */ 1826 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP); 1827 1828 /* 1829 * Wait for interface to enter stopped state, but limit # of checks to 1830 * 'n' (about 5ms). It shouldn't even take 5us on modern DS8390's, but 1831 * just in case it's an old one. 1832 */ 1833 if (sc->chip_type != ED_CHIP_TYPE_AX88190) 1834 while (((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RST) == 0) && --n); 1835} 1836 1837/* 1838 * Device timeout/watchdog routine. Entered if the device neglects to 1839 * generate an interrupt after a transmit has been started on it. 1840 */ 1841static void 1842ed_watchdog(ifp) 1843 struct ifnet *ifp; 1844{ 1845 struct ed_softc *sc = ifp->if_softc; 1846 1847 if (sc->gone) 1848 return; 1849 log(LOG_ERR, "%s: device timeout\n", ifp->if_xname); 1850 ifp->if_oerrors++; 1851 1852 ed_reset(ifp); 1853} 1854 1855#ifndef ED_NO_MIIBUS 1856static void 1857ed_tick(arg) 1858 void *arg; 1859{ 1860 struct ed_softc *sc = arg; 1861 struct mii_data *mii; 1862 int s; 1863 1864 if (sc->gone) { 1865 callout_handle_init(&sc->tick_ch); 1866 return; 1867 } 1868 s = splimp(); 1869 if (sc->miibus != NULL) { 1870 mii = device_get_softc(sc->miibus); 1871 mii_tick(mii); 1872 } 1873 sc->tick_ch = timeout(ed_tick, sc, hz); 1874 splx(s); 1875} 1876#endif 1877 1878/* 1879 * Initialize device. 1880 */ 1881static void 1882ed_init(xsc) 1883 void *xsc; 1884{ 1885 struct ed_softc *sc = xsc; 1886 struct ifnet *ifp = &sc->arpcom.ac_if; 1887 int i, s; 1888 1889 if (sc->gone) 1890 return; 1891 1892 /* address not known */ 1893 if (TAILQ_EMPTY(&ifp->if_addrhead)) /* unlikely? XXX */ 1894 return; 1895 1896 /* 1897 * Initialize the NIC in the exact order outlined in the NS manual. 1898 * This init procedure is "mandatory"...don't change what or when 1899 * things happen. 1900 */ 1901 s = splimp(); 1902 1903 /* reset transmitter flags */ 1904 sc->xmit_busy = 0; 1905 ifp->if_timer = 0; 1906 1907 sc->txb_inuse = 0; 1908 sc->txb_new = 0; 1909 sc->txb_next_tx = 0; 1910 1911 /* This variable is used below - don't move this assignment */ 1912 sc->next_packet = sc->rec_page_start + 1; 1913 1914 /* 1915 * Set interface for page 0, Remote DMA complete, Stopped 1916 */ 1917 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP); 1918 1919 if (sc->isa16bit) { 1920 1921 /* 1922 * Set FIFO threshold to 8, No auto-init Remote DMA, byte 1923 * order=80x86, word-wide DMA xfers, 1924 */ 1925 ed_nic_outb(sc, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_WTS | ED_DCR_LS); 1926 } else { 1927 1928 /* 1929 * Same as above, but byte-wide DMA xfers 1930 */ 1931 ed_nic_outb(sc, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS); 1932 } 1933 1934 /* 1935 * Clear Remote Byte Count Registers 1936 */ 1937 ed_nic_outb(sc, ED_P0_RBCR0, 0); 1938 ed_nic_outb(sc, ED_P0_RBCR1, 0); 1939 1940 /* 1941 * For the moment, don't store incoming packets in memory. 1942 */ 1943 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_MON); 1944 1945 /* 1946 * Place NIC in internal loopback mode 1947 */ 1948 ed_nic_outb(sc, ED_P0_TCR, ED_TCR_LB0); 1949 1950 /* 1951 * Initialize transmit/receive (ring-buffer) Page Start 1952 */ 1953 ed_nic_outb(sc, ED_P0_TPSR, sc->tx_page_start); 1954 ed_nic_outb(sc, ED_P0_PSTART, sc->rec_page_start); 1955 /* Set lower bits of byte addressable framing to 0 */ 1956 if (sc->chip_type == ED_CHIP_TYPE_WD790) 1957 ed_nic_outb(sc, 0x09, 0); 1958 1959 /* 1960 * Initialize Receiver (ring-buffer) Page Stop and Boundry 1961 */ 1962 ed_nic_outb(sc, ED_P0_PSTOP, sc->rec_page_stop); 1963 ed_nic_outb(sc, ED_P0_BNRY, sc->rec_page_start); 1964 1965 /* 1966 * Clear all interrupts. A '1' in each bit position clears the 1967 * corresponding flag. 1968 */ 1969 ed_nic_outb(sc, ED_P0_ISR, 0xff); 1970 1971 /* 1972 * Enable the following interrupts: receive/transmit complete, 1973 * receive/transmit error, and Receiver OverWrite. 1974 * 1975 * Counter overflow and Remote DMA complete are *not* enabled. 1976 */ 1977 ed_nic_outb(sc, ED_P0_IMR, 1978 ED_IMR_PRXE | ED_IMR_PTXE | ED_IMR_RXEE | ED_IMR_TXEE | ED_IMR_OVWE); 1979 1980 /* 1981 * Program Command Register for page 1 1982 */ 1983 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP); 1984 1985 /* 1986 * Copy out our station address 1987 */ 1988 for (i = 0; i < ETHER_ADDR_LEN; ++i) 1989 ed_nic_outb(sc, ED_P1_PAR(i), sc->arpcom.ac_enaddr[i]); 1990 1991 /* 1992 * Set Current Page pointer to next_packet (initialized above) 1993 */ 1994 ed_nic_outb(sc, ED_P1_CURR, sc->next_packet); 1995 1996 /* 1997 * Program Receiver Configuration Register and multicast filter. CR is 1998 * set to page 0 on return. 1999 */ 2000 ed_setrcr(sc); 2001 2002 /* 2003 * Take interface out of loopback 2004 */ 2005 ed_nic_outb(sc, ED_P0_TCR, 0); 2006 2007 /* 2008 * If this is a 3Com board, the tranceiver must be software enabled 2009 * (there is no settable hardware default). 2010 */ 2011 if (sc->vendor == ED_VENDOR_3COM) { 2012 if (ifp->if_flags & IFF_ALTPHYS) { 2013 ed_asic_outb(sc, ED_3COM_CR, 0); 2014 } else { 2015 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_XSEL); 2016 } 2017 } 2018 2019#ifndef ED_NO_MIIBUS 2020 if (sc->miibus != NULL) { 2021 struct mii_data *mii; 2022 mii = device_get_softc(sc->miibus); 2023 mii_mediachg(mii); 2024 } 2025#endif 2026 /* 2027 * Set 'running' flag, and clear output active flag. 2028 */ 2029 ifp->if_flags |= IFF_RUNNING; 2030 ifp->if_flags &= ~IFF_OACTIVE; 2031 2032 /* 2033 * ...and attempt to start output 2034 */ 2035 ed_start(ifp); 2036 2037#ifndef ED_NO_MIIBUS 2038 untimeout(ed_tick, sc, sc->tick_ch); 2039 sc->tick_ch = timeout(ed_tick, sc, hz); 2040#endif 2041 (void) splx(s); 2042} 2043 2044/* 2045 * This routine actually starts the transmission on the interface 2046 */ 2047static __inline void 2048ed_xmit(sc) 2049 struct ed_softc *sc; 2050{ 2051 struct ifnet *ifp = (struct ifnet *)sc; 2052 unsigned short len; 2053 2054 if (sc->gone) 2055 return; 2056 len = sc->txb_len[sc->txb_next_tx]; 2057 2058 /* 2059 * Set NIC for page 0 register access 2060 */ 2061 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA); 2062 2063 /* 2064 * Set TX buffer start page 2065 */ 2066 ed_nic_outb(sc, ED_P0_TPSR, sc->tx_page_start + 2067 sc->txb_next_tx * ED_TXBUF_SIZE); 2068 2069 /* 2070 * Set TX length 2071 */ 2072 ed_nic_outb(sc, ED_P0_TBCR0, len); 2073 ed_nic_outb(sc, ED_P0_TBCR1, len >> 8); 2074 2075 /* 2076 * Set page 0, Remote DMA complete, Transmit Packet, and *Start* 2077 */ 2078 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_TXP | ED_CR_STA); 2079 sc->xmit_busy = 1; 2080 2081 /* 2082 * Point to next transmit buffer slot and wrap if necessary. 2083 */ 2084 sc->txb_next_tx++; 2085 if (sc->txb_next_tx == sc->txb_cnt) 2086 sc->txb_next_tx = 0; 2087 2088 /* 2089 * Set a timer just in case we never hear from the board again 2090 */ 2091 ifp->if_timer = 2; 2092} 2093 2094/* 2095 * Start output on interface. 2096 * We make two assumptions here: 2097 * 1) that the current priority is set to splimp _before_ this code 2098 * is called *and* is returned to the appropriate priority after 2099 * return 2100 * 2) that the IFF_OACTIVE flag is checked before this code is called 2101 * (i.e. that the output part of the interface is idle) 2102 */ 2103static void 2104ed_start(ifp) 2105 struct ifnet *ifp; 2106{ 2107 struct ed_softc *sc = ifp->if_softc; 2108 struct mbuf *m0, *m; 2109 caddr_t buffer; 2110 int len; 2111 2112 if (sc->gone) { 2113 printf("ed_start(%p) GONE\n",ifp); 2114 return; 2115 } 2116outloop: 2117 2118 /* 2119 * First, see if there are buffered packets and an idle transmitter - 2120 * should never happen at this point. 2121 */ 2122 if (sc->txb_inuse && (sc->xmit_busy == 0)) { 2123 printf("ed: packets buffered, but transmitter idle\n"); 2124 ed_xmit(sc); 2125 } 2126 2127 /* 2128 * See if there is room to put another packet in the buffer. 2129 */ 2130 if (sc->txb_inuse == sc->txb_cnt) { 2131 2132 /* 2133 * No room. Indicate this to the outside world and exit. 2134 */ 2135 ifp->if_flags |= IFF_OACTIVE; 2136 return; 2137 } 2138 IF_DEQUEUE(&ifp->if_snd, m); 2139 if (m == 0) { 2140 2141 /* 2142 * We are using the !OACTIVE flag to indicate to the outside 2143 * world that we can accept an additional packet rather than 2144 * that the transmitter is _actually_ active. Indeed, the 2145 * transmitter may be active, but if we haven't filled all the 2146 * buffers with data then we still want to accept more. 2147 */ 2148 ifp->if_flags &= ~IFF_OACTIVE; 2149 return; 2150 } 2151 2152 /* 2153 * Copy the mbuf chain into the transmit buffer 2154 */ 2155 2156 m0 = m; 2157 2158 /* txb_new points to next open buffer slot */ 2159 buffer = sc->mem_start + (sc->txb_new * ED_TXBUF_SIZE * ED_PAGE_SIZE); 2160 2161 if (sc->mem_shared) { 2162 2163 /* 2164 * Special case setup for 16 bit boards... 2165 */ 2166 if (sc->isa16bit) { 2167 switch (sc->vendor) { 2168 2169 /* 2170 * For 16bit 3Com boards (which have 16k of 2171 * memory), we have the xmit buffers in a 2172 * different page of memory ('page 0') - so 2173 * change pages. 2174 */ 2175 case ED_VENDOR_3COM: 2176 ed_asic_outb(sc, ED_3COM_GACFR, 2177 ED_3COM_GACFR_RSEL); 2178 break; 2179 2180 /* 2181 * Enable 16bit access to shared memory on 2182 * WD/SMC boards. 2183 */ 2184 case ED_VENDOR_WD_SMC: 2185 ed_asic_outb(sc, ED_WD_LAAR, 2186 sc->wd_laar_proto | ED_WD_LAAR_M16EN); 2187 if (sc->chip_type == ED_CHIP_TYPE_WD790) { 2188 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_MENB); 2189 } 2190 break; 2191 } 2192 } 2193 for (len = 0; m != 0; m = m->m_next) { 2194 bcopy(mtod(m, caddr_t), buffer, m->m_len); 2195 buffer += m->m_len; 2196 len += m->m_len; 2197 } 2198 2199 /* 2200 * Restore previous shared memory access 2201 */ 2202 if (sc->isa16bit) { 2203 switch (sc->vendor) { 2204 case ED_VENDOR_3COM: 2205 ed_asic_outb(sc, ED_3COM_GACFR, 2206 ED_3COM_GACFR_RSEL | ED_3COM_GACFR_MBS0); 2207 break; 2208 case ED_VENDOR_WD_SMC: 2209 if (sc->chip_type == ED_CHIP_TYPE_WD790) { 2210 ed_asic_outb(sc, ED_WD_MSR, 0x00); 2211 } 2212 ed_asic_outb(sc, ED_WD_LAAR, 2213 sc->wd_laar_proto & ~ED_WD_LAAR_M16EN); 2214 break; 2215 } 2216 } 2217 } else { 2218 len = ed_pio_write_mbufs(sc, m, (long)buffer); 2219 if (len == 0) { 2220 m_freem(m0); 2221 goto outloop; 2222 } 2223 } 2224 2225 sc->txb_len[sc->txb_new] = max(len, (ETHER_MIN_LEN-ETHER_CRC_LEN)); 2226 2227 sc->txb_inuse++; 2228 2229 /* 2230 * Point to next buffer slot and wrap if necessary. 2231 */ 2232 sc->txb_new++; 2233 if (sc->txb_new == sc->txb_cnt) 2234 sc->txb_new = 0; 2235 2236 if (sc->xmit_busy == 0) 2237 ed_xmit(sc); 2238 2239 /* 2240 * Tap off here if there is a bpf listener. 2241 */ 2242 BPF_MTAP(ifp, m0); 2243 2244 m_freem(m0); 2245 2246 /* 2247 * Loop back to the top to possibly buffer more packets 2248 */ 2249 goto outloop; 2250} 2251 2252/* 2253 * Ethernet interface receiver interrupt. 2254 */ 2255static __inline void 2256ed_rint(sc) 2257 struct ed_softc *sc; 2258{ 2259 struct ifnet *ifp = &sc->arpcom.ac_if; 2260 u_char boundry; 2261 u_short len; 2262 struct ed_ring packet_hdr; 2263 char *packet_ptr; 2264 2265 if (sc->gone) 2266 return; 2267 2268 /* 2269 * Set NIC to page 1 registers to get 'current' pointer 2270 */ 2271 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA); 2272 2273 /* 2274 * 'sc->next_packet' is the logical beginning of the ring-buffer - 2275 * i.e. it points to where new data has been buffered. The 'CURR' 2276 * (current) register points to the logical end of the ring-buffer - 2277 * i.e. it points to where additional new data will be added. We loop 2278 * here until the logical beginning equals the logical end (or in 2279 * other words, until the ring-buffer is empty). 2280 */ 2281 while (sc->next_packet != ed_nic_inb(sc, ED_P1_CURR)) { 2282 2283 /* get pointer to this buffer's header structure */ 2284 packet_ptr = sc->mem_ring + 2285 (sc->next_packet - sc->rec_page_start) * ED_PAGE_SIZE; 2286 2287 /* 2288 * The byte count includes a 4 byte header that was added by 2289 * the NIC. 2290 */ 2291 if (sc->mem_shared) 2292 packet_hdr = *(struct ed_ring *) packet_ptr; 2293 else 2294 ed_pio_readmem(sc, (long)packet_ptr, (char *) &packet_hdr, 2295 sizeof(packet_hdr)); 2296 len = packet_hdr.count; 2297 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring)) || 2298 len < (ETHER_MIN_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring))) { 2299 /* 2300 * Length is a wild value. There's a good chance that 2301 * this was caused by the NIC being old and buggy. 2302 * The bug is that the length low byte is duplicated in 2303 * the high byte. Try to recalculate the length based on 2304 * the pointer to the next packet. 2305 */ 2306 /* 2307 * NOTE: sc->next_packet is pointing at the current packet. 2308 */ 2309 len &= ED_PAGE_SIZE - 1; /* preserve offset into page */ 2310 if (packet_hdr.next_packet >= sc->next_packet) { 2311 len += (packet_hdr.next_packet - sc->next_packet) * ED_PAGE_SIZE; 2312 } else { 2313 len += ((packet_hdr.next_packet - sc->rec_page_start) + 2314 (sc->rec_page_stop - sc->next_packet)) * ED_PAGE_SIZE; 2315 } 2316 /* 2317 * because buffers are aligned on 256-byte boundary, 2318 * the length computed above is off by 256 in almost 2319 * all cases. Fix it... 2320 */ 2321 if (len & 0xff) 2322 len -= 256 ; 2323 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN 2324 + sizeof(struct ed_ring))) 2325 sc->mibdata.dot3StatsFrameTooLongs++; 2326 } 2327 /* 2328 * Be fairly liberal about what we allow as a "reasonable" length 2329 * so that a [crufty] packet will make it to BPF (and can thus 2330 * be analyzed). Note that all that is really important is that 2331 * we have a length that will fit into one mbuf cluster or less; 2332 * the upper layer protocols can then figure out the length from 2333 * their own length field(s). 2334 * But make sure that we have at least a full ethernet header 2335 * or we would be unable to call ether_input() later. 2336 */ 2337 if ((len >= sizeof(struct ed_ring) + ETHER_HDR_LEN) && 2338 (len <= MCLBYTES) && 2339 (packet_hdr.next_packet >= sc->rec_page_start) && 2340 (packet_hdr.next_packet < sc->rec_page_stop)) { 2341 /* 2342 * Go get packet. 2343 */ 2344 ed_get_packet(sc, packet_ptr + sizeof(struct ed_ring), 2345 len - sizeof(struct ed_ring)); 2346 ifp->if_ipackets++; 2347 } else { 2348 /* 2349 * Really BAD. The ring pointers are corrupted. 2350 */ 2351 log(LOG_ERR, 2352 "%s: NIC memory corrupt - invalid packet length %d\n", 2353 ifp->if_xname, len); 2354 ifp->if_ierrors++; 2355 ed_reset(ifp); 2356 return; 2357 } 2358 2359 /* 2360 * Update next packet pointer 2361 */ 2362 sc->next_packet = packet_hdr.next_packet; 2363 2364 /* 2365 * Update NIC boundry pointer - being careful to keep it one 2366 * buffer behind. (as recommended by NS databook) 2367 */ 2368 boundry = sc->next_packet - 1; 2369 if (boundry < sc->rec_page_start) 2370 boundry = sc->rec_page_stop - 1; 2371 2372 /* 2373 * Set NIC to page 0 registers to update boundry register 2374 */ 2375 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA); 2376 2377 ed_nic_outb(sc, ED_P0_BNRY, boundry); 2378 2379 /* 2380 * Set NIC to page 1 registers before looping to top (prepare 2381 * to get 'CURR' current pointer) 2382 */ 2383 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA); 2384 } 2385} 2386 2387/* 2388 * Ethernet interface interrupt processor 2389 */ 2390void 2391edintr(arg) 2392 void *arg; 2393{ 2394 struct ed_softc *sc = (struct ed_softc*) arg; 2395 struct ifnet *ifp = (struct ifnet *)sc; 2396 u_char isr; 2397 int count; 2398 2399 if (sc->gone) 2400 return; 2401 /* 2402 * Set NIC to page 0 registers 2403 */ 2404 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA); 2405 2406 /* 2407 * loop until there are no more new interrupts. When the card 2408 * goes away, the hardware will read back 0xff. Looking at 2409 * the interrupts, it would appear that 0xff is impossible, 2410 * or at least extremely unlikely. 2411 */ 2412 while ((isr = ed_nic_inb(sc, ED_P0_ISR)) != 0 && isr != 0xff) { 2413 2414 /* 2415 * reset all the bits that we are 'acknowledging' by writing a 2416 * '1' to each bit position that was set (writing a '1' 2417 * *clears* the bit) 2418 */ 2419 ed_nic_outb(sc, ED_P0_ISR, isr); 2420 2421 /* 2422 * XXX workaround for AX88190 2423 * We limit this to 5000 iterations. At 1us per inb/outb, 2424 * this translates to about 15ms, which should be plenty 2425 * of time, and also gives protection in the card eject 2426 * case. 2427 */ 2428 if (sc->chip_type == ED_CHIP_TYPE_AX88190) { 2429 count = 5000; /* 15ms */ 2430 while (count-- && (ed_nic_inb(sc, ED_P0_ISR) & isr)) { 2431 ed_nic_outb(sc, ED_P0_ISR,0); 2432 ed_nic_outb(sc, ED_P0_ISR,isr); 2433 } 2434 if (count == 0) 2435 break; 2436 } 2437 2438 /* 2439 * Handle transmitter interrupts. Handle these first because 2440 * the receiver will reset the board under some conditions. 2441 */ 2442 if (isr & (ED_ISR_PTX | ED_ISR_TXE)) { 2443 u_char collisions = ed_nic_inb(sc, ED_P0_NCR) & 0x0f; 2444 2445 /* 2446 * Check for transmit error. If a TX completed with an 2447 * error, we end up throwing the packet away. Really 2448 * the only error that is possible is excessive 2449 * collisions, and in this case it is best to allow 2450 * the automatic mechanisms of TCP to backoff the 2451 * flow. Of course, with UDP we're screwed, but this 2452 * is expected when a network is heavily loaded. 2453 */ 2454 (void) ed_nic_inb(sc, ED_P0_TSR); 2455 if (isr & ED_ISR_TXE) { 2456 u_char tsr; 2457 2458 /* 2459 * Excessive collisions (16) 2460 */ 2461 tsr = ed_nic_inb(sc, ED_P0_TSR); 2462 if ((tsr & ED_TSR_ABT) 2463 && (collisions == 0)) { 2464 2465 /* 2466 * When collisions total 16, the 2467 * P0_NCR will indicate 0, and the 2468 * TSR_ABT is set. 2469 */ 2470 collisions = 16; 2471 sc->mibdata.dot3StatsExcessiveCollisions++; 2472 sc->mibdata.dot3StatsCollFrequencies[15]++; 2473 } 2474 if (tsr & ED_TSR_OWC) 2475 sc->mibdata.dot3StatsLateCollisions++; 2476 if (tsr & ED_TSR_CDH) 2477 sc->mibdata.dot3StatsSQETestErrors++; 2478 if (tsr & ED_TSR_CRS) 2479 sc->mibdata.dot3StatsCarrierSenseErrors++; 2480 if (tsr & ED_TSR_FU) 2481 sc->mibdata.dot3StatsInternalMacTransmitErrors++; 2482 2483 /* 2484 * update output errors counter 2485 */ 2486 ifp->if_oerrors++; 2487 } else { 2488 2489 /* 2490 * Update total number of successfully 2491 * transmitted packets. 2492 */ 2493 ifp->if_opackets++; 2494 } 2495 2496 /* 2497 * reset tx busy and output active flags 2498 */ 2499 sc->xmit_busy = 0; 2500 ifp->if_flags &= ~IFF_OACTIVE; 2501 2502 /* 2503 * clear watchdog timer 2504 */ 2505 ifp->if_timer = 0; 2506 2507 /* 2508 * Add in total number of collisions on last 2509 * transmission. 2510 */ 2511 ifp->if_collisions += collisions; 2512 switch(collisions) { 2513 case 0: 2514 case 16: 2515 break; 2516 case 1: 2517 sc->mibdata.dot3StatsSingleCollisionFrames++; 2518 sc->mibdata.dot3StatsCollFrequencies[0]++; 2519 break; 2520 default: 2521 sc->mibdata.dot3StatsMultipleCollisionFrames++; 2522 sc->mibdata. 2523 dot3StatsCollFrequencies[collisions-1] 2524 ++; 2525 break; 2526 } 2527 2528 /* 2529 * Decrement buffer in-use count if not zero (can only 2530 * be zero if a transmitter interrupt occured while 2531 * not actually transmitting). If data is ready to 2532 * transmit, start it transmitting, otherwise defer 2533 * until after handling receiver 2534 */ 2535 if (sc->txb_inuse && --sc->txb_inuse) 2536 ed_xmit(sc); 2537 } 2538 2539 /* 2540 * Handle receiver interrupts 2541 */ 2542 if (isr & (ED_ISR_PRX | ED_ISR_RXE | ED_ISR_OVW)) { 2543 2544 /* 2545 * Overwrite warning. In order to make sure that a 2546 * lockup of the local DMA hasn't occurred, we reset 2547 * and re-init the NIC. The NSC manual suggests only a 2548 * partial reset/re-init is necessary - but some chips 2549 * seem to want more. The DMA lockup has been seen 2550 * only with early rev chips - Methinks this bug was 2551 * fixed in later revs. -DG 2552 */ 2553 if (isr & ED_ISR_OVW) { 2554 ifp->if_ierrors++; 2555#ifdef DIAGNOSTIC 2556 log(LOG_WARNING, 2557 "%s: warning - receiver ring buffer overrun\n", 2558 ifp->if_xname); 2559#endif 2560 2561 /* 2562 * Stop/reset/re-init NIC 2563 */ 2564 ed_reset(ifp); 2565 } else { 2566 2567 /* 2568 * Receiver Error. One or more of: CRC error, 2569 * frame alignment error FIFO overrun, or 2570 * missed packet. 2571 */ 2572 if (isr & ED_ISR_RXE) { 2573 u_char rsr; 2574 rsr = ed_nic_inb(sc, ED_P0_RSR); 2575 if (rsr & ED_RSR_CRC) 2576 sc->mibdata.dot3StatsFCSErrors++; 2577 if (rsr & ED_RSR_FAE) 2578 sc->mibdata.dot3StatsAlignmentErrors++; 2579 if (rsr & ED_RSR_FO) 2580 sc->mibdata.dot3StatsInternalMacReceiveErrors++; 2581 ifp->if_ierrors++; 2582#ifdef ED_DEBUG 2583 if_printf(ifp, "receive error %x\n", 2584 ed_nic_inb(sc, ED_P0_RSR)); 2585#endif 2586 } 2587 2588 /* 2589 * Go get the packet(s) XXX - Doing this on an 2590 * error is dubious because there shouldn't be 2591 * any data to get (we've configured the 2592 * interface to not accept packets with 2593 * errors). 2594 */ 2595 2596 /* 2597 * Enable 16bit access to shared memory first 2598 * on WD/SMC boards. 2599 */ 2600 if (sc->isa16bit && 2601 (sc->vendor == ED_VENDOR_WD_SMC)) { 2602 2603 ed_asic_outb(sc, ED_WD_LAAR, 2604 sc->wd_laar_proto | ED_WD_LAAR_M16EN); 2605 if (sc->chip_type == ED_CHIP_TYPE_WD790) { 2606 ed_asic_outb(sc, ED_WD_MSR, 2607 ED_WD_MSR_MENB); 2608 } 2609 } 2610 ed_rint(sc); 2611 2612 /* disable 16bit access */ 2613 if (sc->isa16bit && 2614 (sc->vendor == ED_VENDOR_WD_SMC)) { 2615 2616 if (sc->chip_type == ED_CHIP_TYPE_WD790) { 2617 ed_asic_outb(sc, ED_WD_MSR, 0x00); 2618 } 2619 ed_asic_outb(sc, ED_WD_LAAR, 2620 sc->wd_laar_proto & ~ED_WD_LAAR_M16EN); 2621 } 2622 } 2623 } 2624 2625 /* 2626 * If it looks like the transmitter can take more data, 2627 * attempt to start output on the interface. This is done 2628 * after handling the receiver to give the receiver priority. 2629 */ 2630 if ((ifp->if_flags & IFF_OACTIVE) == 0) 2631 ed_start(ifp); 2632 2633 /* 2634 * return NIC CR to standard state: page 0, remote DMA 2635 * complete, start (toggling the TXP bit off, even if was just 2636 * set in the transmit routine, is *okay* - it is 'edge' 2637 * triggered from low to high) 2638 */ 2639 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA); 2640 2641 /* 2642 * If the Network Talley Counters overflow, read them to reset 2643 * them. It appears that old 8390's won't clear the ISR flag 2644 * otherwise - resulting in an infinite loop. 2645 */ 2646 if (isr & ED_ISR_CNT) { 2647 (void) ed_nic_inb(sc, ED_P0_CNTR0); 2648 (void) ed_nic_inb(sc, ED_P0_CNTR1); 2649 (void) ed_nic_inb(sc, ED_P0_CNTR2); 2650 } 2651 } 2652} 2653 2654/* 2655 * Process an ioctl request. This code needs some work - it looks 2656 * pretty ugly. 2657 */ 2658static int 2659ed_ioctl(ifp, command, data) 2660 register struct ifnet *ifp; 2661 u_long command; 2662 caddr_t data; 2663{ 2664 struct ed_softc *sc = ifp->if_softc; 2665#ifndef ED_NO_MIIBUS 2666 struct ifreq *ifr = (struct ifreq *)data; 2667 struct mii_data *mii; 2668#endif 2669 int s, error = 0; 2670 2671 if (sc == NULL || sc->gone) { 2672 ifp->if_flags &= ~IFF_RUNNING; 2673 return ENXIO; 2674 } 2675 s = splimp(); 2676 2677 switch (command) { 2678 case SIOCSIFFLAGS: 2679 2680 /* 2681 * If the interface is marked up and stopped, then start it. 2682 * If it is marked down and running, then stop it. 2683 */ 2684 if (ifp->if_flags & IFF_UP) { 2685 if ((ifp->if_flags & IFF_RUNNING) == 0) 2686 ed_init(sc); 2687 } else { 2688 if (ifp->if_flags & IFF_RUNNING) { 2689 ed_stop(sc); 2690 ifp->if_flags &= ~IFF_RUNNING; 2691 } 2692 } 2693 2694 /* 2695 * Promiscuous flag may have changed, so reprogram the RCR. 2696 */ 2697 ed_setrcr(sc); 2698 2699 /* 2700 * An unfortunate hack to provide the (required) software 2701 * control of the tranceiver for 3Com boards. The ALTPHYS flag 2702 * disables the tranceiver if set. 2703 */ 2704 if (sc->vendor == ED_VENDOR_3COM) { 2705 if (ifp->if_flags & IFF_ALTPHYS) { 2706 ed_asic_outb(sc, ED_3COM_CR, 0); 2707 } else { 2708 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_XSEL); 2709 } 2710 } else if (sc->vendor == ED_VENDOR_HP) 2711 ed_hpp_set_physical_link(sc); 2712 break; 2713 2714 case SIOCADDMULTI: 2715 case SIOCDELMULTI: 2716 /* 2717 * Multicast list has changed; set the hardware filter 2718 * accordingly. 2719 */ 2720 ed_setrcr(sc); 2721 error = 0; 2722 break; 2723 2724#ifndef ED_NO_MIIBUS 2725 case SIOCGIFMEDIA: 2726 case SIOCSIFMEDIA: 2727 if (sc->miibus == NULL) { 2728 error = EINVAL; 2729 break; 2730 } 2731 mii = device_get_softc(sc->miibus); 2732 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2733 break; 2734#endif 2735 2736 default: 2737 error = ether_ioctl(ifp, command, data); 2738 } 2739 (void) splx(s); 2740 return (error); 2741} 2742 2743/* 2744 * Given a source and destination address, copy 'amount' of a packet from 2745 * the ring buffer into a linear destination buffer. Takes into account 2746 * ring-wrap. 2747 */ 2748static __inline char * 2749ed_ring_copy(sc, src, dst, amount) 2750 struct ed_softc *sc; 2751 char *src; 2752 char *dst; 2753 u_short amount; 2754{ 2755 u_short tmp_amount; 2756 2757 /* does copy wrap to lower addr in ring buffer? */ 2758 if (src + amount > sc->mem_end) { 2759 tmp_amount = sc->mem_end - src; 2760 2761 /* copy amount up to end of NIC memory */ 2762 if (sc->mem_shared) 2763 bcopy(src, dst, tmp_amount); 2764 else 2765 ed_pio_readmem(sc, (long)src, dst, tmp_amount); 2766 2767 amount -= tmp_amount; 2768 src = sc->mem_ring; 2769 dst += tmp_amount; 2770 } 2771 if (sc->mem_shared) 2772 bcopy(src, dst, amount); 2773 else 2774 ed_pio_readmem(sc, (long)src, dst, amount); 2775 2776 return (src + amount); 2777} 2778 2779/* 2780 * Retreive packet from shared memory and send to the next level up via 2781 * ether_input(). 2782 */ 2783static void 2784ed_get_packet(sc, buf, len) 2785 struct ed_softc *sc; 2786 char *buf; 2787 u_short len; 2788{ 2789 struct ifnet *ifp = &sc->arpcom.ac_if; 2790 struct ether_header *eh; 2791 struct mbuf *m; 2792 2793 /* Allocate a header mbuf */ 2794 MGETHDR(m, M_DONTWAIT, MT_DATA); 2795 if (m == NULL) 2796 return; 2797 m->m_pkthdr.rcvif = ifp; 2798 m->m_pkthdr.len = m->m_len = len; 2799 2800 /* 2801 * We always put the received packet in a single buffer - 2802 * either with just an mbuf header or in a cluster attached 2803 * to the header. The +2 is to compensate for the alignment 2804 * fixup below. 2805 */ 2806 if ((len + 2) > MHLEN) { 2807 /* Attach an mbuf cluster */ 2808 MCLGET(m, M_DONTWAIT); 2809 2810 /* Insist on getting a cluster */ 2811 if ((m->m_flags & M_EXT) == 0) { 2812 m_freem(m); 2813 return; 2814 } 2815 } 2816 2817 /* 2818 * The +2 is to longword align the start of the real packet. 2819 * This is important for NFS. 2820 */ 2821 m->m_data += 2; 2822 eh = mtod(m, struct ether_header *); 2823 2824 /* 2825 * Don't read in the entire packet if we know we're going to drop it 2826 * and no bpf is active. 2827 */ 2828 if (!ifp->if_bpf && BDG_ACTIVE( (ifp) ) ) { 2829 struct ifnet *bif; 2830 2831 ed_ring_copy(sc, buf, (char *)eh, ETHER_HDR_LEN); 2832 bif = bridge_in_ptr(ifp, eh) ; 2833 if (bif == BDG_DROP) { 2834 m_freem(m); 2835 return; 2836 } 2837 if (len > ETHER_HDR_LEN) 2838 ed_ring_copy(sc, buf + ETHER_HDR_LEN, 2839 (char *)(eh + 1), len - ETHER_HDR_LEN); 2840 } else 2841 /* 2842 * Get packet, including link layer address, from interface. 2843 */ 2844 ed_ring_copy(sc, buf, (char *)eh, len); 2845 2846 m->m_pkthdr.len = m->m_len = len; 2847 2848 (*ifp->if_input)(ifp, m); 2849} 2850 2851/* 2852 * Supporting routines 2853 */ 2854 2855/* 2856 * Given a NIC memory source address and a host memory destination 2857 * address, copy 'amount' from NIC to host using Programmed I/O. 2858 * The 'amount' is rounded up to a word - okay as long as mbufs 2859 * are word sized. 2860 * This routine is currently Novell-specific. 2861 */ 2862void 2863ed_pio_readmem(sc, src, dst, amount) 2864 struct ed_softc *sc; 2865 long src; 2866 unsigned char *dst; 2867 unsigned short amount; 2868{ 2869 /* HP PC Lan+ cards need special handling */ 2870 if (sc->vendor == ED_VENDOR_HP && sc->type == ED_TYPE_HP_PCLANPLUS) { 2871 ed_hpp_readmem(sc, src, dst, amount); 2872 return; 2873 } 2874 2875 /* Regular Novell cards */ 2876 /* select page 0 registers */ 2877 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STA); 2878 2879 /* round up to a word */ 2880 if (amount & 1) 2881 ++amount; 2882 2883 /* set up DMA byte count */ 2884 ed_nic_outb(sc, ED_P0_RBCR0, amount); 2885 ed_nic_outb(sc, ED_P0_RBCR1, amount >> 8); 2886 2887 /* set up source address in NIC mem */ 2888 ed_nic_outb(sc, ED_P0_RSAR0, src); 2889 ed_nic_outb(sc, ED_P0_RSAR1, src >> 8); 2890 2891 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD0 | ED_CR_STA); 2892 2893 if (sc->isa16bit) { 2894 ed_asic_insw(sc, ED_NOVELL_DATA, dst, amount / 2); 2895 } else { 2896 ed_asic_insb(sc, ED_NOVELL_DATA, dst, amount); 2897 } 2898} 2899 2900/* 2901 * Stripped down routine for writing a linear buffer to NIC memory. 2902 * Only used in the probe routine to test the memory. 'len' must 2903 * be even. 2904 */ 2905void 2906ed_pio_writemem(sc, src, dst, len) 2907 struct ed_softc *sc; 2908 char *src; 2909 unsigned short dst; 2910 unsigned short len; 2911{ 2912 int maxwait = 200; /* about 240us */ 2913 2914 /* select page 0 registers */ 2915 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STA); 2916 2917 /* reset remote DMA complete flag */ 2918 ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC); 2919 2920 /* set up DMA byte count */ 2921 ed_nic_outb(sc, ED_P0_RBCR0, len); 2922 ed_nic_outb(sc, ED_P0_RBCR1, len >> 8); 2923 2924 /* set up destination address in NIC mem */ 2925 ed_nic_outb(sc, ED_P0_RSAR0, dst); 2926 ed_nic_outb(sc, ED_P0_RSAR1, dst >> 8); 2927 2928 /* set remote DMA write */ 2929 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD1 | ED_CR_STA); 2930 2931 if (sc->isa16bit) { 2932 ed_asic_outsw(sc, ED_NOVELL_DATA, src, len / 2); 2933 } else { 2934 ed_asic_outsb(sc, ED_NOVELL_DATA, src, len); 2935 } 2936 2937 /* 2938 * Wait for remote DMA complete. This is necessary because on the 2939 * transmit side, data is handled internally by the NIC in bursts and 2940 * we can't start another remote DMA until this one completes. Not 2941 * waiting causes really bad things to happen - like the NIC 2942 * irrecoverably jamming the ISA bus. 2943 */ 2944 while (((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait); 2945} 2946 2947/* 2948 * Write an mbuf chain to the destination NIC memory address using 2949 * programmed I/O. 2950 */ 2951static u_short 2952ed_pio_write_mbufs(sc, m, dst) 2953 struct ed_softc *sc; 2954 struct mbuf *m; 2955 long dst; 2956{ 2957 struct ifnet *ifp = (struct ifnet *)sc; 2958 unsigned short total_len, dma_len; 2959 struct mbuf *mp; 2960 int maxwait = 200; /* about 240us */ 2961 2962 /* HP PC Lan+ cards need special handling */ 2963 if (sc->vendor == ED_VENDOR_HP && sc->type == ED_TYPE_HP_PCLANPLUS) { 2964 return ed_hpp_write_mbufs(sc, m, dst); 2965 } 2966 2967 /* Regular Novell cards */ 2968 /* First, count up the total number of bytes to copy */ 2969 for (total_len = 0, mp = m; mp; mp = mp->m_next) 2970 total_len += mp->m_len; 2971 2972 dma_len = total_len; 2973 if (sc->isa16bit && (dma_len & 1)) 2974 dma_len++; 2975 2976 /* select page 0 registers */ 2977 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STA); 2978 2979 /* reset remote DMA complete flag */ 2980 ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC); 2981 2982 /* set up DMA byte count */ 2983 ed_nic_outb(sc, ED_P0_RBCR0, dma_len); 2984 ed_nic_outb(sc, ED_P0_RBCR1, dma_len >> 8); 2985 2986 /* set up destination address in NIC mem */ 2987 ed_nic_outb(sc, ED_P0_RSAR0, dst); 2988 ed_nic_outb(sc, ED_P0_RSAR1, dst >> 8); 2989 2990 /* set remote DMA write */ 2991 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD1 | ED_CR_STA); 2992 2993 /* 2994 * Transfer the mbuf chain to the NIC memory. 2995 * 16-bit cards require that data be transferred as words, and only words. 2996 * So that case requires some extra code to patch over odd-length mbufs. 2997 */ 2998 2999 if (!sc->isa16bit) { 3000 /* NE1000s are easy */ 3001 while (m) { 3002 if (m->m_len) { 3003 ed_asic_outsb(sc, ED_NOVELL_DATA, 3004 m->m_data, m->m_len); 3005 } 3006 m = m->m_next; 3007 } 3008 } else { 3009 /* NE2000s are a pain */ 3010 unsigned char *data; 3011 int len, wantbyte; 3012 unsigned char savebyte[2]; 3013 3014 wantbyte = 0; 3015 3016 while (m) { 3017 len = m->m_len; 3018 if (len) { 3019 data = mtod(m, caddr_t); 3020 /* finish the last word */ 3021 if (wantbyte) { 3022 savebyte[1] = *data; 3023 ed_asic_outw(sc, ED_NOVELL_DATA, 3024 *(u_short *)savebyte); 3025 data++; 3026 len--; 3027 wantbyte = 0; 3028 } 3029 /* output contiguous words */ 3030 if (len > 1) { 3031 ed_asic_outsw(sc, ED_NOVELL_DATA, 3032 data, len >> 1); 3033 data += len & ~1; 3034 len &= 1; 3035 } 3036 /* save last byte, if necessary */ 3037 if (len == 1) { 3038 savebyte[0] = *data; 3039 wantbyte = 1; 3040 } 3041 } 3042 m = m->m_next; 3043 } 3044 /* spit last byte */ 3045 if (wantbyte) { 3046 ed_asic_outw(sc, ED_NOVELL_DATA, *(u_short *)savebyte); 3047 } 3048 } 3049 3050 /* 3051 * Wait for remote DMA complete. This is necessary because on the 3052 * transmit side, data is handled internally by the NIC in bursts and 3053 * we can't start another remote DMA until this one completes. Not 3054 * waiting causes really bad things to happen - like the NIC 3055 * irrecoverably jamming the ISA bus. 3056 */ 3057 while (((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait); 3058 3059 if (!maxwait) { 3060 log(LOG_WARNING, "%s: remote transmit DMA failed to complete\n", 3061 ifp->if_xname); 3062 ed_reset(ifp); 3063 return(0); 3064 } 3065 return (total_len); 3066} 3067 3068/* 3069 * Support routines to handle the HP PC Lan+ card. 3070 */ 3071 3072/* 3073 * HP PC Lan+: Read from NIC memory, using either PIO or memory mapped 3074 * IO. 3075 */ 3076 3077static void 3078ed_hpp_readmem(sc, src, dst, amount) 3079 struct ed_softc *sc; 3080 unsigned short src; 3081 unsigned char *dst; 3082 unsigned short amount; 3083{ 3084 3085 int use_32bit_access = !(sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS); 3086 3087 3088 /* Program the source address in RAM */ 3089 ed_asic_outw(sc, ED_HPP_PAGE_2, src); 3090 3091 /* 3092 * The HP PC Lan+ card supports word reads as well as 3093 * a memory mapped i/o port that is aliased to every 3094 * even address on the board. 3095 */ 3096 3097 if (sc->hpp_mem_start) { 3098 3099 /* Enable memory mapped access. */ 3100 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options & 3101 ~(ED_HPP_OPTION_MEM_DISABLE | 3102 ED_HPP_OPTION_BOOT_ROM_ENB)); 3103 3104 if (use_32bit_access && (amount > 3)) { 3105 u_int32_t *dl = (u_int32_t *) dst; 3106 volatile u_int32_t *const sl = 3107 (u_int32_t *) sc->hpp_mem_start; 3108 u_int32_t *const fence = dl + (amount >> 2); 3109 3110 /* Copy out NIC data. We could probably write this 3111 as a `movsl'. The currently generated code is lousy. 3112 */ 3113 3114 while (dl < fence) 3115 *dl++ = *sl; 3116 3117 dst += (amount & ~3); 3118 amount &= 3; 3119 3120 } 3121 3122 /* Finish off any words left, as a series of short reads */ 3123 if (amount > 1) { 3124 u_short *d = (u_short *) dst; 3125 volatile u_short *const s = 3126 (u_short *) sc->hpp_mem_start; 3127 u_short *const fence = d + (amount >> 1); 3128 3129 /* Copy out NIC data. */ 3130 3131 while (d < fence) 3132 *d++ = *s; 3133 3134 dst += (amount & ~1); 3135 amount &= 1; 3136 } 3137 3138 /* 3139 * read in a byte; however we need to always read 16 bits 3140 * at a time or the hardware gets into a funny state 3141 */ 3142 3143 if (amount == 1) { 3144 /* need to read in a short and copy LSB */ 3145 volatile u_short *const s = 3146 (volatile u_short *) sc->hpp_mem_start; 3147 3148 *dst = (*s) & 0xFF; 3149 } 3150 3151 /* Restore Boot ROM access. */ 3152 3153 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options); 3154 3155 3156 } else { 3157 /* Read in data using the I/O port */ 3158 if (use_32bit_access && (amount > 3)) { 3159 ed_asic_insl(sc, ED_HPP_PAGE_4, dst, amount >> 2); 3160 dst += (amount & ~3); 3161 amount &= 3; 3162 } 3163 if (amount > 1) { 3164 ed_asic_insw(sc, ED_HPP_PAGE_4, dst, amount >> 1); 3165 dst += (amount & ~1); 3166 amount &= 1; 3167 } 3168 if (amount == 1) { /* read in a short and keep the LSB */ 3169 *dst = ed_asic_inw(sc, ED_HPP_PAGE_4) & 0xFF; 3170 } 3171 } 3172} 3173 3174/* 3175 * HP PC Lan+: Write to NIC memory, using either PIO or memory mapped 3176 * IO. 3177 * Only used in the probe routine to test the memory. 'len' must 3178 * be even. 3179 */ 3180static void 3181ed_hpp_writemem(sc, src, dst, len) 3182 struct ed_softc *sc; 3183 unsigned char *src; 3184 unsigned short dst; 3185 unsigned short len; 3186{ 3187 /* reset remote DMA complete flag */ 3188 ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC); 3189 3190 /* program the write address in RAM */ 3191 ed_asic_outw(sc, ED_HPP_PAGE_0, dst); 3192 3193 if (sc->hpp_mem_start) { 3194 u_short *s = (u_short *) src; 3195 volatile u_short *d = (u_short *) sc->hpp_mem_start; 3196 u_short *const fence = s + (len >> 1); 3197 3198 /* 3199 * Enable memory mapped access. 3200 */ 3201 3202 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options & 3203 ~(ED_HPP_OPTION_MEM_DISABLE | 3204 ED_HPP_OPTION_BOOT_ROM_ENB)); 3205 3206 /* 3207 * Copy to NIC memory. 3208 */ 3209 3210 while (s < fence) 3211 *d = *s++; 3212 3213 /* 3214 * Restore Boot ROM access. 3215 */ 3216 3217 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options); 3218 3219 } else { 3220 /* write data using I/O writes */ 3221 ed_asic_outsw(sc, ED_HPP_PAGE_4, src, len / 2); 3222 } 3223} 3224 3225/* 3226 * Write to HP PC Lan+ NIC memory. Access to the NIC can be by using 3227 * outsw() or via the memory mapped interface to the same register. 3228 * Writes have to be in word units; byte accesses won't work and may cause 3229 * the NIC to behave weirdly. Long word accesses are permitted if the ASIC 3230 * allows it. 3231 */ 3232 3233static u_short 3234ed_hpp_write_mbufs(struct ed_softc *sc, struct mbuf *m, int dst) 3235{ 3236 int len, wantbyte; 3237 unsigned short total_len; 3238 unsigned char savebyte[2]; 3239 volatile u_short * const d = 3240 (volatile u_short *) sc->hpp_mem_start; 3241 int use_32bit_accesses = !(sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS); 3242 3243 /* select page 0 registers */ 3244 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA); 3245 3246 /* reset remote DMA complete flag */ 3247 ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC); 3248 3249 /* program the write address in RAM */ 3250 ed_asic_outw(sc, ED_HPP_PAGE_0, dst); 3251 3252 if (sc->hpp_mem_start) /* enable memory mapped I/O */ 3253 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options & 3254 ~(ED_HPP_OPTION_MEM_DISABLE | 3255 ED_HPP_OPTION_BOOT_ROM_ENB)); 3256 3257 wantbyte = 0; 3258 total_len = 0; 3259 3260 if (sc->hpp_mem_start) { /* Memory mapped I/O port */ 3261 while (m) { 3262 total_len += (len = m->m_len); 3263 if (len) { 3264 caddr_t data = mtod(m, caddr_t); 3265 /* finish the last word of the previous mbuf */ 3266 if (wantbyte) { 3267 savebyte[1] = *data; 3268 *d = *((u_short *) savebyte); 3269 data++; len--; wantbyte = 0; 3270 } 3271 /* output contiguous words */ 3272 if ((len > 3) && (use_32bit_accesses)) { 3273 volatile u_int32_t *const dl = 3274 (volatile u_int32_t *) d; 3275 u_int32_t *sl = (u_int32_t *) data; 3276 u_int32_t *fence = sl + (len >> 2); 3277 3278 while (sl < fence) 3279 *dl = *sl++; 3280 3281 data += (len & ~3); 3282 len &= 3; 3283 } 3284 /* finish off remain 16 bit writes */ 3285 if (len > 1) { 3286 u_short *s = (u_short *) data; 3287 u_short *fence = s + (len >> 1); 3288 3289 while (s < fence) 3290 *d = *s++; 3291 3292 data += (len & ~1); 3293 len &= 1; 3294 } 3295 /* save last byte if needed */ 3296 if ((wantbyte = (len == 1)) != 0) 3297 savebyte[0] = *data; 3298 } 3299 m = m->m_next; /* to next mbuf */ 3300 } 3301 if (wantbyte) /* write last byte */ 3302 *d = *((u_short *) savebyte); 3303 } else { 3304 /* use programmed I/O */ 3305 while (m) { 3306 total_len += (len = m->m_len); 3307 if (len) { 3308 caddr_t data = mtod(m, caddr_t); 3309 /* finish the last word of the previous mbuf */ 3310 if (wantbyte) { 3311 savebyte[1] = *data; 3312 ed_asic_outw(sc, ED_HPP_PAGE_4, 3313 *((u_short *)savebyte)); 3314 data++; 3315 len--; 3316 wantbyte = 0; 3317 } 3318 /* output contiguous words */ 3319 if ((len > 3) && use_32bit_accesses) { 3320 ed_asic_outsl(sc, ED_HPP_PAGE_4, 3321 data, len >> 2); 3322 data += (len & ~3); 3323 len &= 3; 3324 } 3325 /* finish off remaining 16 bit accesses */ 3326 if (len > 1) { 3327 ed_asic_outsw(sc, ED_HPP_PAGE_4, 3328 data, len >> 1); 3329 data += (len & ~1); 3330 len &= 1; 3331 } 3332 if ((wantbyte = (len == 1)) != 0) 3333 savebyte[0] = *data; 3334 3335 } /* if len != 0 */ 3336 m = m->m_next; 3337 } 3338 if (wantbyte) /* spit last byte */ 3339 ed_asic_outw(sc, ED_HPP_PAGE_4, *(u_short *)savebyte); 3340 3341 } 3342 3343 if (sc->hpp_mem_start) /* turn off memory mapped i/o */ 3344 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options); 3345 3346 return (total_len); 3347} 3348 3349#ifndef ED_NO_MIIBUS 3350/* 3351 * MII bus support routines. 3352 */ 3353int 3354ed_miibus_readreg(dev, phy, reg) 3355 device_t dev; 3356 int phy, reg; 3357{ 3358 struct ed_softc *sc; 3359 int failed, s, val; 3360 3361 s = splimp(); 3362 sc = device_get_softc(dev); 3363 if (sc->gone) { 3364 splx(s); 3365 return (0); 3366 } 3367 3368 (*sc->mii_writebits)(sc, 0xffffffff, 32); 3369 (*sc->mii_writebits)(sc, ED_MII_STARTDELIM, ED_MII_STARTDELIM_BITS); 3370 (*sc->mii_writebits)(sc, ED_MII_READOP, ED_MII_OP_BITS); 3371 (*sc->mii_writebits)(sc, phy, ED_MII_PHY_BITS); 3372 (*sc->mii_writebits)(sc, reg, ED_MII_REG_BITS); 3373 3374 failed = (*sc->mii_readbits)(sc, ED_MII_ACK_BITS); 3375 val = (*sc->mii_readbits)(sc, ED_MII_DATA_BITS); 3376 (*sc->mii_writebits)(sc, ED_MII_IDLE, ED_MII_IDLE_BITS); 3377 3378 splx(s); 3379 return (failed ? 0 : val); 3380} 3381 3382void 3383ed_miibus_writereg(dev, phy, reg, data) 3384 device_t dev; 3385 int phy, reg, data; 3386{ 3387 struct ed_softc *sc; 3388 int s; 3389 3390 s = splimp(); 3391 sc = device_get_softc(dev); 3392 if (sc->gone) { 3393 splx(s); 3394 return; 3395 } 3396 3397 (*sc->mii_writebits)(sc, 0xffffffff, 32); 3398 (*sc->mii_writebits)(sc, ED_MII_STARTDELIM, ED_MII_STARTDELIM_BITS); 3399 (*sc->mii_writebits)(sc, ED_MII_WRITEOP, ED_MII_OP_BITS); 3400 (*sc->mii_writebits)(sc, phy, ED_MII_PHY_BITS); 3401 (*sc->mii_writebits)(sc, reg, ED_MII_REG_BITS); 3402 (*sc->mii_writebits)(sc, ED_MII_TURNAROUND, ED_MII_TURNAROUND_BITS); 3403 (*sc->mii_writebits)(sc, data, ED_MII_DATA_BITS); 3404 (*sc->mii_writebits)(sc, ED_MII_IDLE, ED_MII_IDLE_BITS); 3405 3406 splx(s); 3407} 3408 3409int 3410ed_ifmedia_upd(ifp) 3411 struct ifnet *ifp; 3412{ 3413 struct ed_softc *sc; 3414 struct mii_data *mii; 3415 3416 sc = ifp->if_softc; 3417 if (sc->gone || sc->miibus == NULL) 3418 return (ENXIO); 3419 3420 mii = device_get_softc(sc->miibus); 3421 return mii_mediachg(mii); 3422} 3423 3424void 3425ed_ifmedia_sts(ifp, ifmr) 3426 struct ifnet *ifp; 3427 struct ifmediareq *ifmr; 3428{ 3429 struct ed_softc *sc; 3430 struct mii_data *mii; 3431 3432 sc = ifp->if_softc; 3433 if (sc->gone || sc->miibus == NULL) 3434 return; 3435 3436 mii = device_get_softc(sc->miibus); 3437 mii_pollstat(mii); 3438 ifmr->ifm_active = mii->mii_media_active; 3439 ifmr->ifm_status = mii->mii_media_status; 3440} 3441 3442void 3443ed_child_detached(dev, child) 3444 device_t dev; 3445 device_t child; 3446{ 3447 struct ed_softc *sc; 3448 3449 sc = device_get_softc(dev); 3450 if (child == sc->miibus) 3451 sc->miibus = NULL; 3452} 3453#endif 3454 3455static void 3456ed_setrcr(sc) 3457 struct ed_softc *sc; 3458{ 3459 struct ifnet *ifp = (struct ifnet *)sc; 3460 int i; 3461 u_char reg1; 3462 3463 /* Bit 6 in AX88190 RCR register must be set. */ 3464 if (sc->chip_type == ED_CHIP_TYPE_AX88190) 3465 reg1 = ED_RCR_INTT; 3466 else 3467 reg1 = 0x00; 3468 3469 /* set page 1 registers */ 3470 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP); 3471 3472 if (ifp->if_flags & IFF_PROMISC) { 3473 3474 /* 3475 * Reconfigure the multicast filter. 3476 */ 3477 for (i = 0; i < 8; i++) 3478 ed_nic_outb(sc, ED_P1_MAR(i), 0xff); 3479 3480 /* 3481 * And turn on promiscuous mode. Also enable reception of 3482 * runts and packets with CRC & alignment errors. 3483 */ 3484 /* Set page 0 registers */ 3485 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP); 3486 3487 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_PRO | ED_RCR_AM | 3488 ED_RCR_AB | ED_RCR_AR | ED_RCR_SEP | reg1); 3489 } else { 3490 /* set up multicast addresses and filter modes */ 3491 if (ifp->if_flags & IFF_MULTICAST) { 3492 u_int32_t mcaf[2]; 3493 3494 if (ifp->if_flags & IFF_ALLMULTI) { 3495 mcaf[0] = 0xffffffff; 3496 mcaf[1] = 0xffffffff; 3497 } else 3498 ds_getmcaf(sc, mcaf); 3499 3500 /* 3501 * Set multicast filter on chip. 3502 */ 3503 for (i = 0; i < 8; i++) 3504 ed_nic_outb(sc, ED_P1_MAR(i), ((u_char *) mcaf)[i]); 3505 3506 /* Set page 0 registers */ 3507 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP); 3508 3509 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_AM | ED_RCR_AB | reg1); 3510 } else { 3511 3512 /* 3513 * Initialize multicast address hashing registers to 3514 * not accept multicasts. 3515 */ 3516 for (i = 0; i < 8; ++i) 3517 ed_nic_outb(sc, ED_P1_MAR(i), 0x00); 3518 3519 /* Set page 0 registers */ 3520 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP); 3521 3522 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_AB | reg1); 3523 } 3524 } 3525 3526 /* 3527 * Start interface. 3528 */ 3529 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA); 3530} 3531 3532/* 3533 * Compute crc for ethernet address 3534 */ 3535static uint32_t 3536ds_mchash(addr) 3537 const uint8_t *addr; 3538{ 3539#define ED_POLYNOMIAL 0x04c11db6 3540 register uint32_t crc = 0xffffffff; 3541 register int carry, idx, bit; 3542 register uint8_t data; 3543 3544 for (idx = 6; --idx >= 0;) { 3545 for (data = *addr++, bit = 8; --bit >= 0; data >>=1 ) { 3546 carry = ((crc & 0x80000000) ? 1 : 0) ^ (data & 0x01); 3547 crc <<= 1; 3548 if (carry) 3549 crc = (crc ^ ED_POLYNOMIAL) | carry; 3550 } 3551 } 3552 return crc; 3553#undef POLYNOMIAL 3554} 3555 3556/* 3557 * Compute the multicast address filter from the 3558 * list of multicast addresses we need to listen to. 3559 */ 3560static void 3561ds_getmcaf(sc, mcaf) 3562 struct ed_softc *sc; 3563 u_int32_t *mcaf; 3564{ 3565 register u_int32_t index; 3566 register u_char *af = (u_char *) mcaf; 3567 struct ifmultiaddr *ifma; 3568 3569 mcaf[0] = 0; 3570 mcaf[1] = 0; 3571 3572 TAILQ_FOREACH(ifma, &sc->arpcom.ac_if.if_multiaddrs, ifma_link) { 3573 if (ifma->ifma_addr->sa_family != AF_LINK) 3574 continue; 3575 index = ds_mchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)) 3576 >> 26; 3577 af[index >> 3] |= 1 << (index & 7); 3578 } 3579} 3580