if_ed.c revision 123289
1/* 2 * Copyright (c) 1995, David Greenman 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28#include <sys/cdefs.h> 29__FBSDID("$FreeBSD: head/sys/dev/ed/if_ed.c 123289 2003-12-08 07:54:15Z obrien $"); 30 31/* 32 * Device driver for National Semiconductor DS8390/WD83C690 based ethernet 33 * adapters. By David Greenman, 29-April-1993 34 * 35 * Currently supports the Western Digital/SMC 8003 and 8013 series, 36 * the SMC Elite Ultra (8216), the 3Com 3c503, the NE1000 and NE2000, 37 * and a variety of similar clones. 38 * 39 */ 40 41#include "opt_ed.h" 42 43#include <sys/param.h> 44#include <sys/systm.h> 45#include <sys/sockio.h> 46#include <sys/mbuf.h> 47#include <sys/kernel.h> 48#include <sys/socket.h> 49#include <sys/syslog.h> 50 51#include <sys/bus.h> 52 53#include <machine/bus.h> 54#include <sys/rman.h> 55#include <machine/resource.h> 56 57#include <net/ethernet.h> 58#include <net/if.h> 59#include <net/if_arp.h> 60#include <net/if_dl.h> 61#include <net/if_mib.h> 62#include <net/if_media.h> 63 64#ifndef ED_NO_MIIBUS 65#include <dev/mii/mii.h> 66#include <dev/mii/miivar.h> 67#endif 68 69#include <net/bpf.h> 70#include <net/bridge.h> 71 72#include <machine/md_var.h> 73 74#include <dev/ed/if_edreg.h> 75#include <dev/ed/if_edvar.h> 76 77devclass_t ed_devclass; 78 79static void ed_init (void *); 80static int ed_ioctl (struct ifnet *, u_long, caddr_t); 81static void ed_start (struct ifnet *); 82static void ed_reset (struct ifnet *); 83static void ed_watchdog (struct ifnet *); 84#ifndef ED_NO_MIIBUS 85static void ed_tick (void *); 86#endif 87 88static void ds_getmcaf (struct ed_softc *, u_int32_t *); 89 90static void ed_get_packet (struct ed_softc *, char *, /* u_short */ int); 91 92static __inline void ed_rint (struct ed_softc *); 93static __inline void ed_xmit (struct ed_softc *); 94static __inline char * ed_ring_copy(struct ed_softc *, char *, char *, 95 /* u_short */ int); 96static void ed_hpp_set_physical_link(struct ed_softc *); 97static void ed_hpp_readmem (struct ed_softc *, int, unsigned char *, 98 /* u_short */ int); 99static void ed_hpp_writemem (struct ed_softc *, unsigned char *, 100 /* u_short */ int, /* u_short */ int); 101static u_short ed_hpp_write_mbufs(struct ed_softc *, struct mbuf *, int); 102 103static u_short ed_pio_write_mbufs(struct ed_softc *, struct mbuf *, int); 104 105static void ed_setrcr (struct ed_softc *); 106 107static uint32_t ds_mchash (const uint8_t *); 108 109/* 110 * Interrupt conversion table for WD/SMC ASIC/83C584 111 */ 112static unsigned short ed_intr_val[] = { 113 9, 114 3, 115 5, 116 7, 117 10, 118 11, 119 15, 120 4 121}; 122 123/* 124 * Interrupt conversion table for 83C790 125 */ 126static unsigned short ed_790_intr_val[] = { 127 0, 128 9, 129 3, 130 5, 131 7, 132 10, 133 11, 134 15 135}; 136 137/* 138 * Interrupt conversion table for the HP PC LAN+ 139 */ 140 141static unsigned short ed_hpp_intr_val[] = { 142 0, /* 0 */ 143 0, /* 1 */ 144 0, /* 2 */ 145 3, /* 3 */ 146 4, /* 4 */ 147 5, /* 5 */ 148 6, /* 6 */ 149 7, /* 7 */ 150 0, /* 8 */ 151 9, /* 9 */ 152 10, /* 10 */ 153 11, /* 11 */ 154 12, /* 12 */ 155 0, /* 13 */ 156 0, /* 14 */ 157 15 /* 15 */ 158}; 159 160/* 161 * Generic probe routine for testing for the existance of a DS8390. 162 * Must be called after the NIC has just been reset. This routine 163 * works by looking at certain register values that are guaranteed 164 * to be initialized a certain way after power-up or reset. Seems 165 * not to currently work on the 83C690. 166 * 167 * Specifically: 168 * 169 * Register reset bits set bits 170 * Command Register (CR) TXP, STA RD2, STP 171 * Interrupt Status (ISR) RST 172 * Interrupt Mask (IMR) All bits 173 * Data Control (DCR) LAS 174 * Transmit Config. (TCR) LB1, LB0 175 * 176 * We only look at the CR and ISR registers, however, because looking at 177 * the others would require changing register pages (which would be 178 * intrusive if this isn't an 8390). 179 * 180 * Return 1 if 8390 was found, 0 if not. 181 */ 182 183int 184ed_probe_generic8390(sc) 185 struct ed_softc *sc; 186{ 187 if ((ed_nic_inb(sc, ED_P0_CR) & 188 (ED_CR_RD2 | ED_CR_TXP | ED_CR_STA | ED_CR_STP)) != 189 (ED_CR_RD2 | ED_CR_STP)) 190 return (0); 191 if ((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RST) != ED_ISR_RST) 192 return (0); 193 194 return (1); 195} 196 197/* 198 * Probe and vendor-specific initialization routine for SMC/WD80x3 boards 199 */ 200int 201ed_probe_WD80x3_generic(dev, flags, intr_vals) 202 device_t dev; 203 int flags; 204 unsigned short *intr_vals[]; 205{ 206 struct ed_softc *sc = device_get_softc(dev); 207 int error; 208 int i; 209 u_int memsize, maddr; 210 u_char iptr, isa16bit, sum, totalsum; 211 u_long conf_maddr, conf_msize, irq, junk; 212 213 sc->chip_type = ED_CHIP_TYPE_DP8390; 214 215 if (ED_FLAGS_GETTYPE(flags) == ED_FLAGS_TOSH_ETHER) { 216 totalsum = ED_WD_ROM_CHECKSUM_TOTAL_TOSH_ETHER; 217 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_POW); 218 DELAY(10000); 219 } 220 else 221 totalsum = ED_WD_ROM_CHECKSUM_TOTAL; 222 223 /* 224 * Attempt to do a checksum over the station address PROM. If it 225 * fails, it's probably not a SMC/WD board. There is a problem with 226 * this, though: some clone WD boards don't pass the checksum test. 227 * Danpex boards for one. 228 */ 229 for (sum = 0, i = 0; i < 8; ++i) 230 sum += ed_asic_inb(sc, ED_WD_PROM + i); 231 232 if (sum != totalsum) { 233 234 /* 235 * Checksum is invalid. This often happens with cheap WD8003E 236 * clones. In this case, the checksum byte (the eighth byte) 237 * seems to always be zero. 238 */ 239 if (ed_asic_inb(sc, ED_WD_CARD_ID) != ED_TYPE_WD8003E || 240 ed_asic_inb(sc, ED_WD_PROM + 7) != 0) 241 return (ENXIO); 242 } 243 /* reset card to force it into a known state. */ 244 if (ED_FLAGS_GETTYPE(flags) == ED_FLAGS_TOSH_ETHER) 245 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_RST | ED_WD_MSR_POW); 246 else 247 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_RST); 248 249 DELAY(100); 250 ed_asic_outb(sc, ED_WD_MSR, ed_asic_inb(sc, ED_WD_MSR) & ~ED_WD_MSR_RST); 251 /* wait in the case this card is reading its EEROM */ 252 DELAY(5000); 253 254 sc->vendor = ED_VENDOR_WD_SMC; 255 sc->type = ed_asic_inb(sc, ED_WD_CARD_ID); 256 257 /* 258 * Set initial values for width/size. 259 */ 260 memsize = 8192; 261 isa16bit = 0; 262 switch (sc->type) { 263 case ED_TYPE_WD8003S: 264 sc->type_str = "WD8003S"; 265 break; 266 case ED_TYPE_WD8003E: 267 sc->type_str = "WD8003E"; 268 break; 269 case ED_TYPE_WD8003EB: 270 sc->type_str = "WD8003EB"; 271 break; 272 case ED_TYPE_WD8003W: 273 sc->type_str = "WD8003W"; 274 break; 275 case ED_TYPE_WD8013EBT: 276 sc->type_str = "WD8013EBT"; 277 memsize = 16384; 278 isa16bit = 1; 279 break; 280 case ED_TYPE_WD8013W: 281 sc->type_str = "WD8013W"; 282 memsize = 16384; 283 isa16bit = 1; 284 break; 285 case ED_TYPE_WD8013EP: /* also WD8003EP */ 286 if (ed_asic_inb(sc, ED_WD_ICR) & ED_WD_ICR_16BIT) { 287 isa16bit = 1; 288 memsize = 16384; 289 sc->type_str = "WD8013EP"; 290 } else { 291 sc->type_str = "WD8003EP"; 292 } 293 break; 294 case ED_TYPE_WD8013WC: 295 sc->type_str = "WD8013WC"; 296 memsize = 16384; 297 isa16bit = 1; 298 break; 299 case ED_TYPE_WD8013EBP: 300 sc->type_str = "WD8013EBP"; 301 memsize = 16384; 302 isa16bit = 1; 303 break; 304 case ED_TYPE_WD8013EPC: 305 sc->type_str = "WD8013EPC"; 306 memsize = 16384; 307 isa16bit = 1; 308 break; 309 case ED_TYPE_SMC8216C: /* 8216 has 16K shared mem -- 8416 has 8K */ 310 case ED_TYPE_SMC8216T: 311 if (sc->type == ED_TYPE_SMC8216C) { 312 sc->type_str = "SMC8216/SMC8216C"; 313 } else { 314 sc->type_str = "SMC8216T"; 315 } 316 317 ed_asic_outb(sc, ED_WD790_HWR, 318 ed_asic_inb(sc, ED_WD790_HWR) | ED_WD790_HWR_SWH); 319 switch (ed_asic_inb(sc, ED_WD790_RAR) & ED_WD790_RAR_SZ64) { 320 case ED_WD790_RAR_SZ64: 321 memsize = 65536; 322 break; 323 case ED_WD790_RAR_SZ32: 324 memsize = 32768; 325 break; 326 case ED_WD790_RAR_SZ16: 327 memsize = 16384; 328 break; 329 case ED_WD790_RAR_SZ8: 330 /* 8216 has 16K shared mem -- 8416 has 8K */ 331 if (sc->type == ED_TYPE_SMC8216C) { 332 sc->type_str = "SMC8416C/SMC8416BT"; 333 } else { 334 sc->type_str = "SMC8416T"; 335 } 336 memsize = 8192; 337 break; 338 } 339 ed_asic_outb(sc, ED_WD790_HWR, 340 ed_asic_inb(sc, ED_WD790_HWR) & ~ED_WD790_HWR_SWH); 341 342 isa16bit = 1; 343 sc->chip_type = ED_CHIP_TYPE_WD790; 344 break; 345 case ED_TYPE_TOSHIBA1: 346 sc->type_str = "Toshiba1"; 347 memsize = 32768; 348 isa16bit = 1; 349 break; 350 case ED_TYPE_TOSHIBA4: 351 sc->type_str = "Toshiba4"; 352 memsize = 32768; 353 isa16bit = 1; 354 break; 355 default: 356 sc->type_str = ""; 357 break; 358 } 359 360 /* 361 * Make some adjustments to initial values depending on what is found 362 * in the ICR. 363 */ 364 if (isa16bit && (sc->type != ED_TYPE_WD8013EBT) 365 && (sc->type != ED_TYPE_TOSHIBA1) && (sc->type != ED_TYPE_TOSHIBA4) 366 && ((ed_asic_inb(sc, ED_WD_ICR) & ED_WD_ICR_16BIT) == 0)) { 367 isa16bit = 0; 368 memsize = 8192; 369 } 370 371 error = bus_get_resource(dev, SYS_RES_MEMORY, 0, 372 &conf_maddr, &conf_msize); 373 if (error) 374 return (error); 375 376#if ED_DEBUG 377 printf("type = %x type_str=%s isa16bit=%d memsize=%d id_msize=%d\n", 378 sc->type, sc->type_str, isa16bit, memsize, conf_msize); 379 for (i = 0; i < 8; i++) 380 printf("%x -> %x\n", i, ed_asic_inb(sc, i)); 381#endif 382 383 /* 384 * Allow the user to override the autoconfiguration 385 */ 386 if (conf_msize > 1) 387 memsize = conf_msize; 388 389 maddr = conf_maddr; 390 if (maddr < 0xa0000 || maddr + memsize > 0x1000000) { 391 device_printf(dev, "Invalid ISA memory address range configured: 0x%x - 0x%x\n", 392 maddr, maddr + memsize); 393 return (ENXIO); 394 } 395 396 /* 397 * (note that if the user specifies both of the following flags that 398 * '8bit' mode intentionally has precedence) 399 */ 400 if (flags & ED_FLAGS_FORCE_16BIT_MODE) 401 isa16bit = 1; 402 if (flags & ED_FLAGS_FORCE_8BIT_MODE) 403 isa16bit = 0; 404 405 /* 406 * If possible, get the assigned interrupt number from the card and 407 * use it. 408 */ 409 if ((sc->type & ED_WD_SOFTCONFIG) && 410 (sc->chip_type != ED_CHIP_TYPE_WD790)) { 411 412 /* 413 * Assemble together the encoded interrupt number. 414 */ 415 iptr = (ed_asic_inb(sc, ED_WD_ICR) & ED_WD_ICR_IR2) | 416 ((ed_asic_inb(sc, ED_WD_IRR) & 417 (ED_WD_IRR_IR0 | ED_WD_IRR_IR1)) >> 5); 418 419 /* 420 * If no interrupt specified (or "?"), use what the board tells us. 421 */ 422 error = bus_get_resource(dev, SYS_RES_IRQ, 0, 423 &irq, &junk); 424 if (error && intr_vals[0] != NULL) { 425 error = bus_set_resource(dev, SYS_RES_IRQ, 0, 426 intr_vals[0][iptr], 1); 427 } 428 if (error) 429 return (error); 430 431 /* 432 * Enable the interrupt. 433 */ 434 ed_asic_outb(sc, ED_WD_IRR, 435 ed_asic_inb(sc, ED_WD_IRR) | ED_WD_IRR_IEN); 436 } 437 if (sc->chip_type == ED_CHIP_TYPE_WD790) { 438 ed_asic_outb(sc, ED_WD790_HWR, 439 ed_asic_inb(sc, ED_WD790_HWR) | ED_WD790_HWR_SWH); 440 iptr = (((ed_asic_inb(sc, ED_WD790_GCR) & ED_WD790_GCR_IR2) >> 4) | 441 (ed_asic_inb(sc, ED_WD790_GCR) & 442 (ED_WD790_GCR_IR1 | ED_WD790_GCR_IR0)) >> 2); 443 ed_asic_outb(sc, ED_WD790_HWR, 444 ed_asic_inb(sc, ED_WD790_HWR) & ~ED_WD790_HWR_SWH); 445 446 /* 447 * If no interrupt specified (or "?"), use what the board tells us. 448 */ 449 error = bus_get_resource(dev, SYS_RES_IRQ, 0, 450 &irq, &junk); 451 if (error && intr_vals[1] != NULL) { 452 error = bus_set_resource(dev, SYS_RES_IRQ, 0, 453 intr_vals[1][iptr], 1); 454 } 455 if (error) 456 return (error); 457 458 /* 459 * Enable interrupts. 460 */ 461 ed_asic_outb(sc, ED_WD790_ICR, 462 ed_asic_inb(sc, ED_WD790_ICR) | ED_WD790_ICR_EIL); 463 } 464 error = bus_get_resource(dev, SYS_RES_IRQ, 0, 465 &irq, &junk); 466 if (error) { 467 device_printf(dev, "%s cards don't support auto-detected/assigned interrupts.\n", 468 sc->type_str); 469 return (ENXIO); 470 } 471 sc->isa16bit = isa16bit; 472 sc->mem_shared = 1; 473 474 error = ed_alloc_memory(dev, 0, memsize); 475 if (error) { 476 printf("*** ed_alloc_memory() failed! (%d)\n", error); 477 return (error); 478 } 479 sc->mem_start = (caddr_t) rman_get_virtual(sc->mem_res); 480 481 /* 482 * allocate one xmit buffer if < 16k, two buffers otherwise 483 */ 484 if ((memsize < 16384) || 485 (flags & ED_FLAGS_NO_MULTI_BUFFERING)) { 486 sc->txb_cnt = 1; 487 } else { 488 sc->txb_cnt = 2; 489 } 490 sc->tx_page_start = ED_WD_PAGE_OFFSET; 491 sc->rec_page_start = ED_WD_PAGE_OFFSET + ED_TXBUF_SIZE * sc->txb_cnt; 492 sc->rec_page_stop = ED_WD_PAGE_OFFSET + memsize / ED_PAGE_SIZE; 493 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * sc->rec_page_start); 494 sc->mem_size = memsize; 495 sc->mem_end = sc->mem_start + memsize; 496 497 /* 498 * Get station address from on-board ROM 499 */ 500 for (i = 0; i < ETHER_ADDR_LEN; ++i) 501 sc->arpcom.ac_enaddr[i] = ed_asic_inb(sc, ED_WD_PROM + i); 502 503 /* 504 * Set upper address bits and 8/16 bit access to shared memory. 505 */ 506 if (isa16bit) { 507 if (sc->chip_type == ED_CHIP_TYPE_WD790) { 508 sc->wd_laar_proto = ed_asic_inb(sc, ED_WD_LAAR); 509 } else { 510 sc->wd_laar_proto = ED_WD_LAAR_L16EN | 511 ((kvtop(sc->mem_start) >> 19) & ED_WD_LAAR_ADDRHI); 512 } 513 /* 514 * Enable 16bit access 515 */ 516 ed_asic_outb(sc, ED_WD_LAAR, sc->wd_laar_proto | 517 ED_WD_LAAR_M16EN); 518 } else { 519 if (((sc->type & ED_WD_SOFTCONFIG) || 520 (sc->type == ED_TYPE_TOSHIBA1) || 521 (sc->type == ED_TYPE_TOSHIBA4) || 522 (sc->type == ED_TYPE_WD8013EBT)) && 523 (sc->chip_type != ED_CHIP_TYPE_WD790)) { 524 sc->wd_laar_proto = (kvtop(sc->mem_start) >> 19) & 525 ED_WD_LAAR_ADDRHI; 526 ed_asic_outb(sc, ED_WD_LAAR, sc->wd_laar_proto); 527 } 528 } 529 530 /* 531 * Set address and enable interface shared memory. 532 */ 533 if (sc->chip_type != ED_CHIP_TYPE_WD790) { 534 if (ED_FLAGS_GETTYPE(flags) == ED_FLAGS_TOSH_ETHER) { 535 ed_asic_outb(sc, ED_WD_MSR + 1, 536 ((kvtop(sc->mem_start) >> 8) & 0xe0) | 4); 537 ed_asic_outb(sc, ED_WD_MSR + 2, 538 ((kvtop(sc->mem_start) >> 16) & 0x0f)); 539 ed_asic_outb(sc, ED_WD_MSR, 540 ED_WD_MSR_MENB | ED_WD_MSR_POW); 541 } else { 542 ed_asic_outb(sc, ED_WD_MSR, 543 ((kvtop(sc->mem_start) >> 13) & 544 ED_WD_MSR_ADDR) | ED_WD_MSR_MENB); 545 } 546 sc->cr_proto = ED_CR_RD2; 547 } else { 548 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_MENB); 549 ed_asic_outb(sc, ED_WD790_HWR, (ed_asic_inb(sc, ED_WD790_HWR) | ED_WD790_HWR_SWH)); 550 ed_asic_outb(sc, ED_WD790_RAR, ((kvtop(sc->mem_start) >> 13) & 0x0f) | 551 ((kvtop(sc->mem_start) >> 11) & 0x40) | 552 (ed_asic_inb(sc, ED_WD790_RAR) & 0xb0)); 553 ed_asic_outb(sc, ED_WD790_HWR, (ed_asic_inb(sc, ED_WD790_HWR) & ~ED_WD790_HWR_SWH)); 554 sc->cr_proto = 0; 555 } 556 557#if 0 558 printf("starting memory performance test at 0x%x, size %d...\n", 559 sc->mem_start, memsize*16384); 560 for (i = 0; i < 16384; i++) 561 bzero(sc->mem_start, memsize); 562 printf("***DONE***\n"); 563#endif 564 565 /* 566 * Now zero memory and verify that it is clear 567 */ 568 bzero(sc->mem_start, memsize); 569 570 for (i = 0; i < memsize; ++i) { 571 if (sc->mem_start[i]) { 572 device_printf(dev, "failed to clear shared memory at %jx - check configuration\n", 573 (uintmax_t)kvtop(sc->mem_start + i)); 574 575 /* 576 * Disable 16 bit access to shared memory 577 */ 578 if (isa16bit) { 579 if (sc->chip_type == ED_CHIP_TYPE_WD790) { 580 ed_asic_outb(sc, ED_WD_MSR, 0x00); 581 } 582 ed_asic_outb(sc, ED_WD_LAAR, sc->wd_laar_proto & 583 ~ED_WD_LAAR_M16EN); 584 } 585 return (ENXIO); 586 } 587 } 588 589 /* 590 * Disable 16bit access to shared memory - we leave it 591 * disabled so that 1) machines reboot properly when the board 592 * is set 16 bit mode and there are conflicting 8bit 593 * devices/ROMS in the same 128k address space as this boards 594 * shared memory. and 2) so that other 8 bit devices with 595 * shared memory can be used in this 128k region, too. 596 */ 597 if (isa16bit) { 598 if (sc->chip_type == ED_CHIP_TYPE_WD790) { 599 ed_asic_outb(sc, ED_WD_MSR, 0x00); 600 } 601 ed_asic_outb(sc, ED_WD_LAAR, sc->wd_laar_proto & 602 ~ED_WD_LAAR_M16EN); 603 } 604 return (0); 605} 606 607int 608ed_probe_WD80x3(dev, port_rid, flags) 609 device_t dev; 610 int port_rid; 611 int flags; 612{ 613 struct ed_softc *sc = device_get_softc(dev); 614 int error; 615 static unsigned short *intr_vals[] = {ed_intr_val, ed_790_intr_val}; 616 617 error = ed_alloc_port(dev, port_rid, ED_WD_IO_PORTS); 618 if (error) 619 return (error); 620 621 sc->asic_offset = ED_WD_ASIC_OFFSET; 622 sc->nic_offset = ED_WD_NIC_OFFSET; 623 624 return ed_probe_WD80x3_generic(dev, flags, intr_vals); 625} 626 627/* 628 * Probe and vendor-specific initialization routine for 3Com 3c503 boards 629 */ 630int 631ed_probe_3Com(dev, port_rid, flags) 632 device_t dev; 633 int port_rid; 634 int flags; 635{ 636 struct ed_softc *sc = device_get_softc(dev); 637 int error; 638 int i; 639 u_int memsize; 640 u_char isa16bit; 641 u_long conf_maddr, conf_msize, irq, junk; 642 643 error = ed_alloc_port(dev, 0, ED_3COM_IO_PORTS); 644 if (error) 645 return (error); 646 647 sc->asic_offset = ED_3COM_ASIC_OFFSET; 648 sc->nic_offset = ED_3COM_NIC_OFFSET; 649 650 /* 651 * Verify that the kernel configured I/O address matches the board 652 * configured address 653 */ 654 switch (ed_asic_inb(sc, ED_3COM_BCFR)) { 655 case ED_3COM_BCFR_300: 656 if (rman_get_start(sc->port_res) != 0x300) 657 return (ENXIO); 658 break; 659 case ED_3COM_BCFR_310: 660 if (rman_get_start(sc->port_res) != 0x310) 661 return (ENXIO); 662 break; 663 case ED_3COM_BCFR_330: 664 if (rman_get_start(sc->port_res) != 0x330) 665 return (ENXIO); 666 break; 667 case ED_3COM_BCFR_350: 668 if (rman_get_start(sc->port_res) != 0x350) 669 return (ENXIO); 670 break; 671 case ED_3COM_BCFR_250: 672 if (rman_get_start(sc->port_res) != 0x250) 673 return (ENXIO); 674 break; 675 case ED_3COM_BCFR_280: 676 if (rman_get_start(sc->port_res) != 0x280) 677 return (ENXIO); 678 break; 679 case ED_3COM_BCFR_2A0: 680 if (rman_get_start(sc->port_res) != 0x2a0) 681 return (ENXIO); 682 break; 683 case ED_3COM_BCFR_2E0: 684 if (rman_get_start(sc->port_res) != 0x2e0) 685 return (ENXIO); 686 break; 687 default: 688 return (ENXIO); 689 } 690 691 error = bus_get_resource(dev, SYS_RES_MEMORY, 0, 692 &conf_maddr, &conf_msize); 693 if (error) 694 return (error); 695 696 /* 697 * Verify that the kernel shared memory address matches the board 698 * configured address. 699 */ 700 switch (ed_asic_inb(sc, ED_3COM_PCFR)) { 701 case ED_3COM_PCFR_DC000: 702 if (conf_maddr != 0xdc000) 703 return (ENXIO); 704 break; 705 case ED_3COM_PCFR_D8000: 706 if (conf_maddr != 0xd8000) 707 return (ENXIO); 708 break; 709 case ED_3COM_PCFR_CC000: 710 if (conf_maddr != 0xcc000) 711 return (ENXIO); 712 break; 713 case ED_3COM_PCFR_C8000: 714 if (conf_maddr != 0xc8000) 715 return (ENXIO); 716 break; 717 default: 718 return (ENXIO); 719 } 720 721 722 /* 723 * Reset NIC and ASIC. Enable on-board transceiver throughout reset 724 * sequence because it'll lock up if the cable isn't connected if we 725 * don't. 726 */ 727 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_RST | ED_3COM_CR_XSEL); 728 729 /* 730 * Wait for a while, then un-reset it 731 */ 732 DELAY(50); 733 734 /* 735 * The 3Com ASIC defaults to rather strange settings for the CR after 736 * a reset - it's important to set it again after the following outb 737 * (this is done when we map the PROM below). 738 */ 739 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_XSEL); 740 741 /* 742 * Wait a bit for the NIC to recover from the reset 743 */ 744 DELAY(5000); 745 746 sc->vendor = ED_VENDOR_3COM; 747 sc->type_str = "3c503"; 748 sc->mem_shared = 1; 749 sc->cr_proto = ED_CR_RD2; 750 751 /* 752 * Hmmm...a 16bit 3Com board has 16k of memory, but only an 8k window 753 * to it. 754 */ 755 memsize = 8192; 756 757 /* 758 * Get station address from on-board ROM 759 */ 760 761 /* 762 * First, map ethernet address PROM over the top of where the NIC 763 * registers normally appear. 764 */ 765 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_EALO | ED_3COM_CR_XSEL); 766 767 for (i = 0; i < ETHER_ADDR_LEN; ++i) 768 sc->arpcom.ac_enaddr[i] = ed_nic_inb(sc, i); 769 770 /* 771 * Unmap PROM - select NIC registers. The proper setting of the 772 * tranceiver is set in ed_init so that the attach code is given a 773 * chance to set the default based on a compile-time config option 774 */ 775 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_XSEL); 776 777 /* 778 * Determine if this is an 8bit or 16bit board 779 */ 780 781 /* 782 * select page 0 registers 783 */ 784 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STP); 785 786 /* 787 * Attempt to clear WTS bit. If it doesn't clear, then this is a 16bit 788 * board. 789 */ 790 ed_nic_outb(sc, ED_P0_DCR, 0); 791 792 /* 793 * select page 2 registers 794 */ 795 ed_nic_outb(sc, ED_P0_CR, ED_CR_PAGE_2 | ED_CR_RD2 | ED_CR_STP); 796 797 /* 798 * The 3c503 forces the WTS bit to a one if this is a 16bit board 799 */ 800 if (ed_nic_inb(sc, ED_P2_DCR) & ED_DCR_WTS) 801 isa16bit = 1; 802 else 803 isa16bit = 0; 804 805 /* 806 * select page 0 registers 807 */ 808 ed_nic_outb(sc, ED_P2_CR, ED_CR_RD2 | ED_CR_STP); 809 810 error = ed_alloc_memory(dev, 0, memsize); 811 if (error) 812 return (error); 813 814 sc->mem_start = (caddr_t) rman_get_virtual(sc->mem_res); 815 sc->mem_size = memsize; 816 sc->mem_end = sc->mem_start + memsize; 817 818 /* 819 * We have an entire 8k window to put the transmit buffers on the 820 * 16bit boards. But since the 16bit 3c503's shared memory is only 821 * fast enough to overlap the loading of one full-size packet, trying 822 * to load more than 2 buffers can actually leave the transmitter idle 823 * during the load. So 2 seems the best value. (Although a mix of 824 * variable-sized packets might change this assumption. Nonetheless, 825 * we optimize for linear transfers of same-size packets.) 826 */ 827 if (isa16bit) { 828 if (flags & ED_FLAGS_NO_MULTI_BUFFERING) 829 sc->txb_cnt = 1; 830 else 831 sc->txb_cnt = 2; 832 833 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_16BIT; 834 sc->rec_page_start = ED_3COM_RX_PAGE_OFFSET_16BIT; 835 sc->rec_page_stop = memsize / ED_PAGE_SIZE + 836 ED_3COM_RX_PAGE_OFFSET_16BIT; 837 sc->mem_ring = sc->mem_start; 838 } else { 839 sc->txb_cnt = 1; 840 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_8BIT; 841 sc->rec_page_start = ED_TXBUF_SIZE + ED_3COM_TX_PAGE_OFFSET_8BIT; 842 sc->rec_page_stop = memsize / ED_PAGE_SIZE + 843 ED_3COM_TX_PAGE_OFFSET_8BIT; 844 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * ED_TXBUF_SIZE); 845 } 846 847 sc->isa16bit = isa16bit; 848 849 /* 850 * Initialize GA page start/stop registers. Probably only needed if 851 * doing DMA, but what the hell. 852 */ 853 ed_asic_outb(sc, ED_3COM_PSTR, sc->rec_page_start); 854 ed_asic_outb(sc, ED_3COM_PSPR, sc->rec_page_stop); 855 856 /* 857 * Set IRQ. 3c503 only allows a choice of irq 2-5. 858 */ 859 error = bus_get_resource(dev, SYS_RES_IRQ, 0, &irq, &junk); 860 if (error) 861 return (error); 862 863 switch (irq) { 864 case 2: 865 case 9: 866 ed_asic_outb(sc, ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ2); 867 break; 868 case 3: 869 ed_asic_outb(sc, ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ3); 870 break; 871 case 4: 872 ed_asic_outb(sc, ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ4); 873 break; 874 case 5: 875 ed_asic_outb(sc, ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ5); 876 break; 877 default: 878 device_printf(dev, "Invalid irq configuration (%ld) must be 3-5,9 for 3c503\n", 879 irq); 880 return (ENXIO); 881 } 882 883 /* 884 * Initialize GA configuration register. Set bank and enable shared 885 * mem. 886 */ 887 ed_asic_outb(sc, ED_3COM_GACFR, ED_3COM_GACFR_RSEL | 888 ED_3COM_GACFR_MBS0); 889 890 /* 891 * Initialize "Vector Pointer" registers. These gawd-awful things are 892 * compared to 20 bits of the address on ISA, and if they match, the 893 * shared memory is disabled. We set them to 0xffff0...allegedly the 894 * reset vector. 895 */ 896 ed_asic_outb(sc, ED_3COM_VPTR2, 0xff); 897 ed_asic_outb(sc, ED_3COM_VPTR1, 0xff); 898 ed_asic_outb(sc, ED_3COM_VPTR0, 0x00); 899 900 /* 901 * Zero memory and verify that it is clear 902 */ 903 bzero(sc->mem_start, memsize); 904 905 for (i = 0; i < memsize; ++i) 906 if (sc->mem_start[i]) { 907 device_printf(dev, "failed to clear shared memory at %jx - check configuration\n", 908 (uintmax_t)kvtop(sc->mem_start + i)); 909 return (ENXIO); 910 } 911 return (0); 912} 913 914/* 915 * Probe and vendor-specific initialization routine for SIC boards 916 */ 917int 918ed_probe_SIC(dev, port_rid, flags) 919 device_t dev; 920 int port_rid; 921 int flags; 922{ 923 struct ed_softc *sc = device_get_softc(dev); 924 int error; 925 int i; 926 u_int memsize; 927 u_long conf_maddr, conf_msize; 928 u_char sum; 929 930 error = ed_alloc_port(dev, 0, ED_SIC_IO_PORTS); 931 if (error) 932 return (error); 933 934 sc->asic_offset = ED_SIC_ASIC_OFFSET; 935 sc->nic_offset = ED_SIC_NIC_OFFSET; 936 937 error = bus_get_resource(dev, SYS_RES_MEMORY, 0, 938 &conf_maddr, &conf_msize); 939 if (error) 940 return (error); 941 942 memsize = 16384; 943 if (conf_msize > 1) 944 memsize = conf_msize; 945 946 error = ed_alloc_memory(dev, 0, memsize); 947 if (error) 948 return (error); 949 950 sc->mem_start = (caddr_t) rman_get_virtual(sc->mem_res); 951 sc->mem_size = memsize; 952 953 /* Reset card to force it into a known state. */ 954 ed_asic_outb(sc, 0, 0x00); 955 DELAY(100); 956 957 /* 958 * Here we check the card ROM, if the checksum passes, and the 959 * type code and ethernet address check out, then we know we have 960 * an SIC card. 961 */ 962 ed_asic_outb(sc, 0, 0x81); 963 DELAY(100); 964 965 sum = sc->mem_start[6]; 966 for (i = 0; i < ETHER_ADDR_LEN; i++) { 967 sum ^= (sc->arpcom.ac_enaddr[i] = sc->mem_start[i]); 968 } 969#ifdef ED_DEBUG 970 device_printf(dev, "ed_probe_sic: got address %6D\n", 971 sc->arpcom.ac_enaddr, ":"); 972#endif 973 if (sum != 0) { 974 return (ENXIO); 975 } 976 if ((sc->arpcom.ac_enaddr[0] | sc->arpcom.ac_enaddr[1] | 977 sc->arpcom.ac_enaddr[2]) == 0) { 978 return (ENXIO); 979 } 980 981 sc->vendor = ED_VENDOR_SIC; 982 sc->type_str = "SIC"; 983 sc->isa16bit = 0; 984 sc->cr_proto = 0; 985 986 /* 987 * SIC RAM page 0x0000-0x3fff(or 0x7fff) 988 */ 989 ed_asic_outb(sc, 0, 0x80); 990 DELAY(100); 991 992 /* 993 * Now zero memory and verify that it is clear 994 */ 995 bzero(sc->mem_start, sc->mem_size); 996 997 for (i = 0; i < sc->mem_size; i++) { 998 if (sc->mem_start[i]) { 999 device_printf(dev, "failed to clear shared memory " 1000 "at %jx - check configuration\n", 1001 (uintmax_t)kvtop(sc->mem_start + i)); 1002 1003 return (ENXIO); 1004 } 1005 } 1006 1007 sc->mem_shared = 1; 1008 sc->mem_end = sc->mem_start + sc->mem_size; 1009 1010 /* 1011 * allocate one xmit buffer if < 16k, two buffers otherwise 1012 */ 1013 if ((sc->mem_size < 16384) || (flags & ED_FLAGS_NO_MULTI_BUFFERING)) { 1014 sc->txb_cnt = 1; 1015 } else { 1016 sc->txb_cnt = 2; 1017 } 1018 sc->tx_page_start = 0; 1019 1020 sc->rec_page_start = sc->tx_page_start + ED_TXBUF_SIZE * sc->txb_cnt; 1021 sc->rec_page_stop = sc->tx_page_start + sc->mem_size / ED_PAGE_SIZE; 1022 1023 sc->mem_ring = sc->mem_start + sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE; 1024 1025 return (0); 1026} 1027 1028/* 1029 * Probe and vendor-specific initialization routine for NE1000/2000 boards 1030 */ 1031int 1032ed_probe_Novell_generic(dev, flags) 1033 device_t dev; 1034 int flags; 1035{ 1036 struct ed_softc *sc = device_get_softc(dev); 1037 u_int memsize, n; 1038 u_char romdata[16], tmp; 1039 static char test_pattern[32] = "THIS is A memory TEST pattern"; 1040 char test_buffer[32]; 1041 1042 /* XXX - do Novell-specific probe here */ 1043 1044 /* Reset the board */ 1045 if (ED_FLAGS_GETTYPE(flags) == ED_FLAGS_GWETHER) { 1046 ed_asic_outb(sc, ED_NOVELL_RESET, 0); 1047 DELAY(200); 1048 } 1049 tmp = ed_asic_inb(sc, ED_NOVELL_RESET); 1050 1051 /* 1052 * I don't know if this is necessary; probably cruft leftover from 1053 * Clarkson packet driver code. Doesn't do a thing on the boards I've 1054 * tested. -DG [note that an outb(0x84, 0) seems to work here, and is 1055 * non-invasive...but some boards don't seem to reset and I don't have 1056 * complete documentation on what the 'right' thing to do is...so we 1057 * do the invasive thing for now. Yuck.] 1058 */ 1059 ed_asic_outb(sc, ED_NOVELL_RESET, tmp); 1060 DELAY(5000); 1061 1062 /* 1063 * This is needed because some NE clones apparently don't reset the 1064 * NIC properly (or the NIC chip doesn't reset fully on power-up) XXX 1065 * - this makes the probe invasive! ...Done against my better 1066 * judgement. -DLG 1067 */ 1068 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STP); 1069 1070 DELAY(5000); 1071 1072 /* Make sure that we really have an 8390 based board */ 1073 if (!ed_probe_generic8390(sc)) 1074 return (ENXIO); 1075 1076 sc->vendor = ED_VENDOR_NOVELL; 1077 sc->mem_shared = 0; 1078 sc->cr_proto = ED_CR_RD2; 1079 1080 /* 1081 * Test the ability to read and write to the NIC memory. This has the 1082 * side affect of determining if this is an NE1000 or an NE2000. 1083 */ 1084 1085 /* 1086 * This prevents packets from being stored in the NIC memory when the 1087 * readmem routine turns on the start bit in the CR. 1088 */ 1089 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_MON); 1090 1091 /* Temporarily initialize DCR for byte operations */ 1092 ed_nic_outb(sc, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS); 1093 1094 ed_nic_outb(sc, ED_P0_PSTART, 8192 / ED_PAGE_SIZE); 1095 ed_nic_outb(sc, ED_P0_PSTOP, 16384 / ED_PAGE_SIZE); 1096 1097 sc->isa16bit = 0; 1098 1099 /* 1100 * Write a test pattern in byte mode. If this fails, then there 1101 * probably isn't any memory at 8k - which likely means that the board 1102 * is an NE2000. 1103 */ 1104 ed_pio_writemem(sc, test_pattern, 8192, sizeof(test_pattern)); 1105 ed_pio_readmem(sc, 8192, test_buffer, sizeof(test_pattern)); 1106 1107 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern)) == 0) { 1108 sc->type = ED_TYPE_NE1000; 1109 sc->type_str = "NE1000"; 1110 } else { 1111 1112 /* neither an NE1000 nor a Linksys - try NE2000 */ 1113 ed_nic_outb(sc, ED_P0_DCR, ED_DCR_WTS | ED_DCR_FT1 | ED_DCR_LS); 1114 ed_nic_outb(sc, ED_P0_PSTART, 16384 / ED_PAGE_SIZE); 1115 ed_nic_outb(sc, ED_P0_PSTOP, 32768 / ED_PAGE_SIZE); 1116 1117 sc->isa16bit = 1; 1118 1119 /* 1120 * Write a test pattern in word mode. If this also fails, then 1121 * we don't know what this board is. 1122 */ 1123 ed_pio_writemem(sc, test_pattern, 16384, sizeof(test_pattern)); 1124 ed_pio_readmem(sc, 16384, test_buffer, sizeof(test_pattern)); 1125 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern)) == 0) { 1126 sc->type = ED_TYPE_NE2000; 1127 sc->type_str = "NE2000"; 1128 } else { 1129 return (ENXIO); 1130 } 1131 } 1132 1133 1134 /* 8k of memory plus an additional 8k if 16bit */ 1135 memsize = 8192 + sc->isa16bit * 8192; 1136 1137#if 0 /* probably not useful - NE boards only come two ways */ 1138 /* allow kernel config file overrides */ 1139 if (isa_dev->id_msize) 1140 memsize = isa_dev->id_msize; 1141#endif 1142 1143 sc->mem_size = memsize; 1144 1145 /* NIC memory doesn't start at zero on an NE board */ 1146 /* The start address is tied to the bus width */ 1147 sc->mem_start = (char *) 8192 + sc->isa16bit * 8192; 1148 sc->mem_end = sc->mem_start + memsize; 1149 sc->tx_page_start = memsize / ED_PAGE_SIZE; 1150 1151 if (ED_FLAGS_GETTYPE(flags) == ED_FLAGS_GWETHER) { 1152 int x, i, mstart = 0, msize = 0; 1153 char pbuf0[ED_PAGE_SIZE], pbuf[ED_PAGE_SIZE], tbuf[ED_PAGE_SIZE]; 1154 1155 for (i = 0; i < ED_PAGE_SIZE; i++) 1156 pbuf0[i] = 0; 1157 1158 /* Clear all the memory. */ 1159 for (x = 1; x < 256; x++) 1160 ed_pio_writemem(sc, pbuf0, x * 256, ED_PAGE_SIZE); 1161 1162 /* Search for the start of RAM. */ 1163 for (x = 1; x < 256; x++) { 1164 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE); 1165 if (bcmp(pbuf0, tbuf, ED_PAGE_SIZE) == 0) { 1166 for (i = 0; i < ED_PAGE_SIZE; i++) 1167 pbuf[i] = 255 - x; 1168 ed_pio_writemem(sc, pbuf, x * 256, ED_PAGE_SIZE); 1169 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE); 1170 if (bcmp(pbuf, tbuf, ED_PAGE_SIZE) == 0) { 1171 mstart = x * ED_PAGE_SIZE; 1172 msize = ED_PAGE_SIZE; 1173 break; 1174 } 1175 } 1176 } 1177 1178 if (mstart == 0) { 1179 device_printf(dev, "Cannot find start of RAM.\n"); 1180 return (ENXIO); 1181 } 1182 /* Search for the start of RAM. */ 1183 for (x = (mstart / ED_PAGE_SIZE) + 1; x < 256; x++) { 1184 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE); 1185 if (bcmp(pbuf0, tbuf, ED_PAGE_SIZE) == 0) { 1186 for (i = 0; i < ED_PAGE_SIZE; i++) 1187 pbuf[i] = 255 - x; 1188 ed_pio_writemem(sc, pbuf, x * 256, ED_PAGE_SIZE); 1189 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE); 1190 if (bcmp(pbuf, tbuf, ED_PAGE_SIZE) == 0) 1191 msize += ED_PAGE_SIZE; 1192 else { 1193 break; 1194 } 1195 } else { 1196 break; 1197 } 1198 } 1199 1200 if (msize == 0) { 1201 device_printf(dev, "Cannot find any RAM, start : %d, x = %d.\n", mstart, x); 1202 return (ENXIO); 1203 } 1204 device_printf(dev, "RAM start at %d, size : %d.\n", mstart, msize); 1205 1206 sc->mem_size = msize; 1207 sc->mem_start = (caddr_t) mstart; 1208 sc->mem_end = (caddr_t) (msize + mstart); 1209 sc->tx_page_start = mstart / ED_PAGE_SIZE; 1210 } 1211 1212 /* 1213 * Use one xmit buffer if < 16k, two buffers otherwise (if not told 1214 * otherwise). 1215 */ 1216 if ((memsize < 16384) || (flags & ED_FLAGS_NO_MULTI_BUFFERING)) 1217 sc->txb_cnt = 1; 1218 else 1219 sc->txb_cnt = 2; 1220 1221 sc->rec_page_start = sc->tx_page_start + sc->txb_cnt * ED_TXBUF_SIZE; 1222 sc->rec_page_stop = sc->tx_page_start + memsize / ED_PAGE_SIZE; 1223 1224 sc->mem_ring = sc->mem_start + sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE; 1225 1226 ed_pio_readmem(sc, 0, romdata, 16); 1227 for (n = 0; n < ETHER_ADDR_LEN; n++) 1228 sc->arpcom.ac_enaddr[n] = romdata[n * (sc->isa16bit + 1)]; 1229 1230 if ((ED_FLAGS_GETTYPE(flags) == ED_FLAGS_GWETHER) && 1231 (sc->arpcom.ac_enaddr[2] == 0x86)) { 1232 sc->type_str = "Gateway AT"; 1233 } 1234 1235 /* clear any pending interrupts that might have occurred above */ 1236 ed_nic_outb(sc, ED_P0_ISR, 0xff); 1237 1238 return (0); 1239} 1240 1241int 1242ed_probe_Novell(dev, port_rid, flags) 1243 device_t dev; 1244 int port_rid; 1245 int flags; 1246{ 1247 struct ed_softc *sc = device_get_softc(dev); 1248 int error; 1249 1250 error = ed_alloc_port(dev, port_rid, ED_NOVELL_IO_PORTS); 1251 if (error) 1252 return (error); 1253 1254 sc->asic_offset = ED_NOVELL_ASIC_OFFSET; 1255 sc->nic_offset = ED_NOVELL_NIC_OFFSET; 1256 1257 return ed_probe_Novell_generic(dev, flags); 1258} 1259 1260#define ED_HPP_TEST_SIZE 16 1261 1262/* 1263 * Probe and vendor specific initialization for the HP PC Lan+ Cards. 1264 * (HP Part nos: 27247B and 27252A). 1265 * 1266 * The card has an asic wrapper around a DS8390 core. The asic handles 1267 * host accesses and offers both standard register IO and memory mapped 1268 * IO. Memory mapped I/O allows better performance at the expense of greater 1269 * chance of an incompatibility with existing ISA cards. 1270 * 1271 * The card has a few caveats: it isn't tolerant of byte wide accesses, only 1272 * short (16 bit) or word (32 bit) accesses are allowed. Some card revisions 1273 * don't allow 32 bit accesses; these are indicated by a bit in the software 1274 * ID register (see if_edreg.h). 1275 * 1276 * Other caveats are: we should read the MAC address only when the card 1277 * is inactive. 1278 * 1279 * For more information; please consult the CRYNWR packet driver. 1280 * 1281 * The AUI port is turned on using the "link2" option on the ifconfig 1282 * command line. 1283 */ 1284int 1285ed_probe_HP_pclanp(dev, port_rid, flags) 1286 device_t dev; 1287 int port_rid; 1288 int flags; 1289{ 1290 struct ed_softc *sc = device_get_softc(dev); 1291 int error; 1292 int n; /* temp var */ 1293 int memsize; /* mem on board */ 1294 u_char checksum; /* checksum of board address */ 1295 u_char irq; /* board configured IRQ */ 1296 char test_pattern[ED_HPP_TEST_SIZE]; /* read/write areas for */ 1297 char test_buffer[ED_HPP_TEST_SIZE]; /* probing card */ 1298 u_long conf_maddr, conf_msize, conf_irq, junk; 1299 1300 error = ed_alloc_port(dev, 0, ED_HPP_IO_PORTS); 1301 if (error) 1302 return (error); 1303 1304 /* Fill in basic information */ 1305 sc->asic_offset = ED_HPP_ASIC_OFFSET; 1306 sc->nic_offset = ED_HPP_NIC_OFFSET; 1307 1308 sc->chip_type = ED_CHIP_TYPE_DP8390; 1309 sc->isa16bit = 0; /* the 8390 core needs to be in byte mode */ 1310 1311 /* 1312 * Look for the HP PCLAN+ signature: "0x50,0x48,0x00,0x53" 1313 */ 1314 1315 if ((ed_asic_inb(sc, ED_HPP_ID) != 0x50) || 1316 (ed_asic_inb(sc, ED_HPP_ID + 1) != 0x48) || 1317 ((ed_asic_inb(sc, ED_HPP_ID + 2) & 0xF0) != 0) || 1318 (ed_asic_inb(sc, ED_HPP_ID + 3) != 0x53)) 1319 return ENXIO; 1320 1321 /* 1322 * Read the MAC address and verify checksum on the address. 1323 */ 1324 1325 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_MAC); 1326 for (n = 0, checksum = 0; n < ETHER_ADDR_LEN; n++) 1327 checksum += (sc->arpcom.ac_enaddr[n] = 1328 ed_asic_inb(sc, ED_HPP_MAC_ADDR + n)); 1329 1330 checksum += ed_asic_inb(sc, ED_HPP_MAC_ADDR + ETHER_ADDR_LEN); 1331 1332 if (checksum != 0xFF) 1333 return ENXIO; 1334 1335 /* 1336 * Verify that the software model number is 0. 1337 */ 1338 1339 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_ID); 1340 if (((sc->hpp_id = ed_asic_inw(sc, ED_HPP_PAGE_4)) & 1341 ED_HPP_ID_SOFT_MODEL_MASK) != 0x0000) 1342 return ENXIO; 1343 1344 /* 1345 * Read in and save the current options configured on card. 1346 */ 1347 1348 sc->hpp_options = ed_asic_inw(sc, ED_HPP_OPTION); 1349 1350 sc->hpp_options |= (ED_HPP_OPTION_NIC_RESET | 1351 ED_HPP_OPTION_CHIP_RESET | 1352 ED_HPP_OPTION_ENABLE_IRQ); 1353 1354 /* 1355 * Reset the chip. This requires writing to the option register 1356 * so take care to preserve the other bits. 1357 */ 1358 1359 ed_asic_outw(sc, ED_HPP_OPTION, 1360 (sc->hpp_options & ~(ED_HPP_OPTION_NIC_RESET | 1361 ED_HPP_OPTION_CHIP_RESET))); 1362 1363 DELAY(5000); /* wait for chip reset to complete */ 1364 1365 ed_asic_outw(sc, ED_HPP_OPTION, 1366 (sc->hpp_options | (ED_HPP_OPTION_NIC_RESET | 1367 ED_HPP_OPTION_CHIP_RESET | 1368 ED_HPP_OPTION_ENABLE_IRQ))); 1369 1370 DELAY(5000); 1371 1372 if (!(ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RST)) 1373 return ENXIO; /* reset did not complete */ 1374 1375 /* 1376 * Read out configuration information. 1377 */ 1378 1379 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_HW); 1380 1381 irq = ed_asic_inb(sc, ED_HPP_HW_IRQ); 1382 1383 /* 1384 * Check for impossible IRQ. 1385 */ 1386 1387 if (irq >= (sizeof(ed_hpp_intr_val) / sizeof(ed_hpp_intr_val[0]))) 1388 return ENXIO; 1389 1390 /* 1391 * If the kernel IRQ was specified with a '?' use the cards idea 1392 * of the IRQ. If the kernel IRQ was explicitly specified, it 1393 * should match that of the hardware. 1394 */ 1395 error = bus_get_resource(dev, SYS_RES_IRQ, 0, 1396 &conf_irq, &junk); 1397 if (error) { 1398 bus_set_resource(dev, SYS_RES_IRQ, 0, 1399 ed_hpp_intr_val[irq], 1); 1400 } else { 1401 if (conf_irq != ed_hpp_intr_val[irq]) 1402 return (ENXIO); 1403 } 1404 1405 /* 1406 * Fill in softconfig info. 1407 */ 1408 1409 sc->vendor = ED_VENDOR_HP; 1410 sc->type = ED_TYPE_HP_PCLANPLUS; 1411 sc->type_str = "HP-PCLAN+"; 1412 1413 sc->mem_shared = 0; /* we DON'T have dual ported RAM */ 1414 sc->mem_start = 0; /* we use offsets inside the card RAM */ 1415 1416 sc->hpp_mem_start = NULL;/* no memory mapped I/O by default */ 1417 1418 /* 1419 * The board has 32KB of memory. Is there a way to determine 1420 * this programmatically? 1421 */ 1422 1423 memsize = 32768; 1424 1425 /* 1426 * Check if memory mapping of the I/O registers possible. 1427 */ 1428 1429 if (sc->hpp_options & ED_HPP_OPTION_MEM_ENABLE) 1430 { 1431 u_long mem_addr; 1432 1433 /* 1434 * determine the memory address from the board. 1435 */ 1436 1437 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_HW); 1438 mem_addr = (ed_asic_inw(sc, ED_HPP_HW_MEM_MAP) << 8); 1439 1440 /* 1441 * Check that the kernel specified start of memory and 1442 * hardware's idea of it match. 1443 */ 1444 error = bus_get_resource(dev, SYS_RES_MEMORY, 0, 1445 &conf_maddr, &conf_msize); 1446 if (error) 1447 return (error); 1448 1449 if (mem_addr != conf_maddr) 1450 return ENXIO; 1451 1452 error = ed_alloc_memory(dev, 0, memsize); 1453 if (error) 1454 return (error); 1455 1456 sc->hpp_mem_start = rman_get_virtual(sc->mem_res); 1457 } 1458 1459 /* 1460 * Fill in the rest of the soft config structure. 1461 */ 1462 1463 /* 1464 * The transmit page index. 1465 */ 1466 1467 sc->tx_page_start = ED_HPP_TX_PAGE_OFFSET; 1468 1469 if (device_get_flags(dev) & ED_FLAGS_NO_MULTI_BUFFERING) 1470 sc->txb_cnt = 1; 1471 else 1472 sc->txb_cnt = 2; 1473 1474 /* 1475 * Memory description 1476 */ 1477 1478 sc->mem_size = memsize; 1479 sc->mem_ring = sc->mem_start + 1480 (sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE); 1481 sc->mem_end = sc->mem_start + sc->mem_size; 1482 1483 /* 1484 * Receive area starts after the transmit area and 1485 * continues till the end of memory. 1486 */ 1487 1488 sc->rec_page_start = sc->tx_page_start + 1489 (sc->txb_cnt * ED_TXBUF_SIZE); 1490 sc->rec_page_stop = (sc->mem_size / ED_PAGE_SIZE); 1491 1492 1493 sc->cr_proto = 0; /* value works */ 1494 1495 /* 1496 * Set the wrap registers for string I/O reads. 1497 */ 1498 1499 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_HW); 1500 ed_asic_outw(sc, ED_HPP_HW_WRAP, 1501 ((sc->rec_page_start / ED_PAGE_SIZE) | 1502 (((sc->rec_page_stop / ED_PAGE_SIZE) - 1) << 8))); 1503 1504 /* 1505 * Reset the register page to normal operation. 1506 */ 1507 1508 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_PERF); 1509 1510 /* 1511 * Verify that we can read/write from adapter memory. 1512 * Create test pattern. 1513 */ 1514 1515 for (n = 0; n < ED_HPP_TEST_SIZE; n++) 1516 { 1517 test_pattern[n] = (n*n) ^ ~n; 1518 } 1519 1520#undef ED_HPP_TEST_SIZE 1521 1522 /* 1523 * Check that the memory is accessible thru the I/O ports. 1524 * Write out the contents of "test_pattern", read back 1525 * into "test_buffer" and compare the two for any 1526 * mismatch. 1527 */ 1528 1529 for (n = 0; n < (32768 / ED_PAGE_SIZE); n ++) { 1530 1531 ed_hpp_writemem(sc, test_pattern, (n * ED_PAGE_SIZE), 1532 sizeof(test_pattern)); 1533 ed_hpp_readmem(sc, (n * ED_PAGE_SIZE), 1534 test_buffer, sizeof(test_pattern)); 1535 1536 if (bcmp(test_pattern, test_buffer, 1537 sizeof(test_pattern))) 1538 return ENXIO; 1539 } 1540 1541 return (0); 1542 1543} 1544 1545/* 1546 * HP PC Lan+ : Set the physical link to use AUI or TP/TL. 1547 */ 1548 1549static void 1550ed_hpp_set_physical_link(struct ed_softc *sc) 1551{ 1552 struct ifnet *ifp = &sc->arpcom.ac_if; 1553 int lan_page; 1554 1555 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_LAN); 1556 lan_page = ed_asic_inw(sc, ED_HPP_PAGE_0); 1557 1558 if (ifp->if_flags & IFF_ALTPHYS) { 1559 1560 /* 1561 * Use the AUI port. 1562 */ 1563 1564 lan_page |= ED_HPP_LAN_AUI; 1565 1566 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_LAN); 1567 ed_asic_outw(sc, ED_HPP_PAGE_0, lan_page); 1568 1569 1570 } else { 1571 1572 /* 1573 * Use the ThinLan interface 1574 */ 1575 1576 lan_page &= ~ED_HPP_LAN_AUI; 1577 1578 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_LAN); 1579 ed_asic_outw(sc, ED_HPP_PAGE_0, lan_page); 1580 1581 } 1582 1583 /* 1584 * Wait for the lan card to re-initialize itself 1585 */ 1586 1587 DELAY(150000); /* wait 150 ms */ 1588 1589 /* 1590 * Restore normal pages. 1591 */ 1592 1593 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_PERF); 1594 1595} 1596 1597/* 1598 * Allocate a port resource with the given resource id. 1599 */ 1600int 1601ed_alloc_port(dev, rid, size) 1602 device_t dev; 1603 int rid; 1604 int size; 1605{ 1606 struct ed_softc *sc = device_get_softc(dev); 1607 struct resource *res; 1608 1609 res = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 1610 0ul, ~0ul, size, RF_ACTIVE); 1611 if (res) { 1612 sc->port_rid = rid; 1613 sc->port_res = res; 1614 sc->port_used = size; 1615 return (0); 1616 } else { 1617 return (ENOENT); 1618 } 1619} 1620 1621/* 1622 * Allocate a memory resource with the given resource id. 1623 */ 1624int 1625ed_alloc_memory(dev, rid, size) 1626 device_t dev; 1627 int rid; 1628 int size; 1629{ 1630 struct ed_softc *sc = device_get_softc(dev); 1631 struct resource *res; 1632 1633 res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 1634 0ul, ~0ul, size, RF_ACTIVE); 1635 if (res) { 1636 sc->mem_rid = rid; 1637 sc->mem_res = res; 1638 sc->mem_used = size; 1639 return (0); 1640 } else { 1641 return (ENOENT); 1642 } 1643} 1644 1645/* 1646 * Allocate an irq resource with the given resource id. 1647 */ 1648int 1649ed_alloc_irq(dev, rid, flags) 1650 device_t dev; 1651 int rid; 1652 int flags; 1653{ 1654 struct ed_softc *sc = device_get_softc(dev); 1655 struct resource *res; 1656 1657 res = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 1658 0ul, ~0ul, 1, (RF_ACTIVE | flags)); 1659 if (res) { 1660 sc->irq_rid = rid; 1661 sc->irq_res = res; 1662 return (0); 1663 } else { 1664 return (ENOENT); 1665 } 1666} 1667 1668/* 1669 * Release all resources 1670 */ 1671void 1672ed_release_resources(dev) 1673 device_t dev; 1674{ 1675 struct ed_softc *sc = device_get_softc(dev); 1676 1677 if (sc->port_res) { 1678 bus_deactivate_resource(dev, SYS_RES_IOPORT, 1679 sc->port_rid, sc->port_res); 1680 bus_release_resource(dev, SYS_RES_IOPORT, 1681 sc->port_rid, sc->port_res); 1682 sc->port_res = 0; 1683 } 1684 if (sc->mem_res) { 1685 bus_deactivate_resource(dev, SYS_RES_MEMORY, 1686 sc->mem_rid, sc->mem_res); 1687 bus_release_resource(dev, SYS_RES_MEMORY, 1688 sc->mem_rid, sc->mem_res); 1689 sc->mem_res = 0; 1690 } 1691 if (sc->irq_res) { 1692 bus_deactivate_resource(dev, SYS_RES_IRQ, 1693 sc->irq_rid, sc->irq_res); 1694 bus_release_resource(dev, SYS_RES_IRQ, 1695 sc->irq_rid, sc->irq_res); 1696 sc->irq_res = 0; 1697 } 1698} 1699 1700/* 1701 * Install interface into kernel networking data structures 1702 */ 1703int 1704ed_attach(dev) 1705 device_t dev; 1706{ 1707 struct ed_softc *sc = device_get_softc(dev); 1708 struct ifnet *ifp = &sc->arpcom.ac_if; 1709 1710 callout_handle_init(&sc->tick_ch); 1711 /* 1712 * Set interface to stopped condition (reset) 1713 */ 1714 ed_stop(sc); 1715 1716 /* 1717 * Initialize ifnet structure 1718 */ 1719 ifp->if_softc = sc; 1720 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1721 ifp->if_output = ether_output; 1722 ifp->if_start = ed_start; 1723 ifp->if_ioctl = ed_ioctl; 1724 ifp->if_watchdog = ed_watchdog; 1725 ifp->if_init = ed_init; 1726 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 1727 ifp->if_linkmib = &sc->mibdata; 1728 ifp->if_linkmiblen = sizeof sc->mibdata; 1729 /* 1730 * XXX - should do a better job. 1731 */ 1732 if (sc->chip_type == ED_CHIP_TYPE_WD790) 1733 sc->mibdata.dot3StatsEtherChipSet = 1734 DOT3CHIPSET(dot3VendorWesternDigital, 1735 dot3ChipSetWesternDigital83C790); 1736 else 1737 sc->mibdata.dot3StatsEtherChipSet = 1738 DOT3CHIPSET(dot3VendorNational, 1739 dot3ChipSetNational8390); 1740 sc->mibdata.dot3Compliance = DOT3COMPLIANCE_COLLS; 1741 1742 /* 1743 * Set default state for ALTPHYS flag (used to disable the 1744 * tranceiver for AUI operation), based on compile-time 1745 * config option. 1746 */ 1747 if (device_get_flags(dev) & ED_FLAGS_DISABLE_TRANCEIVER) 1748 ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX | 1749 IFF_MULTICAST | IFF_ALTPHYS); 1750 else 1751 ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX | 1752 IFF_MULTICAST); 1753 1754 /* 1755 * Attach the interface 1756 */ 1757 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 1758 /* device attach does transition from UNCONFIGURED to IDLE state */ 1759 1760 /* 1761 * Print additional info when attached 1762 */ 1763 if_printf(ifp, "address %6D, ", sc->arpcom.ac_enaddr, ":"); 1764 1765 if (sc->type_str && (*sc->type_str != 0)) 1766 printf("type %s ", sc->type_str); 1767 else 1768 printf("type unknown (0x%x) ", sc->type); 1769 1770 if (sc->vendor == ED_VENDOR_HP) 1771 printf("(%s %s IO)", (sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS) ? 1772 "16-bit" : "32-bit", 1773 sc->hpp_mem_start ? "memory mapped" : "regular"); 1774 else 1775 printf("%s ", sc->isa16bit ? "(16 bit)" : "(8 bit)"); 1776 1777 printf("%s\n", (((sc->vendor == ED_VENDOR_3COM) || 1778 (sc->vendor == ED_VENDOR_HP)) && 1779 (ifp->if_flags & IFF_ALTPHYS)) ? " tranceiver disabled" : ""); 1780 1781 return (0); 1782} 1783 1784/* 1785 * Reset interface. 1786 */ 1787static void 1788ed_reset(ifp) 1789 struct ifnet *ifp; 1790{ 1791 struct ed_softc *sc = ifp->if_softc; 1792 int s; 1793 1794 if (sc->gone) 1795 return; 1796 s = splimp(); 1797 1798 /* 1799 * Stop interface and re-initialize. 1800 */ 1801 ed_stop(sc); 1802 ed_init(sc); 1803 1804 (void) splx(s); 1805} 1806 1807/* 1808 * Take interface offline. 1809 */ 1810void 1811ed_stop(sc) 1812 struct ed_softc *sc; 1813{ 1814 int n = 5000; 1815 1816#ifndef ED_NO_MIIBUS 1817 untimeout(ed_tick, sc, sc->tick_ch); 1818 callout_handle_init(&sc->tick_ch); 1819#endif 1820 if (sc->gone) 1821 return; 1822 /* 1823 * Stop everything on the interface, and select page 0 registers. 1824 */ 1825 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP); 1826 1827 /* 1828 * Wait for interface to enter stopped state, but limit # of checks to 1829 * 'n' (about 5ms). It shouldn't even take 5us on modern DS8390's, but 1830 * just in case it's an old one. 1831 */ 1832 if (sc->chip_type != ED_CHIP_TYPE_AX88190) 1833 while (((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RST) == 0) && --n); 1834} 1835 1836/* 1837 * Device timeout/watchdog routine. Entered if the device neglects to 1838 * generate an interrupt after a transmit has been started on it. 1839 */ 1840static void 1841ed_watchdog(ifp) 1842 struct ifnet *ifp; 1843{ 1844 struct ed_softc *sc = ifp->if_softc; 1845 1846 if (sc->gone) 1847 return; 1848 log(LOG_ERR, "%s: device timeout\n", ifp->if_xname); 1849 ifp->if_oerrors++; 1850 1851 ed_reset(ifp); 1852} 1853 1854#ifndef ED_NO_MIIBUS 1855static void 1856ed_tick(arg) 1857 void *arg; 1858{ 1859 struct ed_softc *sc = arg; 1860 struct mii_data *mii; 1861 int s; 1862 1863 if (sc->gone) { 1864 callout_handle_init(&sc->tick_ch); 1865 return; 1866 } 1867 s = splimp(); 1868 if (sc->miibus != NULL) { 1869 mii = device_get_softc(sc->miibus); 1870 mii_tick(mii); 1871 } 1872 sc->tick_ch = timeout(ed_tick, sc, hz); 1873 splx(s); 1874} 1875#endif 1876 1877/* 1878 * Initialize device. 1879 */ 1880static void 1881ed_init(xsc) 1882 void *xsc; 1883{ 1884 struct ed_softc *sc = xsc; 1885 struct ifnet *ifp = &sc->arpcom.ac_if; 1886 int i, s; 1887 1888 if (sc->gone) 1889 return; 1890 1891 /* address not known */ 1892 if (TAILQ_EMPTY(&ifp->if_addrhead)) /* unlikely? XXX */ 1893 return; 1894 1895 /* 1896 * Initialize the NIC in the exact order outlined in the NS manual. 1897 * This init procedure is "mandatory"...don't change what or when 1898 * things happen. 1899 */ 1900 s = splimp(); 1901 1902 /* reset transmitter flags */ 1903 sc->xmit_busy = 0; 1904 ifp->if_timer = 0; 1905 1906 sc->txb_inuse = 0; 1907 sc->txb_new = 0; 1908 sc->txb_next_tx = 0; 1909 1910 /* This variable is used below - don't move this assignment */ 1911 sc->next_packet = sc->rec_page_start + 1; 1912 1913 /* 1914 * Set interface for page 0, Remote DMA complete, Stopped 1915 */ 1916 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP); 1917 1918 if (sc->isa16bit) { 1919 1920 /* 1921 * Set FIFO threshold to 8, No auto-init Remote DMA, byte 1922 * order=80x86, word-wide DMA xfers, 1923 */ 1924 ed_nic_outb(sc, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_WTS | ED_DCR_LS); 1925 } else { 1926 1927 /* 1928 * Same as above, but byte-wide DMA xfers 1929 */ 1930 ed_nic_outb(sc, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS); 1931 } 1932 1933 /* 1934 * Clear Remote Byte Count Registers 1935 */ 1936 ed_nic_outb(sc, ED_P0_RBCR0, 0); 1937 ed_nic_outb(sc, ED_P0_RBCR1, 0); 1938 1939 /* 1940 * For the moment, don't store incoming packets in memory. 1941 */ 1942 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_MON); 1943 1944 /* 1945 * Place NIC in internal loopback mode 1946 */ 1947 ed_nic_outb(sc, ED_P0_TCR, ED_TCR_LB0); 1948 1949 /* 1950 * Initialize transmit/receive (ring-buffer) Page Start 1951 */ 1952 ed_nic_outb(sc, ED_P0_TPSR, sc->tx_page_start); 1953 ed_nic_outb(sc, ED_P0_PSTART, sc->rec_page_start); 1954 /* Set lower bits of byte addressable framing to 0 */ 1955 if (sc->chip_type == ED_CHIP_TYPE_WD790) 1956 ed_nic_outb(sc, 0x09, 0); 1957 1958 /* 1959 * Initialize Receiver (ring-buffer) Page Stop and Boundry 1960 */ 1961 ed_nic_outb(sc, ED_P0_PSTOP, sc->rec_page_stop); 1962 ed_nic_outb(sc, ED_P0_BNRY, sc->rec_page_start); 1963 1964 /* 1965 * Clear all interrupts. A '1' in each bit position clears the 1966 * corresponding flag. 1967 */ 1968 ed_nic_outb(sc, ED_P0_ISR, 0xff); 1969 1970 /* 1971 * Enable the following interrupts: receive/transmit complete, 1972 * receive/transmit error, and Receiver OverWrite. 1973 * 1974 * Counter overflow and Remote DMA complete are *not* enabled. 1975 */ 1976 ed_nic_outb(sc, ED_P0_IMR, 1977 ED_IMR_PRXE | ED_IMR_PTXE | ED_IMR_RXEE | ED_IMR_TXEE | ED_IMR_OVWE); 1978 1979 /* 1980 * Program Command Register for page 1 1981 */ 1982 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP); 1983 1984 /* 1985 * Copy out our station address 1986 */ 1987 for (i = 0; i < ETHER_ADDR_LEN; ++i) 1988 ed_nic_outb(sc, ED_P1_PAR(i), sc->arpcom.ac_enaddr[i]); 1989 1990 /* 1991 * Set Current Page pointer to next_packet (initialized above) 1992 */ 1993 ed_nic_outb(sc, ED_P1_CURR, sc->next_packet); 1994 1995 /* 1996 * Program Receiver Configuration Register and multicast filter. CR is 1997 * set to page 0 on return. 1998 */ 1999 ed_setrcr(sc); 2000 2001 /* 2002 * Take interface out of loopback 2003 */ 2004 ed_nic_outb(sc, ED_P0_TCR, 0); 2005 2006 /* 2007 * If this is a 3Com board, the tranceiver must be software enabled 2008 * (there is no settable hardware default). 2009 */ 2010 if (sc->vendor == ED_VENDOR_3COM) { 2011 if (ifp->if_flags & IFF_ALTPHYS) { 2012 ed_asic_outb(sc, ED_3COM_CR, 0); 2013 } else { 2014 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_XSEL); 2015 } 2016 } 2017 2018#ifndef ED_NO_MIIBUS 2019 if (sc->miibus != NULL) { 2020 struct mii_data *mii; 2021 mii = device_get_softc(sc->miibus); 2022 mii_mediachg(mii); 2023 } 2024#endif 2025 /* 2026 * Set 'running' flag, and clear output active flag. 2027 */ 2028 ifp->if_flags |= IFF_RUNNING; 2029 ifp->if_flags &= ~IFF_OACTIVE; 2030 2031 /* 2032 * ...and attempt to start output 2033 */ 2034 ed_start(ifp); 2035 2036#ifndef ED_NO_MIIBUS 2037 untimeout(ed_tick, sc, sc->tick_ch); 2038 sc->tick_ch = timeout(ed_tick, sc, hz); 2039#endif 2040 (void) splx(s); 2041} 2042 2043/* 2044 * This routine actually starts the transmission on the interface 2045 */ 2046static __inline void 2047ed_xmit(sc) 2048 struct ed_softc *sc; 2049{ 2050 struct ifnet *ifp = (struct ifnet *)sc; 2051 unsigned short len; 2052 2053 if (sc->gone) 2054 return; 2055 len = sc->txb_len[sc->txb_next_tx]; 2056 2057 /* 2058 * Set NIC for page 0 register access 2059 */ 2060 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA); 2061 2062 /* 2063 * Set TX buffer start page 2064 */ 2065 ed_nic_outb(sc, ED_P0_TPSR, sc->tx_page_start + 2066 sc->txb_next_tx * ED_TXBUF_SIZE); 2067 2068 /* 2069 * Set TX length 2070 */ 2071 ed_nic_outb(sc, ED_P0_TBCR0, len); 2072 ed_nic_outb(sc, ED_P0_TBCR1, len >> 8); 2073 2074 /* 2075 * Set page 0, Remote DMA complete, Transmit Packet, and *Start* 2076 */ 2077 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_TXP | ED_CR_STA); 2078 sc->xmit_busy = 1; 2079 2080 /* 2081 * Point to next transmit buffer slot and wrap if necessary. 2082 */ 2083 sc->txb_next_tx++; 2084 if (sc->txb_next_tx == sc->txb_cnt) 2085 sc->txb_next_tx = 0; 2086 2087 /* 2088 * Set a timer just in case we never hear from the board again 2089 */ 2090 ifp->if_timer = 2; 2091} 2092 2093/* 2094 * Start output on interface. 2095 * We make two assumptions here: 2096 * 1) that the current priority is set to splimp _before_ this code 2097 * is called *and* is returned to the appropriate priority after 2098 * return 2099 * 2) that the IFF_OACTIVE flag is checked before this code is called 2100 * (i.e. that the output part of the interface is idle) 2101 */ 2102static void 2103ed_start(ifp) 2104 struct ifnet *ifp; 2105{ 2106 struct ed_softc *sc = ifp->if_softc; 2107 struct mbuf *m0, *m; 2108 caddr_t buffer; 2109 int len; 2110 2111 if (sc->gone) { 2112 printf("ed_start(%p) GONE\n",ifp); 2113 return; 2114 } 2115outloop: 2116 2117 /* 2118 * First, see if there are buffered packets and an idle transmitter - 2119 * should never happen at this point. 2120 */ 2121 if (sc->txb_inuse && (sc->xmit_busy == 0)) { 2122 printf("ed: packets buffered, but transmitter idle\n"); 2123 ed_xmit(sc); 2124 } 2125 2126 /* 2127 * See if there is room to put another packet in the buffer. 2128 */ 2129 if (sc->txb_inuse == sc->txb_cnt) { 2130 2131 /* 2132 * No room. Indicate this to the outside world and exit. 2133 */ 2134 ifp->if_flags |= IFF_OACTIVE; 2135 return; 2136 } 2137 IF_DEQUEUE(&ifp->if_snd, m); 2138 if (m == 0) { 2139 2140 /* 2141 * We are using the !OACTIVE flag to indicate to the outside 2142 * world that we can accept an additional packet rather than 2143 * that the transmitter is _actually_ active. Indeed, the 2144 * transmitter may be active, but if we haven't filled all the 2145 * buffers with data then we still want to accept more. 2146 */ 2147 ifp->if_flags &= ~IFF_OACTIVE; 2148 return; 2149 } 2150 2151 /* 2152 * Copy the mbuf chain into the transmit buffer 2153 */ 2154 2155 m0 = m; 2156 2157 /* txb_new points to next open buffer slot */ 2158 buffer = sc->mem_start + (sc->txb_new * ED_TXBUF_SIZE * ED_PAGE_SIZE); 2159 2160 if (sc->mem_shared) { 2161 2162 /* 2163 * Special case setup for 16 bit boards... 2164 */ 2165 if (sc->isa16bit) { 2166 switch (sc->vendor) { 2167 2168 /* 2169 * For 16bit 3Com boards (which have 16k of 2170 * memory), we have the xmit buffers in a 2171 * different page of memory ('page 0') - so 2172 * change pages. 2173 */ 2174 case ED_VENDOR_3COM: 2175 ed_asic_outb(sc, ED_3COM_GACFR, 2176 ED_3COM_GACFR_RSEL); 2177 break; 2178 2179 /* 2180 * Enable 16bit access to shared memory on 2181 * WD/SMC boards. 2182 */ 2183 case ED_VENDOR_WD_SMC: 2184 ed_asic_outb(sc, ED_WD_LAAR, 2185 sc->wd_laar_proto | ED_WD_LAAR_M16EN); 2186 if (sc->chip_type == ED_CHIP_TYPE_WD790) { 2187 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_MENB); 2188 } 2189 break; 2190 } 2191 } 2192 for (len = 0; m != 0; m = m->m_next) { 2193 bcopy(mtod(m, caddr_t), buffer, m->m_len); 2194 buffer += m->m_len; 2195 len += m->m_len; 2196 } 2197 2198 /* 2199 * Restore previous shared memory access 2200 */ 2201 if (sc->isa16bit) { 2202 switch (sc->vendor) { 2203 case ED_VENDOR_3COM: 2204 ed_asic_outb(sc, ED_3COM_GACFR, 2205 ED_3COM_GACFR_RSEL | ED_3COM_GACFR_MBS0); 2206 break; 2207 case ED_VENDOR_WD_SMC: 2208 if (sc->chip_type == ED_CHIP_TYPE_WD790) { 2209 ed_asic_outb(sc, ED_WD_MSR, 0x00); 2210 } 2211 ed_asic_outb(sc, ED_WD_LAAR, 2212 sc->wd_laar_proto & ~ED_WD_LAAR_M16EN); 2213 break; 2214 } 2215 } 2216 } else { 2217 len = ed_pio_write_mbufs(sc, m, (int)buffer); 2218 if (len == 0) { 2219 m_freem(m0); 2220 goto outloop; 2221 } 2222 } 2223 2224 sc->txb_len[sc->txb_new] = max(len, (ETHER_MIN_LEN-ETHER_CRC_LEN)); 2225 2226 sc->txb_inuse++; 2227 2228 /* 2229 * Point to next buffer slot and wrap if necessary. 2230 */ 2231 sc->txb_new++; 2232 if (sc->txb_new == sc->txb_cnt) 2233 sc->txb_new = 0; 2234 2235 if (sc->xmit_busy == 0) 2236 ed_xmit(sc); 2237 2238 /* 2239 * Tap off here if there is a bpf listener. 2240 */ 2241 BPF_MTAP(ifp, m0); 2242 2243 m_freem(m0); 2244 2245 /* 2246 * Loop back to the top to possibly buffer more packets 2247 */ 2248 goto outloop; 2249} 2250 2251/* 2252 * Ethernet interface receiver interrupt. 2253 */ 2254static __inline void 2255ed_rint(sc) 2256 struct ed_softc *sc; 2257{ 2258 struct ifnet *ifp = &sc->arpcom.ac_if; 2259 u_char boundry; 2260 u_short len; 2261 struct ed_ring packet_hdr; 2262 char *packet_ptr; 2263 2264 if (sc->gone) 2265 return; 2266 2267 /* 2268 * Set NIC to page 1 registers to get 'current' pointer 2269 */ 2270 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA); 2271 2272 /* 2273 * 'sc->next_packet' is the logical beginning of the ring-buffer - 2274 * i.e. it points to where new data has been buffered. The 'CURR' 2275 * (current) register points to the logical end of the ring-buffer - 2276 * i.e. it points to where additional new data will be added. We loop 2277 * here until the logical beginning equals the logical end (or in 2278 * other words, until the ring-buffer is empty). 2279 */ 2280 while (sc->next_packet != ed_nic_inb(sc, ED_P1_CURR)) { 2281 2282 /* get pointer to this buffer's header structure */ 2283 packet_ptr = sc->mem_ring + 2284 (sc->next_packet - sc->rec_page_start) * ED_PAGE_SIZE; 2285 2286 /* 2287 * The byte count includes a 4 byte header that was added by 2288 * the NIC. 2289 */ 2290 if (sc->mem_shared) 2291 packet_hdr = *(struct ed_ring *) packet_ptr; 2292 else 2293 ed_pio_readmem(sc, (int)packet_ptr, (char *) &packet_hdr, 2294 sizeof(packet_hdr)); 2295 len = packet_hdr.count; 2296 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring)) || 2297 len < (ETHER_MIN_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring))) { 2298 /* 2299 * Length is a wild value. There's a good chance that 2300 * this was caused by the NIC being old and buggy. 2301 * The bug is that the length low byte is duplicated in 2302 * the high byte. Try to recalculate the length based on 2303 * the pointer to the next packet. 2304 */ 2305 /* 2306 * NOTE: sc->next_packet is pointing at the current packet. 2307 */ 2308 len &= ED_PAGE_SIZE - 1; /* preserve offset into page */ 2309 if (packet_hdr.next_packet >= sc->next_packet) { 2310 len += (packet_hdr.next_packet - sc->next_packet) * ED_PAGE_SIZE; 2311 } else { 2312 len += ((packet_hdr.next_packet - sc->rec_page_start) + 2313 (sc->rec_page_stop - sc->next_packet)) * ED_PAGE_SIZE; 2314 } 2315 /* 2316 * because buffers are aligned on 256-byte boundary, 2317 * the length computed above is off by 256 in almost 2318 * all cases. Fix it... 2319 */ 2320 if (len & 0xff) 2321 len -= 256 ; 2322 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN 2323 + sizeof(struct ed_ring))) 2324 sc->mibdata.dot3StatsFrameTooLongs++; 2325 } 2326 /* 2327 * Be fairly liberal about what we allow as a "reasonable" length 2328 * so that a [crufty] packet will make it to BPF (and can thus 2329 * be analyzed). Note that all that is really important is that 2330 * we have a length that will fit into one mbuf cluster or less; 2331 * the upper layer protocols can then figure out the length from 2332 * their own length field(s). 2333 * But make sure that we have at least a full ethernet header 2334 * or we would be unable to call ether_input() later. 2335 */ 2336 if ((len >= sizeof(struct ed_ring) + ETHER_HDR_LEN) && 2337 (len <= MCLBYTES) && 2338 (packet_hdr.next_packet >= sc->rec_page_start) && 2339 (packet_hdr.next_packet < sc->rec_page_stop)) { 2340 /* 2341 * Go get packet. 2342 */ 2343 ed_get_packet(sc, packet_ptr + sizeof(struct ed_ring), 2344 len - sizeof(struct ed_ring)); 2345 ifp->if_ipackets++; 2346 } else { 2347 /* 2348 * Really BAD. The ring pointers are corrupted. 2349 */ 2350 log(LOG_ERR, 2351 "%s: NIC memory corrupt - invalid packet length %d\n", 2352 ifp->if_xname, len); 2353 ifp->if_ierrors++; 2354 ed_reset(ifp); 2355 return; 2356 } 2357 2358 /* 2359 * Update next packet pointer 2360 */ 2361 sc->next_packet = packet_hdr.next_packet; 2362 2363 /* 2364 * Update NIC boundry pointer - being careful to keep it one 2365 * buffer behind. (as recommended by NS databook) 2366 */ 2367 boundry = sc->next_packet - 1; 2368 if (boundry < sc->rec_page_start) 2369 boundry = sc->rec_page_stop - 1; 2370 2371 /* 2372 * Set NIC to page 0 registers to update boundry register 2373 */ 2374 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA); 2375 2376 ed_nic_outb(sc, ED_P0_BNRY, boundry); 2377 2378 /* 2379 * Set NIC to page 1 registers before looping to top (prepare 2380 * to get 'CURR' current pointer) 2381 */ 2382 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA); 2383 } 2384} 2385 2386/* 2387 * Ethernet interface interrupt processor 2388 */ 2389void 2390edintr(arg) 2391 void *arg; 2392{ 2393 struct ed_softc *sc = (struct ed_softc*) arg; 2394 struct ifnet *ifp = (struct ifnet *)sc; 2395 u_char isr; 2396 int count; 2397 2398 if (sc->gone) 2399 return; 2400 /* 2401 * Set NIC to page 0 registers 2402 */ 2403 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA); 2404 2405 /* 2406 * loop until there are no more new interrupts. When the card 2407 * goes away, the hardware will read back 0xff. Looking at 2408 * the interrupts, it would appear that 0xff is impossible, 2409 * or at least extremely unlikely. 2410 */ 2411 while ((isr = ed_nic_inb(sc, ED_P0_ISR)) != 0 && isr != 0xff) { 2412 2413 /* 2414 * reset all the bits that we are 'acknowledging' by writing a 2415 * '1' to each bit position that was set (writing a '1' 2416 * *clears* the bit) 2417 */ 2418 ed_nic_outb(sc, ED_P0_ISR, isr); 2419 2420 /* 2421 * XXX workaround for AX88190 2422 * We limit this to 5000 iterations. At 1us per inb/outb, 2423 * this translates to about 15ms, which should be plenty 2424 * of time, and also gives protection in the card eject 2425 * case. 2426 */ 2427 if (sc->chip_type == ED_CHIP_TYPE_AX88190) { 2428 count = 5000; /* 15ms */ 2429 while (count-- && (ed_nic_inb(sc, ED_P0_ISR) & isr)) { 2430 ed_nic_outb(sc, ED_P0_ISR,0); 2431 ed_nic_outb(sc, ED_P0_ISR,isr); 2432 } 2433 if (count == 0) 2434 break; 2435 } 2436 2437 /* 2438 * Handle transmitter interrupts. Handle these first because 2439 * the receiver will reset the board under some conditions. 2440 */ 2441 if (isr & (ED_ISR_PTX | ED_ISR_TXE)) { 2442 u_char collisions = ed_nic_inb(sc, ED_P0_NCR) & 0x0f; 2443 2444 /* 2445 * Check for transmit error. If a TX completed with an 2446 * error, we end up throwing the packet away. Really 2447 * the only error that is possible is excessive 2448 * collisions, and in this case it is best to allow 2449 * the automatic mechanisms of TCP to backoff the 2450 * flow. Of course, with UDP we're screwed, but this 2451 * is expected when a network is heavily loaded. 2452 */ 2453 (void) ed_nic_inb(sc, ED_P0_TSR); 2454 if (isr & ED_ISR_TXE) { 2455 u_char tsr; 2456 2457 /* 2458 * Excessive collisions (16) 2459 */ 2460 tsr = ed_nic_inb(sc, ED_P0_TSR); 2461 if ((tsr & ED_TSR_ABT) 2462 && (collisions == 0)) { 2463 2464 /* 2465 * When collisions total 16, the 2466 * P0_NCR will indicate 0, and the 2467 * TSR_ABT is set. 2468 */ 2469 collisions = 16; 2470 sc->mibdata.dot3StatsExcessiveCollisions++; 2471 sc->mibdata.dot3StatsCollFrequencies[15]++; 2472 } 2473 if (tsr & ED_TSR_OWC) 2474 sc->mibdata.dot3StatsLateCollisions++; 2475 if (tsr & ED_TSR_CDH) 2476 sc->mibdata.dot3StatsSQETestErrors++; 2477 if (tsr & ED_TSR_CRS) 2478 sc->mibdata.dot3StatsCarrierSenseErrors++; 2479 if (tsr & ED_TSR_FU) 2480 sc->mibdata.dot3StatsInternalMacTransmitErrors++; 2481 2482 /* 2483 * update output errors counter 2484 */ 2485 ifp->if_oerrors++; 2486 } else { 2487 2488 /* 2489 * Update total number of successfully 2490 * transmitted packets. 2491 */ 2492 ifp->if_opackets++; 2493 } 2494 2495 /* 2496 * reset tx busy and output active flags 2497 */ 2498 sc->xmit_busy = 0; 2499 ifp->if_flags &= ~IFF_OACTIVE; 2500 2501 /* 2502 * clear watchdog timer 2503 */ 2504 ifp->if_timer = 0; 2505 2506 /* 2507 * Add in total number of collisions on last 2508 * transmission. 2509 */ 2510 ifp->if_collisions += collisions; 2511 switch(collisions) { 2512 case 0: 2513 case 16: 2514 break; 2515 case 1: 2516 sc->mibdata.dot3StatsSingleCollisionFrames++; 2517 sc->mibdata.dot3StatsCollFrequencies[0]++; 2518 break; 2519 default: 2520 sc->mibdata.dot3StatsMultipleCollisionFrames++; 2521 sc->mibdata. 2522 dot3StatsCollFrequencies[collisions-1] 2523 ++; 2524 break; 2525 } 2526 2527 /* 2528 * Decrement buffer in-use count if not zero (can only 2529 * be zero if a transmitter interrupt occured while 2530 * not actually transmitting). If data is ready to 2531 * transmit, start it transmitting, otherwise defer 2532 * until after handling receiver 2533 */ 2534 if (sc->txb_inuse && --sc->txb_inuse) 2535 ed_xmit(sc); 2536 } 2537 2538 /* 2539 * Handle receiver interrupts 2540 */ 2541 if (isr & (ED_ISR_PRX | ED_ISR_RXE | ED_ISR_OVW)) { 2542 2543 /* 2544 * Overwrite warning. In order to make sure that a 2545 * lockup of the local DMA hasn't occurred, we reset 2546 * and re-init the NIC. The NSC manual suggests only a 2547 * partial reset/re-init is necessary - but some chips 2548 * seem to want more. The DMA lockup has been seen 2549 * only with early rev chips - Methinks this bug was 2550 * fixed in later revs. -DG 2551 */ 2552 if (isr & ED_ISR_OVW) { 2553 ifp->if_ierrors++; 2554#ifdef DIAGNOSTIC 2555 log(LOG_WARNING, 2556 "%s: warning - receiver ring buffer overrun\n", 2557 ifp->if_xname); 2558#endif 2559 2560 /* 2561 * Stop/reset/re-init NIC 2562 */ 2563 ed_reset(ifp); 2564 } else { 2565 2566 /* 2567 * Receiver Error. One or more of: CRC error, 2568 * frame alignment error FIFO overrun, or 2569 * missed packet. 2570 */ 2571 if (isr & ED_ISR_RXE) { 2572 u_char rsr; 2573 rsr = ed_nic_inb(sc, ED_P0_RSR); 2574 if (rsr & ED_RSR_CRC) 2575 sc->mibdata.dot3StatsFCSErrors++; 2576 if (rsr & ED_RSR_FAE) 2577 sc->mibdata.dot3StatsAlignmentErrors++; 2578 if (rsr & ED_RSR_FO) 2579 sc->mibdata.dot3StatsInternalMacReceiveErrors++; 2580 ifp->if_ierrors++; 2581#ifdef ED_DEBUG 2582 if_printf(ifp, "receive error %x\n", 2583 ed_nic_inb(sc, ED_P0_RSR)); 2584#endif 2585 } 2586 2587 /* 2588 * Go get the packet(s) XXX - Doing this on an 2589 * error is dubious because there shouldn't be 2590 * any data to get (we've configured the 2591 * interface to not accept packets with 2592 * errors). 2593 */ 2594 2595 /* 2596 * Enable 16bit access to shared memory first 2597 * on WD/SMC boards. 2598 */ 2599 if (sc->isa16bit && 2600 (sc->vendor == ED_VENDOR_WD_SMC)) { 2601 2602 ed_asic_outb(sc, ED_WD_LAAR, 2603 sc->wd_laar_proto | ED_WD_LAAR_M16EN); 2604 if (sc->chip_type == ED_CHIP_TYPE_WD790) { 2605 ed_asic_outb(sc, ED_WD_MSR, 2606 ED_WD_MSR_MENB); 2607 } 2608 } 2609 ed_rint(sc); 2610 2611 /* disable 16bit access */ 2612 if (sc->isa16bit && 2613 (sc->vendor == ED_VENDOR_WD_SMC)) { 2614 2615 if (sc->chip_type == ED_CHIP_TYPE_WD790) { 2616 ed_asic_outb(sc, ED_WD_MSR, 0x00); 2617 } 2618 ed_asic_outb(sc, ED_WD_LAAR, 2619 sc->wd_laar_proto & ~ED_WD_LAAR_M16EN); 2620 } 2621 } 2622 } 2623 2624 /* 2625 * If it looks like the transmitter can take more data, 2626 * attempt to start output on the interface. This is done 2627 * after handling the receiver to give the receiver priority. 2628 */ 2629 if ((ifp->if_flags & IFF_OACTIVE) == 0) 2630 ed_start(ifp); 2631 2632 /* 2633 * return NIC CR to standard state: page 0, remote DMA 2634 * complete, start (toggling the TXP bit off, even if was just 2635 * set in the transmit routine, is *okay* - it is 'edge' 2636 * triggered from low to high) 2637 */ 2638 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA); 2639 2640 /* 2641 * If the Network Talley Counters overflow, read them to reset 2642 * them. It appears that old 8390's won't clear the ISR flag 2643 * otherwise - resulting in an infinite loop. 2644 */ 2645 if (isr & ED_ISR_CNT) { 2646 (void) ed_nic_inb(sc, ED_P0_CNTR0); 2647 (void) ed_nic_inb(sc, ED_P0_CNTR1); 2648 (void) ed_nic_inb(sc, ED_P0_CNTR2); 2649 } 2650 } 2651} 2652 2653/* 2654 * Process an ioctl request. This code needs some work - it looks 2655 * pretty ugly. 2656 */ 2657static int 2658ed_ioctl(ifp, command, data) 2659 register struct ifnet *ifp; 2660 u_long command; 2661 caddr_t data; 2662{ 2663 struct ed_softc *sc = ifp->if_softc; 2664#ifndef ED_NO_MIIBUS 2665 struct ifreq *ifr = (struct ifreq *)data; 2666 struct mii_data *mii; 2667#endif 2668 int s, error = 0; 2669 2670 if (sc == NULL || sc->gone) { 2671 ifp->if_flags &= ~IFF_RUNNING; 2672 return ENXIO; 2673 } 2674 s = splimp(); 2675 2676 switch (command) { 2677 case SIOCSIFFLAGS: 2678 2679 /* 2680 * If the interface is marked up and stopped, then start it. 2681 * If it is marked down and running, then stop it. 2682 */ 2683 if (ifp->if_flags & IFF_UP) { 2684 if ((ifp->if_flags & IFF_RUNNING) == 0) 2685 ed_init(sc); 2686 } else { 2687 if (ifp->if_flags & IFF_RUNNING) { 2688 ed_stop(sc); 2689 ifp->if_flags &= ~IFF_RUNNING; 2690 } 2691 } 2692 2693 /* 2694 * Promiscuous flag may have changed, so reprogram the RCR. 2695 */ 2696 ed_setrcr(sc); 2697 2698 /* 2699 * An unfortunate hack to provide the (required) software 2700 * control of the tranceiver for 3Com boards. The ALTPHYS flag 2701 * disables the tranceiver if set. 2702 */ 2703 if (sc->vendor == ED_VENDOR_3COM) { 2704 if (ifp->if_flags & IFF_ALTPHYS) { 2705 ed_asic_outb(sc, ED_3COM_CR, 0); 2706 } else { 2707 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_XSEL); 2708 } 2709 } else if (sc->vendor == ED_VENDOR_HP) 2710 ed_hpp_set_physical_link(sc); 2711 break; 2712 2713 case SIOCADDMULTI: 2714 case SIOCDELMULTI: 2715 /* 2716 * Multicast list has changed; set the hardware filter 2717 * accordingly. 2718 */ 2719 ed_setrcr(sc); 2720 error = 0; 2721 break; 2722 2723#ifndef ED_NO_MIIBUS 2724 case SIOCGIFMEDIA: 2725 case SIOCSIFMEDIA: 2726 if (sc->miibus == NULL) { 2727 error = EINVAL; 2728 break; 2729 } 2730 mii = device_get_softc(sc->miibus); 2731 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2732 break; 2733#endif 2734 2735 default: 2736 error = ether_ioctl(ifp, command, data); 2737 } 2738 (void) splx(s); 2739 return (error); 2740} 2741 2742/* 2743 * Given a source and destination address, copy 'amount' of a packet from 2744 * the ring buffer into a linear destination buffer. Takes into account 2745 * ring-wrap. 2746 */ 2747static __inline char * 2748ed_ring_copy(sc, src, dst, amount) 2749 struct ed_softc *sc; 2750 char *src; 2751 char *dst; 2752 u_short amount; 2753{ 2754 u_short tmp_amount; 2755 2756 /* does copy wrap to lower addr in ring buffer? */ 2757 if (src + amount > sc->mem_end) { 2758 tmp_amount = sc->mem_end - src; 2759 2760 /* copy amount up to end of NIC memory */ 2761 if (sc->mem_shared) 2762 bcopy(src, dst, tmp_amount); 2763 else 2764 ed_pio_readmem(sc, (int)src, dst, tmp_amount); 2765 2766 amount -= tmp_amount; 2767 src = sc->mem_ring; 2768 dst += tmp_amount; 2769 } 2770 if (sc->mem_shared) 2771 bcopy(src, dst, amount); 2772 else 2773 ed_pio_readmem(sc, (int)src, dst, amount); 2774 2775 return (src + amount); 2776} 2777 2778/* 2779 * Retreive packet from shared memory and send to the next level up via 2780 * ether_input(). 2781 */ 2782static void 2783ed_get_packet(sc, buf, len) 2784 struct ed_softc *sc; 2785 char *buf; 2786 u_short len; 2787{ 2788 struct ifnet *ifp = &sc->arpcom.ac_if; 2789 struct ether_header *eh; 2790 struct mbuf *m; 2791 2792 /* Allocate a header mbuf */ 2793 MGETHDR(m, M_DONTWAIT, MT_DATA); 2794 if (m == NULL) 2795 return; 2796 m->m_pkthdr.rcvif = ifp; 2797 m->m_pkthdr.len = m->m_len = len; 2798 2799 /* 2800 * We always put the received packet in a single buffer - 2801 * either with just an mbuf header or in a cluster attached 2802 * to the header. The +2 is to compensate for the alignment 2803 * fixup below. 2804 */ 2805 if ((len + 2) > MHLEN) { 2806 /* Attach an mbuf cluster */ 2807 MCLGET(m, M_DONTWAIT); 2808 2809 /* Insist on getting a cluster */ 2810 if ((m->m_flags & M_EXT) == 0) { 2811 m_freem(m); 2812 return; 2813 } 2814 } 2815 2816 /* 2817 * The +2 is to longword align the start of the real packet. 2818 * This is important for NFS. 2819 */ 2820 m->m_data += 2; 2821 eh = mtod(m, struct ether_header *); 2822 2823 /* 2824 * Don't read in the entire packet if we know we're going to drop it 2825 * and no bpf is active. 2826 */ 2827 if (!ifp->if_bpf && BDG_ACTIVE( (ifp) ) ) { 2828 struct ifnet *bif; 2829 2830 ed_ring_copy(sc, buf, (char *)eh, ETHER_HDR_LEN); 2831 bif = bridge_in_ptr(ifp, eh) ; 2832 if (bif == BDG_DROP) { 2833 m_freem(m); 2834 return; 2835 } 2836 if (len > ETHER_HDR_LEN) 2837 ed_ring_copy(sc, buf + ETHER_HDR_LEN, 2838 (char *)(eh + 1), len - ETHER_HDR_LEN); 2839 } else 2840 /* 2841 * Get packet, including link layer address, from interface. 2842 */ 2843 ed_ring_copy(sc, buf, (char *)eh, len); 2844 2845 m->m_pkthdr.len = m->m_len = len; 2846 2847 (*ifp->if_input)(ifp, m); 2848} 2849 2850/* 2851 * Supporting routines 2852 */ 2853 2854/* 2855 * Given a NIC memory source address and a host memory destination 2856 * address, copy 'amount' from NIC to host using Programmed I/O. 2857 * The 'amount' is rounded up to a word - okay as long as mbufs 2858 * are word sized. 2859 * This routine is currently Novell-specific. 2860 */ 2861void 2862ed_pio_readmem(sc, src, dst, amount) 2863 struct ed_softc *sc; 2864 int src; 2865 unsigned char *dst; 2866 unsigned short amount; 2867{ 2868 /* HP PC Lan+ cards need special handling */ 2869 if (sc->vendor == ED_VENDOR_HP && sc->type == ED_TYPE_HP_PCLANPLUS) { 2870 ed_hpp_readmem(sc, src, dst, amount); 2871 return; 2872 } 2873 2874 /* Regular Novell cards */ 2875 /* select page 0 registers */ 2876 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STA); 2877 2878 /* round up to a word */ 2879 if (amount & 1) 2880 ++amount; 2881 2882 /* set up DMA byte count */ 2883 ed_nic_outb(sc, ED_P0_RBCR0, amount); 2884 ed_nic_outb(sc, ED_P0_RBCR1, amount >> 8); 2885 2886 /* set up source address in NIC mem */ 2887 ed_nic_outb(sc, ED_P0_RSAR0, src); 2888 ed_nic_outb(sc, ED_P0_RSAR1, src >> 8); 2889 2890 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD0 | ED_CR_STA); 2891 2892 if (sc->isa16bit) { 2893 ed_asic_insw(sc, ED_NOVELL_DATA, dst, amount / 2); 2894 } else { 2895 ed_asic_insb(sc, ED_NOVELL_DATA, dst, amount); 2896 } 2897} 2898 2899/* 2900 * Stripped down routine for writing a linear buffer to NIC memory. 2901 * Only used in the probe routine to test the memory. 'len' must 2902 * be even. 2903 */ 2904void 2905ed_pio_writemem(sc, src, dst, len) 2906 struct ed_softc *sc; 2907 char *src; 2908 unsigned short dst; 2909 unsigned short len; 2910{ 2911 int maxwait = 200; /* about 240us */ 2912 2913 /* select page 0 registers */ 2914 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STA); 2915 2916 /* reset remote DMA complete flag */ 2917 ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC); 2918 2919 /* set up DMA byte count */ 2920 ed_nic_outb(sc, ED_P0_RBCR0, len); 2921 ed_nic_outb(sc, ED_P0_RBCR1, len >> 8); 2922 2923 /* set up destination address in NIC mem */ 2924 ed_nic_outb(sc, ED_P0_RSAR0, dst); 2925 ed_nic_outb(sc, ED_P0_RSAR1, dst >> 8); 2926 2927 /* set remote DMA write */ 2928 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD1 | ED_CR_STA); 2929 2930 if (sc->isa16bit) { 2931 ed_asic_outsw(sc, ED_NOVELL_DATA, src, len / 2); 2932 } else { 2933 ed_asic_outsb(sc, ED_NOVELL_DATA, src, len); 2934 } 2935 2936 /* 2937 * Wait for remote DMA complete. This is necessary because on the 2938 * transmit side, data is handled internally by the NIC in bursts and 2939 * we can't start another remote DMA until this one completes. Not 2940 * waiting causes really bad things to happen - like the NIC 2941 * irrecoverably jamming the ISA bus. 2942 */ 2943 while (((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait); 2944} 2945 2946/* 2947 * Write an mbuf chain to the destination NIC memory address using 2948 * programmed I/O. 2949 */ 2950static u_short 2951ed_pio_write_mbufs(sc, m, dst) 2952 struct ed_softc *sc; 2953 struct mbuf *m; 2954 int dst; 2955{ 2956 struct ifnet *ifp = (struct ifnet *)sc; 2957 unsigned short total_len, dma_len; 2958 struct mbuf *mp; 2959 int maxwait = 200; /* about 240us */ 2960 2961 /* HP PC Lan+ cards need special handling */ 2962 if (sc->vendor == ED_VENDOR_HP && sc->type == ED_TYPE_HP_PCLANPLUS) { 2963 return ed_hpp_write_mbufs(sc, m, dst); 2964 } 2965 2966 /* Regular Novell cards */ 2967 /* First, count up the total number of bytes to copy */ 2968 for (total_len = 0, mp = m; mp; mp = mp->m_next) 2969 total_len += mp->m_len; 2970 2971 dma_len = total_len; 2972 if (sc->isa16bit && (dma_len & 1)) 2973 dma_len++; 2974 2975 /* select page 0 registers */ 2976 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STA); 2977 2978 /* reset remote DMA complete flag */ 2979 ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC); 2980 2981 /* set up DMA byte count */ 2982 ed_nic_outb(sc, ED_P0_RBCR0, dma_len); 2983 ed_nic_outb(sc, ED_P0_RBCR1, dma_len >> 8); 2984 2985 /* set up destination address in NIC mem */ 2986 ed_nic_outb(sc, ED_P0_RSAR0, dst); 2987 ed_nic_outb(sc, ED_P0_RSAR1, dst >> 8); 2988 2989 /* set remote DMA write */ 2990 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD1 | ED_CR_STA); 2991 2992 /* 2993 * Transfer the mbuf chain to the NIC memory. 2994 * 16-bit cards require that data be transferred as words, and only words. 2995 * So that case requires some extra code to patch over odd-length mbufs. 2996 */ 2997 2998 if (!sc->isa16bit) { 2999 /* NE1000s are easy */ 3000 while (m) { 3001 if (m->m_len) { 3002 ed_asic_outsb(sc, ED_NOVELL_DATA, 3003 m->m_data, m->m_len); 3004 } 3005 m = m->m_next; 3006 } 3007 } else { 3008 /* NE2000s are a pain */ 3009 unsigned char *data; 3010 int len, wantbyte; 3011 unsigned char savebyte[2]; 3012 3013 wantbyte = 0; 3014 3015 while (m) { 3016 len = m->m_len; 3017 if (len) { 3018 data = mtod(m, caddr_t); 3019 /* finish the last word */ 3020 if (wantbyte) { 3021 savebyte[1] = *data; 3022 ed_asic_outw(sc, ED_NOVELL_DATA, 3023 *(u_short *)savebyte); 3024 data++; 3025 len--; 3026 wantbyte = 0; 3027 } 3028 /* output contiguous words */ 3029 if (len > 1) { 3030 ed_asic_outsw(sc, ED_NOVELL_DATA, 3031 data, len >> 1); 3032 data += len & ~1; 3033 len &= 1; 3034 } 3035 /* save last byte, if necessary */ 3036 if (len == 1) { 3037 savebyte[0] = *data; 3038 wantbyte = 1; 3039 } 3040 } 3041 m = m->m_next; 3042 } 3043 /* spit last byte */ 3044 if (wantbyte) { 3045 ed_asic_outw(sc, ED_NOVELL_DATA, *(u_short *)savebyte); 3046 } 3047 } 3048 3049 /* 3050 * Wait for remote DMA complete. This is necessary because on the 3051 * transmit side, data is handled internally by the NIC in bursts and 3052 * we can't start another remote DMA until this one completes. Not 3053 * waiting causes really bad things to happen - like the NIC 3054 * irrecoverably jamming the ISA bus. 3055 */ 3056 while (((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait); 3057 3058 if (!maxwait) { 3059 log(LOG_WARNING, "%s: remote transmit DMA failed to complete\n", 3060 ifp->if_xname); 3061 ed_reset(ifp); 3062 return(0); 3063 } 3064 return (total_len); 3065} 3066 3067/* 3068 * Support routines to handle the HP PC Lan+ card. 3069 */ 3070 3071/* 3072 * HP PC Lan+: Read from NIC memory, using either PIO or memory mapped 3073 * IO. 3074 */ 3075 3076static void 3077ed_hpp_readmem(sc, src, dst, amount) 3078 struct ed_softc *sc; 3079 unsigned short src; 3080 unsigned char *dst; 3081 unsigned short amount; 3082{ 3083 3084 int use_32bit_access = !(sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS); 3085 3086 3087 /* Program the source address in RAM */ 3088 ed_asic_outw(sc, ED_HPP_PAGE_2, src); 3089 3090 /* 3091 * The HP PC Lan+ card supports word reads as well as 3092 * a memory mapped i/o port that is aliased to every 3093 * even address on the board. 3094 */ 3095 3096 if (sc->hpp_mem_start) { 3097 3098 /* Enable memory mapped access. */ 3099 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options & 3100 ~(ED_HPP_OPTION_MEM_DISABLE | 3101 ED_HPP_OPTION_BOOT_ROM_ENB)); 3102 3103 if (use_32bit_access && (amount > 3)) { 3104 u_int32_t *dl = (u_int32_t *) dst; 3105 volatile u_int32_t *const sl = 3106 (u_int32_t *) sc->hpp_mem_start; 3107 u_int32_t *const fence = dl + (amount >> 2); 3108 3109 /* Copy out NIC data. We could probably write this 3110 as a `movsl'. The currently generated code is lousy. 3111 */ 3112 3113 while (dl < fence) 3114 *dl++ = *sl; 3115 3116 dst += (amount & ~3); 3117 amount &= 3; 3118 3119 } 3120 3121 /* Finish off any words left, as a series of short reads */ 3122 if (amount > 1) { 3123 u_short *d = (u_short *) dst; 3124 volatile u_short *const s = 3125 (u_short *) sc->hpp_mem_start; 3126 u_short *const fence = d + (amount >> 1); 3127 3128 /* Copy out NIC data. */ 3129 3130 while (d < fence) 3131 *d++ = *s; 3132 3133 dst += (amount & ~1); 3134 amount &= 1; 3135 } 3136 3137 /* 3138 * read in a byte; however we need to always read 16 bits 3139 * at a time or the hardware gets into a funny state 3140 */ 3141 3142 if (amount == 1) { 3143 /* need to read in a short and copy LSB */ 3144 volatile u_short *const s = 3145 (volatile u_short *) sc->hpp_mem_start; 3146 3147 *dst = (*s) & 0xFF; 3148 } 3149 3150 /* Restore Boot ROM access. */ 3151 3152 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options); 3153 3154 3155 } else { 3156 /* Read in data using the I/O port */ 3157 if (use_32bit_access && (amount > 3)) { 3158 ed_asic_insl(sc, ED_HPP_PAGE_4, dst, amount >> 2); 3159 dst += (amount & ~3); 3160 amount &= 3; 3161 } 3162 if (amount > 1) { 3163 ed_asic_insw(sc, ED_HPP_PAGE_4, dst, amount >> 1); 3164 dst += (amount & ~1); 3165 amount &= 1; 3166 } 3167 if (amount == 1) { /* read in a short and keep the LSB */ 3168 *dst = ed_asic_inw(sc, ED_HPP_PAGE_4) & 0xFF; 3169 } 3170 } 3171} 3172 3173/* 3174 * HP PC Lan+: Write to NIC memory, using either PIO or memory mapped 3175 * IO. 3176 * Only used in the probe routine to test the memory. 'len' must 3177 * be even. 3178 */ 3179static void 3180ed_hpp_writemem(sc, src, dst, len) 3181 struct ed_softc *sc; 3182 unsigned char *src; 3183 unsigned short dst; 3184 unsigned short len; 3185{ 3186 /* reset remote DMA complete flag */ 3187 ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC); 3188 3189 /* program the write address in RAM */ 3190 ed_asic_outw(sc, ED_HPP_PAGE_0, dst); 3191 3192 if (sc->hpp_mem_start) { 3193 u_short *s = (u_short *) src; 3194 volatile u_short *d = (u_short *) sc->hpp_mem_start; 3195 u_short *const fence = s + (len >> 1); 3196 3197 /* 3198 * Enable memory mapped access. 3199 */ 3200 3201 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options & 3202 ~(ED_HPP_OPTION_MEM_DISABLE | 3203 ED_HPP_OPTION_BOOT_ROM_ENB)); 3204 3205 /* 3206 * Copy to NIC memory. 3207 */ 3208 3209 while (s < fence) 3210 *d = *s++; 3211 3212 /* 3213 * Restore Boot ROM access. 3214 */ 3215 3216 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options); 3217 3218 } else { 3219 /* write data using I/O writes */ 3220 ed_asic_outsw(sc, ED_HPP_PAGE_4, src, len / 2); 3221 } 3222} 3223 3224/* 3225 * Write to HP PC Lan+ NIC memory. Access to the NIC can be by using 3226 * outsw() or via the memory mapped interface to the same register. 3227 * Writes have to be in word units; byte accesses won't work and may cause 3228 * the NIC to behave weirdly. Long word accesses are permitted if the ASIC 3229 * allows it. 3230 */ 3231 3232static u_short 3233ed_hpp_write_mbufs(struct ed_softc *sc, struct mbuf *m, int dst) 3234{ 3235 int len, wantbyte; 3236 unsigned short total_len; 3237 unsigned char savebyte[2]; 3238 volatile u_short * const d = 3239 (volatile u_short *) sc->hpp_mem_start; 3240 int use_32bit_accesses = !(sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS); 3241 3242 /* select page 0 registers */ 3243 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA); 3244 3245 /* reset remote DMA complete flag */ 3246 ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC); 3247 3248 /* program the write address in RAM */ 3249 ed_asic_outw(sc, ED_HPP_PAGE_0, dst); 3250 3251 if (sc->hpp_mem_start) /* enable memory mapped I/O */ 3252 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options & 3253 ~(ED_HPP_OPTION_MEM_DISABLE | 3254 ED_HPP_OPTION_BOOT_ROM_ENB)); 3255 3256 wantbyte = 0; 3257 total_len = 0; 3258 3259 if (sc->hpp_mem_start) { /* Memory mapped I/O port */ 3260 while (m) { 3261 total_len += (len = m->m_len); 3262 if (len) { 3263 caddr_t data = mtod(m, caddr_t); 3264 /* finish the last word of the previous mbuf */ 3265 if (wantbyte) { 3266 savebyte[1] = *data; 3267 *d = *((u_short *) savebyte); 3268 data++; len--; wantbyte = 0; 3269 } 3270 /* output contiguous words */ 3271 if ((len > 3) && (use_32bit_accesses)) { 3272 volatile u_int32_t *const dl = 3273 (volatile u_int32_t *) d; 3274 u_int32_t *sl = (u_int32_t *) data; 3275 u_int32_t *fence = sl + (len >> 2); 3276 3277 while (sl < fence) 3278 *dl = *sl++; 3279 3280 data += (len & ~3); 3281 len &= 3; 3282 } 3283 /* finish off remain 16 bit writes */ 3284 if (len > 1) { 3285 u_short *s = (u_short *) data; 3286 u_short *fence = s + (len >> 1); 3287 3288 while (s < fence) 3289 *d = *s++; 3290 3291 data += (len & ~1); 3292 len &= 1; 3293 } 3294 /* save last byte if needed */ 3295 if ((wantbyte = (len == 1)) != 0) 3296 savebyte[0] = *data; 3297 } 3298 m = m->m_next; /* to next mbuf */ 3299 } 3300 if (wantbyte) /* write last byte */ 3301 *d = *((u_short *) savebyte); 3302 } else { 3303 /* use programmed I/O */ 3304 while (m) { 3305 total_len += (len = m->m_len); 3306 if (len) { 3307 caddr_t data = mtod(m, caddr_t); 3308 /* finish the last word of the previous mbuf */ 3309 if (wantbyte) { 3310 savebyte[1] = *data; 3311 ed_asic_outw(sc, ED_HPP_PAGE_4, 3312 *((u_short *)savebyte)); 3313 data++; 3314 len--; 3315 wantbyte = 0; 3316 } 3317 /* output contiguous words */ 3318 if ((len > 3) && use_32bit_accesses) { 3319 ed_asic_outsl(sc, ED_HPP_PAGE_4, 3320 data, len >> 2); 3321 data += (len & ~3); 3322 len &= 3; 3323 } 3324 /* finish off remaining 16 bit accesses */ 3325 if (len > 1) { 3326 ed_asic_outsw(sc, ED_HPP_PAGE_4, 3327 data, len >> 1); 3328 data += (len & ~1); 3329 len &= 1; 3330 } 3331 if ((wantbyte = (len == 1)) != 0) 3332 savebyte[0] = *data; 3333 3334 } /* if len != 0 */ 3335 m = m->m_next; 3336 } 3337 if (wantbyte) /* spit last byte */ 3338 ed_asic_outw(sc, ED_HPP_PAGE_4, *(u_short *)savebyte); 3339 3340 } 3341 3342 if (sc->hpp_mem_start) /* turn off memory mapped i/o */ 3343 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options); 3344 3345 return (total_len); 3346} 3347 3348#ifndef ED_NO_MIIBUS 3349/* 3350 * MII bus support routines. 3351 */ 3352int 3353ed_miibus_readreg(dev, phy, reg) 3354 device_t dev; 3355 int phy, reg; 3356{ 3357 struct ed_softc *sc; 3358 int failed, s, val; 3359 3360 s = splimp(); 3361 sc = device_get_softc(dev); 3362 if (sc->gone) { 3363 splx(s); 3364 return (0); 3365 } 3366 3367 (*sc->mii_writebits)(sc, 0xffffffff, 32); 3368 (*sc->mii_writebits)(sc, ED_MII_STARTDELIM, ED_MII_STARTDELIM_BITS); 3369 (*sc->mii_writebits)(sc, ED_MII_READOP, ED_MII_OP_BITS); 3370 (*sc->mii_writebits)(sc, phy, ED_MII_PHY_BITS); 3371 (*sc->mii_writebits)(sc, reg, ED_MII_REG_BITS); 3372 3373 failed = (*sc->mii_readbits)(sc, ED_MII_ACK_BITS); 3374 val = (*sc->mii_readbits)(sc, ED_MII_DATA_BITS); 3375 (*sc->mii_writebits)(sc, ED_MII_IDLE, ED_MII_IDLE_BITS); 3376 3377 splx(s); 3378 return (failed ? 0 : val); 3379} 3380 3381void 3382ed_miibus_writereg(dev, phy, reg, data) 3383 device_t dev; 3384 int phy, reg, data; 3385{ 3386 struct ed_softc *sc; 3387 int s; 3388 3389 s = splimp(); 3390 sc = device_get_softc(dev); 3391 if (sc->gone) { 3392 splx(s); 3393 return; 3394 } 3395 3396 (*sc->mii_writebits)(sc, 0xffffffff, 32); 3397 (*sc->mii_writebits)(sc, ED_MII_STARTDELIM, ED_MII_STARTDELIM_BITS); 3398 (*sc->mii_writebits)(sc, ED_MII_WRITEOP, ED_MII_OP_BITS); 3399 (*sc->mii_writebits)(sc, phy, ED_MII_PHY_BITS); 3400 (*sc->mii_writebits)(sc, reg, ED_MII_REG_BITS); 3401 (*sc->mii_writebits)(sc, ED_MII_TURNAROUND, ED_MII_TURNAROUND_BITS); 3402 (*sc->mii_writebits)(sc, data, ED_MII_DATA_BITS); 3403 (*sc->mii_writebits)(sc, ED_MII_IDLE, ED_MII_IDLE_BITS); 3404 3405 splx(s); 3406} 3407 3408int 3409ed_ifmedia_upd(ifp) 3410 struct ifnet *ifp; 3411{ 3412 struct ed_softc *sc; 3413 struct mii_data *mii; 3414 3415 sc = ifp->if_softc; 3416 if (sc->gone || sc->miibus == NULL) 3417 return (ENXIO); 3418 3419 mii = device_get_softc(sc->miibus); 3420 return mii_mediachg(mii); 3421} 3422 3423void 3424ed_ifmedia_sts(ifp, ifmr) 3425 struct ifnet *ifp; 3426 struct ifmediareq *ifmr; 3427{ 3428 struct ed_softc *sc; 3429 struct mii_data *mii; 3430 3431 sc = ifp->if_softc; 3432 if (sc->gone || sc->miibus == NULL) 3433 return; 3434 3435 mii = device_get_softc(sc->miibus); 3436 mii_pollstat(mii); 3437 ifmr->ifm_active = mii->mii_media_active; 3438 ifmr->ifm_status = mii->mii_media_status; 3439} 3440 3441void 3442ed_child_detached(dev, child) 3443 device_t dev; 3444 device_t child; 3445{ 3446 struct ed_softc *sc; 3447 3448 sc = device_get_softc(dev); 3449 if (child == sc->miibus) 3450 sc->miibus = NULL; 3451} 3452#endif 3453 3454static void 3455ed_setrcr(sc) 3456 struct ed_softc *sc; 3457{ 3458 struct ifnet *ifp = (struct ifnet *)sc; 3459 int i; 3460 u_char reg1; 3461 3462 /* Bit 6 in AX88190 RCR register must be set. */ 3463 if (sc->chip_type == ED_CHIP_TYPE_AX88190) 3464 reg1 = ED_RCR_INTT; 3465 else 3466 reg1 = 0x00; 3467 3468 /* set page 1 registers */ 3469 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP); 3470 3471 if (ifp->if_flags & IFF_PROMISC) { 3472 3473 /* 3474 * Reconfigure the multicast filter. 3475 */ 3476 for (i = 0; i < 8; i++) 3477 ed_nic_outb(sc, ED_P1_MAR(i), 0xff); 3478 3479 /* 3480 * And turn on promiscuous mode. Also enable reception of 3481 * runts and packets with CRC & alignment errors. 3482 */ 3483 /* Set page 0 registers */ 3484 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP); 3485 3486 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_PRO | ED_RCR_AM | 3487 ED_RCR_AB | ED_RCR_AR | ED_RCR_SEP | reg1); 3488 } else { 3489 /* set up multicast addresses and filter modes */ 3490 if (ifp->if_flags & IFF_MULTICAST) { 3491 u_int32_t mcaf[2]; 3492 3493 if (ifp->if_flags & IFF_ALLMULTI) { 3494 mcaf[0] = 0xffffffff; 3495 mcaf[1] = 0xffffffff; 3496 } else 3497 ds_getmcaf(sc, mcaf); 3498 3499 /* 3500 * Set multicast filter on chip. 3501 */ 3502 for (i = 0; i < 8; i++) 3503 ed_nic_outb(sc, ED_P1_MAR(i), ((u_char *) mcaf)[i]); 3504 3505 /* Set page 0 registers */ 3506 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP); 3507 3508 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_AM | ED_RCR_AB | reg1); 3509 } else { 3510 3511 /* 3512 * Initialize multicast address hashing registers to 3513 * not accept multicasts. 3514 */ 3515 for (i = 0; i < 8; ++i) 3516 ed_nic_outb(sc, ED_P1_MAR(i), 0x00); 3517 3518 /* Set page 0 registers */ 3519 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP); 3520 3521 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_AB | reg1); 3522 } 3523 } 3524 3525 /* 3526 * Start interface. 3527 */ 3528 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA); 3529} 3530 3531/* 3532 * Compute crc for ethernet address 3533 */ 3534static uint32_t 3535ds_mchash(addr) 3536 const uint8_t *addr; 3537{ 3538#define ED_POLYNOMIAL 0x04c11db6 3539 register uint32_t crc = 0xffffffff; 3540 register int carry, idx, bit; 3541 register uint8_t data; 3542 3543 for (idx = 6; --idx >= 0;) { 3544 for (data = *addr++, bit = 8; --bit >= 0; data >>=1 ) { 3545 carry = ((crc & 0x80000000) ? 1 : 0) ^ (data & 0x01); 3546 crc <<= 1; 3547 if (carry) 3548 crc = (crc ^ ED_POLYNOMIAL) | carry; 3549 } 3550 } 3551 return crc; 3552#undef POLYNOMIAL 3553} 3554 3555/* 3556 * Compute the multicast address filter from the 3557 * list of multicast addresses we need to listen to. 3558 */ 3559static void 3560ds_getmcaf(sc, mcaf) 3561 struct ed_softc *sc; 3562 u_int32_t *mcaf; 3563{ 3564 register u_int32_t index; 3565 register u_char *af = (u_char *) mcaf; 3566 struct ifmultiaddr *ifma; 3567 3568 mcaf[0] = 0; 3569 mcaf[1] = 0; 3570 3571 TAILQ_FOREACH(ifma, &sc->arpcom.ac_if.if_multiaddrs, ifma_link) { 3572 if (ifma->ifma_addr->sa_family != AF_LINK) 3573 continue; 3574 index = ds_mchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)) 3575 >> 26; 3576 af[index >> 3] |= 1 << (index & 7); 3577 } 3578} 3579