e1000_82571.c revision 194865
1/****************************************************************************** 2 3 Copyright (c) 2001-2009, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ 33/*$FreeBSD: head/sys/dev/e1000/e1000_82571.c 194865 2009-06-24 17:41:29Z jfv $*/ 34 35/* 36 * 82571EB Gigabit Ethernet Controller 37 * 82571EB Gigabit Ethernet Controller (Copper) 38 * 82571EB Gigabit Ethernet Controller (Fiber) 39 * 82571EB Dual Port Gigabit Mezzanine Adapter 40 * 82571EB Quad Port Gigabit Mezzanine Adapter 41 * 82571PT Gigabit PT Quad Port Server ExpressModule 42 * 82572EI Gigabit Ethernet Controller (Copper) 43 * 82572EI Gigabit Ethernet Controller (Fiber) 44 * 82572EI Gigabit Ethernet Controller 45 * 82573V Gigabit Ethernet Controller (Copper) 46 * 82573E Gigabit Ethernet Controller (Copper) 47 * 82573L Gigabit Ethernet Controller 48 * 82574L Gigabit Network Connection 49 * 82574L Gigabit Network Connection 50 * 82583V Gigabit Network Connection 51 */ 52 53#include "e1000_api.h" 54 55static s32 e1000_init_phy_params_82571(struct e1000_hw *hw); 56static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw); 57static s32 e1000_init_mac_params_82571(struct e1000_hw *hw); 58static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw); 59static void e1000_release_nvm_82571(struct e1000_hw *hw); 60static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, 61 u16 words, u16 *data); 62static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw); 63static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw); 64static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw); 65static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, 66 bool active); 67static s32 e1000_reset_hw_82571(struct e1000_hw *hw); 68static s32 e1000_init_hw_82571(struct e1000_hw *hw); 69static void e1000_clear_vfta_82571(struct e1000_hw *hw); 70static bool e1000_check_mng_mode_82574(struct e1000_hw *hw); 71static s32 e1000_led_on_82574(struct e1000_hw *hw); 72static s32 e1000_setup_link_82571(struct e1000_hw *hw); 73static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw); 74static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw); 75static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw); 76static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data); 77static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw); 78static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw); 79static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw); 80static s32 e1000_get_phy_id_82571(struct e1000_hw *hw); 81static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw); 82static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw); 83static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, 84 u16 words, u16 *data); 85static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw); 86static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw); 87 88/** 89 * e1000_init_phy_params_82571 - Init PHY func ptrs. 90 * @hw: pointer to the HW structure 91 **/ 92static s32 e1000_init_phy_params_82571(struct e1000_hw *hw) 93{ 94 struct e1000_phy_info *phy = &hw->phy; 95 s32 ret_val = E1000_SUCCESS; 96 97 DEBUGFUNC("e1000_init_phy_params_82571"); 98 99 if (hw->phy.media_type != e1000_media_type_copper) { 100 phy->type = e1000_phy_none; 101 goto out; 102 } 103 104 phy->addr = 1; 105 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 106 phy->reset_delay_us = 100; 107 108 phy->ops.acquire = e1000_get_hw_semaphore_82571; 109 phy->ops.check_polarity = e1000_check_polarity_igp; 110 phy->ops.check_reset_block = e1000_check_reset_block_generic; 111 phy->ops.release = e1000_put_hw_semaphore_82571; 112 phy->ops.reset = e1000_phy_hw_reset_generic; 113 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82571; 114 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic; 115 phy->ops.power_up = e1000_power_up_phy_copper; 116 phy->ops.power_down = e1000_power_down_phy_copper_82571; 117 118 switch (hw->mac.type) { 119 case e1000_82571: 120 case e1000_82572: 121 phy->type = e1000_phy_igp_2; 122 phy->ops.get_cfg_done = e1000_get_cfg_done_82571; 123 phy->ops.get_info = e1000_get_phy_info_igp; 124 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp; 125 phy->ops.get_cable_length = e1000_get_cable_length_igp_2; 126 phy->ops.read_reg = e1000_read_phy_reg_igp; 127 phy->ops.write_reg = e1000_write_phy_reg_igp; 128 129 /* This uses above function pointers */ 130 ret_val = e1000_get_phy_id_82571(hw); 131 132 /* Verify PHY ID */ 133 if (phy->id != IGP01E1000_I_PHY_ID) { 134 ret_val = -E1000_ERR_PHY; 135 goto out; 136 } 137 break; 138 case e1000_82573: 139 phy->type = e1000_phy_m88; 140 phy->ops.get_cfg_done = e1000_get_cfg_done_generic; 141 phy->ops.get_info = e1000_get_phy_info_m88; 142 phy->ops.commit = e1000_phy_sw_reset_generic; 143 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; 144 phy->ops.get_cable_length = e1000_get_cable_length_m88; 145 phy->ops.read_reg = e1000_read_phy_reg_m88; 146 phy->ops.write_reg = e1000_write_phy_reg_m88; 147 148 /* This uses above function pointers */ 149 ret_val = e1000_get_phy_id_82571(hw); 150 151 /* Verify PHY ID */ 152 if (phy->id != M88E1111_I_PHY_ID) { 153 ret_val = -E1000_ERR_PHY; 154 DEBUGOUT1("PHY ID unknown: type = 0x%08x\n", phy->id); 155 goto out; 156 } 157 break; 158 case e1000_82583: 159 case e1000_82574: 160 phy->type = e1000_phy_bm; 161 phy->ops.get_cfg_done = e1000_get_cfg_done_generic; 162 phy->ops.get_info = e1000_get_phy_info_m88; 163 phy->ops.commit = e1000_phy_sw_reset_generic; 164 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; 165 phy->ops.get_cable_length = e1000_get_cable_length_m88; 166 phy->ops.read_reg = e1000_read_phy_reg_bm2; 167 phy->ops.write_reg = e1000_write_phy_reg_bm2; 168 169 /* This uses above function pointers */ 170 ret_val = e1000_get_phy_id_82571(hw); 171 /* Verify PHY ID */ 172 if (phy->id != BME1000_E_PHY_ID_R2) { 173 ret_val = -E1000_ERR_PHY; 174 DEBUGOUT1("PHY ID unknown: type = 0x%08x\n", phy->id); 175 goto out; 176 } 177 break; 178 default: 179 ret_val = -E1000_ERR_PHY; 180 goto out; 181 break; 182 } 183 184out: 185 return ret_val; 186} 187 188/** 189 * e1000_init_nvm_params_82571 - Init NVM func ptrs. 190 * @hw: pointer to the HW structure 191 **/ 192static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw) 193{ 194 struct e1000_nvm_info *nvm = &hw->nvm; 195 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 196 u16 size; 197 198 DEBUGFUNC("e1000_init_nvm_params_82571"); 199 200 nvm->opcode_bits = 8; 201 nvm->delay_usec = 1; 202 switch (nvm->override) { 203 case e1000_nvm_override_spi_large: 204 nvm->page_size = 32; 205 nvm->address_bits = 16; 206 break; 207 case e1000_nvm_override_spi_small: 208 nvm->page_size = 8; 209 nvm->address_bits = 8; 210 break; 211 default: 212 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; 213 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; 214 break; 215 } 216 217 switch (hw->mac.type) { 218 case e1000_82573: 219 case e1000_82574: 220 case e1000_82583: 221 if (((eecd >> 15) & 0x3) == 0x3) { 222 nvm->type = e1000_nvm_flash_hw; 223 nvm->word_size = 2048; 224 /* 225 * Autonomous Flash update bit must be cleared due 226 * to Flash update issue. 227 */ 228 eecd &= ~E1000_EECD_AUPDEN; 229 E1000_WRITE_REG(hw, E1000_EECD, eecd); 230 break; 231 } 232 /* Fall Through */ 233 default: 234 nvm->type = e1000_nvm_eeprom_spi; 235 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> 236 E1000_EECD_SIZE_EX_SHIFT); 237 /* 238 * Added to a constant, "size" becomes the left-shift value 239 * for setting word_size. 240 */ 241 size += NVM_WORD_SIZE_BASE_SHIFT; 242 243 /* EEPROM access above 16k is unsupported */ 244 if (size > 14) 245 size = 14; 246 nvm->word_size = 1 << size; 247 break; 248 } 249 250 /* Function Pointers */ 251 nvm->ops.acquire = e1000_acquire_nvm_82571; 252 nvm->ops.read = e1000_read_nvm_eerd; 253 nvm->ops.release = e1000_release_nvm_82571; 254 nvm->ops.update = e1000_update_nvm_checksum_82571; 255 nvm->ops.validate = e1000_validate_nvm_checksum_82571; 256 nvm->ops.valid_led_default = e1000_valid_led_default_82571; 257 nvm->ops.write = e1000_write_nvm_82571; 258 259 return E1000_SUCCESS; 260} 261 262/** 263 * e1000_init_mac_params_82571 - Init MAC func ptrs. 264 * @hw: pointer to the HW structure 265 **/ 266static s32 e1000_init_mac_params_82571(struct e1000_hw *hw) 267{ 268 struct e1000_mac_info *mac = &hw->mac; 269 s32 ret_val = E1000_SUCCESS; 270 u32 swsm = 0; 271 u32 swsm2 = 0; 272 bool force_clear_smbi = FALSE; 273 274 DEBUGFUNC("e1000_init_mac_params_82571"); 275 276 /* Set media type */ 277 switch (hw->device_id) { 278 case E1000_DEV_ID_82571EB_FIBER: 279 case E1000_DEV_ID_82572EI_FIBER: 280 case E1000_DEV_ID_82571EB_QUAD_FIBER: 281 hw->phy.media_type = e1000_media_type_fiber; 282 break; 283 case E1000_DEV_ID_82571EB_SERDES: 284 case E1000_DEV_ID_82571EB_SERDES_DUAL: 285 case E1000_DEV_ID_82571EB_SERDES_QUAD: 286 case E1000_DEV_ID_82572EI_SERDES: 287 hw->phy.media_type = e1000_media_type_internal_serdes; 288 break; 289 default: 290 hw->phy.media_type = e1000_media_type_copper; 291 break; 292 } 293 294 /* Set mta register count */ 295 mac->mta_reg_count = 128; 296 /* Set rar entry count */ 297 mac->rar_entry_count = E1000_RAR_ENTRIES; 298 /* Set if part includes ASF firmware */ 299 mac->asf_firmware_present = TRUE; 300 /* Set if manageability features are enabled. */ 301 mac->arc_subsystem_valid = 302 (E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK) 303 ? TRUE : FALSE; 304 305 /* Function pointers */ 306 307 /* bus type/speed/width */ 308 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic; 309 /* function id */ 310 switch (hw->mac.type) { 311 case e1000_82573: 312 case e1000_82574: 313 case e1000_82583: 314 mac->ops.set_lan_id = e1000_set_lan_id_single_port; 315 break; 316 default: 317 break; 318 } 319 /* reset */ 320 mac->ops.reset_hw = e1000_reset_hw_82571; 321 /* hw initialization */ 322 mac->ops.init_hw = e1000_init_hw_82571; 323 /* link setup */ 324 mac->ops.setup_link = e1000_setup_link_82571; 325 /* physical interface link setup */ 326 mac->ops.setup_physical_interface = 327 (hw->phy.media_type == e1000_media_type_copper) 328 ? e1000_setup_copper_link_82571 329 : e1000_setup_fiber_serdes_link_82571; 330 /* check for link */ 331 switch (hw->phy.media_type) { 332 case e1000_media_type_copper: 333 mac->ops.check_for_link = e1000_check_for_copper_link_generic; 334 break; 335 case e1000_media_type_fiber: 336 mac->ops.check_for_link = e1000_check_for_fiber_link_generic; 337 break; 338 case e1000_media_type_internal_serdes: 339 mac->ops.check_for_link = e1000_check_for_serdes_link_82571; 340 break; 341 default: 342 ret_val = -E1000_ERR_CONFIG; 343 goto out; 344 break; 345 } 346 /* check management mode */ 347 switch (hw->mac.type) { 348 case e1000_82574: 349 case e1000_82583: 350 mac->ops.check_mng_mode = e1000_check_mng_mode_82574; 351 break; 352 default: 353 mac->ops.check_mng_mode = e1000_check_mng_mode_generic; 354 break; 355 } 356 /* multicast address update */ 357 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; 358 /* writing VFTA */ 359 mac->ops.write_vfta = e1000_write_vfta_generic; 360 /* clearing VFTA */ 361 mac->ops.clear_vfta = e1000_clear_vfta_82571; 362 /* setting MTA */ 363 mac->ops.mta_set = e1000_mta_set_generic; 364 /* read mac address */ 365 mac->ops.read_mac_addr = e1000_read_mac_addr_82571; 366 /* ID LED init */ 367 mac->ops.id_led_init = e1000_id_led_init_generic; 368 /* blink LED */ 369 mac->ops.blink_led = e1000_blink_led_generic; 370 /* setup LED */ 371 mac->ops.setup_led = e1000_setup_led_generic; 372 /* cleanup LED */ 373 mac->ops.cleanup_led = e1000_cleanup_led_generic; 374 /* turn on/off LED */ 375 switch (hw->mac.type) { 376 case e1000_82574: 377 case e1000_82583: 378 mac->ops.led_on = e1000_led_on_82574; 379 break; 380 default: 381 mac->ops.led_on = e1000_led_on_generic; 382 break; 383 } 384 mac->ops.led_off = e1000_led_off_generic; 385 /* clear hardware counters */ 386 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82571; 387 /* link info */ 388 mac->ops.get_link_up_info = 389 (hw->phy.media_type == e1000_media_type_copper) 390 ? e1000_get_speed_and_duplex_copper_generic 391 : e1000_get_speed_and_duplex_fiber_serdes_generic; 392 393 /* 394 * Ensure that the inter-port SWSM.SMBI lock bit is clear before 395 * first NVM or PHY acess. This should be done for single-port 396 * devices, and for one port only on dual-port devices so that 397 * for those devices we can still use the SMBI lock to synchronize 398 * inter-port accesses to the PHY & NVM. 399 */ 400 switch (hw->mac.type) { 401 case e1000_82571: 402 case e1000_82572: 403 swsm2 = E1000_READ_REG(hw, E1000_SWSM2); 404 405 if (!(swsm2 & E1000_SWSM2_LOCK)) { 406 /* Only do this for the first interface on this card */ 407 E1000_WRITE_REG(hw, E1000_SWSM2, 408 swsm2 | E1000_SWSM2_LOCK); 409 force_clear_smbi = TRUE; 410 } else 411 force_clear_smbi = FALSE; 412 break; 413 default: 414 force_clear_smbi = TRUE; 415 break; 416 } 417 418 if (force_clear_smbi) { 419 /* Make sure SWSM.SMBI is clear */ 420 swsm = E1000_READ_REG(hw, E1000_SWSM); 421 if (swsm & E1000_SWSM_SMBI) { 422 /* This bit should not be set on a first interface, and 423 * indicates that the bootagent or EFI code has 424 * improperly left this bit enabled 425 */ 426 DEBUGOUT("Please update your 82571 Bootagent\n"); 427 } 428 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_SMBI); 429 } 430 431 /* 432 * Initialze device specific counter of SMBI acquisition 433 * timeouts. 434 */ 435 hw->dev_spec._82571.smb_counter = 0; 436 437out: 438 return ret_val; 439} 440 441/** 442 * e1000_init_function_pointers_82571 - Init func ptrs. 443 * @hw: pointer to the HW structure 444 * 445 * Called to initialize all function pointers and parameters. 446 **/ 447void e1000_init_function_pointers_82571(struct e1000_hw *hw) 448{ 449 DEBUGFUNC("e1000_init_function_pointers_82571"); 450 451 hw->mac.ops.init_params = e1000_init_mac_params_82571; 452 hw->nvm.ops.init_params = e1000_init_nvm_params_82571; 453 hw->phy.ops.init_params = e1000_init_phy_params_82571; 454} 455 456/** 457 * e1000_get_phy_id_82571 - Retrieve the PHY ID and revision 458 * @hw: pointer to the HW structure 459 * 460 * Reads the PHY registers and stores the PHY ID and possibly the PHY 461 * revision in the hardware structure. 462 **/ 463static s32 e1000_get_phy_id_82571(struct e1000_hw *hw) 464{ 465 struct e1000_phy_info *phy = &hw->phy; 466 s32 ret_val = E1000_SUCCESS; 467 u16 phy_id = 0; 468 469 DEBUGFUNC("e1000_get_phy_id_82571"); 470 471 switch (hw->mac.type) { 472 case e1000_82571: 473 case e1000_82572: 474 /* 475 * The 82571 firmware may still be configuring the PHY. 476 * In this case, we cannot access the PHY until the 477 * configuration is done. So we explicitly set the 478 * PHY ID. 479 */ 480 phy->id = IGP01E1000_I_PHY_ID; 481 break; 482 case e1000_82573: 483 ret_val = e1000_get_phy_id(hw); 484 break; 485 case e1000_82574: 486 case e1000_82583: 487 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id); 488 if (ret_val) 489 goto out; 490 491 phy->id = (u32)(phy_id << 16); 492 usec_delay(20); 493 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id); 494 if (ret_val) 495 goto out; 496 497 phy->id |= (u32)(phy_id); 498 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); 499 break; 500 default: 501 ret_val = -E1000_ERR_PHY; 502 break; 503 } 504 505out: 506 return ret_val; 507} 508 509/** 510 * e1000_get_hw_semaphore_82571 - Acquire hardware semaphore 511 * @hw: pointer to the HW structure 512 * 513 * Acquire the HW semaphore to access the PHY or NVM 514 **/ 515s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw) 516{ 517 u32 swsm; 518 s32 ret_val = E1000_SUCCESS; 519 s32 sw_timeout = hw->nvm.word_size + 1; 520 s32 fw_timeout = hw->nvm.word_size + 1; 521 s32 i = 0; 522 523 DEBUGFUNC("e1000_get_hw_semaphore_82571"); 524 525 /* 526 * If we have timedout 3 times on trying to acquire 527 * the inter-port SMBI semaphore, there is old code 528 * operating on the other port, and it is not 529 * releasing SMBI. Modify the number of times that 530 * we try for the semaphore to interwork with this 531 * older code. 532 */ 533 if (hw->dev_spec._82571.smb_counter > 2) 534 sw_timeout = 1; 535 536 /* Get the SW semaphore */ 537 while (i < sw_timeout) { 538 swsm = E1000_READ_REG(hw, E1000_SWSM); 539 if (!(swsm & E1000_SWSM_SMBI)) 540 break; 541 542 usec_delay(50); 543 i++; 544 } 545 546 if (i == sw_timeout) { 547 DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); 548 hw->dev_spec._82571.smb_counter++; 549 } 550 /* Get the FW semaphore. */ 551 for (i = 0; i < fw_timeout; i++) { 552 swsm = E1000_READ_REG(hw, E1000_SWSM); 553 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI); 554 555 /* Semaphore acquired if bit latched */ 556 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI) 557 break; 558 559 usec_delay(50); 560 } 561 562 if (i == fw_timeout) { 563 /* Release semaphores */ 564 e1000_put_hw_semaphore_82571(hw); 565 DEBUGOUT("Driver can't access the NVM\n"); 566 ret_val = -E1000_ERR_NVM; 567 goto out; 568 } 569 570out: 571 return ret_val; 572} 573 574/** 575 * e1000_put_hw_semaphore_82571 - Release hardware semaphore 576 * @hw: pointer to the HW structure 577 * 578 * Release hardware semaphore used to access the PHY or NVM 579 **/ 580void e1000_put_hw_semaphore_82571(struct e1000_hw *hw) 581{ 582 u32 swsm; 583 584 DEBUGFUNC("e1000_put_hw_semaphore_generic"); 585 586 swsm = E1000_READ_REG(hw, E1000_SWSM); 587 588 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); 589 590 E1000_WRITE_REG(hw, E1000_SWSM, swsm); 591} 592 593/** 594 * e1000_acquire_nvm_82571 - Request for access to the EEPROM 595 * @hw: pointer to the HW structure 596 * 597 * To gain access to the EEPROM, first we must obtain a hardware semaphore. 598 * Then for non-82573 hardware, set the EEPROM access request bit and wait 599 * for EEPROM access grant bit. If the access grant bit is not set, release 600 * hardware semaphore. 601 **/ 602static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw) 603{ 604 s32 ret_val; 605 606 DEBUGFUNC("e1000_acquire_nvm_82571"); 607 608 ret_val = e1000_get_hw_semaphore_82571(hw); 609 if (ret_val) 610 goto out; 611 612 switch (hw->mac.type) { 613 case e1000_82574: 614 case e1000_82583: 615 case e1000_82573: 616 break; 617 default: 618 ret_val = e1000_acquire_nvm_generic(hw); 619 break; 620 } 621 622 if (ret_val) 623 e1000_put_hw_semaphore_82571(hw); 624 625out: 626 return ret_val; 627} 628 629/** 630 * e1000_release_nvm_82571 - Release exclusive access to EEPROM 631 * @hw: pointer to the HW structure 632 * 633 * Stop any current commands to the EEPROM and clear the EEPROM request bit. 634 **/ 635static void e1000_release_nvm_82571(struct e1000_hw *hw) 636{ 637 DEBUGFUNC("e1000_release_nvm_82571"); 638 639 e1000_release_nvm_generic(hw); 640 e1000_put_hw_semaphore_82571(hw); 641} 642 643/** 644 * e1000_write_nvm_82571 - Write to EEPROM using appropriate interface 645 * @hw: pointer to the HW structure 646 * @offset: offset within the EEPROM to be written to 647 * @words: number of words to write 648 * @data: 16 bit word(s) to be written to the EEPROM 649 * 650 * For non-82573 silicon, write data to EEPROM at offset using SPI interface. 651 * 652 * If e1000_update_nvm_checksum is not called after this function, the 653 * EEPROM will most likely contain an invalid checksum. 654 **/ 655static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words, 656 u16 *data) 657{ 658 s32 ret_val = E1000_SUCCESS; 659 660 DEBUGFUNC("e1000_write_nvm_82571"); 661 662 switch (hw->mac.type) { 663 case e1000_82573: 664 case e1000_82574: 665 case e1000_82583: 666 ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data); 667 break; 668 case e1000_82571: 669 case e1000_82572: 670 ret_val = e1000_write_nvm_spi(hw, offset, words, data); 671 break; 672 default: 673 ret_val = -E1000_ERR_NVM; 674 break; 675 } 676 677 return ret_val; 678} 679 680/** 681 * e1000_update_nvm_checksum_82571 - Update EEPROM checksum 682 * @hw: pointer to the HW structure 683 * 684 * Updates the EEPROM checksum by reading/adding each word of the EEPROM 685 * up to the checksum. Then calculates the EEPROM checksum and writes the 686 * value to the EEPROM. 687 **/ 688static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw) 689{ 690 u32 eecd; 691 s32 ret_val; 692 u16 i; 693 694 DEBUGFUNC("e1000_update_nvm_checksum_82571"); 695 696 ret_val = e1000_update_nvm_checksum_generic(hw); 697 if (ret_val) 698 goto out; 699 700 /* 701 * If our nvm is an EEPROM, then we're done 702 * otherwise, commit the checksum to the flash NVM. 703 */ 704 if (hw->nvm.type != e1000_nvm_flash_hw) 705 goto out; 706 707 /* Check for pending operations. */ 708 for (i = 0; i < E1000_FLASH_UPDATES; i++) { 709 msec_delay(1); 710 if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD) == 0) 711 break; 712 } 713 714 if (i == E1000_FLASH_UPDATES) { 715 ret_val = -E1000_ERR_NVM; 716 goto out; 717 } 718 719 /* Reset the firmware if using STM opcode. */ 720 if ((E1000_READ_REG(hw, E1000_FLOP) & 0xFF00) == E1000_STM_OPCODE) { 721 /* 722 * The enabling of and the actual reset must be done 723 * in two write cycles. 724 */ 725 E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET_ENABLE); 726 E1000_WRITE_FLUSH(hw); 727 E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET); 728 } 729 730 /* Commit the write to flash */ 731 eecd = E1000_READ_REG(hw, E1000_EECD) | E1000_EECD_FLUPD; 732 E1000_WRITE_REG(hw, E1000_EECD, eecd); 733 734 for (i = 0; i < E1000_FLASH_UPDATES; i++) { 735 msec_delay(1); 736 if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD) == 0) 737 break; 738 } 739 740 if (i == E1000_FLASH_UPDATES) { 741 ret_val = -E1000_ERR_NVM; 742 goto out; 743 } 744 745out: 746 return ret_val; 747} 748 749/** 750 * e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum 751 * @hw: pointer to the HW structure 752 * 753 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM 754 * and then verifies that the sum of the EEPROM is equal to 0xBABA. 755 **/ 756static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw) 757{ 758 DEBUGFUNC("e1000_validate_nvm_checksum_82571"); 759 760 if (hw->nvm.type == e1000_nvm_flash_hw) 761 e1000_fix_nvm_checksum_82571(hw); 762 763 return e1000_validate_nvm_checksum_generic(hw); 764} 765 766/** 767 * e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon 768 * @hw: pointer to the HW structure 769 * @offset: offset within the EEPROM to be written to 770 * @words: number of words to write 771 * @data: 16 bit word(s) to be written to the EEPROM 772 * 773 * After checking for invalid values, poll the EEPROM to ensure the previous 774 * command has completed before trying to write the next word. After write 775 * poll for completion. 776 * 777 * If e1000_update_nvm_checksum is not called after this function, the 778 * EEPROM will most likely contain an invalid checksum. 779 **/ 780static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, 781 u16 words, u16 *data) 782{ 783 struct e1000_nvm_info *nvm = &hw->nvm; 784 u32 i, eewr = 0; 785 s32 ret_val = 0; 786 787 DEBUGFUNC("e1000_write_nvm_eewr_82571"); 788 789 /* 790 * A check for invalid values: offset too large, too many words, 791 * and not enough words. 792 */ 793 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 794 (words == 0)) { 795 DEBUGOUT("nvm parameter(s) out of bounds\n"); 796 ret_val = -E1000_ERR_NVM; 797 goto out; 798 } 799 800 for (i = 0; i < words; i++) { 801 eewr = (data[i] << E1000_NVM_RW_REG_DATA) | 802 ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) | 803 E1000_NVM_RW_REG_START; 804 805 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE); 806 if (ret_val) 807 break; 808 809 E1000_WRITE_REG(hw, E1000_EEWR, eewr); 810 811 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE); 812 if (ret_val) 813 break; 814 } 815 816out: 817 return ret_val; 818} 819 820/** 821 * e1000_get_cfg_done_82571 - Poll for configuration done 822 * @hw: pointer to the HW structure 823 * 824 * Reads the management control register for the config done bit to be set. 825 **/ 826static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw) 827{ 828 s32 timeout = PHY_CFG_TIMEOUT; 829 s32 ret_val = E1000_SUCCESS; 830 831 DEBUGFUNC("e1000_get_cfg_done_82571"); 832 833 while (timeout) { 834 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & E1000_NVM_CFG_DONE_PORT_0) 835 break; 836 msec_delay(1); 837 timeout--; 838 } 839 if (!timeout) { 840 DEBUGOUT("MNG configuration cycle has not completed.\n"); 841 ret_val = -E1000_ERR_RESET; 842 goto out; 843 } 844 845out: 846 return ret_val; 847} 848 849/** 850 * e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state 851 * @hw: pointer to the HW structure 852 * @active: TRUE to enable LPLU, FALSE to disable 853 * 854 * Sets the LPLU D0 state according to the active flag. When activating LPLU 855 * this function also disables smart speed and vice versa. LPLU will not be 856 * activated unless the device autonegotiation advertisement meets standards 857 * of either 10 or 10/100 or 10/100/1000 at all duplexes. This is a function 858 * pointer entry point only called by PHY setup routines. 859 **/ 860static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active) 861{ 862 struct e1000_phy_info *phy = &hw->phy; 863 s32 ret_val = E1000_SUCCESS; 864 u16 data; 865 866 DEBUGFUNC("e1000_set_d0_lplu_state_82571"); 867 868 if (!(phy->ops.read_reg)) 869 goto out; 870 871 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); 872 if (ret_val) 873 goto out; 874 875 if (active) { 876 data |= IGP02E1000_PM_D0_LPLU; 877 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 878 data); 879 if (ret_val) 880 goto out; 881 882 /* When LPLU is enabled, we should disable SmartSpeed */ 883 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 884 &data); 885 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 886 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 887 data); 888 if (ret_val) 889 goto out; 890 } else { 891 data &= ~IGP02E1000_PM_D0_LPLU; 892 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 893 data); 894 /* 895 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 896 * during Dx states where the power conservation is most 897 * important. During driver activity we should enable 898 * SmartSpeed, so performance is maintained. 899 */ 900 if (phy->smart_speed == e1000_smart_speed_on) { 901 ret_val = phy->ops.read_reg(hw, 902 IGP01E1000_PHY_PORT_CONFIG, 903 &data); 904 if (ret_val) 905 goto out; 906 907 data |= IGP01E1000_PSCFR_SMART_SPEED; 908 ret_val = phy->ops.write_reg(hw, 909 IGP01E1000_PHY_PORT_CONFIG, 910 data); 911 if (ret_val) 912 goto out; 913 } else if (phy->smart_speed == e1000_smart_speed_off) { 914 ret_val = phy->ops.read_reg(hw, 915 IGP01E1000_PHY_PORT_CONFIG, 916 &data); 917 if (ret_val) 918 goto out; 919 920 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 921 ret_val = phy->ops.write_reg(hw, 922 IGP01E1000_PHY_PORT_CONFIG, 923 data); 924 if (ret_val) 925 goto out; 926 } 927 } 928 929out: 930 return ret_val; 931} 932 933/** 934 * e1000_reset_hw_82571 - Reset hardware 935 * @hw: pointer to the HW structure 936 * 937 * This resets the hardware into a known state. 938 **/ 939static s32 e1000_reset_hw_82571(struct e1000_hw *hw) 940{ 941 u32 ctrl, extcnf_ctrl, ctrl_ext, icr; 942 s32 ret_val; 943 u16 i = 0; 944 945 DEBUGFUNC("e1000_reset_hw_82571"); 946 947 /* 948 * Prevent the PCI-E bus from sticking if there is no TLP connection 949 * on the last TLP read/write transaction when MAC is reset. 950 */ 951 ret_val = e1000_disable_pcie_master_generic(hw); 952 if (ret_val) 953 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 954 955 DEBUGOUT("Masking off all interrupts\n"); 956 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 957 958 E1000_WRITE_REG(hw, E1000_RCTL, 0); 959 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 960 E1000_WRITE_FLUSH(hw); 961 962 msec_delay(10); 963 964 /* 965 * Must acquire the MDIO ownership before MAC reset. 966 * Ownership defaults to firmware after a reset. 967 */ 968 switch (hw->mac.type) { 969 case e1000_82574: 970 case e1000_82583: 971 case e1000_82573: 972 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 973 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; 974 975 do { 976 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); 977 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 978 979 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP) 980 break; 981 982 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; 983 984 msec_delay(2); 985 i++; 986 } while (i < MDIO_OWNERSHIP_TIMEOUT); 987 break; 988 default: 989 break; 990 } 991 992 ctrl = E1000_READ_REG(hw, E1000_CTRL); 993 994 DEBUGOUT("Issuing a global reset to MAC\n"); 995 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 996 997 if (hw->nvm.type == e1000_nvm_flash_hw) { 998 usec_delay(10); 999 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 1000 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 1001 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 1002 E1000_WRITE_FLUSH(hw); 1003 } 1004 1005 ret_val = e1000_get_auto_rd_done_generic(hw); 1006 if (ret_val) 1007 /* We don't want to continue accessing MAC registers. */ 1008 goto out; 1009 1010 /* 1011 * Phy configuration from NVM just starts after EECD_AUTO_RD is set. 1012 * Need to wait for Phy configuration completion before accessing 1013 * NVM and Phy. 1014 */ 1015 1016 switch (hw->mac.type) { 1017 case e1000_82574: 1018 case e1000_82583: 1019 case e1000_82573: 1020 msec_delay(25); 1021 break; 1022 default: 1023 break; 1024 } 1025 1026 /* Clear any pending interrupt events. */ 1027 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 1028 icr = E1000_READ_REG(hw, E1000_ICR); 1029 1030 /* Install any alternate MAC address into RAR0 */ 1031 ret_val = e1000_check_alt_mac_addr_generic(hw); 1032 if (ret_val) 1033 goto out; 1034 1035 e1000_set_laa_state_82571(hw, TRUE); 1036 1037 /* Reinitialize the 82571 serdes link state machine */ 1038 if (hw->phy.media_type == e1000_media_type_internal_serdes) 1039 hw->mac.serdes_link_state = e1000_serdes_link_down; 1040 1041out: 1042 return ret_val; 1043} 1044 1045/** 1046 * e1000_init_hw_82571 - Initialize hardware 1047 * @hw: pointer to the HW structure 1048 * 1049 * This inits the hardware readying it for operation. 1050 **/ 1051static s32 e1000_init_hw_82571(struct e1000_hw *hw) 1052{ 1053 struct e1000_mac_info *mac = &hw->mac; 1054 u32 reg_data; 1055 s32 ret_val; 1056 u16 i, rar_count = mac->rar_entry_count; 1057 1058 DEBUGFUNC("e1000_init_hw_82571"); 1059 1060 e1000_initialize_hw_bits_82571(hw); 1061 1062 /* Initialize identification LED */ 1063 ret_val = mac->ops.id_led_init(hw); 1064 if (ret_val) { 1065 DEBUGOUT("Error initializing identification LED\n"); 1066 /* This is not fatal and we should not stop init due to this */ 1067 } 1068 1069 /* Disabling VLAN filtering */ 1070 DEBUGOUT("Initializing the IEEE VLAN\n"); 1071 mac->ops.clear_vfta(hw); 1072 1073 /* Setup the receive address. */ 1074 /* 1075 * If, however, a locally administered address was assigned to the 1076 * 82571, we must reserve a RAR for it to work around an issue where 1077 * resetting one port will reload the MAC on the other port. 1078 */ 1079 if (e1000_get_laa_state_82571(hw)) 1080 rar_count--; 1081 e1000_init_rx_addrs_generic(hw, rar_count); 1082 1083 /* Zero out the Multicast HASH table */ 1084 DEBUGOUT("Zeroing the MTA\n"); 1085 for (i = 0; i < mac->mta_reg_count; i++) 1086 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 1087 1088 /* Setup link and flow control */ 1089 ret_val = mac->ops.setup_link(hw); 1090 1091 /* Set the transmit descriptor write-back policy */ 1092 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0)); 1093 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | 1094 E1000_TXDCTL_FULL_TX_DESC_WB | 1095 E1000_TXDCTL_COUNT_DESC; 1096 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data); 1097 1098 /* ...for both queues. */ 1099 switch (mac->type) { 1100 case e1000_82574: 1101 case e1000_82583: 1102 case e1000_82573: 1103 e1000_enable_tx_pkt_filtering_generic(hw); 1104 reg_data = E1000_READ_REG(hw, E1000_GCR); 1105 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; 1106 E1000_WRITE_REG(hw, E1000_GCR, reg_data); 1107 break; 1108 default: 1109 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1)); 1110 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | 1111 E1000_TXDCTL_FULL_TX_DESC_WB | 1112 E1000_TXDCTL_COUNT_DESC; 1113 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data); 1114 break; 1115 } 1116 1117 /* 1118 * Clear all of the statistics registers (clear on read). It is 1119 * important that we do this after we have tried to establish link 1120 * because the symbol error count will increment wildly if there 1121 * is no link. 1122 */ 1123 e1000_clear_hw_cntrs_82571(hw); 1124 1125 return ret_val; 1126} 1127 1128/** 1129 * e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits 1130 * @hw: pointer to the HW structure 1131 * 1132 * Initializes required hardware-dependent bits needed for normal operation. 1133 **/ 1134static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw) 1135{ 1136 u32 reg; 1137 1138 DEBUGFUNC("e1000_initialize_hw_bits_82571"); 1139 1140 /* Transmit Descriptor Control 0 */ 1141 reg = E1000_READ_REG(hw, E1000_TXDCTL(0)); 1142 reg |= (1 << 22); 1143 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg); 1144 1145 /* Transmit Descriptor Control 1 */ 1146 reg = E1000_READ_REG(hw, E1000_TXDCTL(1)); 1147 reg |= (1 << 22); 1148 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg); 1149 1150 /* Transmit Arbitration Control 0 */ 1151 reg = E1000_READ_REG(hw, E1000_TARC(0)); 1152 reg &= ~(0xF << 27); /* 30:27 */ 1153 switch (hw->mac.type) { 1154 case e1000_82571: 1155 case e1000_82572: 1156 reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26); 1157 break; 1158 default: 1159 break; 1160 } 1161 E1000_WRITE_REG(hw, E1000_TARC(0), reg); 1162 1163 /* Transmit Arbitration Control 1 */ 1164 reg = E1000_READ_REG(hw, E1000_TARC(1)); 1165 switch (hw->mac.type) { 1166 case e1000_82571: 1167 case e1000_82572: 1168 reg &= ~((1 << 29) | (1 << 30)); 1169 reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26); 1170 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR) 1171 reg &= ~(1 << 28); 1172 else 1173 reg |= (1 << 28); 1174 E1000_WRITE_REG(hw, E1000_TARC(1), reg); 1175 break; 1176 default: 1177 break; 1178 } 1179 1180 /* Device Control */ 1181 1182 switch (hw->mac.type) { 1183 case e1000_82574: 1184 case e1000_82583: 1185 case e1000_82573: 1186 reg = E1000_READ_REG(hw, E1000_CTRL); 1187 reg &= ~(1 << 29); 1188 E1000_WRITE_REG(hw, E1000_CTRL, reg); 1189 break; 1190 default: 1191 break; 1192 } 1193 1194 /* Extended Device Control */ 1195 switch (hw->mac.type) { 1196 case e1000_82574: 1197 case e1000_82583: 1198 case e1000_82573: 1199 reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 1200 reg &= ~(1 << 23); 1201 reg |= (1 << 22); 1202 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 1203 break; 1204 default: 1205 break; 1206 } 1207 1208 1209 if (hw->mac.type == e1000_82571) { 1210 reg = E1000_READ_REG(hw, E1000_PBA_ECC); 1211 reg |= E1000_PBA_ECC_CORR_EN; 1212 E1000_WRITE_REG(hw, E1000_PBA_ECC, reg); 1213 } 1214 1215 /* 1216 * Workaround for hardware errata. 1217 * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572 1218 */ 1219 1220 if ((hw->mac.type == e1000_82571) || 1221 (hw->mac.type == e1000_82572)) { 1222 reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 1223 reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN; 1224 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 1225 } 1226 1227 /* PCI-Ex Control Registers */ 1228 1229 switch (hw->mac.type) { 1230 case e1000_82574: 1231 case e1000_82583: 1232 reg = E1000_READ_REG(hw, E1000_GCR); 1233 reg |= (1 << 22); 1234 E1000_WRITE_REG(hw, E1000_GCR, reg); 1235 /* 1236 * Workaround for hardware errata. 1237 * apply workaround for hardware errata documented in errata 1238 * docs Fixes issue where some error prone or unreliable PCIe 1239 * completions are occurring, particularly with ASPM enabled. 1240 * Without fix, issue can cause tx timeouts. 1241 */ 1242 reg = E1000_READ_REG(hw, E1000_GCR2); 1243 reg |= 1; 1244 E1000_WRITE_REG(hw, E1000_GCR2, reg); 1245 break; 1246 default: 1247 break; 1248 } 1249 1250 return; 1251} 1252 1253/** 1254 * e1000_clear_vfta_82571 - Clear VLAN filter table 1255 * @hw: pointer to the HW structure 1256 * 1257 * Clears the register array which contains the VLAN filter table by 1258 * setting all the values to 0. 1259 **/ 1260static void e1000_clear_vfta_82571(struct e1000_hw *hw) 1261{ 1262 u32 offset; 1263 u32 vfta_value = 0; 1264 u32 vfta_offset = 0; 1265 u32 vfta_bit_in_reg = 0; 1266 1267 DEBUGFUNC("e1000_clear_vfta_82571"); 1268 1269 switch (hw->mac.type) { 1270 case e1000_82574: 1271 case e1000_82583: 1272 case e1000_82573: 1273 if (hw->mng_cookie.vlan_id != 0) { 1274 /* 1275 *The VFTA is a 4096b bit-field, each identifying 1276 *a single VLAN ID. The following operations 1277 *determine which 32b entry (i.e. offset) into the 1278 *array we want to set the VLAN ID (i.e. bit) of 1279 *the manageability unit. 1280 */ 1281 vfta_offset = (hw->mng_cookie.vlan_id >> 1282 E1000_VFTA_ENTRY_SHIFT) & E1000_VFTA_ENTRY_MASK; 1283 vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id & 1284 E1000_VFTA_ENTRY_BIT_SHIFT_MASK); 1285 } 1286 1287 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 1288 /* 1289 *If the offset we want to clear is the same offset of 1290 *the manageability VLAN ID, then clear all bits except 1291 *that of the manageability unit 1292 */ 1293 vfta_value = (offset == vfta_offset) ? 1294 vfta_bit_in_reg : 0; 1295 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 1296 vfta_value); 1297 E1000_WRITE_FLUSH(hw); 1298 } 1299 break; 1300 default: 1301 break; 1302 } 1303} 1304 1305/** 1306 * e1000_check_mng_mode_82574 - Check manageability is enabled 1307 * @hw: pointer to the HW structure 1308 * 1309 * Reads the NVM Initialization Control Word 2 and returns TRUE 1310 * (>0) if any manageability is enabled, else FALSE (0). 1311 **/ 1312static bool e1000_check_mng_mode_82574(struct e1000_hw *hw) 1313{ 1314 u16 data; 1315 1316 DEBUGFUNC("e1000_check_mng_mode_82574"); 1317 1318 hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &data); 1319 return (data & E1000_NVM_INIT_CTRL2_MNGM) != 0; 1320} 1321 1322/** 1323 * e1000_led_on_82574 - Turn LED on 1324 * @hw: pointer to the HW structure 1325 * 1326 * Turn LED on. 1327 **/ 1328static s32 e1000_led_on_82574(struct e1000_hw *hw) 1329{ 1330 u32 ctrl; 1331 u32 i; 1332 1333 DEBUGFUNC("e1000_led_on_82574"); 1334 1335 ctrl = hw->mac.ledctl_mode2; 1336 if (!(E1000_STATUS_LU & E1000_READ_REG(hw, E1000_STATUS))) { 1337 /* 1338 * If no link, then turn LED on by setting the invert bit 1339 * for each LED that's "on" (0x0E) in ledctl_mode2. 1340 */ 1341 for (i = 0; i < 4; i++) 1342 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) == 1343 E1000_LEDCTL_MODE_LED_ON) 1344 ctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8)); 1345 } 1346 E1000_WRITE_REG(hw, E1000_LEDCTL, ctrl); 1347 1348 return E1000_SUCCESS; 1349} 1350 1351 1352/** 1353 * e1000_setup_link_82571 - Setup flow control and link settings 1354 * @hw: pointer to the HW structure 1355 * 1356 * Determines which flow control settings to use, then configures flow 1357 * control. Calls the appropriate media-specific link configuration 1358 * function. Assuming the adapter has a valid link partner, a valid link 1359 * should be established. Assumes the hardware has previously been reset 1360 * and the transmitter and receiver are not enabled. 1361 **/ 1362static s32 e1000_setup_link_82571(struct e1000_hw *hw) 1363{ 1364 DEBUGFUNC("e1000_setup_link_82571"); 1365 1366 /* 1367 * 82573 does not have a word in the NVM to determine 1368 * the default flow control setting, so we explicitly 1369 * set it to full. 1370 */ 1371 switch (hw->mac.type) { 1372 case e1000_82574: 1373 case e1000_82583: 1374 case e1000_82573: 1375 if (hw->fc.requested_mode == e1000_fc_default) 1376 hw->fc.requested_mode = e1000_fc_full; 1377 break; 1378 default: 1379 break; 1380 } 1381 return e1000_setup_link_generic(hw); 1382} 1383 1384/** 1385 * e1000_setup_copper_link_82571 - Configure copper link settings 1386 * @hw: pointer to the HW structure 1387 * 1388 * Configures the link for auto-neg or forced speed and duplex. Then we check 1389 * for link, once link is established calls to configure collision distance 1390 * and flow control are called. 1391 **/ 1392static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw) 1393{ 1394 u32 ctrl; 1395 s32 ret_val; 1396 1397 DEBUGFUNC("e1000_setup_copper_link_82571"); 1398 1399 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1400 ctrl |= E1000_CTRL_SLU; 1401 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1402 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1403 1404 switch (hw->phy.type) { 1405 case e1000_phy_m88: 1406 case e1000_phy_bm: 1407 ret_val = e1000_copper_link_setup_m88(hw); 1408 break; 1409 case e1000_phy_igp_2: 1410 ret_val = e1000_copper_link_setup_igp(hw); 1411 break; 1412 default: 1413 ret_val = -E1000_ERR_PHY; 1414 break; 1415 } 1416 1417 if (ret_val) 1418 goto out; 1419 1420 ret_val = e1000_setup_copper_link_generic(hw); 1421 1422out: 1423 return ret_val; 1424} 1425 1426/** 1427 * e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes 1428 * @hw: pointer to the HW structure 1429 * 1430 * Configures collision distance and flow control for fiber and serdes links. 1431 * Upon successful setup, poll for link. 1432 **/ 1433static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw) 1434{ 1435 DEBUGFUNC("e1000_setup_fiber_serdes_link_82571"); 1436 1437 switch (hw->mac.type) { 1438 case e1000_82571: 1439 case e1000_82572: 1440 /* 1441 * If SerDes loopback mode is entered, there is no form 1442 * of reset to take the adapter out of that mode. So we 1443 * have to explicitly take the adapter out of loopback 1444 * mode. This prevents drivers from twiddling their thumbs 1445 * if another tool failed to take it out of loopback mode. 1446 */ 1447 E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK); 1448 break; 1449 default: 1450 break; 1451 } 1452 1453 return e1000_setup_fiber_serdes_link_generic(hw); 1454} 1455 1456/** 1457 * e1000_check_for_serdes_link_82571 - Check for link (Serdes) 1458 * @hw: pointer to the HW structure 1459 * 1460 * Reports the link state as up or down. 1461 * 1462 * If autonegotiation is supported by the link partner, the link state is 1463 * determined by the result of autongotiation. This is the most likely case. 1464 * If autonegotiation is not supported by the link partner, and the link 1465 * has a valid signal, force the link up. 1466 * 1467 * The link state is represented internally here by 4 states: 1468 * 1469 * 1) down 1470 * 2) autoneg_progress 1471 * 3) autoneg_complete (the link sucessfully autonegotiated) 1472 * 4) forced_up (the link has been forced up, it did not autonegotiate) 1473 * 1474 **/ 1475s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw) 1476{ 1477 struct e1000_mac_info *mac = &hw->mac; 1478 u32 rxcw; 1479 u32 ctrl; 1480 u32 status; 1481 s32 ret_val = E1000_SUCCESS; 1482 1483 DEBUGFUNC("e1000_check_for_serdes_link_82571"); 1484 1485 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1486 status = E1000_READ_REG(hw, E1000_STATUS); 1487 rxcw = E1000_READ_REG(hw, E1000_RXCW); 1488 1489 if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) { 1490 1491 /* Receiver is synchronized with no invalid bits. */ 1492 switch (mac->serdes_link_state) { 1493 case e1000_serdes_link_autoneg_complete: 1494 if (!(status & E1000_STATUS_LU)) { 1495 /* 1496 * We have lost link, retry autoneg before 1497 * reporting link failure 1498 */ 1499 mac->serdes_link_state = 1500 e1000_serdes_link_autoneg_progress; 1501 mac->serdes_has_link = FALSE; 1502 DEBUGOUT("AN_UP -> AN_PROG\n"); 1503 } 1504 break; 1505 1506 case e1000_serdes_link_forced_up: 1507 /* 1508 * If we are receiving /C/ ordered sets, re-enable 1509 * auto-negotiation in the TXCW register and disable 1510 * forced link in the Device Control register in an 1511 * attempt to auto-negotiate with our link partner. 1512 */ 1513 if (rxcw & E1000_RXCW_C) { 1514 /* Enable autoneg, and unforce link up */ 1515 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 1516 E1000_WRITE_REG(hw, E1000_CTRL, 1517 (ctrl & ~E1000_CTRL_SLU)); 1518 mac->serdes_link_state = 1519 e1000_serdes_link_autoneg_progress; 1520 mac->serdes_has_link = FALSE; 1521 DEBUGOUT("FORCED_UP -> AN_PROG\n"); 1522 } 1523 break; 1524 1525 case e1000_serdes_link_autoneg_progress: 1526 if (rxcw & E1000_RXCW_C) { 1527 /* We received /C/ ordered sets, meaning the 1528 * link partner has autonegotiated, and we can 1529 * trust the Link Up (LU) status bit 1530 */ 1531 if (status & E1000_STATUS_LU) { 1532 mac->serdes_link_state = 1533 e1000_serdes_link_autoneg_complete; 1534 DEBUGOUT("AN_PROG -> AN_UP\n"); 1535 mac->serdes_has_link = TRUE; 1536 } else { 1537 /* Autoneg completed, but failed */ 1538 mac->serdes_link_state = 1539 e1000_serdes_link_down; 1540 DEBUGOUT("AN_PROG -> DOWN\n"); 1541 } 1542 } else { 1543 /* The link partner did not autoneg. 1544 * Force link up and full duplex, and change 1545 * state to forced. 1546 */ 1547 E1000_WRITE_REG(hw, E1000_TXCW, 1548 (mac->txcw & ~E1000_TXCW_ANE)); 1549 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 1550 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1551 1552 /* Configure Flow Control after link up. */ 1553 ret_val = 1554 e1000_config_fc_after_link_up_generic(hw); 1555 if (ret_val) { 1556 DEBUGOUT("Error config flow control\n"); 1557 break; 1558 } 1559 mac->serdes_link_state = 1560 e1000_serdes_link_forced_up; 1561 mac->serdes_has_link = TRUE; 1562 DEBUGOUT("AN_PROG -> FORCED_UP\n"); 1563 } 1564 break; 1565 1566 case e1000_serdes_link_down: 1567 default: 1568 /* The link was down but the receiver has now gained 1569 * valid sync, so lets see if we can bring the link 1570 * up. */ 1571 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 1572 E1000_WRITE_REG(hw, E1000_CTRL, 1573 (ctrl & ~E1000_CTRL_SLU)); 1574 mac->serdes_link_state = 1575 e1000_serdes_link_autoneg_progress; 1576 DEBUGOUT("DOWN -> AN_PROG\n"); 1577 break; 1578 } 1579 } else { 1580 if (!(rxcw & E1000_RXCW_SYNCH)) { 1581 mac->serdes_has_link = FALSE; 1582 mac->serdes_link_state = e1000_serdes_link_down; 1583 DEBUGOUT("ANYSTATE -> DOWN\n"); 1584 } else { 1585 /* 1586 * We have sync, and can tolerate one 1587 * invalid (IV) codeword before declaring 1588 * link down, so reread to look again 1589 */ 1590 usec_delay(10); 1591 rxcw = E1000_READ_REG(hw, E1000_RXCW); 1592 if (rxcw & E1000_RXCW_IV) { 1593 mac->serdes_link_state = e1000_serdes_link_down; 1594 mac->serdes_has_link = FALSE; 1595 DEBUGOUT("ANYSTATE -> DOWN\n"); 1596 } 1597 } 1598 } 1599 1600 return ret_val; 1601} 1602 1603/** 1604 * e1000_valid_led_default_82571 - Verify a valid default LED config 1605 * @hw: pointer to the HW structure 1606 * @data: pointer to the NVM (EEPROM) 1607 * 1608 * Read the EEPROM for the current default LED configuration. If the 1609 * LED configuration is not valid, set to a valid LED configuration. 1610 **/ 1611static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data) 1612{ 1613 s32 ret_val; 1614 1615 DEBUGFUNC("e1000_valid_led_default_82571"); 1616 1617 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); 1618 if (ret_val) { 1619 DEBUGOUT("NVM Read Error\n"); 1620 goto out; 1621 } 1622 1623 switch (hw->mac.type) { 1624 case e1000_82574: 1625 case e1000_82583: 1626 case e1000_82573: 1627 if(*data == ID_LED_RESERVED_F746) 1628 *data = ID_LED_DEFAULT_82573; 1629 break; 1630 default: 1631 if (*data == ID_LED_RESERVED_0000 || 1632 *data == ID_LED_RESERVED_FFFF) 1633 *data = ID_LED_DEFAULT; 1634 break; 1635 } 1636 1637out: 1638 return ret_val; 1639} 1640 1641/** 1642 * e1000_get_laa_state_82571 - Get locally administered address state 1643 * @hw: pointer to the HW structure 1644 * 1645 * Retrieve and return the current locally administered address state. 1646 **/ 1647bool e1000_get_laa_state_82571(struct e1000_hw *hw) 1648{ 1649 DEBUGFUNC("e1000_get_laa_state_82571"); 1650 1651 if (hw->mac.type != e1000_82571) 1652 return FALSE; 1653 1654 return hw->dev_spec._82571.laa_is_present; 1655} 1656 1657/** 1658 * e1000_set_laa_state_82571 - Set locally administered address state 1659 * @hw: pointer to the HW structure 1660 * @state: enable/disable locally administered address 1661 * 1662 * Enable/Disable the current locally administered address state. 1663 **/ 1664void e1000_set_laa_state_82571(struct e1000_hw *hw, bool state) 1665{ 1666 DEBUGFUNC("e1000_set_laa_state_82571"); 1667 1668 if (hw->mac.type != e1000_82571) 1669 return; 1670 1671 hw->dev_spec._82571.laa_is_present = state; 1672 1673 /* If workaround is activated... */ 1674 if (state) 1675 /* 1676 * Hold a copy of the LAA in RAR[14] This is done so that 1677 * between the time RAR[0] gets clobbered and the time it 1678 * gets fixed, the actual LAA is in one of the RARs and no 1679 * incoming packets directed to this port are dropped. 1680 * Eventually the LAA will be in RAR[0] and RAR[14]. 1681 */ 1682 e1000_rar_set_generic(hw, hw->mac.addr, 1683 hw->mac.rar_entry_count - 1); 1684 return; 1685} 1686 1687/** 1688 * e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum 1689 * @hw: pointer to the HW structure 1690 * 1691 * Verifies that the EEPROM has completed the update. After updating the 1692 * EEPROM, we need to check bit 15 in work 0x23 for the checksum fix. If 1693 * the checksum fix is not implemented, we need to set the bit and update 1694 * the checksum. Otherwise, if bit 15 is set and the checksum is incorrect, 1695 * we need to return bad checksum. 1696 **/ 1697static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw) 1698{ 1699 struct e1000_nvm_info *nvm = &hw->nvm; 1700 s32 ret_val = E1000_SUCCESS; 1701 u16 data; 1702 1703 DEBUGFUNC("e1000_fix_nvm_checksum_82571"); 1704 1705 if (nvm->type != e1000_nvm_flash_hw) 1706 goto out; 1707 1708 /* 1709 * Check bit 4 of word 10h. If it is 0, firmware is done updating 1710 * 10h-12h. Checksum may need to be fixed. 1711 */ 1712 ret_val = nvm->ops.read(hw, 0x10, 1, &data); 1713 if (ret_val) 1714 goto out; 1715 1716 if (!(data & 0x10)) { 1717 /* 1718 * Read 0x23 and check bit 15. This bit is a 1 1719 * when the checksum has already been fixed. If 1720 * the checksum is still wrong and this bit is a 1721 * 1, we need to return bad checksum. Otherwise, 1722 * we need to set this bit to a 1 and update the 1723 * checksum. 1724 */ 1725 ret_val = nvm->ops.read(hw, 0x23, 1, &data); 1726 if (ret_val) 1727 goto out; 1728 1729 if (!(data & 0x8000)) { 1730 data |= 0x8000; 1731 ret_val = nvm->ops.write(hw, 0x23, 1, &data); 1732 if (ret_val) 1733 goto out; 1734 ret_val = nvm->ops.update(hw); 1735 } 1736 } 1737 1738out: 1739 return ret_val; 1740} 1741 1742 1743/** 1744 * e1000_read_mac_addr_82571 - Read device MAC address 1745 * @hw: pointer to the HW structure 1746 **/ 1747static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw) 1748{ 1749 s32 ret_val = E1000_SUCCESS; 1750 1751 DEBUGFUNC("e1000_read_mac_addr_82571"); 1752 1753 /* 1754 * If there's an alternate MAC address place it in RAR0 1755 * so that it will override the Si installed default perm 1756 * address. 1757 */ 1758 ret_val = e1000_check_alt_mac_addr_generic(hw); 1759 if (ret_val) 1760 goto out; 1761 1762 ret_val = e1000_read_mac_addr_generic(hw); 1763 1764out: 1765 return ret_val; 1766} 1767 1768/** 1769 * e1000_power_down_phy_copper_82571 - Remove link during PHY power down 1770 * @hw: pointer to the HW structure 1771 * 1772 * In the case of a PHY power down to save power, or to turn off link during a 1773 * driver unload, or wake on lan is not enabled, remove the link. 1774 **/ 1775static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw) 1776{ 1777 struct e1000_phy_info *phy = &hw->phy; 1778 struct e1000_mac_info *mac = &hw->mac; 1779 1780 if (!(phy->ops.check_reset_block)) 1781 return; 1782 1783 /* If the management interface is not enabled, then power down */ 1784 if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw))) 1785 e1000_power_down_phy_copper(hw); 1786 1787 return; 1788} 1789 1790/** 1791 * e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters 1792 * @hw: pointer to the HW structure 1793 * 1794 * Clears the hardware counters by reading the counter registers. 1795 **/ 1796static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw) 1797{ 1798 DEBUGFUNC("e1000_clear_hw_cntrs_82571"); 1799 1800 e1000_clear_hw_cntrs_base_generic(hw); 1801 1802 E1000_READ_REG(hw, E1000_PRC64); 1803 E1000_READ_REG(hw, E1000_PRC127); 1804 E1000_READ_REG(hw, E1000_PRC255); 1805 E1000_READ_REG(hw, E1000_PRC511); 1806 E1000_READ_REG(hw, E1000_PRC1023); 1807 E1000_READ_REG(hw, E1000_PRC1522); 1808 E1000_READ_REG(hw, E1000_PTC64); 1809 E1000_READ_REG(hw, E1000_PTC127); 1810 E1000_READ_REG(hw, E1000_PTC255); 1811 E1000_READ_REG(hw, E1000_PTC511); 1812 E1000_READ_REG(hw, E1000_PTC1023); 1813 E1000_READ_REG(hw, E1000_PTC1522); 1814 1815 E1000_READ_REG(hw, E1000_ALGNERRC); 1816 E1000_READ_REG(hw, E1000_RXERRC); 1817 E1000_READ_REG(hw, E1000_TNCRS); 1818 E1000_READ_REG(hw, E1000_CEXTERR); 1819 E1000_READ_REG(hw, E1000_TSCTC); 1820 E1000_READ_REG(hw, E1000_TSCTFC); 1821 1822 E1000_READ_REG(hw, E1000_MGTPRC); 1823 E1000_READ_REG(hw, E1000_MGTPDC); 1824 E1000_READ_REG(hw, E1000_MGTPTC); 1825 1826 E1000_READ_REG(hw, E1000_IAC); 1827 E1000_READ_REG(hw, E1000_ICRXOC); 1828 1829 E1000_READ_REG(hw, E1000_ICRXPTC); 1830 E1000_READ_REG(hw, E1000_ICRXATC); 1831 E1000_READ_REG(hw, E1000_ICTXPTC); 1832 E1000_READ_REG(hw, E1000_ICTXATC); 1833 E1000_READ_REG(hw, E1000_ICTXQEC); 1834 E1000_READ_REG(hw, E1000_ICTXQMTC); 1835 E1000_READ_REG(hw, E1000_ICRXDMTC); 1836} 1837