e1000_82571.c revision 190872
1234353Sdim/****************************************************************************** 2193323Sed 3193323Sed Copyright (c) 2001-2009, Intel Corporation 4193323Sed All rights reserved. 5193323Sed 6193323Sed Redistribution and use in source and binary forms, with or without 7193323Sed modification, are permitted provided that the following conditions are met: 8193323Sed 9193323Sed 1. Redistributions of source code must retain the above copyright notice, 10193323Sed this list of conditions and the following disclaimer. 11193323Sed 12193323Sed 2. Redistributions in binary form must reproduce the above copyright 13193323Sed notice, this list of conditions and the following disclaimer in the 14193323Sed documentation and/or other materials provided with the distribution. 15193323Sed 16193399Sed 3. Neither the name of the Intel Corporation nor the names of its 17224145Sdim contributors may be used to endorse or promote products derived from 18193323Sed this software without specific prior written permission. 19193399Sed 20198090Srdivacky THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21226633Sdim AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22224145Sdim IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23224145Sdim ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24224145Sdim LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25193323Sed CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26193323Sed SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27193323Sed INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28193323Sed CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29193323Sed ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30224145Sdim POSSIBILITY OF SUCH DAMAGE. 31226633Sdim 32234353Sdim******************************************************************************/ 33234353Sdim/*$FreeBSD: head/sys/dev/e1000/e1000_82571.c 190872 2009-04-10 00:05:46Z jfv $*/ 34193323Sed 35234353Sdim/* 36224145Sdim * 82571EB Gigabit Ethernet Controller 37224145Sdim * 82571EB Gigabit Ethernet Controller (Copper) 38224145Sdim * 82571EB Gigabit Ethernet Controller (Fiber) 39193323Sed * 82571EB Dual Port Gigabit Mezzanine Adapter 40193323Sed * 82571EB Quad Port Gigabit Mezzanine Adapter 41193323Sed * 82571PT Gigabit PT Quad Port Server ExpressModule 42193323Sed * 82572EI Gigabit Ethernet Controller (Copper) 43193323Sed * 82572EI Gigabit Ethernet Controller (Fiber) 44193323Sed * 82572EI Gigabit Ethernet Controller 45193323Sed * 82573V Gigabit Ethernet Controller (Copper) 46193323Sed * 82573E Gigabit Ethernet Controller (Copper) 47193323Sed * 82573L Gigabit Ethernet Controller 48193323Sed * 82574L Gigabit Network Connection 49221345Sdim * 82574L Gigabit Network Connection 50193323Sed */ 51226633Sdim 52226633Sdim#include "e1000_api.h" 53226633Sdim 54226633Sdimstatic s32 e1000_init_phy_params_82571(struct e1000_hw *hw); 55226633Sdimstatic s32 e1000_init_nvm_params_82571(struct e1000_hw *hw); 56226633Sdimstatic s32 e1000_init_mac_params_82571(struct e1000_hw *hw); 57224145Sdimstatic s32 e1000_acquire_nvm_82571(struct e1000_hw *hw); 58224145Sdimstatic void e1000_release_nvm_82571(struct e1000_hw *hw); 59224145Sdimstatic s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, 60224145Sdim u16 words, u16 *data); 61193323Sedstatic s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw); 62193323Sedstatic s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw); 63193323Sedstatic s32 e1000_get_cfg_done_82571(struct e1000_hw *hw); 64193323Sedstatic s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, 65193323Sed bool active); 66193323Sedstatic s32 e1000_reset_hw_82571(struct e1000_hw *hw); 67193323Sedstatic s32 e1000_init_hw_82571(struct e1000_hw *hw); 68193323Sedstatic void e1000_clear_vfta_82571(struct e1000_hw *hw); 69193323Sedstatic bool e1000_check_mng_mode_82574(struct e1000_hw *hw); 70193323Sedstatic s32 e1000_led_on_82574(struct e1000_hw *hw); 71193323Sedstatic s32 e1000_setup_link_82571(struct e1000_hw *hw); 72193323Sedstatic s32 e1000_setup_copper_link_82571(struct e1000_hw *hw); 73193323Sedstatic s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw); 74221345Sdimstatic s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw); 75193323Sedstatic s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data); 76226633Sdimstatic void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw); 77226633Sdimstatic s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw); 78226633Sdimstatic s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw); 79226633Sdimstatic s32 e1000_get_phy_id_82571(struct e1000_hw *hw); 80226633Sdimstatic void e1000_put_hw_semaphore_82571(struct e1000_hw *hw); 81226633Sdimstatic void e1000_initialize_hw_bits_82571(struct e1000_hw *hw); 82224145Sdimstatic s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, 83224145Sdim u16 words, u16 *data); 84224145Sdimstatic s32 e1000_read_mac_addr_82571(struct e1000_hw *hw); 85224145Sdimstatic void e1000_power_down_phy_copper_82571(struct e1000_hw *hw); 86193323Sed 87193323Sed/** 88193323Sed * e1000_init_phy_params_82571 - Init PHY func ptrs. 89193323Sed * @hw: pointer to the HW structure 90193323Sed **/ 91193323Sedstatic s32 e1000_init_phy_params_82571(struct e1000_hw *hw) 92193323Sed{ 93193323Sed struct e1000_phy_info *phy = &hw->phy; 94193323Sed s32 ret_val = E1000_SUCCESS; 95221345Sdim 96193323Sed DEBUGFUNC("e1000_init_phy_params_82571"); 97206124Srdivacky 98193323Sed if (hw->phy.media_type != e1000_media_type_copper) { 99193323Sed phy->type = e1000_phy_none; 100193323Sed goto out; 101210299Sed } 102210299Sed 103210299Sed phy->addr = 1; 104210299Sed phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 105210299Sed phy->reset_delay_us = 100; 106226633Sdim 107193323Sed phy->ops.acquire = e1000_get_hw_semaphore_82571; 108226633Sdim phy->ops.check_polarity = e1000_check_polarity_igp; 109226633Sdim phy->ops.check_reset_block = e1000_check_reset_block_generic; 110226633Sdim phy->ops.release = e1000_put_hw_semaphore_82571; 111226633Sdim phy->ops.reset = e1000_phy_hw_reset_generic; 112226633Sdim phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82571; 113210299Sed phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic; 114226633Sdim phy->ops.power_up = e1000_power_up_phy_copper; 115210299Sed phy->ops.power_down = e1000_power_down_phy_copper_82571; 116226633Sdim 117210299Sed switch (hw->mac.type) { 118226633Sdim case e1000_82571: 119210299Sed case e1000_82572: 120226633Sdim phy->type = e1000_phy_igp_2; 121210299Sed phy->ops.get_cfg_done = e1000_get_cfg_done_82571; 122226633Sdim phy->ops.get_info = e1000_get_phy_info_igp; 123210299Sed phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp; 124226633Sdim phy->ops.get_cable_length = e1000_get_cable_length_igp_2; 125210299Sed phy->ops.read_reg = e1000_read_phy_reg_igp; 126226633Sdim phy->ops.write_reg = e1000_write_phy_reg_igp; 127210299Sed 128226633Sdim /* This uses above function pointers */ 129210299Sed ret_val = e1000_get_phy_id_82571(hw); 130226633Sdim 131226633Sdim /* Verify PHY ID */ 132226633Sdim if (phy->id != IGP01E1000_I_PHY_ID) { 133226633Sdim ret_val = -E1000_ERR_PHY; 134234353Sdim goto out; 135234353Sdim } 136226633Sdim break; 137226633Sdim case e1000_82573: 138226633Sdim phy->type = e1000_phy_m88; 139226633Sdim phy->ops.get_cfg_done = e1000_get_cfg_done_generic; 140226633Sdim phy->ops.get_info = e1000_get_phy_info_m88; 141226633Sdim phy->ops.commit = e1000_phy_sw_reset_generic; 142226633Sdim phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; 143226633Sdim phy->ops.get_cable_length = e1000_get_cable_length_m88; 144226633Sdim phy->ops.read_reg = e1000_read_phy_reg_m88; 145234353Sdim phy->ops.write_reg = e1000_write_phy_reg_m88; 146234353Sdim 147210299Sed /* This uses above function pointers */ 148226633Sdim ret_val = e1000_get_phy_id_82571(hw); 149226633Sdim 150226633Sdim /* Verify PHY ID */ 151226633Sdim if (phy->id != M88E1111_I_PHY_ID) { 152226633Sdim ret_val = -E1000_ERR_PHY; 153234353Sdim DEBUGOUT1("PHY ID unknown: type = 0x%08x\n", phy->id); 154234353Sdim goto out; 155210299Sed } 156193323Sed break; 157226633Sdim case e1000_82574: 158226633Sdim phy->type = e1000_phy_bm; 159226633Sdim phy->ops.get_cfg_done = e1000_get_cfg_done_generic; 160234353Sdim phy->ops.get_info = e1000_get_phy_info_m88; 161226633Sdim phy->ops.commit = e1000_phy_sw_reset_generic; 162226633Sdim phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; 163226633Sdim phy->ops.get_cable_length = e1000_get_cable_length_m88; 164226633Sdim phy->ops.read_reg = e1000_read_phy_reg_bm2; 165226633Sdim phy->ops.write_reg = e1000_write_phy_reg_bm2; 166226633Sdim 167226633Sdim /* This uses above function pointers */ 168226633Sdim ret_val = e1000_get_phy_id_82571(hw); 169193323Sed /* Verify PHY ID */ 170193323Sed if (phy->id != BME1000_E_PHY_ID_R2) { 171234353Sdim ret_val = -E1000_ERR_PHY; 172234353Sdim DEBUGOUT1("PHY ID unknown: type = 0x%08x\n", phy->id); 173234353Sdim goto out; 174234353Sdim } 175234353Sdim break; 176234353Sdim default: 177234353Sdim ret_val = -E1000_ERR_PHY; 178234353Sdim goto out; 179234353Sdim break; 180234353Sdim } 181193323Sed 182193323Sedout: 183221345Sdim return ret_val; 184208599Srdivacky} 185208599Srdivacky 186206124Srdivacky/** 187193323Sed * e1000_init_nvm_params_82571 - Init NVM func ptrs. 188234353Sdim * @hw: pointer to the HW structure 189234353Sdim **/ 190226633Sdimstatic s32 e1000_init_nvm_params_82571(struct e1000_hw *hw) 191193323Sed{ 192221345Sdim struct e1000_nvm_info *nvm = &hw->nvm; 193226633Sdim u32 eecd = E1000_READ_REG(hw, E1000_EECD); 194226633Sdim u16 size; 195226633Sdim 196193323Sed DEBUGFUNC("e1000_init_nvm_params_82571"); 197226633Sdim 198226633Sdim nvm->opcode_bits = 8; 199226633Sdim nvm->delay_usec = 1; 200226633Sdim switch (nvm->override) { 201226633Sdim case e1000_nvm_override_spi_large: 202226633Sdim nvm->page_size = 32; 203226633Sdim nvm->address_bits = 16; 204226633Sdim break; 205234353Sdim case e1000_nvm_override_spi_small: 206193323Sed nvm->page_size = 8; 207193323Sed nvm->address_bits = 8; 208193323Sed break; 209193323Sed default: 210193323Sed nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; 211208599Srdivacky nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; 212221345Sdim break; 213193323Sed } 214206124Srdivacky 215199989Srdivacky switch (hw->mac.type) { 216234353Sdim case e1000_82573: 217226633Sdim case e1000_82574: 218199989Srdivacky if (((eecd >> 15) & 0x3) == 0x3) { 219221345Sdim nvm->type = e1000_nvm_flash_hw; 220226633Sdim nvm->word_size = 2048; 221226633Sdim /* 222226633Sdim * Autonomous Flash update bit must be cleared due 223193323Sed * to Flash update issue. 224226633Sdim */ 225226633Sdim eecd &= ~E1000_EECD_AUPDEN; 226226633Sdim E1000_WRITE_REG(hw, E1000_EECD, eecd); 227226633Sdim break; 228226633Sdim } 229226633Sdim /* Fall Through */ 230226633Sdim default: 231234353Sdim nvm->type = e1000_nvm_eeprom_spi; 232234353Sdim size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> 233193323Sed E1000_EECD_SIZE_EX_SHIFT); 234193323Sed /* 235224145Sdim * Added to a constant, "size" becomes the left-shift value 236224145Sdim * for setting word_size. 237224145Sdim */ 238224145Sdim size += NVM_WORD_SIZE_BASE_SHIFT; 239224145Sdim 240224145Sdim /* EEPROM access above 16k is unsupported */ 241224145Sdim if (size > 14) 242224145Sdim size = 14; 243224145Sdim nvm->word_size = 1 << size; 244193323Sed break; 245193323Sed } 246193323Sed 247193323Sed /* Function Pointers */ 248221345Sdim nvm->ops.acquire = e1000_acquire_nvm_82571; 249226633Sdim nvm->ops.read = e1000_read_nvm_eerd; 250226633Sdim nvm->ops.release = e1000_release_nvm_82571; 251226633Sdim nvm->ops.update = e1000_update_nvm_checksum_82571; 252226633Sdim nvm->ops.validate = e1000_validate_nvm_checksum_82571; 253234353Sdim nvm->ops.valid_led_default = e1000_valid_led_default_82571; 254234353Sdim nvm->ops.write = e1000_write_nvm_82571; 255226633Sdim 256193323Sed return E1000_SUCCESS; 257193323Sed} 258221345Sdim 259221345Sdim/** 260221345Sdim * e1000_init_mac_params_82571 - Init MAC func ptrs. 261193323Sed * @hw: pointer to the HW structure 262221345Sdim **/ 263234353Sdimstatic s32 e1000_init_mac_params_82571(struct e1000_hw *hw) 264234353Sdim{ 265234353Sdim struct e1000_mac_info *mac = &hw->mac; 266234353Sdim s32 ret_val = E1000_SUCCESS; 267234353Sdim 268234353Sdim DEBUGFUNC("e1000_init_mac_params_82571"); 269234353Sdim 270234353Sdim /* Set media type */ 271234353Sdim switch (hw->device_id) { 272234353Sdim case E1000_DEV_ID_82571EB_FIBER: 273234353Sdim case E1000_DEV_ID_82572EI_FIBER: 274234353Sdim case E1000_DEV_ID_82571EB_QUAD_FIBER: 275234353Sdim hw->phy.media_type = e1000_media_type_fiber; 276234353Sdim break; 277234353Sdim case E1000_DEV_ID_82571EB_SERDES: 278193323Sed case E1000_DEV_ID_82571EB_SERDES_DUAL: 279193323Sed case E1000_DEV_ID_82571EB_SERDES_QUAD: 280193323Sed case E1000_DEV_ID_82572EI_SERDES: 281221345Sdim hw->phy.media_type = e1000_media_type_internal_serdes; 282221345Sdim break; 283221345Sdim default: 284221345Sdim hw->phy.media_type = e1000_media_type_copper; 285221345Sdim break; 286234353Sdim } 287221345Sdim 288221345Sdim /* Set mta register count */ 289221345Sdim mac->mta_reg_count = 128; 290221345Sdim /* Set rar entry count */ 291221345Sdim mac->rar_entry_count = E1000_RAR_ENTRIES; 292221345Sdim /* Set if part includes ASF firmware */ 293221345Sdim mac->asf_firmware_present = TRUE; 294193323Sed /* Set if manageability features are enabled. */ 295193323Sed mac->arc_subsystem_valid = 296221345Sdim (E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK) 297193323Sed ? TRUE : FALSE; 298193323Sed 299193323Sed /* Function pointers */ 300221345Sdim 301193323Sed /* bus type/speed/width */ 302221345Sdim mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic; 303221345Sdim /* function id */ 304221345Sdim switch (hw->mac.type) { 305221345Sdim case e1000_82573: 306221345Sdim case e1000_82574: 307221345Sdim mac->ops.set_lan_id = e1000_set_lan_id_single_port; 308221345Sdim break; 309221345Sdim default: 310221345Sdim break; 311221345Sdim } 312193323Sed /* reset */ 313206083Srdivacky mac->ops.reset_hw = e1000_reset_hw_82571; 314221345Sdim /* hw initialization */ 315221345Sdim mac->ops.init_hw = e1000_init_hw_82571; 316193323Sed /* link setup */ 317221345Sdim mac->ops.setup_link = e1000_setup_link_82571; 318221345Sdim /* physical interface link setup */ 319221345Sdim mac->ops.setup_physical_interface = 320221345Sdim (hw->phy.media_type == e1000_media_type_copper) 321221345Sdim ? e1000_setup_copper_link_82571 322221345Sdim : e1000_setup_fiber_serdes_link_82571; 323221345Sdim /* check for link */ 324221345Sdim switch (hw->phy.media_type) { 325221345Sdim case e1000_media_type_copper: 326221345Sdim mac->ops.check_for_link = e1000_check_for_copper_link_generic; 327221345Sdim break; 328221345Sdim case e1000_media_type_fiber: 329221345Sdim mac->ops.check_for_link = e1000_check_for_fiber_link_generic; 330221345Sdim break; 331221345Sdim case e1000_media_type_internal_serdes: 332193323Sed mac->ops.check_for_link = e1000_check_for_serdes_link_82571; 333221345Sdim break; 334193323Sed default: 335221345Sdim ret_val = -E1000_ERR_CONFIG; 336221345Sdim goto out; 337193323Sed break; 338234353Sdim } 339193323Sed /* check management mode */ 340193323Sed switch (hw->mac.type) { 341193323Sed case e1000_82574: 342193323Sed mac->ops.check_mng_mode = e1000_check_mng_mode_82574; 343193323Sed break; 344221345Sdim default: 345221345Sdim mac->ops.check_mng_mode = e1000_check_mng_mode_generic; 346221345Sdim break; 347193323Sed } 348221345Sdim /* multicast address update */ 349193323Sed mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; 350221345Sdim /* writing VFTA */ 351193323Sed mac->ops.write_vfta = e1000_write_vfta_generic; 352193323Sed /* clearing VFTA */ 353221345Sdim mac->ops.clear_vfta = e1000_clear_vfta_82571; 354221345Sdim /* setting MTA */ 355234353Sdim mac->ops.mta_set = e1000_mta_set_generic; 356221345Sdim /* read mac address */ 357221345Sdim mac->ops.read_mac_addr = e1000_read_mac_addr_82571; 358221345Sdim /* ID LED init */ 359193323Sed mac->ops.id_led_init = e1000_id_led_init_generic; 360221345Sdim /* blink LED */ 361221345Sdim mac->ops.blink_led = e1000_blink_led_generic; 362221345Sdim /* setup LED */ 363221345Sdim mac->ops.setup_led = e1000_setup_led_generic; 364193323Sed /* cleanup LED */ 365221345Sdim mac->ops.cleanup_led = e1000_cleanup_led_generic; 366221345Sdim /* turn on/off LED */ 367234353Sdim switch (hw->mac.type) { 368221345Sdim case e1000_82574: 369193323Sed mac->ops.led_on = e1000_led_on_82574; 370221345Sdim break; 371221345Sdim default: 372193323Sed mac->ops.led_on = e1000_led_on_generic; 373221345Sdim break; 374234353Sdim } 375234353Sdim mac->ops.led_off = e1000_led_off_generic; 376221345Sdim /* clear hardware counters */ 377221345Sdim mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82571; 378221345Sdim /* link info */ 379221345Sdim mac->ops.get_link_up_info = 380221345Sdim (hw->phy.media_type == e1000_media_type_copper) 381224145Sdim ? e1000_get_speed_and_duplex_copper_generic 382224145Sdim : e1000_get_speed_and_duplex_fiber_serdes_generic; 383193323Sed 384221345Sdimout: 385221345Sdim return ret_val; 386221345Sdim} 387221345Sdim 388193323Sed/** 389193323Sed * e1000_init_function_pointers_82571 - Init func ptrs. 390193323Sed * @hw: pointer to the HW structure 391221345Sdim * 392193323Sed * Called to initialize all function pointers and parameters. 393210299Sed **/ 394210299Sedvoid e1000_init_function_pointers_82571(struct e1000_hw *hw) 395193323Sed{ 396193323Sed DEBUGFUNC("e1000_init_function_pointers_82571"); 397193323Sed 398221345Sdim hw->mac.ops.init_params = e1000_init_mac_params_82571; 399221345Sdim hw->nvm.ops.init_params = e1000_init_nvm_params_82571; 400221345Sdim hw->phy.ops.init_params = e1000_init_phy_params_82571; 401221345Sdim} 402221345Sdim 403221345Sdim/** 404221345Sdim * e1000_get_phy_id_82571 - Retrieve the PHY ID and revision 405193323Sed * @hw: pointer to the HW structure 406221345Sdim * 407221345Sdim * Reads the PHY registers and stores the PHY ID and possibly the PHY 408221345Sdim * revision in the hardware structure. 409234353Sdim **/ 410221345Sdimstatic s32 e1000_get_phy_id_82571(struct e1000_hw *hw) 411193323Sed{ 412193323Sed struct e1000_phy_info *phy = &hw->phy; 413221345Sdim s32 ret_val = E1000_SUCCESS; 414221345Sdim u16 phy_id = 0; 415221345Sdim 416234353Sdim DEBUGFUNC("e1000_get_phy_id_82571"); 417221345Sdim 418221345Sdim switch (hw->mac.type) { 419221345Sdim case e1000_82571: 420193323Sed case e1000_82572: 421193323Sed /* 422193323Sed * The 82571 firmware may still be configuring the PHY. 423221345Sdim * In this case, we cannot access the PHY until the 424193323Sed * configuration is done. So we explicitly set the 425221345Sdim * PHY ID. 426221345Sdim */ 427221345Sdim phy->id = IGP01E1000_I_PHY_ID; 428221345Sdim break; 429221345Sdim case e1000_82573: 430221345Sdim ret_val = e1000_get_phy_id(hw); 431221345Sdim break; 432221345Sdim case e1000_82574: 433221345Sdim ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id); 434221345Sdim if (ret_val) 435221345Sdim goto out; 436221345Sdim 437221345Sdim phy->id = (u32)(phy_id << 16); 438221345Sdim usec_delay(20); 439221345Sdim ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id); 440221345Sdim if (ret_val) 441221345Sdim goto out; 442221345Sdim 443221345Sdim phy->id |= (u32)(phy_id); 444193323Sed phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); 445193323Sed break; 446221345Sdim default: 447193323Sed ret_val = -E1000_ERR_PHY; 448193323Sed break; 449221345Sdim } 450193323Sed 451221345Sdimout: 452193323Sed return ret_val; 453221345Sdim} 454193323Sed 455193323Sed/** 456193399Sed * e1000_get_hw_semaphore_82571 - Acquire hardware semaphore 457 * @hw: pointer to the HW structure 458 * 459 * Acquire the HW semaphore to access the PHY or NVM 460 **/ 461static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw) 462{ 463 u32 swsm; 464 s32 ret_val = E1000_SUCCESS; 465 s32 timeout = hw->nvm.word_size + 1; 466 s32 i = 0; 467 468 DEBUGFUNC("e1000_get_hw_semaphore_82571"); 469 470 /* Get the FW semaphore. */ 471 for (i = 0; i < timeout; i++) { 472 swsm = E1000_READ_REG(hw, E1000_SWSM); 473 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI); 474 475 /* Semaphore acquired if bit latched */ 476 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI) 477 break; 478 479 usec_delay(50); 480 } 481 482 if (i == timeout) { 483 /* Release semaphores */ 484 e1000_put_hw_semaphore_generic(hw); 485 DEBUGOUT("Driver can't access the NVM\n"); 486 ret_val = -E1000_ERR_NVM; 487 goto out; 488 } 489 490out: 491 return ret_val; 492} 493 494/** 495 * e1000_put_hw_semaphore_82571 - Release hardware semaphore 496 * @hw: pointer to the HW structure 497 * 498 * Release hardware semaphore used to access the PHY or NVM 499 **/ 500static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw) 501{ 502 u32 swsm; 503 504 DEBUGFUNC("e1000_put_hw_semaphore_82571"); 505 506 swsm = E1000_READ_REG(hw, E1000_SWSM); 507 508 swsm &= ~E1000_SWSM_SWESMBI; 509 510 E1000_WRITE_REG(hw, E1000_SWSM, swsm); 511} 512 513/** 514 * e1000_acquire_nvm_82571 - Request for access to the EEPROM 515 * @hw: pointer to the HW structure 516 * 517 * To gain access to the EEPROM, first we must obtain a hardware semaphore. 518 * Then for non-82573 hardware, set the EEPROM access request bit and wait 519 * for EEPROM access grant bit. If the access grant bit is not set, release 520 * hardware semaphore. 521 **/ 522static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw) 523{ 524 s32 ret_val; 525 526 DEBUGFUNC("e1000_acquire_nvm_82571"); 527 528 ret_val = e1000_get_hw_semaphore_82571(hw); 529 if (ret_val) 530 goto out; 531 532 switch (hw->mac.type) { 533 case e1000_82574: 534 case e1000_82573: 535 break; 536 default: 537 ret_val = e1000_acquire_nvm_generic(hw); 538 break; 539 } 540 541 if (ret_val) 542 e1000_put_hw_semaphore_82571(hw); 543 544out: 545 return ret_val; 546} 547 548/** 549 * e1000_release_nvm_82571 - Release exclusive access to EEPROM 550 * @hw: pointer to the HW structure 551 * 552 * Stop any current commands to the EEPROM and clear the EEPROM request bit. 553 **/ 554static void e1000_release_nvm_82571(struct e1000_hw *hw) 555{ 556 DEBUGFUNC("e1000_release_nvm_82571"); 557 558 e1000_release_nvm_generic(hw); 559 e1000_put_hw_semaphore_82571(hw); 560} 561 562/** 563 * e1000_write_nvm_82571 - Write to EEPROM using appropriate interface 564 * @hw: pointer to the HW structure 565 * @offset: offset within the EEPROM to be written to 566 * @words: number of words to write 567 * @data: 16 bit word(s) to be written to the EEPROM 568 * 569 * For non-82573 silicon, write data to EEPROM at offset using SPI interface. 570 * 571 * If e1000_update_nvm_checksum is not called after this function, the 572 * EEPROM will most likely contain an invalid checksum. 573 **/ 574static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words, 575 u16 *data) 576{ 577 s32 ret_val = E1000_SUCCESS; 578 579 DEBUGFUNC("e1000_write_nvm_82571"); 580 581 switch (hw->mac.type) { 582 case e1000_82573: 583 case e1000_82574: 584 ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data); 585 break; 586 case e1000_82571: 587 case e1000_82572: 588 ret_val = e1000_write_nvm_spi(hw, offset, words, data); 589 break; 590 default: 591 ret_val = -E1000_ERR_NVM; 592 break; 593 } 594 595 return ret_val; 596} 597 598/** 599 * e1000_update_nvm_checksum_82571 - Update EEPROM checksum 600 * @hw: pointer to the HW structure 601 * 602 * Updates the EEPROM checksum by reading/adding each word of the EEPROM 603 * up to the checksum. Then calculates the EEPROM checksum and writes the 604 * value to the EEPROM. 605 **/ 606static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw) 607{ 608 u32 eecd; 609 s32 ret_val; 610 u16 i; 611 612 DEBUGFUNC("e1000_update_nvm_checksum_82571"); 613 614 ret_val = e1000_update_nvm_checksum_generic(hw); 615 if (ret_val) 616 goto out; 617 618 /* 619 * If our nvm is an EEPROM, then we're done 620 * otherwise, commit the checksum to the flash NVM. 621 */ 622 if (hw->nvm.type != e1000_nvm_flash_hw) 623 goto out; 624 625 /* Check for pending operations. */ 626 for (i = 0; i < E1000_FLASH_UPDATES; i++) { 627 msec_delay(1); 628 if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD) == 0) 629 break; 630 } 631 632 if (i == E1000_FLASH_UPDATES) { 633 ret_val = -E1000_ERR_NVM; 634 goto out; 635 } 636 637 /* Reset the firmware if using STM opcode. */ 638 if ((E1000_READ_REG(hw, E1000_FLOP) & 0xFF00) == E1000_STM_OPCODE) { 639 /* 640 * The enabling of and the actual reset must be done 641 * in two write cycles. 642 */ 643 E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET_ENABLE); 644 E1000_WRITE_FLUSH(hw); 645 E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET); 646 } 647 648 /* Commit the write to flash */ 649 eecd = E1000_READ_REG(hw, E1000_EECD) | E1000_EECD_FLUPD; 650 E1000_WRITE_REG(hw, E1000_EECD, eecd); 651 652 for (i = 0; i < E1000_FLASH_UPDATES; i++) { 653 msec_delay(1); 654 if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD) == 0) 655 break; 656 } 657 658 if (i == E1000_FLASH_UPDATES) { 659 ret_val = -E1000_ERR_NVM; 660 goto out; 661 } 662 663out: 664 return ret_val; 665} 666 667/** 668 * e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum 669 * @hw: pointer to the HW structure 670 * 671 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM 672 * and then verifies that the sum of the EEPROM is equal to 0xBABA. 673 **/ 674static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw) 675{ 676 DEBUGFUNC("e1000_validate_nvm_checksum_82571"); 677 678 if (hw->nvm.type == e1000_nvm_flash_hw) 679 e1000_fix_nvm_checksum_82571(hw); 680 681 return e1000_validate_nvm_checksum_generic(hw); 682} 683 684/** 685 * e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon 686 * @hw: pointer to the HW structure 687 * @offset: offset within the EEPROM to be written to 688 * @words: number of words to write 689 * @data: 16 bit word(s) to be written to the EEPROM 690 * 691 * After checking for invalid values, poll the EEPROM to ensure the previous 692 * command has completed before trying to write the next word. After write 693 * poll for completion. 694 * 695 * If e1000_update_nvm_checksum is not called after this function, the 696 * EEPROM will most likely contain an invalid checksum. 697 **/ 698static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, 699 u16 words, u16 *data) 700{ 701 struct e1000_nvm_info *nvm = &hw->nvm; 702 u32 i, eewr = 0; 703 s32 ret_val = 0; 704 705 DEBUGFUNC("e1000_write_nvm_eewr_82571"); 706 707 /* 708 * A check for invalid values: offset too large, too many words, 709 * and not enough words. 710 */ 711 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 712 (words == 0)) { 713 DEBUGOUT("nvm parameter(s) out of bounds\n"); 714 ret_val = -E1000_ERR_NVM; 715 goto out; 716 } 717 718 for (i = 0; i < words; i++) { 719 eewr = (data[i] << E1000_NVM_RW_REG_DATA) | 720 ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) | 721 E1000_NVM_RW_REG_START; 722 723 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE); 724 if (ret_val) 725 break; 726 727 E1000_WRITE_REG(hw, E1000_EEWR, eewr); 728 729 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE); 730 if (ret_val) 731 break; 732 } 733 734out: 735 return ret_val; 736} 737 738/** 739 * e1000_get_cfg_done_82571 - Poll for configuration done 740 * @hw: pointer to the HW structure 741 * 742 * Reads the management control register for the config done bit to be set. 743 **/ 744static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw) 745{ 746 s32 timeout = PHY_CFG_TIMEOUT; 747 s32 ret_val = E1000_SUCCESS; 748 749 DEBUGFUNC("e1000_get_cfg_done_82571"); 750 751 while (timeout) { 752 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & E1000_NVM_CFG_DONE_PORT_0) 753 break; 754 msec_delay(1); 755 timeout--; 756 } 757 if (!timeout) { 758 DEBUGOUT("MNG configuration cycle has not completed.\n"); 759 ret_val = -E1000_ERR_RESET; 760 goto out; 761 } 762 763out: 764 return ret_val; 765} 766 767/** 768 * e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state 769 * @hw: pointer to the HW structure 770 * @active: TRUE to enable LPLU, FALSE to disable 771 * 772 * Sets the LPLU D0 state according to the active flag. When activating LPLU 773 * this function also disables smart speed and vice versa. LPLU will not be 774 * activated unless the device autonegotiation advertisement meets standards 775 * of either 10 or 10/100 or 10/100/1000 at all duplexes. This is a function 776 * pointer entry point only called by PHY setup routines. 777 **/ 778static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active) 779{ 780 struct e1000_phy_info *phy = &hw->phy; 781 s32 ret_val = E1000_SUCCESS; 782 u16 data; 783 784 DEBUGFUNC("e1000_set_d0_lplu_state_82571"); 785 786 if (!(phy->ops.read_reg)) 787 goto out; 788 789 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); 790 if (ret_val) 791 goto out; 792 793 if (active) { 794 data |= IGP02E1000_PM_D0_LPLU; 795 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 796 data); 797 if (ret_val) 798 goto out; 799 800 /* When LPLU is enabled, we should disable SmartSpeed */ 801 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 802 &data); 803 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 804 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 805 data); 806 if (ret_val) 807 goto out; 808 } else { 809 data &= ~IGP02E1000_PM_D0_LPLU; 810 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 811 data); 812 /* 813 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 814 * during Dx states where the power conservation is most 815 * important. During driver activity we should enable 816 * SmartSpeed, so performance is maintained. 817 */ 818 if (phy->smart_speed == e1000_smart_speed_on) { 819 ret_val = phy->ops.read_reg(hw, 820 IGP01E1000_PHY_PORT_CONFIG, 821 &data); 822 if (ret_val) 823 goto out; 824 825 data |= IGP01E1000_PSCFR_SMART_SPEED; 826 ret_val = phy->ops.write_reg(hw, 827 IGP01E1000_PHY_PORT_CONFIG, 828 data); 829 if (ret_val) 830 goto out; 831 } else if (phy->smart_speed == e1000_smart_speed_off) { 832 ret_val = phy->ops.read_reg(hw, 833 IGP01E1000_PHY_PORT_CONFIG, 834 &data); 835 if (ret_val) 836 goto out; 837 838 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 839 ret_val = phy->ops.write_reg(hw, 840 IGP01E1000_PHY_PORT_CONFIG, 841 data); 842 if (ret_val) 843 goto out; 844 } 845 } 846 847out: 848 return ret_val; 849} 850 851/** 852 * e1000_reset_hw_82571 - Reset hardware 853 * @hw: pointer to the HW structure 854 * 855 * This resets the hardware into a known state. 856 **/ 857static s32 e1000_reset_hw_82571(struct e1000_hw *hw) 858{ 859 u32 ctrl, extcnf_ctrl, ctrl_ext, icr; 860 s32 ret_val; 861 u16 i = 0; 862 863 DEBUGFUNC("e1000_reset_hw_82571"); 864 865 /* 866 * Prevent the PCI-E bus from sticking if there is no TLP connection 867 * on the last TLP read/write transaction when MAC is reset. 868 */ 869 ret_val = e1000_disable_pcie_master_generic(hw); 870 if (ret_val) 871 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 872 873 DEBUGOUT("Masking off all interrupts\n"); 874 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 875 876 E1000_WRITE_REG(hw, E1000_RCTL, 0); 877 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 878 E1000_WRITE_FLUSH(hw); 879 880 msec_delay(10); 881 882 /* 883 * Must acquire the MDIO ownership before MAC reset. 884 * Ownership defaults to firmware after a reset. 885 */ 886 switch (hw->mac.type) { 887 case e1000_82574: 888 case e1000_82573: 889 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 890 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; 891 892 do { 893 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); 894 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 895 896 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP) 897 break; 898 899 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; 900 901 msec_delay(2); 902 i++; 903 } while (i < MDIO_OWNERSHIP_TIMEOUT); 904 break; 905 default: 906 break; 907 } 908 909 ctrl = E1000_READ_REG(hw, E1000_CTRL); 910 911 DEBUGOUT("Issuing a global reset to MAC\n"); 912 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 913 914 if (hw->nvm.type == e1000_nvm_flash_hw) { 915 usec_delay(10); 916 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 917 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 918 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 919 E1000_WRITE_FLUSH(hw); 920 } 921 922 ret_val = e1000_get_auto_rd_done_generic(hw); 923 if (ret_val) 924 /* We don't want to continue accessing MAC registers. */ 925 goto out; 926 927 /* 928 * Phy configuration from NVM just starts after EECD_AUTO_RD is set. 929 * Need to wait for Phy configuration completion before accessing 930 * NVM and Phy. 931 */ 932 933 switch (hw->mac.type) { 934 case e1000_82574: 935 case e1000_82573: 936 msec_delay(25); 937 break; 938 default: 939 break; 940 } 941 942 /* Clear any pending interrupt events. */ 943 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 944 icr = E1000_READ_REG(hw, E1000_ICR); 945 946 /* Install any alternate MAC address into RAR0 */ 947 ret_val = e1000_check_alt_mac_addr_generic(hw); 948 if (ret_val) 949 goto out; 950 951 e1000_set_laa_state_82571(hw, TRUE); 952 953 /* Reinitialize the 82571 serdes link state machine */ 954 if (hw->phy.media_type == e1000_media_type_internal_serdes) 955 hw->mac.serdes_link_state = e1000_serdes_link_down; 956 957out: 958 return ret_val; 959} 960 961/** 962 * e1000_init_hw_82571 - Initialize hardware 963 * @hw: pointer to the HW structure 964 * 965 * This inits the hardware readying it for operation. 966 **/ 967static s32 e1000_init_hw_82571(struct e1000_hw *hw) 968{ 969 struct e1000_mac_info *mac = &hw->mac; 970 u32 reg_data; 971 s32 ret_val; 972 u16 i, rar_count = mac->rar_entry_count; 973 974 DEBUGFUNC("e1000_init_hw_82571"); 975 976 e1000_initialize_hw_bits_82571(hw); 977 978 /* Initialize identification LED */ 979 ret_val = mac->ops.id_led_init(hw); 980 if (ret_val) { 981 DEBUGOUT("Error initializing identification LED\n"); 982 /* This is not fatal and we should not stop init due to this */ 983 } 984 985 /* Disabling VLAN filtering */ 986 DEBUGOUT("Initializing the IEEE VLAN\n"); 987 mac->ops.clear_vfta(hw); 988 989 /* Setup the receive address. */ 990 /* 991 * If, however, a locally administered address was assigned to the 992 * 82571, we must reserve a RAR for it to work around an issue where 993 * resetting one port will reload the MAC on the other port. 994 */ 995 if (e1000_get_laa_state_82571(hw)) 996 rar_count--; 997 e1000_init_rx_addrs_generic(hw, rar_count); 998 999 /* Zero out the Multicast HASH table */ 1000 DEBUGOUT("Zeroing the MTA\n"); 1001 for (i = 0; i < mac->mta_reg_count; i++) 1002 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 1003 1004 /* Setup link and flow control */ 1005 ret_val = mac->ops.setup_link(hw); 1006 1007 /* Set the transmit descriptor write-back policy */ 1008 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0)); 1009 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | 1010 E1000_TXDCTL_FULL_TX_DESC_WB | 1011 E1000_TXDCTL_COUNT_DESC; 1012 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data); 1013 1014 /* ...for both queues. */ 1015 switch (mac->type) { 1016 case e1000_82574: 1017 case e1000_82573: 1018 e1000_enable_tx_pkt_filtering_generic(hw); 1019 reg_data = E1000_READ_REG(hw, E1000_GCR); 1020 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; 1021 E1000_WRITE_REG(hw, E1000_GCR, reg_data); 1022 break; 1023 default: 1024 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1)); 1025 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | 1026 E1000_TXDCTL_FULL_TX_DESC_WB | 1027 E1000_TXDCTL_COUNT_DESC; 1028 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data); 1029 break; 1030 } 1031 1032 /* 1033 * Clear all of the statistics registers (clear on read). It is 1034 * important that we do this after we have tried to establish link 1035 * because the symbol error count will increment wildly if there 1036 * is no link. 1037 */ 1038 e1000_clear_hw_cntrs_82571(hw); 1039 1040 return ret_val; 1041} 1042 1043/** 1044 * e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits 1045 * @hw: pointer to the HW structure 1046 * 1047 * Initializes required hardware-dependent bits needed for normal operation. 1048 **/ 1049static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw) 1050{ 1051 u32 reg; 1052 1053 DEBUGFUNC("e1000_initialize_hw_bits_82571"); 1054 1055 /* Transmit Descriptor Control 0 */ 1056 reg = E1000_READ_REG(hw, E1000_TXDCTL(0)); 1057 reg |= (1 << 22); 1058 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg); 1059 1060 /* Transmit Descriptor Control 1 */ 1061 reg = E1000_READ_REG(hw, E1000_TXDCTL(1)); 1062 reg |= (1 << 22); 1063 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg); 1064 1065 /* Transmit Arbitration Control 0 */ 1066 reg = E1000_READ_REG(hw, E1000_TARC(0)); 1067 reg &= ~(0xF << 27); /* 30:27 */ 1068 switch (hw->mac.type) { 1069 case e1000_82571: 1070 case e1000_82572: 1071 reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26); 1072 break; 1073 default: 1074 break; 1075 } 1076 E1000_WRITE_REG(hw, E1000_TARC(0), reg); 1077 1078 /* Transmit Arbitration Control 1 */ 1079 reg = E1000_READ_REG(hw, E1000_TARC(1)); 1080 switch (hw->mac.type) { 1081 case e1000_82571: 1082 case e1000_82572: 1083 reg &= ~((1 << 29) | (1 << 30)); 1084 reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26); 1085 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR) 1086 reg &= ~(1 << 28); 1087 else 1088 reg |= (1 << 28); 1089 E1000_WRITE_REG(hw, E1000_TARC(1), reg); 1090 break; 1091 default: 1092 break; 1093 } 1094 1095 /* Device Control */ 1096 1097 switch (hw->mac.type) { 1098 case e1000_82574: 1099 case e1000_82573: 1100 reg = E1000_READ_REG(hw, E1000_CTRL); 1101 reg &= ~(1 << 29); 1102 E1000_WRITE_REG(hw, E1000_CTRL, reg); 1103 break; 1104 default: 1105 break; 1106 } 1107 1108 /* Extended Device Control */ 1109 switch (hw->mac.type) { 1110 case e1000_82574: 1111 case e1000_82573: 1112 reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 1113 reg &= ~(1 << 23); 1114 reg |= (1 << 22); 1115 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 1116 break; 1117 default: 1118 break; 1119 } 1120 1121 1122 if (hw->mac.type == e1000_82571) { 1123 reg = E1000_READ_REG(hw, E1000_PBA_ECC); 1124 reg |= E1000_PBA_ECC_CORR_EN; 1125 E1000_WRITE_REG(hw, E1000_PBA_ECC, reg); 1126 } 1127 1128 /* 1129 * Workaround for hardware errata. 1130 * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572 1131 */ 1132 1133 if ((hw->mac.type == e1000_82571) || 1134 (hw->mac.type == e1000_82572)) { 1135 reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 1136 reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN; 1137 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 1138 } 1139 1140 /* PCI-Ex Control Registers */ 1141 1142 switch (hw->mac.type) { 1143 case e1000_82574: 1144 reg = E1000_READ_REG(hw, E1000_GCR); 1145 reg |= (1 << 22); 1146 E1000_WRITE_REG(hw, E1000_GCR, reg); 1147 /* 1148 * Workaround for hardware errata. 1149 * apply workaround for hardware errata documented in errata 1150 * docs Fixes issue where some error prone or unreliable PCIe 1151 * completions are occurring, particularly with ASPM enabled. 1152 * Without fix, issue can cause tx timeouts. 1153 */ 1154 reg = E1000_READ_REG(hw, E1000_GCR2); 1155 reg |= 1; 1156 E1000_WRITE_REG(hw, E1000_GCR2, reg); 1157 break; 1158 default: 1159 break; 1160 } 1161 1162 return; 1163} 1164 1165/** 1166 * e1000_clear_vfta_82571 - Clear VLAN filter table 1167 * @hw: pointer to the HW structure 1168 * 1169 * Clears the register array which contains the VLAN filter table by 1170 * setting all the values to 0. 1171 **/ 1172static void e1000_clear_vfta_82571(struct e1000_hw *hw) 1173{ 1174 u32 offset; 1175 u32 vfta_value = 0; 1176 u32 vfta_offset = 0; 1177 u32 vfta_bit_in_reg = 0; 1178 1179 DEBUGFUNC("e1000_clear_vfta_82571"); 1180 1181 switch (hw->mac.type) { 1182 case e1000_82574: 1183 case e1000_82573: 1184 if (hw->mng_cookie.vlan_id != 0) { 1185 /* 1186 *The VFTA is a 4096b bit-field, each identifying 1187 *a single VLAN ID. The following operations 1188 *determine which 32b entry (i.e. offset) into the 1189 *array we want to set the VLAN ID (i.e. bit) of 1190 *the manageability unit. 1191 */ 1192 vfta_offset = (hw->mng_cookie.vlan_id >> 1193 E1000_VFTA_ENTRY_SHIFT) & E1000_VFTA_ENTRY_MASK; 1194 vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id & 1195 E1000_VFTA_ENTRY_BIT_SHIFT_MASK); 1196 } 1197 1198 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 1199 /* 1200 *If the offset we want to clear is the same offset of 1201 *the manageability VLAN ID, then clear all bits except 1202 *that of the manageability unit 1203 */ 1204 vfta_value = (offset == vfta_offset) ? 1205 vfta_bit_in_reg : 0; 1206 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 1207 vfta_value); 1208 E1000_WRITE_FLUSH(hw); 1209 } 1210 break; 1211 default: 1212 break; 1213 } 1214} 1215 1216/** 1217 * e1000_check_mng_mode_82574 - Check manageability is enabled 1218 * @hw: pointer to the HW structure 1219 * 1220 * Reads the NVM Initialization Control Word 2 and returns TRUE 1221 * (>0) if any manageability is enabled, else FALSE (0). 1222 **/ 1223static bool e1000_check_mng_mode_82574(struct e1000_hw *hw) 1224{ 1225 u16 data; 1226 1227 DEBUGFUNC("e1000_check_mng_mode_82574"); 1228 1229 hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &data); 1230 return (data & E1000_NVM_INIT_CTRL2_MNGM) != 0; 1231} 1232 1233/** 1234 * e1000_led_on_82574 - Turn LED on 1235 * @hw: pointer to the HW structure 1236 * 1237 * Turn LED on. 1238 **/ 1239static s32 e1000_led_on_82574(struct e1000_hw *hw) 1240{ 1241 u32 ctrl; 1242 u32 i; 1243 1244 DEBUGFUNC("e1000_led_on_82574"); 1245 1246 ctrl = hw->mac.ledctl_mode2; 1247 if (!(E1000_STATUS_LU & E1000_READ_REG(hw, E1000_STATUS))) { 1248 /* 1249 * If no link, then turn LED on by setting the invert bit 1250 * for each LED that's "on" (0x0E) in ledctl_mode2. 1251 */ 1252 for (i = 0; i < 4; i++) 1253 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) == 1254 E1000_LEDCTL_MODE_LED_ON) 1255 ctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8)); 1256 } 1257 E1000_WRITE_REG(hw, E1000_LEDCTL, ctrl); 1258 1259 return E1000_SUCCESS; 1260} 1261 1262 1263/** 1264 * e1000_setup_link_82571 - Setup flow control and link settings 1265 * @hw: pointer to the HW structure 1266 * 1267 * Determines which flow control settings to use, then configures flow 1268 * control. Calls the appropriate media-specific link configuration 1269 * function. Assuming the adapter has a valid link partner, a valid link 1270 * should be established. Assumes the hardware has previously been reset 1271 * and the transmitter and receiver are not enabled. 1272 **/ 1273static s32 e1000_setup_link_82571(struct e1000_hw *hw) 1274{ 1275 DEBUGFUNC("e1000_setup_link_82571"); 1276 1277 /* 1278 * 82573 does not have a word in the NVM to determine 1279 * the default flow control setting, so we explicitly 1280 * set it to full. 1281 */ 1282 switch (hw->mac.type) { 1283 case e1000_82574: 1284 case e1000_82573: 1285 if (hw->fc.requested_mode == e1000_fc_default) 1286 hw->fc.requested_mode = e1000_fc_full; 1287 break; 1288 default: 1289 break; 1290 } 1291 return e1000_setup_link_generic(hw); 1292} 1293 1294/** 1295 * e1000_setup_copper_link_82571 - Configure copper link settings 1296 * @hw: pointer to the HW structure 1297 * 1298 * Configures the link for auto-neg or forced speed and duplex. Then we check 1299 * for link, once link is established calls to configure collision distance 1300 * and flow control are called. 1301 **/ 1302static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw) 1303{ 1304 u32 ctrl, led_ctrl; 1305 s32 ret_val; 1306 1307 DEBUGFUNC("e1000_setup_copper_link_82571"); 1308 1309 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1310 ctrl |= E1000_CTRL_SLU; 1311 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1312 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1313 1314 switch (hw->phy.type) { 1315 case e1000_phy_m88: 1316 case e1000_phy_bm: 1317 ret_val = e1000_copper_link_setup_m88(hw); 1318 break; 1319 case e1000_phy_igp_2: 1320 ret_val = e1000_copper_link_setup_igp(hw); 1321 /* Setup activity LED */ 1322 led_ctrl = E1000_READ_REG(hw, E1000_LEDCTL); 1323 led_ctrl &= IGP_ACTIVITY_LED_MASK; 1324 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 1325 E1000_WRITE_REG(hw, E1000_LEDCTL, led_ctrl); 1326 break; 1327 default: 1328 ret_val = -E1000_ERR_PHY; 1329 break; 1330 } 1331 1332 if (ret_val) 1333 goto out; 1334 1335 ret_val = e1000_setup_copper_link_generic(hw); 1336 1337out: 1338 return ret_val; 1339} 1340 1341/** 1342 * e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes 1343 * @hw: pointer to the HW structure 1344 * 1345 * Configures collision distance and flow control for fiber and serdes links. 1346 * Upon successful setup, poll for link. 1347 **/ 1348static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw) 1349{ 1350 DEBUGFUNC("e1000_setup_fiber_serdes_link_82571"); 1351 1352 switch (hw->mac.type) { 1353 case e1000_82571: 1354 case e1000_82572: 1355 /* 1356 * If SerDes loopback mode is entered, there is no form 1357 * of reset to take the adapter out of that mode. So we 1358 * have to explicitly take the adapter out of loopback 1359 * mode. This prevents drivers from twiddling their thumbs 1360 * if another tool failed to take it out of loopback mode. 1361 */ 1362 E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK); 1363 break; 1364 default: 1365 break; 1366 } 1367 1368 return e1000_setup_fiber_serdes_link_generic(hw); 1369} 1370 1371/** 1372 * e1000_check_for_serdes_link_82571 - Check for link (Serdes) 1373 * @hw: pointer to the HW structure 1374 * 1375 * Checks for link up on the hardware. If link is not up and we have 1376 * a signal, then we need to force link up. 1377 **/ 1378s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw) 1379{ 1380 struct e1000_mac_info *mac = &hw->mac; 1381 u32 rxcw; 1382 u32 ctrl; 1383 u32 status; 1384 s32 ret_val = E1000_SUCCESS; 1385 1386 DEBUGFUNC("e1000_check_for_serdes_link_82571"); 1387 1388 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1389 status = E1000_READ_REG(hw, E1000_STATUS); 1390 rxcw = E1000_READ_REG(hw, E1000_RXCW); 1391 1392 if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) { 1393 1394 /* Receiver is synchronized with no invalid bits. */ 1395 switch (mac->serdes_link_state) { 1396 case e1000_serdes_link_autoneg_complete: 1397 if (!(status & E1000_STATUS_LU)) { 1398 /* 1399 * We have lost link, retry autoneg before 1400 * reporting link failure 1401 */ 1402 mac->serdes_link_state = 1403 e1000_serdes_link_autoneg_progress; 1404 DEBUGOUT("AN_UP -> AN_PROG\n"); 1405 } 1406 break; 1407 1408 case e1000_serdes_link_forced_up: 1409 /* 1410 * If we are receiving /C/ ordered sets, re-enable 1411 * auto-negotiation in the TXCW register and disable 1412 * forced link in the Device Control register in an 1413 * attempt to auto-negotiate with our link partner. 1414 */ 1415 if (rxcw & E1000_RXCW_C) { 1416 /* Enable autoneg, and unforce link up */ 1417 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 1418 E1000_WRITE_REG(hw, E1000_CTRL, 1419 (ctrl & ~E1000_CTRL_SLU)); 1420 mac->serdes_link_state = 1421 e1000_serdes_link_autoneg_progress; 1422 DEBUGOUT("FORCED_UP -> AN_PROG\n"); 1423 } 1424 break; 1425 1426 case e1000_serdes_link_autoneg_progress: 1427 /* 1428 * If the LU bit is set in the STATUS register, 1429 * autoneg has completed sucessfully. If not, 1430 * try foring the link because the far end may be 1431 * available but not capable of autonegotiation. 1432 */ 1433 if (status & E1000_STATUS_LU) { 1434 mac->serdes_link_state = 1435 e1000_serdes_link_autoneg_complete; 1436 DEBUGOUT("AN_PROG -> AN_UP\n"); 1437 } else { 1438 /* 1439 * Disable autoneg, force link up and 1440 * full duplex, and change state to forced 1441 */ 1442 E1000_WRITE_REG(hw, E1000_TXCW, 1443 (mac->txcw & ~E1000_TXCW_ANE)); 1444 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 1445 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1446 1447 /* Configure Flow Control after link up. */ 1448 ret_val = 1449 e1000_config_fc_after_link_up_generic(hw); 1450 if (ret_val) { 1451 DEBUGOUT("Error config flow control\n"); 1452 break; 1453 } 1454 mac->serdes_link_state = 1455 e1000_serdes_link_forced_up; 1456 DEBUGOUT("AN_PROG -> FORCED_UP\n"); 1457 } 1458 mac->serdes_has_link = TRUE; 1459 break; 1460 1461 case e1000_serdes_link_down: 1462 default: 1463 /* The link was down but the receiver has now gained 1464 * valid sync, so lets see if we can bring the link 1465 * up. */ 1466 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 1467 E1000_WRITE_REG(hw, E1000_CTRL, 1468 (ctrl & ~E1000_CTRL_SLU)); 1469 mac->serdes_link_state = 1470 e1000_serdes_link_autoneg_progress; 1471 DEBUGOUT("DOWN -> AN_PROG\n"); 1472 break; 1473 } 1474 } else { 1475 if (!(rxcw & E1000_RXCW_SYNCH)) { 1476 mac->serdes_has_link = FALSE; 1477 mac->serdes_link_state = e1000_serdes_link_down; 1478 DEBUGOUT("ANYSTATE -> DOWN\n"); 1479 } else { 1480 /* 1481 * We have sync, and can tolerate one 1482 * invalid (IV) codeword before declaring 1483 * link down, so reread to look again 1484 */ 1485 usec_delay(10); 1486 rxcw = E1000_READ_REG(hw, E1000_RXCW); 1487 if (rxcw & E1000_RXCW_IV) { 1488 mac->serdes_link_state = e1000_serdes_link_down; 1489 mac->serdes_has_link = FALSE; 1490 DEBUGOUT("ANYSTATE -> DOWN\n"); 1491 } 1492 } 1493 } 1494 1495 return ret_val; 1496} 1497 1498/** 1499 * e1000_valid_led_default_82571 - Verify a valid default LED config 1500 * @hw: pointer to the HW structure 1501 * @data: pointer to the NVM (EEPROM) 1502 * 1503 * Read the EEPROM for the current default LED configuration. If the 1504 * LED configuration is not valid, set to a valid LED configuration. 1505 **/ 1506static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data) 1507{ 1508 s32 ret_val; 1509 1510 DEBUGFUNC("e1000_valid_led_default_82571"); 1511 1512 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); 1513 if (ret_val) { 1514 DEBUGOUT("NVM Read Error\n"); 1515 goto out; 1516 } 1517 1518 switch (hw->mac.type) { 1519 case e1000_82574: 1520 case e1000_82573: 1521 if(*data == ID_LED_RESERVED_F746) 1522 *data = ID_LED_DEFAULT_82573; 1523 break; 1524 default: 1525 if (*data == ID_LED_RESERVED_0000 || 1526 *data == ID_LED_RESERVED_FFFF) 1527 *data = ID_LED_DEFAULT; 1528 break; 1529 } 1530 1531out: 1532 return ret_val; 1533} 1534 1535/** 1536 * e1000_get_laa_state_82571 - Get locally administered address state 1537 * @hw: pointer to the HW structure 1538 * 1539 * Retrieve and return the current locally administered address state. 1540 **/ 1541bool e1000_get_laa_state_82571(struct e1000_hw *hw) 1542{ 1543 DEBUGFUNC("e1000_get_laa_state_82571"); 1544 1545 if (hw->mac.type != e1000_82571) 1546 return FALSE; 1547 1548 return hw->dev_spec._82571.laa_is_present; 1549} 1550 1551/** 1552 * e1000_set_laa_state_82571 - Set locally administered address state 1553 * @hw: pointer to the HW structure 1554 * @state: enable/disable locally administered address 1555 * 1556 * Enable/Disable the current locally administered address state. 1557 **/ 1558void e1000_set_laa_state_82571(struct e1000_hw *hw, bool state) 1559{ 1560 DEBUGFUNC("e1000_set_laa_state_82571"); 1561 1562 if (hw->mac.type != e1000_82571) 1563 return; 1564 1565 hw->dev_spec._82571.laa_is_present = state; 1566 1567 /* If workaround is activated... */ 1568 if (state) 1569 /* 1570 * Hold a copy of the LAA in RAR[14] This is done so that 1571 * between the time RAR[0] gets clobbered and the time it 1572 * gets fixed, the actual LAA is in one of the RARs and no 1573 * incoming packets directed to this port are dropped. 1574 * Eventually the LAA will be in RAR[0] and RAR[14]. 1575 */ 1576 e1000_rar_set_generic(hw, hw->mac.addr, 1577 hw->mac.rar_entry_count - 1); 1578 return; 1579} 1580 1581/** 1582 * e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum 1583 * @hw: pointer to the HW structure 1584 * 1585 * Verifies that the EEPROM has completed the update. After updating the 1586 * EEPROM, we need to check bit 15 in work 0x23 for the checksum fix. If 1587 * the checksum fix is not implemented, we need to set the bit and update 1588 * the checksum. Otherwise, if bit 15 is set and the checksum is incorrect, 1589 * we need to return bad checksum. 1590 **/ 1591static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw) 1592{ 1593 struct e1000_nvm_info *nvm = &hw->nvm; 1594 s32 ret_val = E1000_SUCCESS; 1595 u16 data; 1596 1597 DEBUGFUNC("e1000_fix_nvm_checksum_82571"); 1598 1599 if (nvm->type != e1000_nvm_flash_hw) 1600 goto out; 1601 1602 /* 1603 * Check bit 4 of word 10h. If it is 0, firmware is done updating 1604 * 10h-12h. Checksum may need to be fixed. 1605 */ 1606 ret_val = nvm->ops.read(hw, 0x10, 1, &data); 1607 if (ret_val) 1608 goto out; 1609 1610 if (!(data & 0x10)) { 1611 /* 1612 * Read 0x23 and check bit 15. This bit is a 1 1613 * when the checksum has already been fixed. If 1614 * the checksum is still wrong and this bit is a 1615 * 1, we need to return bad checksum. Otherwise, 1616 * we need to set this bit to a 1 and update the 1617 * checksum. 1618 */ 1619 ret_val = nvm->ops.read(hw, 0x23, 1, &data); 1620 if (ret_val) 1621 goto out; 1622 1623 if (!(data & 0x8000)) { 1624 data |= 0x8000; 1625 ret_val = nvm->ops.write(hw, 0x23, 1, &data); 1626 if (ret_val) 1627 goto out; 1628 ret_val = nvm->ops.update(hw); 1629 } 1630 } 1631 1632out: 1633 return ret_val; 1634} 1635 1636 1637/** 1638 * e1000_read_mac_addr_82571 - Read device MAC address 1639 * @hw: pointer to the HW structure 1640 **/ 1641static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw) 1642{ 1643 s32 ret_val = E1000_SUCCESS; 1644 1645 DEBUGFUNC("e1000_read_mac_addr_82571"); 1646 1647 /* 1648 * If there's an alternate MAC address place it in RAR0 1649 * so that it will override the Si installed default perm 1650 * address. 1651 */ 1652 ret_val = e1000_check_alt_mac_addr_generic(hw); 1653 if (ret_val) 1654 goto out; 1655 1656 ret_val = e1000_read_mac_addr_generic(hw); 1657 1658out: 1659 return ret_val; 1660} 1661 1662/** 1663 * e1000_power_down_phy_copper_82571 - Remove link during PHY power down 1664 * @hw: pointer to the HW structure 1665 * 1666 * In the case of a PHY power down to save power, or to turn off link during a 1667 * driver unload, or wake on lan is not enabled, remove the link. 1668 **/ 1669static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw) 1670{ 1671 struct e1000_phy_info *phy = &hw->phy; 1672 struct e1000_mac_info *mac = &hw->mac; 1673 1674 if (!(phy->ops.check_reset_block)) 1675 return; 1676 1677 /* If the management interface is not enabled, then power down */ 1678 if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw))) 1679 e1000_power_down_phy_copper(hw); 1680 1681 return; 1682} 1683 1684/** 1685 * e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters 1686 * @hw: pointer to the HW structure 1687 * 1688 * Clears the hardware counters by reading the counter registers. 1689 **/ 1690static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw) 1691{ 1692 DEBUGFUNC("e1000_clear_hw_cntrs_82571"); 1693 1694 e1000_clear_hw_cntrs_base_generic(hw); 1695 1696 E1000_READ_REG(hw, E1000_PRC64); 1697 E1000_READ_REG(hw, E1000_PRC127); 1698 E1000_READ_REG(hw, E1000_PRC255); 1699 E1000_READ_REG(hw, E1000_PRC511); 1700 E1000_READ_REG(hw, E1000_PRC1023); 1701 E1000_READ_REG(hw, E1000_PRC1522); 1702 E1000_READ_REG(hw, E1000_PTC64); 1703 E1000_READ_REG(hw, E1000_PTC127); 1704 E1000_READ_REG(hw, E1000_PTC255); 1705 E1000_READ_REG(hw, E1000_PTC511); 1706 E1000_READ_REG(hw, E1000_PTC1023); 1707 E1000_READ_REG(hw, E1000_PTC1522); 1708 1709 E1000_READ_REG(hw, E1000_ALGNERRC); 1710 E1000_READ_REG(hw, E1000_RXERRC); 1711 E1000_READ_REG(hw, E1000_TNCRS); 1712 E1000_READ_REG(hw, E1000_CEXTERR); 1713 E1000_READ_REG(hw, E1000_TSCTC); 1714 E1000_READ_REG(hw, E1000_TSCTFC); 1715 1716 E1000_READ_REG(hw, E1000_MGTPRC); 1717 E1000_READ_REG(hw, E1000_MGTPDC); 1718 E1000_READ_REG(hw, E1000_MGTPTC); 1719 1720 E1000_READ_REG(hw, E1000_IAC); 1721 E1000_READ_REG(hw, E1000_ICRXOC); 1722 1723 E1000_READ_REG(hw, E1000_ICRXPTC); 1724 E1000_READ_REG(hw, E1000_ICRXATC); 1725 E1000_READ_REG(hw, E1000_ICTXPTC); 1726 E1000_READ_REG(hw, E1000_ICTXATC); 1727 E1000_READ_REG(hw, E1000_ICTXQEC); 1728 E1000_READ_REG(hw, E1000_ICTXQMTC); 1729 E1000_READ_REG(hw, E1000_ICRXDMTC); 1730} 1731