e1000_82571.c revision 176667
1/******************************************************************************* 2 3 Copyright (c) 2001-2008, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32*******************************************************************************/ 33/* $FreeBSD: head/sys/dev/em/e1000_82571.c 176667 2008-02-29 21:50:11Z jfv $ */ 34 35 36/* e1000_82571 37 * e1000_82572 38 * e1000_82573 39 * e1000_82574 40 */ 41 42#include "e1000_api.h" 43#include "e1000_82571.h" 44 45STATIC s32 e1000_init_phy_params_82571(struct e1000_hw *hw); 46STATIC s32 e1000_init_nvm_params_82571(struct e1000_hw *hw); 47STATIC s32 e1000_init_mac_params_82571(struct e1000_hw *hw); 48STATIC s32 e1000_acquire_nvm_82571(struct e1000_hw *hw); 49STATIC void e1000_release_nvm_82571(struct e1000_hw *hw); 50STATIC s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, 51 u16 words, u16 *data); 52STATIC s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw); 53STATIC s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw); 54STATIC s32 e1000_get_cfg_done_82571(struct e1000_hw *hw); 55STATIC s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, 56 bool active); 57STATIC s32 e1000_reset_hw_82571(struct e1000_hw *hw); 58STATIC s32 e1000_init_hw_82571(struct e1000_hw *hw); 59STATIC void e1000_clear_vfta_82571(struct e1000_hw *hw); 60STATIC void e1000_update_mc_addr_list_82571(struct e1000_hw *hw, 61 u8 *mc_addr_list, u32 mc_addr_count, 62 u32 rar_used_count, u32 rar_count); 63STATIC s32 e1000_setup_link_82571(struct e1000_hw *hw); 64STATIC s32 e1000_setup_copper_link_82571(struct e1000_hw *hw); 65STATIC s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw); 66STATIC s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data); 67STATIC void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw); 68static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw); 69static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw); 70static s32 e1000_get_phy_id_82571(struct e1000_hw *hw); 71static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw); 72static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw); 73static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, 74 u16 words, u16 *data); 75STATIC s32 e1000_read_mac_addr_82571(struct e1000_hw *hw); 76STATIC void e1000_power_down_phy_copper_82571(struct e1000_hw *hw); 77 78struct e1000_dev_spec_82571 { 79 bool laa_is_present; 80}; 81 82/** 83 * e1000_init_phy_params_82571 - Init PHY func ptrs. 84 * @hw: pointer to the HW structure 85 * 86 * This is a function pointer entry point called by the api module. 87 **/ 88STATIC s32 e1000_init_phy_params_82571(struct e1000_hw *hw) 89{ 90 struct e1000_phy_info *phy = &hw->phy; 91 struct e1000_functions *func = &hw->func; 92 s32 ret_val = E1000_SUCCESS; 93 94 DEBUGFUNC("e1000_init_phy_params_82571"); 95 96 if (hw->phy.media_type != e1000_media_type_copper) { 97 phy->type = e1000_phy_none; 98 goto out; 99 } 100 101 phy->addr = 1; 102 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 103 phy->reset_delay_us = 100; 104 105 func->acquire_phy = e1000_get_hw_semaphore_82571; 106 func->check_polarity = e1000_check_polarity_igp; 107 func->check_reset_block = e1000_check_reset_block_generic; 108 func->release_phy = e1000_put_hw_semaphore_82571; 109 func->reset_phy = e1000_phy_hw_reset_generic; 110 func->set_d0_lplu_state = e1000_set_d0_lplu_state_82571; 111 func->set_d3_lplu_state = e1000_set_d3_lplu_state_generic; 112 func->power_up_phy = e1000_power_up_phy_copper; 113 func->power_down_phy = e1000_power_down_phy_copper_82571; 114 115 switch (hw->mac.type) { 116 case e1000_82571: 117 case e1000_82572: 118 phy->type = e1000_phy_igp_2; 119 func->get_cfg_done = e1000_get_cfg_done_82571; 120 func->get_phy_info = e1000_get_phy_info_igp; 121 func->force_speed_duplex = e1000_phy_force_speed_duplex_igp; 122 func->get_cable_length = e1000_get_cable_length_igp_2; 123 func->read_phy_reg = e1000_read_phy_reg_igp; 124 func->write_phy_reg = e1000_write_phy_reg_igp; 125 126 /* This uses above function pointers */ 127 ret_val = e1000_get_phy_id_82571(hw); 128 129 /* Verify PHY ID */ 130 if (phy->id != IGP01E1000_I_PHY_ID) { 131 ret_val = -E1000_ERR_PHY; 132 goto out; 133 } 134 break; 135 case e1000_82573: 136 phy->type = e1000_phy_m88; 137 func->get_cfg_done = e1000_get_cfg_done_generic; 138 func->get_phy_info = e1000_get_phy_info_m88; 139 func->commit_phy = e1000_phy_sw_reset_generic; 140 func->force_speed_duplex = e1000_phy_force_speed_duplex_m88; 141 func->get_cable_length = e1000_get_cable_length_m88; 142 func->read_phy_reg = e1000_read_phy_reg_m88; 143 func->write_phy_reg = e1000_write_phy_reg_m88; 144 145 /* This uses above function pointers */ 146 ret_val = e1000_get_phy_id_82571(hw); 147 148 /* Verify PHY ID */ 149 if (phy->id != M88E1111_I_PHY_ID) { 150 ret_val = -E1000_ERR_PHY; 151 DEBUGOUT1("PHY ID unknown: type = 0x%08x\n", phy->id); 152 goto out; 153 } 154 break; 155 case e1000_82574: 156 phy->type = e1000_phy_bm; 157 func->get_cfg_done = e1000_get_cfg_done_generic; 158 func->get_phy_info = e1000_get_phy_info_m88; 159 func->commit_phy = e1000_phy_sw_reset_generic; 160 func->force_speed_duplex = e1000_phy_force_speed_duplex_m88; 161 func->get_cable_length = e1000_get_cable_length_m88; 162 func->read_phy_reg = e1000_read_phy_reg_bm2; 163 func->write_phy_reg = e1000_write_phy_reg_bm2; 164 165 /* This uses above function pointers */ 166 ret_val = e1000_get_phy_id_82571(hw); 167 /* Verify PHY ID */ 168 if (phy->id != BME1000_E_PHY_ID_R2) { 169 ret_val = -E1000_ERR_PHY; 170 DEBUGOUT1("PHY ID unknown: type = 0x%08x\n", phy->id); 171 goto out; 172 } 173 break; 174 default: 175 ret_val = -E1000_ERR_PHY; 176 goto out; 177 break; 178 } 179 180out: 181 return ret_val; 182} 183 184/** 185 * e1000_init_nvm_params_82571 - Init NVM func ptrs. 186 * @hw: pointer to the HW structure 187 * 188 * This is a function pointer entry point called by the api module. 189 **/ 190STATIC s32 e1000_init_nvm_params_82571(struct e1000_hw *hw) 191{ 192 struct e1000_nvm_info *nvm = &hw->nvm; 193 struct e1000_functions *func = &hw->func; 194 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 195 u16 size; 196 197 DEBUGFUNC("e1000_init_nvm_params_82571"); 198 199 nvm->opcode_bits = 8; 200 nvm->delay_usec = 1; 201 switch (nvm->override) { 202 case e1000_nvm_override_spi_large: 203 nvm->page_size = 32; 204 nvm->address_bits = 16; 205 break; 206 case e1000_nvm_override_spi_small: 207 nvm->page_size = 8; 208 nvm->address_bits = 8; 209 break; 210 default: 211 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; 212 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; 213 break; 214 } 215 216 switch (hw->mac.type) { 217 case e1000_82573: 218 case e1000_82574: 219 if (((eecd >> 15) & 0x3) == 0x3) { 220 nvm->type = e1000_nvm_flash_hw; 221 nvm->word_size = 2048; 222 /* 223 * Autonomous Flash update bit must be cleared due 224 * to Flash update issue. 225 */ 226 eecd &= ~E1000_EECD_AUPDEN; 227 E1000_WRITE_REG(hw, E1000_EECD, eecd); 228 break; 229 } 230 /* Fall Through */ 231 default: 232 nvm->type = e1000_nvm_eeprom_spi; 233 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> 234 E1000_EECD_SIZE_EX_SHIFT); 235 /* 236 * Added to a constant, "size" becomes the left-shift value 237 * for setting word_size. 238 */ 239 size += NVM_WORD_SIZE_BASE_SHIFT; 240 241 /* EEPROM access above 16k is unsupported */ 242 if (size > 14) 243 size = 14; 244 nvm->word_size = 1 << size; 245 break; 246 } 247 248 /* Function Pointers */ 249 func->acquire_nvm = e1000_acquire_nvm_82571; 250 func->read_nvm = e1000_read_nvm_eerd; 251 func->release_nvm = e1000_release_nvm_82571; 252 func->update_nvm = e1000_update_nvm_checksum_82571; 253 func->validate_nvm = e1000_validate_nvm_checksum_82571; 254 func->valid_led_default = e1000_valid_led_default_82571; 255 func->write_nvm = e1000_write_nvm_82571; 256 257 return E1000_SUCCESS; 258} 259 260/** 261 * e1000_init_mac_params_82571 - Init MAC func ptrs. 262 * @hw: pointer to the HW structure 263 * 264 * This is a function pointer entry point called by the api module. 265 **/ 266STATIC s32 e1000_init_mac_params_82571(struct e1000_hw *hw) 267{ 268 struct e1000_mac_info *mac = &hw->mac; 269 struct e1000_functions *func = &hw->func; 270 s32 ret_val = E1000_SUCCESS; 271 272 DEBUGFUNC("e1000_init_mac_params_82571"); 273 274 /* Set media type */ 275 switch (hw->device_id) { 276 case E1000_DEV_ID_82571EB_FIBER: 277 case E1000_DEV_ID_82572EI_FIBER: 278 case E1000_DEV_ID_82571EB_QUAD_FIBER: 279 hw->phy.media_type = e1000_media_type_fiber; 280 break; 281 case E1000_DEV_ID_82571EB_SERDES: 282 case E1000_DEV_ID_82571EB_SERDES_DUAL: 283 case E1000_DEV_ID_82571EB_SERDES_QUAD: 284 case E1000_DEV_ID_82572EI_SERDES: 285 hw->phy.media_type = e1000_media_type_internal_serdes; 286 break; 287 default: 288 hw->phy.media_type = e1000_media_type_copper; 289 break; 290 } 291 292 /* Set mta register count */ 293 mac->mta_reg_count = 128; 294 /* Set rar entry count */ 295 mac->rar_entry_count = E1000_RAR_ENTRIES; 296 /* Set if part includes ASF firmware */ 297 mac->asf_firmware_present = TRUE; 298 /* Set if manageability features are enabled. */ 299 mac->arc_subsystem_valid = 300 (E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK) 301 ? TRUE : FALSE; 302 303 /* Function pointers */ 304 305 /* bus type/speed/width */ 306 func->get_bus_info = e1000_get_bus_info_pcie_generic; 307 /* reset */ 308 func->reset_hw = e1000_reset_hw_82571; 309 /* hw initialization */ 310 func->init_hw = e1000_init_hw_82571; 311 /* link setup */ 312 func->setup_link = e1000_setup_link_82571; 313 /* physical interface link setup */ 314 func->setup_physical_interface = 315 (hw->phy.media_type == e1000_media_type_copper) 316 ? e1000_setup_copper_link_82571 317 : e1000_setup_fiber_serdes_link_82571; 318 /* check for link */ 319 switch (hw->phy.media_type) { 320 case e1000_media_type_copper: 321 func->check_for_link = e1000_check_for_copper_link_generic; 322 break; 323 case e1000_media_type_fiber: 324 func->check_for_link = e1000_check_for_fiber_link_generic; 325 break; 326 case e1000_media_type_internal_serdes: 327 func->check_for_link = e1000_check_for_serdes_link_generic; 328 break; 329 default: 330 ret_val = -E1000_ERR_CONFIG; 331 goto out; 332 break; 333 } 334 /* check management mode */ 335 func->check_mng_mode = e1000_check_mng_mode_generic; 336 /* multicast address update */ 337 func->update_mc_addr_list = e1000_update_mc_addr_list_82571; 338 /* writing VFTA */ 339 func->write_vfta = e1000_write_vfta_generic; 340 /* clearing VFTA */ 341 func->clear_vfta = e1000_clear_vfta_82571; 342 /* setting MTA */ 343 func->mta_set = e1000_mta_set_generic; 344 /* read mac address */ 345 func->read_mac_addr = e1000_read_mac_addr_82571; 346 /* blink LED */ 347 func->blink_led = e1000_blink_led_generic; 348 /* setup LED */ 349 func->setup_led = e1000_setup_led_generic; 350 /* cleanup LED */ 351 func->cleanup_led = e1000_cleanup_led_generic; 352 /* turn on/off LED */ 353 func->led_on = e1000_led_on_generic; 354 func->led_off = e1000_led_off_generic; 355 /* remove device */ 356 func->remove_device = e1000_remove_device_generic; 357 /* clear hardware counters */ 358 func->clear_hw_cntrs = e1000_clear_hw_cntrs_82571; 359 /* link info */ 360 func->get_link_up_info = 361 (hw->phy.media_type == e1000_media_type_copper) 362 ? e1000_get_speed_and_duplex_copper_generic 363 : e1000_get_speed_and_duplex_fiber_serdes_generic; 364 365 hw->dev_spec_size = sizeof(struct e1000_dev_spec_82571); 366 367 /* Device-specific structure allocation */ 368 ret_val = e1000_alloc_zeroed_dev_spec_struct(hw, hw->dev_spec_size); 369 370out: 371 return ret_val; 372} 373 374/** 375 * e1000_init_function_pointers_82571 - Init func ptrs. 376 * @hw: pointer to the HW structure 377 * 378 * The only function explicitly called by the api module to initialize 379 * all function pointers and parameters. 380 **/ 381void e1000_init_function_pointers_82571(struct e1000_hw *hw) 382{ 383 DEBUGFUNC("e1000_init_function_pointers_82571"); 384 385 hw->func.init_mac_params = e1000_init_mac_params_82571; 386 hw->func.init_nvm_params = e1000_init_nvm_params_82571; 387 hw->func.init_phy_params = e1000_init_phy_params_82571; 388} 389 390/** 391 * e1000_get_phy_id_82571 - Retrieve the PHY ID and revision 392 * @hw: pointer to the HW structure 393 * 394 * Reads the PHY registers and stores the PHY ID and possibly the PHY 395 * revision in the hardware structure. 396 **/ 397static s32 e1000_get_phy_id_82571(struct e1000_hw *hw) 398{ 399 struct e1000_phy_info *phy = &hw->phy; 400 s32 ret_val = E1000_SUCCESS; 401 u16 phy_id = 0; 402 403 DEBUGFUNC("e1000_get_phy_id_82571"); 404 405 switch (hw->mac.type) { 406 case e1000_82571: 407 case e1000_82572: 408 /* 409 * The 82571 firmware may still be configuring the PHY. 410 * In this case, we cannot access the PHY until the 411 * configuration is done. So we explicitly set the 412 * PHY ID. 413 */ 414 phy->id = IGP01E1000_I_PHY_ID; 415 break; 416 case e1000_82573: 417 ret_val = e1000_get_phy_id(hw); 418 break; 419 case e1000_82574: 420 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id); 421 if (ret_val) 422 goto out; 423 424 phy->id = (u32)(phy_id << 16); 425 usec_delay(20); 426 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id); 427 if (ret_val) 428 goto out; 429 430 phy->id |= (u32)(phy_id); 431 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); 432 break; 433 default: 434 ret_val = -E1000_ERR_PHY; 435 break; 436 } 437 438out: 439 return ret_val; 440} 441 442/** 443 * e1000_get_hw_semaphore_82571 - Acquire hardware semaphore 444 * @hw: pointer to the HW structure 445 * 446 * Acquire the HW semaphore to access the PHY or NVM 447 **/ 448static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw) 449{ 450 u32 swsm; 451 s32 ret_val = E1000_SUCCESS; 452 s32 timeout = hw->nvm.word_size + 1; 453 s32 i = 0; 454 455 DEBUGFUNC("e1000_get_hw_semaphore_82571"); 456 457 /* Get the FW semaphore. */ 458 for (i = 0; i < timeout; i++) { 459 swsm = E1000_READ_REG(hw, E1000_SWSM); 460 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI); 461 462 /* Semaphore acquired if bit latched */ 463 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI) 464 break; 465 466 usec_delay(50); 467 } 468 469 if (i == timeout) { 470 /* Release semaphores */ 471 e1000_put_hw_semaphore_generic(hw); 472 DEBUGOUT("Driver can't access the NVM\n"); 473 ret_val = -E1000_ERR_NVM; 474 goto out; 475 } 476 477out: 478 return ret_val; 479} 480 481/** 482 * e1000_put_hw_semaphore_82571 - Release hardware semaphore 483 * @hw: pointer to the HW structure 484 * 485 * Release hardware semaphore used to access the PHY or NVM 486 **/ 487static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw) 488{ 489 u32 swsm; 490 491 DEBUGFUNC("e1000_put_hw_semaphore_82571"); 492 493 swsm = E1000_READ_REG(hw, E1000_SWSM); 494 495 swsm &= ~E1000_SWSM_SWESMBI; 496 497 E1000_WRITE_REG(hw, E1000_SWSM, swsm); 498} 499 500/** 501 * e1000_acquire_nvm_82571 - Request for access to the EEPROM 502 * @hw: pointer to the HW structure 503 * 504 * To gain access to the EEPROM, first we must obtain a hardware semaphore. 505 * Then for non-82573 hardware, set the EEPROM access request bit and wait 506 * for EEPROM access grant bit. If the access grant bit is not set, release 507 * hardware semaphore. 508 **/ 509STATIC s32 e1000_acquire_nvm_82571(struct e1000_hw *hw) 510{ 511 s32 ret_val; 512 513 DEBUGFUNC("e1000_acquire_nvm_82571"); 514 515 ret_val = e1000_get_hw_semaphore_82571(hw); 516 if (ret_val) 517 goto out; 518 519 if (hw->mac.type != e1000_82573 && hw->mac.type != e1000_82574) 520 ret_val = e1000_acquire_nvm_generic(hw); 521 522 if (ret_val) 523 e1000_put_hw_semaphore_82571(hw); 524 525out: 526 return ret_val; 527} 528 529/** 530 * e1000_release_nvm_82571 - Release exclusive access to EEPROM 531 * @hw: pointer to the HW structure 532 * 533 * Stop any current commands to the EEPROM and clear the EEPROM request bit. 534 **/ 535STATIC void e1000_release_nvm_82571(struct e1000_hw *hw) 536{ 537 DEBUGFUNC("e1000_release_nvm_82571"); 538 539 e1000_release_nvm_generic(hw); 540 e1000_put_hw_semaphore_82571(hw); 541} 542 543/** 544 * e1000_write_nvm_82571 - Write to EEPROM using appropriate interface 545 * @hw: pointer to the HW structure 546 * @offset: offset within the EEPROM to be written to 547 * @words: number of words to write 548 * @data: 16 bit word(s) to be written to the EEPROM 549 * 550 * For non-82573 silicon, write data to EEPROM at offset using SPI interface. 551 * 552 * If e1000_update_nvm_checksum is not called after this function, the 553 * EEPROM will most likely contain an invalid checksum. 554 **/ 555STATIC s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words, 556 u16 *data) 557{ 558 s32 ret_val = E1000_SUCCESS; 559 560 DEBUGFUNC("e1000_write_nvm_82571"); 561 562 switch (hw->mac.type) { 563 case e1000_82573: 564 case e1000_82574: 565 ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data); 566 break; 567 case e1000_82571: 568 case e1000_82572: 569 ret_val = e1000_write_nvm_spi(hw, offset, words, data); 570 break; 571 default: 572 ret_val = -E1000_ERR_NVM; 573 break; 574 } 575 576 return ret_val; 577} 578 579/** 580 * e1000_update_nvm_checksum_82571 - Update EEPROM checksum 581 * @hw: pointer to the HW structure 582 * 583 * Updates the EEPROM checksum by reading/adding each word of the EEPROM 584 * up to the checksum. Then calculates the EEPROM checksum and writes the 585 * value to the EEPROM. 586 **/ 587STATIC s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw) 588{ 589 u32 eecd; 590 s32 ret_val; 591 u16 i; 592 593 DEBUGFUNC("e1000_update_nvm_checksum_82571"); 594 595 ret_val = e1000_update_nvm_checksum_generic(hw); 596 if (ret_val) 597 goto out; 598 599 /* 600 * If our nvm is an EEPROM, then we're done 601 * otherwise, commit the checksum to the flash NVM. 602 */ 603 if (hw->nvm.type != e1000_nvm_flash_hw) 604 goto out; 605 606 /* Check for pending operations. */ 607 for (i = 0; i < E1000_FLASH_UPDATES; i++) { 608 msec_delay(1); 609 if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD) == 0) 610 break; 611 } 612 613 if (i == E1000_FLASH_UPDATES) { 614 ret_val = -E1000_ERR_NVM; 615 goto out; 616 } 617 618 /* Reset the firmware if using STM opcode. */ 619 if ((E1000_READ_REG(hw, E1000_FLOP) & 0xFF00) == E1000_STM_OPCODE) { 620 /* 621 * The enabling of and the actual reset must be done 622 * in two write cycles. 623 */ 624 E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET_ENABLE); 625 E1000_WRITE_FLUSH(hw); 626 E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET); 627 } 628 629 /* Commit the write to flash */ 630 eecd = E1000_READ_REG(hw, E1000_EECD) | E1000_EECD_FLUPD; 631 E1000_WRITE_REG(hw, E1000_EECD, eecd); 632 633 for (i = 0; i < E1000_FLASH_UPDATES; i++) { 634 msec_delay(1); 635 if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD) == 0) 636 break; 637 } 638 639 if (i == E1000_FLASH_UPDATES) { 640 ret_val = -E1000_ERR_NVM; 641 goto out; 642 } 643 644out: 645 return ret_val; 646} 647 648/** 649 * e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum 650 * @hw: pointer to the HW structure 651 * 652 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM 653 * and then verifies that the sum of the EEPROM is equal to 0xBABA. 654 **/ 655STATIC s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw) 656{ 657 DEBUGFUNC("e1000_validate_nvm_checksum_82571"); 658 659 if (hw->nvm.type == e1000_nvm_flash_hw) 660 e1000_fix_nvm_checksum_82571(hw); 661 662 return e1000_validate_nvm_checksum_generic(hw); 663} 664 665/** 666 * e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon 667 * @hw: pointer to the HW structure 668 * @offset: offset within the EEPROM to be written to 669 * @words: number of words to write 670 * @data: 16 bit word(s) to be written to the EEPROM 671 * 672 * After checking for invalid values, poll the EEPROM to ensure the previous 673 * command has completed before trying to write the next word. After write 674 * poll for completion. 675 * 676 * If e1000_update_nvm_checksum is not called after this function, the 677 * EEPROM will most likely contain an invalid checksum. 678 **/ 679static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, 680 u16 words, u16 *data) 681{ 682 struct e1000_nvm_info *nvm = &hw->nvm; 683 u32 i, eewr = 0; 684 s32 ret_val = 0; 685 686 DEBUGFUNC("e1000_write_nvm_eewr_82571"); 687 688 /* 689 * A check for invalid values: offset too large, too many words, 690 * and not enough words. 691 */ 692 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 693 (words == 0)) { 694 DEBUGOUT("nvm parameter(s) out of bounds\n"); 695 ret_val = -E1000_ERR_NVM; 696 goto out; 697 } 698 699 for (i = 0; i < words; i++) { 700 eewr = (data[i] << E1000_NVM_RW_REG_DATA) | 701 ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) | 702 E1000_NVM_RW_REG_START; 703 704 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE); 705 if (ret_val) 706 break; 707 708 E1000_WRITE_REG(hw, E1000_EEWR, eewr); 709 710 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE); 711 if (ret_val) 712 break; 713 } 714 715out: 716 return ret_val; 717} 718 719/** 720 * e1000_get_cfg_done_82571 - Poll for configuration done 721 * @hw: pointer to the HW structure 722 * 723 * Reads the management control register for the config done bit to be set. 724 **/ 725STATIC s32 e1000_get_cfg_done_82571(struct e1000_hw *hw) 726{ 727 s32 timeout = PHY_CFG_TIMEOUT; 728 s32 ret_val = E1000_SUCCESS; 729 730 DEBUGFUNC("e1000_get_cfg_done_82571"); 731 732 while (timeout) { 733 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & E1000_NVM_CFG_DONE_PORT_0) 734 break; 735 msec_delay(1); 736 timeout--; 737 } 738 if (!timeout) { 739 DEBUGOUT("MNG configuration cycle has not completed.\n"); 740 ret_val = -E1000_ERR_RESET; 741 goto out; 742 } 743 744out: 745 return ret_val; 746} 747 748/** 749 * e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state 750 * @hw: pointer to the HW structure 751 * @active: TRUE to enable LPLU, FALSE to disable 752 * 753 * Sets the LPLU D0 state according to the active flag. When activating LPLU 754 * this function also disables smart speed and vice versa. LPLU will not be 755 * activated unless the device autonegotiation advertisement meets standards 756 * of either 10 or 10/100 or 10/100/1000 at all duplexes. This is a function 757 * pointer entry point only called by PHY setup routines. 758 **/ 759STATIC s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active) 760{ 761 struct e1000_phy_info *phy = &hw->phy; 762 s32 ret_val; 763 u16 data; 764 765 DEBUGFUNC("e1000_set_d0_lplu_state_82571"); 766 767 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); 768 if (ret_val) 769 goto out; 770 771 if (active) { 772 data |= IGP02E1000_PM_D0_LPLU; 773 ret_val = e1000_write_phy_reg(hw, 774 IGP02E1000_PHY_POWER_MGMT, 775 data); 776 if (ret_val) 777 goto out; 778 779 /* When LPLU is enabled, we should disable SmartSpeed */ 780 ret_val = e1000_read_phy_reg(hw, 781 IGP01E1000_PHY_PORT_CONFIG, 782 &data); 783 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 784 ret_val = e1000_write_phy_reg(hw, 785 IGP01E1000_PHY_PORT_CONFIG, 786 data); 787 if (ret_val) 788 goto out; 789 } else { 790 data &= ~IGP02E1000_PM_D0_LPLU; 791 ret_val = e1000_write_phy_reg(hw, 792 IGP02E1000_PHY_POWER_MGMT, 793 data); 794 /* 795 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 796 * during Dx states where the power conservation is most 797 * important. During driver activity we should enable 798 * SmartSpeed, so performance is maintained. 799 */ 800 if (phy->smart_speed == e1000_smart_speed_on) { 801 ret_val = e1000_read_phy_reg(hw, 802 IGP01E1000_PHY_PORT_CONFIG, 803 &data); 804 if (ret_val) 805 goto out; 806 807 data |= IGP01E1000_PSCFR_SMART_SPEED; 808 ret_val = e1000_write_phy_reg(hw, 809 IGP01E1000_PHY_PORT_CONFIG, 810 data); 811 if (ret_val) 812 goto out; 813 } else if (phy->smart_speed == e1000_smart_speed_off) { 814 ret_val = e1000_read_phy_reg(hw, 815 IGP01E1000_PHY_PORT_CONFIG, 816 &data); 817 if (ret_val) 818 goto out; 819 820 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 821 ret_val = e1000_write_phy_reg(hw, 822 IGP01E1000_PHY_PORT_CONFIG, 823 data); 824 if (ret_val) 825 goto out; 826 } 827 } 828 829out: 830 return ret_val; 831} 832 833/** 834 * e1000_reset_hw_82571 - Reset hardware 835 * @hw: pointer to the HW structure 836 * 837 * This resets the hardware into a known state. This is a 838 * function pointer entry point called by the api module. 839 **/ 840STATIC s32 e1000_reset_hw_82571(struct e1000_hw *hw) 841{ 842 u32 ctrl, extcnf_ctrl, ctrl_ext, icr; 843 s32 ret_val; 844 u16 i = 0; 845 846 DEBUGFUNC("e1000_reset_hw_82571"); 847 848 /* 849 * Prevent the PCI-E bus from sticking if there is no TLP connection 850 * on the last TLP read/write transaction when MAC is reset. 851 */ 852 ret_val = e1000_disable_pcie_master_generic(hw); 853 if (ret_val) { 854 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 855 } 856 857 DEBUGOUT("Masking off all interrupts\n"); 858 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 859 860 E1000_WRITE_REG(hw, E1000_RCTL, 0); 861 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 862 E1000_WRITE_FLUSH(hw); 863 864 msec_delay(10); 865 866 /* 867 * Must acquire the MDIO ownership before MAC reset. 868 * Ownership defaults to firmware after a reset. 869 */ 870 if (hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574) { 871 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 872 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; 873 874 do { 875 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); 876 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 877 878 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP) 879 break; 880 881 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; 882 883 msec_delay(2); 884 i++; 885 } while (i < MDIO_OWNERSHIP_TIMEOUT); 886 } 887 888 ctrl = E1000_READ_REG(hw, E1000_CTRL); 889 890 DEBUGOUT("Issuing a global reset to MAC\n"); 891 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 892 893 if (hw->nvm.type == e1000_nvm_flash_hw) { 894 usec_delay(10); 895 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 896 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 897 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 898 E1000_WRITE_FLUSH(hw); 899 } 900 901 ret_val = e1000_get_auto_rd_done_generic(hw); 902 if (ret_val) 903 /* We don't want to continue accessing MAC registers. */ 904 goto out; 905 906 /* 907 * Phy configuration from NVM just starts after EECD_AUTO_RD is set. 908 * Need to wait for Phy configuration completion before accessing 909 * NVM and Phy. 910 */ 911 if (hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574) 912 msec_delay(25); 913 914 /* Clear any pending interrupt events. */ 915 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 916 icr = E1000_READ_REG(hw, E1000_ICR); 917 918 if (!(e1000_check_alt_mac_addr_generic(hw))) 919 e1000_set_laa_state_82571(hw, TRUE); 920 921out: 922 return ret_val; 923} 924 925/** 926 * e1000_init_hw_82571 - Initialize hardware 927 * @hw: pointer to the HW structure 928 * 929 * This inits the hardware readying it for operation. 930 **/ 931STATIC s32 e1000_init_hw_82571(struct e1000_hw *hw) 932{ 933 struct e1000_mac_info *mac = &hw->mac; 934 u32 reg_data; 935 s32 ret_val; 936 u16 i, rar_count = mac->rar_entry_count; 937 938 DEBUGFUNC("e1000_init_hw_82571"); 939 940 e1000_initialize_hw_bits_82571(hw); 941 942 /* Initialize identification LED */ 943 ret_val = e1000_id_led_init_generic(hw); 944 if (ret_val) { 945 DEBUGOUT("Error initializing identification LED\n"); 946 /* This is not fatal and we should not stop init due to this */ 947 } 948 949 /* Disabling VLAN filtering */ 950 DEBUGOUT("Initializing the IEEE VLAN\n"); 951 e1000_clear_vfta(hw); 952 953 /* Setup the receive address. */ 954 /* 955 * If, however, a locally administered address was assigned to the 956 * 82571, we must reserve a RAR for it to work around an issue where 957 * resetting one port will reload the MAC on the other port. 958 */ 959 if (e1000_get_laa_state_82571(hw)) 960 rar_count--; 961 e1000_init_rx_addrs_generic(hw, rar_count); 962 963 /* Zero out the Multicast HASH table */ 964 DEBUGOUT("Zeroing the MTA\n"); 965 for (i = 0; i < mac->mta_reg_count; i++) 966 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 967 968 /* Setup link and flow control */ 969 ret_val = e1000_setup_link(hw); 970 971 /* Set the transmit descriptor write-back policy */ 972 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0)); 973 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | 974 E1000_TXDCTL_FULL_TX_DESC_WB | 975 E1000_TXDCTL_COUNT_DESC; 976 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data); 977 978 /* ...for both queues. */ 979 if (mac->type != e1000_82573 && mac->type != e1000_82574) { 980 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1)); 981 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | 982 E1000_TXDCTL_FULL_TX_DESC_WB | 983 E1000_TXDCTL_COUNT_DESC; 984 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data); 985 } else { 986 e1000_enable_tx_pkt_filtering(hw); 987 reg_data = E1000_READ_REG(hw, E1000_GCR); 988 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; 989 E1000_WRITE_REG(hw, E1000_GCR, reg_data); 990 } 991 992 /* 993 * Clear all of the statistics registers (clear on read). It is 994 * important that we do this after we have tried to establish link 995 * because the symbol error count will increment wildly if there 996 * is no link. 997 */ 998 e1000_clear_hw_cntrs_82571(hw); 999 1000 return ret_val; 1001} 1002 1003/** 1004 * e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits 1005 * @hw: pointer to the HW structure 1006 * 1007 * Initializes required hardware-dependent bits needed for normal operation. 1008 **/ 1009static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw) 1010{ 1011 u32 reg; 1012 1013 DEBUGFUNC("e1000_initialize_hw_bits_82571"); 1014 1015 if (hw->mac.disable_hw_init_bits) 1016 goto out; 1017 1018 /* Transmit Descriptor Control 0 */ 1019 reg = E1000_READ_REG(hw, E1000_TXDCTL(0)); 1020 reg |= (1 << 22); 1021 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg); 1022 1023 /* Transmit Descriptor Control 1 */ 1024 reg = E1000_READ_REG(hw, E1000_TXDCTL(1)); 1025 reg |= (1 << 22); 1026 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg); 1027 1028 /* Transmit Arbitration Control 0 */ 1029 reg = E1000_READ_REG(hw, E1000_TARC(0)); 1030 reg &= ~(0xF << 27); /* 30:27 */ 1031 switch (hw->mac.type) { 1032 case e1000_82571: 1033 case e1000_82572: 1034 reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26); 1035 break; 1036 default: 1037 break; 1038 } 1039 E1000_WRITE_REG(hw, E1000_TARC(0), reg); 1040 1041 /* Transmit Arbitration Control 1 */ 1042 reg = E1000_READ_REG(hw, E1000_TARC(1)); 1043 switch (hw->mac.type) { 1044 case e1000_82571: 1045 case e1000_82572: 1046 reg &= ~((1 << 29) | (1 << 30)); 1047 reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26); 1048 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR) 1049 reg &= ~(1 << 28); 1050 else 1051 reg |= (1 << 28); 1052 E1000_WRITE_REG(hw, E1000_TARC(1), reg); 1053 break; 1054 default: 1055 break; 1056 } 1057 1058 /* Device Control */ 1059 if (hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574) { 1060 reg = E1000_READ_REG(hw, E1000_CTRL); 1061 reg &= ~(1 << 29); 1062 E1000_WRITE_REG(hw, E1000_CTRL, reg); 1063 } 1064 1065 /* Extended Device Control */ 1066 if (hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574) { 1067 reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 1068 reg &= ~(1 << 23); 1069 reg |= (1 << 22); 1070 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 1071 } 1072 1073out: 1074 return; 1075} 1076 1077/** 1078 * e1000_clear_vfta_82571 - Clear VLAN filter table 1079 * @hw: pointer to the HW structure 1080 * 1081 * Clears the register array which contains the VLAN filter table by 1082 * setting all the values to 0. 1083 **/ 1084STATIC void e1000_clear_vfta_82571(struct e1000_hw *hw) 1085{ 1086 u32 offset; 1087 u32 vfta_value = 0; 1088 u32 vfta_offset = 0; 1089 u32 vfta_bit_in_reg = 0; 1090 1091 DEBUGFUNC("e1000_clear_vfta_82571"); 1092 1093 if (hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574) { 1094 if (hw->mng_cookie.vlan_id != 0) { 1095 /* 1096 * The VFTA is a 4096b bit-field, each identifying 1097 * a single VLAN ID. The following operations 1098 * determine which 32b entry (i.e. offset) into the 1099 * array we want to set the VLAN ID (i.e. bit) of 1100 * the manageability unit. 1101 */ 1102 vfta_offset = (hw->mng_cookie.vlan_id >> 1103 E1000_VFTA_ENTRY_SHIFT) & 1104 E1000_VFTA_ENTRY_MASK; 1105 vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id & 1106 E1000_VFTA_ENTRY_BIT_SHIFT_MASK); 1107 } 1108 } 1109 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 1110 /* 1111 * If the offset we want to clear is the same offset of the 1112 * manageability VLAN ID, then clear all bits except that of 1113 * the manageability unit. 1114 */ 1115 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0; 1116 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value); 1117 E1000_WRITE_FLUSH(hw); 1118 } 1119} 1120 1121/** 1122 * e1000_update_mc_addr_list_82571 - Update Multicast addresses 1123 * @hw: pointer to the HW structure 1124 * @mc_addr_list: array of multicast addresses to program 1125 * @mc_addr_count: number of multicast addresses to program 1126 * @rar_used_count: the first RAR register free to program 1127 * @rar_count: total number of supported Receive Address Registers 1128 * 1129 * Updates the Receive Address Registers and Multicast Table Array. 1130 * The caller must have a packed mc_addr_list of multicast addresses. 1131 * The parameter rar_count will usually be hw->mac.rar_entry_count 1132 * unless there are workarounds that change this. 1133 **/ 1134STATIC void e1000_update_mc_addr_list_82571(struct e1000_hw *hw, 1135 u8 *mc_addr_list, u32 mc_addr_count, 1136 u32 rar_used_count, u32 rar_count) 1137{ 1138 DEBUGFUNC("e1000_update_mc_addr_list_82571"); 1139 1140 if (e1000_get_laa_state_82571(hw)) 1141 rar_count--; 1142 1143 e1000_update_mc_addr_list_generic(hw, mc_addr_list, mc_addr_count, 1144 rar_used_count, rar_count); 1145} 1146 1147/** 1148 * e1000_setup_link_82571 - Setup flow control and link settings 1149 * @hw: pointer to the HW structure 1150 * 1151 * Determines which flow control settings to use, then configures flow 1152 * control. Calls the appropriate media-specific link configuration 1153 * function. Assuming the adapter has a valid link partner, a valid link 1154 * should be established. Assumes the hardware has previously been reset 1155 * and the transmitter and receiver are not enabled. 1156 **/ 1157STATIC s32 e1000_setup_link_82571(struct e1000_hw *hw) 1158{ 1159 DEBUGFUNC("e1000_setup_link_82571"); 1160 1161 /* 1162 * 82573 does not have a word in the NVM to determine 1163 * the default flow control setting, so we explicitly 1164 * set it to full. 1165 */ 1166 if (hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574) 1167 hw->fc.type = e1000_fc_full; 1168 1169 return e1000_setup_link_generic(hw); 1170} 1171 1172/** 1173 * e1000_setup_copper_link_82571 - Configure copper link settings 1174 * @hw: pointer to the HW structure 1175 * 1176 * Configures the link for auto-neg or forced speed and duplex. Then we check 1177 * for link, once link is established calls to configure collision distance 1178 * and flow control are called. 1179 **/ 1180STATIC s32 e1000_setup_copper_link_82571(struct e1000_hw *hw) 1181{ 1182 u32 ctrl, led_ctrl; 1183 s32 ret_val; 1184 1185 DEBUGFUNC("e1000_setup_copper_link_82571"); 1186 1187 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1188 ctrl |= E1000_CTRL_SLU; 1189 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1190 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1191 1192 switch (hw->phy.type) { 1193 case e1000_phy_m88: 1194 case e1000_phy_bm: 1195 ret_val = e1000_copper_link_setup_m88(hw); 1196 break; 1197 case e1000_phy_igp_2: 1198 ret_val = e1000_copper_link_setup_igp(hw); 1199 /* Setup activity LED */ 1200 led_ctrl = E1000_READ_REG(hw, E1000_LEDCTL); 1201 led_ctrl &= IGP_ACTIVITY_LED_MASK; 1202 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 1203 E1000_WRITE_REG(hw, E1000_LEDCTL, led_ctrl); 1204 break; 1205 default: 1206 ret_val = -E1000_ERR_PHY; 1207 break; 1208 } 1209 1210 if (ret_val) 1211 goto out; 1212 1213 ret_val = e1000_setup_copper_link_generic(hw); 1214 1215out: 1216 return ret_val; 1217} 1218 1219/** 1220 * e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes 1221 * @hw: pointer to the HW structure 1222 * 1223 * Configures collision distance and flow control for fiber and serdes links. 1224 * Upon successful setup, poll for link. 1225 **/ 1226STATIC s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw) 1227{ 1228 DEBUGFUNC("e1000_setup_fiber_serdes_link_82571"); 1229 1230 switch (hw->mac.type) { 1231 case e1000_82571: 1232 case e1000_82572: 1233 /* 1234 * If SerDes loopback mode is entered, there is no form 1235 * of reset to take the adapter out of that mode. So we 1236 * have to explicitly take the adapter out of loopback 1237 * mode. This prevents drivers from twiddling their thumbs 1238 * if another tool failed to take it out of loopback mode. 1239 */ 1240 E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK); 1241 break; 1242 default: 1243 break; 1244 } 1245 1246 return e1000_setup_fiber_serdes_link_generic(hw); 1247} 1248 1249/** 1250 * e1000_valid_led_default_82571 - Verify a valid default LED config 1251 * @hw: pointer to the HW structure 1252 * @data: pointer to the NVM (EEPROM) 1253 * 1254 * Read the EEPROM for the current default LED configuration. If the 1255 * LED configuration is not valid, set to a valid LED configuration. 1256 **/ 1257STATIC s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data) 1258{ 1259 s32 ret_val; 1260 1261 DEBUGFUNC("e1000_valid_led_default_82571"); 1262 1263 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data); 1264 if (ret_val) { 1265 DEBUGOUT("NVM Read Error\n"); 1266 goto out; 1267 } 1268 1269 if ((hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574) && 1270 *data == ID_LED_RESERVED_F746) 1271 *data = ID_LED_DEFAULT_82573; 1272 else if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) 1273 *data = ID_LED_DEFAULT; 1274out: 1275 return ret_val; 1276} 1277 1278/** 1279 * e1000_get_laa_state_82571 - Get locally administered address state 1280 * @hw: pointer to the HW structure 1281 * 1282 * Retrieve and return the current locally administered address state. 1283 **/ 1284bool e1000_get_laa_state_82571(struct e1000_hw *hw) 1285{ 1286 struct e1000_dev_spec_82571 *dev_spec; 1287 bool state = FALSE; 1288 1289 DEBUGFUNC("e1000_get_laa_state_82571"); 1290 1291 if (hw->mac.type != e1000_82571) 1292 goto out; 1293 1294 dev_spec = (struct e1000_dev_spec_82571 *)hw->dev_spec; 1295 1296 state = dev_spec->laa_is_present; 1297 1298out: 1299 return state; 1300} 1301 1302/** 1303 * e1000_set_laa_state_82571 - Set locally administered address state 1304 * @hw: pointer to the HW structure 1305 * @state: enable/disable locally administered address 1306 * 1307 * Enable/Disable the current locally administered address state. 1308 **/ 1309void e1000_set_laa_state_82571(struct e1000_hw *hw, bool state) 1310{ 1311 struct e1000_dev_spec_82571 *dev_spec; 1312 1313 DEBUGFUNC("e1000_set_laa_state_82571"); 1314 1315 if (hw->mac.type != e1000_82571) 1316 goto out; 1317 1318 dev_spec = (struct e1000_dev_spec_82571 *)hw->dev_spec; 1319 1320 dev_spec->laa_is_present = state; 1321 1322 /* If workaround is activated... */ 1323 if (state) { 1324 /* 1325 * Hold a copy of the LAA in RAR[14] This is done so that 1326 * between the time RAR[0] gets clobbered and the time it 1327 * gets fixed, the actual LAA is in one of the RARs and no 1328 * incoming packets directed to this port are dropped. 1329 * Eventually the LAA will be in RAR[0] and RAR[14]. 1330 */ 1331 e1000_rar_set_generic(hw, hw->mac.addr, 1332 hw->mac.rar_entry_count - 1); 1333 } 1334 1335out: 1336 return; 1337} 1338 1339/** 1340 * e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum 1341 * @hw: pointer to the HW structure 1342 * 1343 * Verifies that the EEPROM has completed the update. After updating the 1344 * EEPROM, we need to check bit 15 in work 0x23 for the checksum fix. If 1345 * the checksum fix is not implemented, we need to set the bit and update 1346 * the checksum. Otherwise, if bit 15 is set and the checksum is incorrect, 1347 * we need to return bad checksum. 1348 **/ 1349static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw) 1350{ 1351 struct e1000_nvm_info *nvm = &hw->nvm; 1352 s32 ret_val = E1000_SUCCESS; 1353 u16 data; 1354 1355 DEBUGFUNC("e1000_fix_nvm_checksum_82571"); 1356 1357 if (nvm->type != e1000_nvm_flash_hw) 1358 goto out; 1359 1360 /* 1361 * Check bit 4 of word 10h. If it is 0, firmware is done updating 1362 * 10h-12h. Checksum may need to be fixed. 1363 */ 1364 ret_val = e1000_read_nvm(hw, 0x10, 1, &data); 1365 if (ret_val) 1366 goto out; 1367 1368 if (!(data & 0x10)) { 1369 /* 1370 * Read 0x23 and check bit 15. This bit is a 1 1371 * when the checksum has already been fixed. If 1372 * the checksum is still wrong and this bit is a 1373 * 1, we need to return bad checksum. Otherwise, 1374 * we need to set this bit to a 1 and update the 1375 * checksum. 1376 */ 1377 ret_val = e1000_read_nvm(hw, 0x23, 1, &data); 1378 if (ret_val) 1379 goto out; 1380 1381 if (!(data & 0x8000)) { 1382 data |= 0x8000; 1383 ret_val = e1000_write_nvm(hw, 0x23, 1, &data); 1384 if (ret_val) 1385 goto out; 1386 ret_val = e1000_update_nvm_checksum(hw); 1387 } 1388 } 1389 1390out: 1391 return ret_val; 1392} 1393 1394/** 1395 * e1000_read_mac_addr_82571 - Read device MAC address 1396 * @hw: pointer to the HW structure 1397 **/ 1398STATIC s32 e1000_read_mac_addr_82571(struct e1000_hw *hw) 1399{ 1400 s32 ret_val = E1000_SUCCESS; 1401 1402 DEBUGFUNC("e1000_read_mac_addr_82571"); 1403 if (e1000_check_alt_mac_addr_generic(hw)) 1404 ret_val = e1000_read_mac_addr_generic(hw); 1405 1406 return ret_val; 1407} 1408 1409/** 1410 * e1000_power_down_phy_copper_82571 - Remove link during PHY power down 1411 * @hw: pointer to the HW structure 1412 * 1413 * In the case of a PHY power down to save power, or to turn off link during a 1414 * driver unload, or wake on lan is not enabled, remove the link. 1415 **/ 1416STATIC void e1000_power_down_phy_copper_82571(struct e1000_hw *hw) 1417{ 1418 /* If the management interface is not enabled, then power down */ 1419 if (!(e1000_check_mng_mode(hw) || e1000_check_reset_block(hw))) 1420 e1000_power_down_phy_copper(hw); 1421 1422 return; 1423} 1424 1425/** 1426 * e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters 1427 * @hw: pointer to the HW structure 1428 * 1429 * Clears the hardware counters by reading the counter registers. 1430 **/ 1431STATIC void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw) 1432{ 1433 volatile u32 temp; 1434 1435 DEBUGFUNC("e1000_clear_hw_cntrs_82571"); 1436 1437 e1000_clear_hw_cntrs_base_generic(hw); 1438 temp = E1000_READ_REG(hw, E1000_PRC64); 1439 temp = E1000_READ_REG(hw, E1000_PRC127); 1440 temp = E1000_READ_REG(hw, E1000_PRC255); 1441 temp = E1000_READ_REG(hw, E1000_PRC511); 1442 temp = E1000_READ_REG(hw, E1000_PRC1023); 1443 temp = E1000_READ_REG(hw, E1000_PRC1522); 1444 temp = E1000_READ_REG(hw, E1000_PTC64); 1445 temp = E1000_READ_REG(hw, E1000_PTC127); 1446 temp = E1000_READ_REG(hw, E1000_PTC255); 1447 temp = E1000_READ_REG(hw, E1000_PTC511); 1448 temp = E1000_READ_REG(hw, E1000_PTC1023); 1449 temp = E1000_READ_REG(hw, E1000_PTC1522); 1450 1451 temp = E1000_READ_REG(hw, E1000_ALGNERRC); 1452 temp = E1000_READ_REG(hw, E1000_RXERRC); 1453 temp = E1000_READ_REG(hw, E1000_TNCRS); 1454 temp = E1000_READ_REG(hw, E1000_CEXTERR); 1455 temp = E1000_READ_REG(hw, E1000_TSCTC); 1456 temp = E1000_READ_REG(hw, E1000_TSCTFC); 1457 1458 temp = E1000_READ_REG(hw, E1000_MGTPRC); 1459 temp = E1000_READ_REG(hw, E1000_MGTPDC); 1460 temp = E1000_READ_REG(hw, E1000_MGTPTC); 1461 1462 temp = E1000_READ_REG(hw, E1000_IAC); 1463 temp = E1000_READ_REG(hw, E1000_ICRXOC); 1464 1465 temp = E1000_READ_REG(hw, E1000_ICRXPTC); 1466 temp = E1000_READ_REG(hw, E1000_ICRXATC); 1467 temp = E1000_READ_REG(hw, E1000_ICTXPTC); 1468 temp = E1000_READ_REG(hw, E1000_ICTXATC); 1469 temp = E1000_READ_REG(hw, E1000_ICTXQEC); 1470 temp = E1000_READ_REG(hw, E1000_ICTXQMTC); 1471 temp = E1000_READ_REG(hw, E1000_ICRXDMTC); 1472} 1473