1254885Sdumbbell/* 2254885Sdumbbell * Copyright 2008 Advanced Micro Devices, Inc. 3254885Sdumbbell * Copyright 2008 Red Hat Inc. 4254885Sdumbbell * Copyright 2009 Jerome Glisse. 5254885Sdumbbell * 6254885Sdumbbell * Permission is hereby granted, free of charge, to any person obtaining a 7254885Sdumbbell * copy of this software and associated documentation files (the "Software"), 8254885Sdumbbell * to deal in the Software without restriction, including without limitation 9254885Sdumbbell * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10254885Sdumbbell * and/or sell copies of the Software, and to permit persons to whom the 11254885Sdumbbell * Software is furnished to do so, subject to the following conditions: 12254885Sdumbbell * 13254885Sdumbbell * The above copyright notice and this permission notice shall be included in 14254885Sdumbbell * all copies or substantial portions of the Software. 15254885Sdumbbell * 16254885Sdumbbell * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17254885Sdumbbell * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18254885Sdumbbell * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19254885Sdumbbell * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20254885Sdumbbell * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21254885Sdumbbell * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22254885Sdumbbell * OTHER DEALINGS IN THE SOFTWARE. 23254885Sdumbbell * 24254885Sdumbbell * Authors: Dave Airlie 25254885Sdumbbell * Alex Deucher 26254885Sdumbbell * Jerome Glisse 27254885Sdumbbell * Christian K��nig 28254885Sdumbbell */ 29254885Sdumbbell 30254885Sdumbbell#include <sys/cdefs.h> 31254885Sdumbbell__FBSDID("$FreeBSD$"); 32254885Sdumbbell 33254885Sdumbbell#include <dev/drm2/drmP.h> 34254885Sdumbbell#include <dev/drm2/radeon/radeon_drm.h> 35254885Sdumbbell#include "radeon_reg.h" 36254885Sdumbbell#include "radeon.h" 37254885Sdumbbell#include "atom.h" 38254885Sdumbbell 39254885Sdumbbell#ifdef DUMBBELL_WIP 40254885Sdumbbell/* 41254885Sdumbbell * IB 42254885Sdumbbell * IBs (Indirect Buffers) and areas of GPU accessible memory where 43254885Sdumbbell * commands are stored. You can put a pointer to the IB in the 44254885Sdumbbell * command ring and the hw will fetch the commands from the IB 45254885Sdumbbell * and execute them. Generally userspace acceleration drivers 46254885Sdumbbell * produce command buffers which are send to the kernel and 47254885Sdumbbell * put in IBs for execution by the requested ring. 48254885Sdumbbell */ 49254885Sdumbbellstatic int radeon_debugfs_sa_init(struct radeon_device *rdev); 50254885Sdumbbell#endif /* DUMBBELL_WIP */ 51254885Sdumbbell 52254885Sdumbbell/** 53254885Sdumbbell * radeon_ib_get - request an IB (Indirect Buffer) 54254885Sdumbbell * 55254885Sdumbbell * @rdev: radeon_device pointer 56254885Sdumbbell * @ring: ring index the IB is associated with 57254885Sdumbbell * @ib: IB object returned 58254885Sdumbbell * @size: requested IB size 59254885Sdumbbell * 60254885Sdumbbell * Request an IB (all asics). IBs are allocated using the 61254885Sdumbbell * suballocator. 62254885Sdumbbell * Returns 0 on success, error on failure. 63254885Sdumbbell */ 64254885Sdumbbellint radeon_ib_get(struct radeon_device *rdev, int ring, 65254885Sdumbbell struct radeon_ib *ib, struct radeon_vm *vm, 66254885Sdumbbell unsigned size) 67254885Sdumbbell{ 68254885Sdumbbell int i, r; 69254885Sdumbbell 70254885Sdumbbell r = radeon_sa_bo_new(rdev, &rdev->ring_tmp_bo, &ib->sa_bo, size, 256, true); 71254885Sdumbbell if (r) { 72254885Sdumbbell dev_err(rdev->dev, "failed to get a new IB (%d)\n", r); 73254885Sdumbbell return r; 74254885Sdumbbell } 75254885Sdumbbell 76254885Sdumbbell r = radeon_semaphore_create(rdev, &ib->semaphore); 77254885Sdumbbell if (r) { 78254885Sdumbbell return r; 79254885Sdumbbell } 80254885Sdumbbell 81254885Sdumbbell ib->ring = ring; 82254885Sdumbbell ib->fence = NULL; 83254885Sdumbbell ib->ptr = radeon_sa_bo_cpu_addr(ib->sa_bo); 84254885Sdumbbell ib->vm = vm; 85254885Sdumbbell if (vm) { 86254885Sdumbbell /* ib pool is bound at RADEON_VA_IB_OFFSET in virtual address 87254885Sdumbbell * space and soffset is the offset inside the pool bo 88254885Sdumbbell */ 89254885Sdumbbell ib->gpu_addr = ib->sa_bo->soffset + RADEON_VA_IB_OFFSET; 90254885Sdumbbell } else { 91254885Sdumbbell ib->gpu_addr = radeon_sa_bo_gpu_addr(ib->sa_bo); 92254885Sdumbbell } 93254885Sdumbbell ib->is_const_ib = false; 94254885Sdumbbell for (i = 0; i < RADEON_NUM_RINGS; ++i) 95254885Sdumbbell ib->sync_to[i] = NULL; 96254885Sdumbbell 97254885Sdumbbell return 0; 98254885Sdumbbell} 99254885Sdumbbell 100254885Sdumbbell/** 101254885Sdumbbell * radeon_ib_free - free an IB (Indirect Buffer) 102254885Sdumbbell * 103254885Sdumbbell * @rdev: radeon_device pointer 104254885Sdumbbell * @ib: IB object to free 105254885Sdumbbell * 106254885Sdumbbell * Free an IB (all asics). 107254885Sdumbbell */ 108254885Sdumbbellvoid radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib) 109254885Sdumbbell{ 110254885Sdumbbell radeon_semaphore_free(rdev, &ib->semaphore, ib->fence); 111254885Sdumbbell radeon_sa_bo_free(rdev, &ib->sa_bo, ib->fence); 112254885Sdumbbell radeon_fence_unref(&ib->fence); 113254885Sdumbbell} 114254885Sdumbbell 115254885Sdumbbell/** 116254885Sdumbbell * radeon_ib_schedule - schedule an IB (Indirect Buffer) on the ring 117254885Sdumbbell * 118254885Sdumbbell * @rdev: radeon_device pointer 119254885Sdumbbell * @ib: IB object to schedule 120254885Sdumbbell * @const_ib: Const IB to schedule (SI only) 121254885Sdumbbell * 122254885Sdumbbell * Schedule an IB on the associated ring (all asics). 123254885Sdumbbell * Returns 0 on success, error on failure. 124254885Sdumbbell * 125254885Sdumbbell * On SI, there are two parallel engines fed from the primary ring, 126254885Sdumbbell * the CE (Constant Engine) and the DE (Drawing Engine). Since 127254885Sdumbbell * resource descriptors have moved to memory, the CE allows you to 128254885Sdumbbell * prime the caches while the DE is updating register state so that 129254885Sdumbbell * the resource descriptors will be already in cache when the draw is 130254885Sdumbbell * processed. To accomplish this, the userspace driver submits two 131254885Sdumbbell * IBs, one for the CE and one for the DE. If there is a CE IB (called 132254885Sdumbbell * a CONST_IB), it will be put on the ring prior to the DE IB. Prior 133254885Sdumbbell * to SI there was just a DE IB. 134254885Sdumbbell */ 135254885Sdumbbellint radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib, 136254885Sdumbbell struct radeon_ib *const_ib) 137254885Sdumbbell{ 138254885Sdumbbell struct radeon_ring *ring = &rdev->ring[ib->ring]; 139254885Sdumbbell bool need_sync = false; 140254885Sdumbbell int i, r = 0; 141254885Sdumbbell 142254885Sdumbbell if (!ib->length_dw || !ring->ready) { 143254885Sdumbbell /* TODO: Nothings in the ib we should report. */ 144254885Sdumbbell dev_err(rdev->dev, "couldn't schedule ib\n"); 145254885Sdumbbell return -EINVAL; 146254885Sdumbbell } 147254885Sdumbbell 148254885Sdumbbell /* 64 dwords should be enough for fence too */ 149254885Sdumbbell r = radeon_ring_lock(rdev, ring, 64 + RADEON_NUM_RINGS * 8); 150254885Sdumbbell if (r) { 151254885Sdumbbell dev_err(rdev->dev, "scheduling IB failed (%d).\n", r); 152254885Sdumbbell return r; 153254885Sdumbbell } 154254885Sdumbbell for (i = 0; i < RADEON_NUM_RINGS; ++i) { 155254885Sdumbbell struct radeon_fence *fence = ib->sync_to[i]; 156254885Sdumbbell if (radeon_fence_need_sync(fence, ib->ring)) { 157254885Sdumbbell need_sync = true; 158254885Sdumbbell radeon_semaphore_sync_rings(rdev, ib->semaphore, 159254885Sdumbbell fence->ring, ib->ring); 160254885Sdumbbell radeon_fence_note_sync(fence, ib->ring); 161254885Sdumbbell } 162254885Sdumbbell } 163254885Sdumbbell /* immediately free semaphore when we don't need to sync */ 164254885Sdumbbell if (!need_sync) { 165254885Sdumbbell radeon_semaphore_free(rdev, &ib->semaphore, NULL); 166254885Sdumbbell } 167254885Sdumbbell /* if we can't remember our last VM flush then flush now! */ 168254885Sdumbbell if (ib->vm && !ib->vm->last_flush) { 169254885Sdumbbell radeon_ring_vm_flush(rdev, ib->ring, ib->vm); 170254885Sdumbbell } 171254885Sdumbbell if (const_ib) { 172254885Sdumbbell radeon_ring_ib_execute(rdev, const_ib->ring, const_ib); 173254885Sdumbbell radeon_semaphore_free(rdev, &const_ib->semaphore, NULL); 174254885Sdumbbell } 175254885Sdumbbell radeon_ring_ib_execute(rdev, ib->ring, ib); 176254885Sdumbbell r = radeon_fence_emit(rdev, &ib->fence, ib->ring); 177254885Sdumbbell if (r) { 178254885Sdumbbell dev_err(rdev->dev, "failed to emit fence for new IB (%d)\n", r); 179254885Sdumbbell radeon_ring_unlock_undo(rdev, ring); 180254885Sdumbbell return r; 181254885Sdumbbell } 182254885Sdumbbell if (const_ib) { 183254885Sdumbbell const_ib->fence = radeon_fence_ref(ib->fence); 184254885Sdumbbell } 185254885Sdumbbell /* we just flushed the VM, remember that */ 186254885Sdumbbell if (ib->vm && !ib->vm->last_flush) { 187254885Sdumbbell ib->vm->last_flush = radeon_fence_ref(ib->fence); 188254885Sdumbbell } 189254885Sdumbbell radeon_ring_unlock_commit(rdev, ring); 190254885Sdumbbell return 0; 191254885Sdumbbell} 192254885Sdumbbell 193254885Sdumbbell/** 194254885Sdumbbell * radeon_ib_pool_init - Init the IB (Indirect Buffer) pool 195254885Sdumbbell * 196254885Sdumbbell * @rdev: radeon_device pointer 197254885Sdumbbell * 198254885Sdumbbell * Initialize the suballocator to manage a pool of memory 199254885Sdumbbell * for use as IBs (all asics). 200254885Sdumbbell * Returns 0 on success, error on failure. 201254885Sdumbbell */ 202254885Sdumbbellint radeon_ib_pool_init(struct radeon_device *rdev) 203254885Sdumbbell{ 204254885Sdumbbell int r; 205254885Sdumbbell 206254885Sdumbbell if (rdev->ib_pool_ready) { 207254885Sdumbbell return 0; 208254885Sdumbbell } 209254885Sdumbbell r = radeon_sa_bo_manager_init(rdev, &rdev->ring_tmp_bo, 210254885Sdumbbell RADEON_IB_POOL_SIZE*64*1024, 211254885Sdumbbell RADEON_GEM_DOMAIN_GTT); 212254885Sdumbbell if (r) { 213254885Sdumbbell return r; 214254885Sdumbbell } 215254885Sdumbbell 216254885Sdumbbell r = radeon_sa_bo_manager_start(rdev, &rdev->ring_tmp_bo); 217254885Sdumbbell if (r) { 218254885Sdumbbell return r; 219254885Sdumbbell } 220254885Sdumbbell 221254885Sdumbbell rdev->ib_pool_ready = true; 222254885Sdumbbell#ifdef DUMBBELL_WIP 223254885Sdumbbell if (radeon_debugfs_sa_init(rdev)) { 224254885Sdumbbell dev_err(rdev->dev, "failed to register debugfs file for SA\n"); 225254885Sdumbbell } 226254885Sdumbbell#endif /* DUMBBELL_WIP */ 227254885Sdumbbell return 0; 228254885Sdumbbell} 229254885Sdumbbell 230254885Sdumbbell/** 231254885Sdumbbell * radeon_ib_pool_fini - Free the IB (Indirect Buffer) pool 232254885Sdumbbell * 233254885Sdumbbell * @rdev: radeon_device pointer 234254885Sdumbbell * 235254885Sdumbbell * Tear down the suballocator managing the pool of memory 236254885Sdumbbell * for use as IBs (all asics). 237254885Sdumbbell */ 238254885Sdumbbellvoid radeon_ib_pool_fini(struct radeon_device *rdev) 239254885Sdumbbell{ 240254885Sdumbbell if (rdev->ib_pool_ready) { 241254885Sdumbbell radeon_sa_bo_manager_suspend(rdev, &rdev->ring_tmp_bo); 242254885Sdumbbell radeon_sa_bo_manager_fini(rdev, &rdev->ring_tmp_bo); 243254885Sdumbbell rdev->ib_pool_ready = false; 244254885Sdumbbell } 245254885Sdumbbell} 246254885Sdumbbell 247254885Sdumbbell/** 248254885Sdumbbell * radeon_ib_ring_tests - test IBs on the rings 249254885Sdumbbell * 250254885Sdumbbell * @rdev: radeon_device pointer 251254885Sdumbbell * 252254885Sdumbbell * Test an IB (Indirect Buffer) on each ring. 253254885Sdumbbell * If the test fails, disable the ring. 254254885Sdumbbell * Returns 0 on success, error if the primary GFX ring 255254885Sdumbbell * IB test fails. 256254885Sdumbbell */ 257254885Sdumbbellint radeon_ib_ring_tests(struct radeon_device *rdev) 258254885Sdumbbell{ 259254885Sdumbbell unsigned i; 260254885Sdumbbell int r; 261254885Sdumbbell 262254885Sdumbbell for (i = 0; i < RADEON_NUM_RINGS; ++i) { 263254885Sdumbbell struct radeon_ring *ring = &rdev->ring[i]; 264254885Sdumbbell 265254885Sdumbbell if (!ring->ready) 266254885Sdumbbell continue; 267254885Sdumbbell 268254885Sdumbbell r = radeon_ib_test(rdev, i, ring); 269254885Sdumbbell if (r) { 270254885Sdumbbell ring->ready = false; 271254885Sdumbbell 272254885Sdumbbell if (i == RADEON_RING_TYPE_GFX_INDEX) { 273254885Sdumbbell /* oh, oh, that's really bad */ 274254885Sdumbbell DRM_ERROR("radeon: failed testing IB on GFX ring (%d).\n", r); 275254885Sdumbbell rdev->accel_working = false; 276254885Sdumbbell return r; 277254885Sdumbbell 278254885Sdumbbell } else { 279254885Sdumbbell /* still not good, but we can live with it */ 280254885Sdumbbell DRM_ERROR("radeon: failed testing IB on ring %d (%d).\n", i, r); 281254885Sdumbbell } 282254885Sdumbbell } 283254885Sdumbbell } 284254885Sdumbbell return 0; 285254885Sdumbbell} 286254885Sdumbbell 287254885Sdumbbell#ifdef DUMBBELL_WIP 288254885Sdumbbell/* 289254885Sdumbbell * Rings 290254885Sdumbbell * Most engines on the GPU are fed via ring buffers. Ring 291254885Sdumbbell * buffers are areas of GPU accessible memory that the host 292254885Sdumbbell * writes commands into and the GPU reads commands out of. 293254885Sdumbbell * There is a rptr (read pointer) that determines where the 294254885Sdumbbell * GPU is currently reading, and a wptr (write pointer) 295254885Sdumbbell * which determines where the host has written. When the 296254885Sdumbbell * pointers are equal, the ring is idle. When the host 297254885Sdumbbell * writes commands to the ring buffer, it increments the 298254885Sdumbbell * wptr. The GPU then starts fetching commands and executes 299254885Sdumbbell * them until the pointers are equal again. 300254885Sdumbbell */ 301254885Sdumbbellstatic int radeon_debugfs_ring_init(struct radeon_device *rdev, struct radeon_ring *ring); 302254885Sdumbbell#endif /* DUMBBELL_WIP */ 303254885Sdumbbell 304254885Sdumbbell#if defined(DRM_DEBUG_CODE) && DRM_DEBUG_CODE != 0 305254885Sdumbbell/** 306254885Sdumbbell * radeon_ring_write - write a value to the ring 307254885Sdumbbell * 308254885Sdumbbell * @ring: radeon_ring structure holding ring information 309254885Sdumbbell * @v: dword (dw) value to write 310254885Sdumbbell * 311254885Sdumbbell * Write a value to the requested ring buffer (all asics). 312254885Sdumbbell */ 313254885Sdumbbellvoid radeon_ring_write(struct radeon_ring *ring, uint32_t v) 314254885Sdumbbell{ 315254885Sdumbbell#if DRM_DEBUG_CODE 316254885Sdumbbell if (ring->count_dw <= 0) { 317254885Sdumbbell DRM_ERROR("radeon: writing more dwords to the ring than expected!\n"); 318254885Sdumbbell } 319254885Sdumbbell#endif 320254885Sdumbbell ring->ring[ring->wptr++] = v; 321254885Sdumbbell ring->wptr &= ring->ptr_mask; 322254885Sdumbbell ring->count_dw--; 323254885Sdumbbell ring->ring_free_dw--; 324254885Sdumbbell} 325254885Sdumbbell#endif 326254885Sdumbbell 327254885Sdumbbell/** 328254885Sdumbbell * radeon_ring_supports_scratch_reg - check if the ring supports 329254885Sdumbbell * writing to scratch registers 330254885Sdumbbell * 331254885Sdumbbell * @rdev: radeon_device pointer 332254885Sdumbbell * @ring: radeon_ring structure holding ring information 333254885Sdumbbell * 334254885Sdumbbell * Check if a specific ring supports writing to scratch registers (all asics). 335254885Sdumbbell * Returns true if the ring supports writing to scratch regs, false if not. 336254885Sdumbbell */ 337254885Sdumbbellbool radeon_ring_supports_scratch_reg(struct radeon_device *rdev, 338254885Sdumbbell struct radeon_ring *ring) 339254885Sdumbbell{ 340254885Sdumbbell switch (ring->idx) { 341254885Sdumbbell case RADEON_RING_TYPE_GFX_INDEX: 342254885Sdumbbell case CAYMAN_RING_TYPE_CP1_INDEX: 343254885Sdumbbell case CAYMAN_RING_TYPE_CP2_INDEX: 344254885Sdumbbell return true; 345254885Sdumbbell default: 346254885Sdumbbell return false; 347254885Sdumbbell } 348254885Sdumbbell} 349254885Sdumbbell 350254885Sdumbbell/** 351254885Sdumbbell * radeon_ring_free_size - update the free size 352254885Sdumbbell * 353254885Sdumbbell * @rdev: radeon_device pointer 354254885Sdumbbell * @ring: radeon_ring structure holding ring information 355254885Sdumbbell * 356254885Sdumbbell * Update the free dw slots in the ring buffer (all asics). 357254885Sdumbbell */ 358254885Sdumbbellvoid radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *ring) 359254885Sdumbbell{ 360254885Sdumbbell u32 rptr; 361254885Sdumbbell 362254885Sdumbbell if (rdev->wb.enabled) 363254885Sdumbbell rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]); 364254885Sdumbbell else 365254885Sdumbbell rptr = RREG32(ring->rptr_reg); 366254885Sdumbbell ring->rptr = (rptr & ring->ptr_reg_mask) >> ring->ptr_reg_shift; 367254885Sdumbbell /* This works because ring_size is a power of 2 */ 368254885Sdumbbell ring->ring_free_dw = (ring->rptr + (ring->ring_size / 4)); 369254885Sdumbbell ring->ring_free_dw -= ring->wptr; 370254885Sdumbbell ring->ring_free_dw &= ring->ptr_mask; 371254885Sdumbbell if (!ring->ring_free_dw) { 372254885Sdumbbell ring->ring_free_dw = ring->ring_size / 4; 373254885Sdumbbell } 374254885Sdumbbell} 375254885Sdumbbell 376254885Sdumbbell/** 377254885Sdumbbell * radeon_ring_alloc - allocate space on the ring buffer 378254885Sdumbbell * 379254885Sdumbbell * @rdev: radeon_device pointer 380254885Sdumbbell * @ring: radeon_ring structure holding ring information 381254885Sdumbbell * @ndw: number of dwords to allocate in the ring buffer 382254885Sdumbbell * 383254885Sdumbbell * Allocate @ndw dwords in the ring buffer (all asics). 384254885Sdumbbell * Returns 0 on success, error on failure. 385254885Sdumbbell */ 386254885Sdumbbellint radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw) 387254885Sdumbbell{ 388254885Sdumbbell int r; 389254885Sdumbbell 390254885Sdumbbell /* make sure we aren't trying to allocate more space than there is on the ring */ 391254885Sdumbbell if (ndw > (ring->ring_size / 4)) 392254885Sdumbbell return -ENOMEM; 393254885Sdumbbell /* Align requested size with padding so unlock_commit can 394254885Sdumbbell * pad safely */ 395254885Sdumbbell ndw = (ndw + ring->align_mask) & ~ring->align_mask; 396254885Sdumbbell while (ndw > (ring->ring_free_dw - 1)) { 397254885Sdumbbell radeon_ring_free_size(rdev, ring); 398254885Sdumbbell if (ndw < ring->ring_free_dw) { 399254885Sdumbbell break; 400254885Sdumbbell } 401254885Sdumbbell r = radeon_fence_wait_next_locked(rdev, ring->idx); 402254885Sdumbbell if (r) 403254885Sdumbbell return r; 404254885Sdumbbell } 405254885Sdumbbell ring->count_dw = ndw; 406254885Sdumbbell ring->wptr_old = ring->wptr; 407254885Sdumbbell return 0; 408254885Sdumbbell} 409254885Sdumbbell 410254885Sdumbbell/** 411254885Sdumbbell * radeon_ring_lock - lock the ring and allocate space on it 412254885Sdumbbell * 413254885Sdumbbell * @rdev: radeon_device pointer 414254885Sdumbbell * @ring: radeon_ring structure holding ring information 415254885Sdumbbell * @ndw: number of dwords to allocate in the ring buffer 416254885Sdumbbell * 417254885Sdumbbell * Lock the ring and allocate @ndw dwords in the ring buffer 418254885Sdumbbell * (all asics). 419254885Sdumbbell * Returns 0 on success, error on failure. 420254885Sdumbbell */ 421254885Sdumbbellint radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw) 422254885Sdumbbell{ 423254885Sdumbbell int r; 424254885Sdumbbell 425254885Sdumbbell sx_xlock(&rdev->ring_lock); 426254885Sdumbbell r = radeon_ring_alloc(rdev, ring, ndw); 427254885Sdumbbell if (r) { 428254885Sdumbbell sx_xunlock(&rdev->ring_lock); 429254885Sdumbbell return r; 430254885Sdumbbell } 431254885Sdumbbell return 0; 432254885Sdumbbell} 433254885Sdumbbell 434254885Sdumbbell/** 435254885Sdumbbell * radeon_ring_commit - tell the GPU to execute the new 436254885Sdumbbell * commands on the ring buffer 437254885Sdumbbell * 438254885Sdumbbell * @rdev: radeon_device pointer 439254885Sdumbbell * @ring: radeon_ring structure holding ring information 440254885Sdumbbell * 441254885Sdumbbell * Update the wptr (write pointer) to tell the GPU to 442254885Sdumbbell * execute new commands on the ring buffer (all asics). 443254885Sdumbbell */ 444254885Sdumbbellvoid radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *ring) 445254885Sdumbbell{ 446254885Sdumbbell /* We pad to match fetch size */ 447254885Sdumbbell while (ring->wptr & ring->align_mask) { 448254885Sdumbbell radeon_ring_write(ring, ring->nop); 449254885Sdumbbell } 450254885Sdumbbell DRM_MEMORYBARRIER(); 451254885Sdumbbell WREG32(ring->wptr_reg, (ring->wptr << ring->ptr_reg_shift) & ring->ptr_reg_mask); 452254885Sdumbbell (void)RREG32(ring->wptr_reg); 453254885Sdumbbell} 454254885Sdumbbell 455254885Sdumbbell/** 456254885Sdumbbell * radeon_ring_unlock_commit - tell the GPU to execute the new 457254885Sdumbbell * commands on the ring buffer and unlock it 458254885Sdumbbell * 459254885Sdumbbell * @rdev: radeon_device pointer 460254885Sdumbbell * @ring: radeon_ring structure holding ring information 461254885Sdumbbell * 462254885Sdumbbell * Call radeon_ring_commit() then unlock the ring (all asics). 463254885Sdumbbell */ 464254885Sdumbbellvoid radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *ring) 465254885Sdumbbell{ 466254885Sdumbbell radeon_ring_commit(rdev, ring); 467254885Sdumbbell sx_xunlock(&rdev->ring_lock); 468254885Sdumbbell} 469254885Sdumbbell 470254885Sdumbbell/** 471254885Sdumbbell * radeon_ring_undo - reset the wptr 472254885Sdumbbell * 473254885Sdumbbell * @ring: radeon_ring structure holding ring information 474254885Sdumbbell * 475254885Sdumbbell * Reset the driver's copy of the wptr (all asics). 476254885Sdumbbell */ 477254885Sdumbbellvoid radeon_ring_undo(struct radeon_ring *ring) 478254885Sdumbbell{ 479254885Sdumbbell ring->wptr = ring->wptr_old; 480254885Sdumbbell} 481254885Sdumbbell 482254885Sdumbbell/** 483254885Sdumbbell * radeon_ring_unlock_undo - reset the wptr and unlock the ring 484254885Sdumbbell * 485254885Sdumbbell * @ring: radeon_ring structure holding ring information 486254885Sdumbbell * 487254885Sdumbbell * Call radeon_ring_undo() then unlock the ring (all asics). 488254885Sdumbbell */ 489254885Sdumbbellvoid radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *ring) 490254885Sdumbbell{ 491254885Sdumbbell radeon_ring_undo(ring); 492254885Sdumbbell sx_xunlock(&rdev->ring_lock); 493254885Sdumbbell} 494254885Sdumbbell 495254885Sdumbbell/** 496254885Sdumbbell * radeon_ring_force_activity - add some nop packets to the ring 497254885Sdumbbell * 498254885Sdumbbell * @rdev: radeon_device pointer 499254885Sdumbbell * @ring: radeon_ring structure holding ring information 500254885Sdumbbell * 501254885Sdumbbell * Add some nop packets to the ring to force activity (all asics). 502254885Sdumbbell * Used for lockup detection to see if the rptr is advancing. 503254885Sdumbbell */ 504254885Sdumbbellvoid radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring) 505254885Sdumbbell{ 506254885Sdumbbell int r; 507254885Sdumbbell 508254885Sdumbbell radeon_ring_free_size(rdev, ring); 509254885Sdumbbell if (ring->rptr == ring->wptr) { 510254885Sdumbbell r = radeon_ring_alloc(rdev, ring, 1); 511254885Sdumbbell if (!r) { 512254885Sdumbbell radeon_ring_write(ring, ring->nop); 513254885Sdumbbell radeon_ring_commit(rdev, ring); 514254885Sdumbbell } 515254885Sdumbbell } 516254885Sdumbbell} 517254885Sdumbbell 518254885Sdumbbell/** 519254885Sdumbbell * radeon_ring_lockup_update - update lockup variables 520254885Sdumbbell * 521254885Sdumbbell * @ring: radeon_ring structure holding ring information 522254885Sdumbbell * 523254885Sdumbbell * Update the last rptr value and timestamp (all asics). 524254885Sdumbbell */ 525254885Sdumbbellvoid radeon_ring_lockup_update(struct radeon_ring *ring) 526254885Sdumbbell{ 527254885Sdumbbell ring->last_rptr = ring->rptr; 528254885Sdumbbell ring->last_activity = jiffies; 529254885Sdumbbell} 530254885Sdumbbell 531254885Sdumbbell/** 532254885Sdumbbell * radeon_ring_test_lockup() - check if ring is lockedup by recording information 533254885Sdumbbell * @rdev: radeon device structure 534254885Sdumbbell * @ring: radeon_ring structure holding ring information 535254885Sdumbbell * 536254885Sdumbbell * We don't need to initialize the lockup tracking information as we will either 537254885Sdumbbell * have CP rptr to a different value of jiffies wrap around which will force 538254885Sdumbbell * initialization of the lockup tracking informations. 539254885Sdumbbell * 540254885Sdumbbell * A possible false positivie is if we get call after while and last_cp_rptr == 541254885Sdumbbell * the current CP rptr, even if it's unlikely it might happen. To avoid this 542254885Sdumbbell * if the elapsed time since last call is bigger than 2 second than we return 543254885Sdumbbell * false and update the tracking information. Due to this the caller must call 544254885Sdumbbell * radeon_ring_test_lockup several time in less than 2sec for lockup to be reported 545254885Sdumbbell * the fencing code should be cautious about that. 546254885Sdumbbell * 547254885Sdumbbell * Caller should write to the ring to force CP to do something so we don't get 548254885Sdumbbell * false positive when CP is just gived nothing to do. 549254885Sdumbbell * 550254885Sdumbbell **/ 551254885Sdumbbellbool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring) 552254885Sdumbbell{ 553254885Sdumbbell unsigned long cjiffies, elapsed; 554254885Sdumbbell uint32_t rptr; 555254885Sdumbbell 556254885Sdumbbell cjiffies = jiffies; 557254885Sdumbbell if (!time_after(cjiffies, ring->last_activity)) { 558254885Sdumbbell /* likely a wrap around */ 559254885Sdumbbell radeon_ring_lockup_update(ring); 560254885Sdumbbell return false; 561254885Sdumbbell } 562254885Sdumbbell rptr = RREG32(ring->rptr_reg); 563254885Sdumbbell ring->rptr = (rptr & ring->ptr_reg_mask) >> ring->ptr_reg_shift; 564254885Sdumbbell if (ring->rptr != ring->last_rptr) { 565254885Sdumbbell /* CP is still working no lockup */ 566254885Sdumbbell radeon_ring_lockup_update(ring); 567254885Sdumbbell return false; 568254885Sdumbbell } 569254885Sdumbbell elapsed = jiffies_to_msecs(cjiffies - ring->last_activity); 570254885Sdumbbell if (radeon_lockup_timeout && elapsed >= radeon_lockup_timeout) { 571254885Sdumbbell dev_err(rdev->dev, "GPU lockup CP stall for more than %lumsec\n", elapsed); 572254885Sdumbbell return true; 573254885Sdumbbell } 574254885Sdumbbell /* give a chance to the GPU ... */ 575254885Sdumbbell return false; 576254885Sdumbbell} 577254885Sdumbbell 578254885Sdumbbell/** 579254885Sdumbbell * radeon_ring_backup - Back up the content of a ring 580254885Sdumbbell * 581254885Sdumbbell * @rdev: radeon_device pointer 582254885Sdumbbell * @ring: the ring we want to back up 583254885Sdumbbell * 584254885Sdumbbell * Saves all unprocessed commits from a ring, returns the number of dwords saved. 585254885Sdumbbell */ 586254885Sdumbbellunsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring, 587254885Sdumbbell uint32_t **data) 588254885Sdumbbell{ 589254885Sdumbbell unsigned size, ptr, i; 590254885Sdumbbell 591254885Sdumbbell /* just in case lock the ring */ 592254885Sdumbbell sx_xlock(&rdev->ring_lock); 593254885Sdumbbell *data = NULL; 594254885Sdumbbell 595254885Sdumbbell if (ring->ring_obj == NULL) { 596254885Sdumbbell sx_xunlock(&rdev->ring_lock); 597254885Sdumbbell return 0; 598254885Sdumbbell } 599254885Sdumbbell 600254885Sdumbbell /* it doesn't make sense to save anything if all fences are signaled */ 601254885Sdumbbell if (!radeon_fence_count_emitted(rdev, ring->idx)) { 602254885Sdumbbell sx_xunlock(&rdev->ring_lock); 603254885Sdumbbell return 0; 604254885Sdumbbell } 605254885Sdumbbell 606254885Sdumbbell /* calculate the number of dw on the ring */ 607254885Sdumbbell if (ring->rptr_save_reg) 608254885Sdumbbell ptr = RREG32(ring->rptr_save_reg); 609254885Sdumbbell else if (rdev->wb.enabled) 610254885Sdumbbell ptr = le32_to_cpu(*ring->next_rptr_cpu_addr); 611254885Sdumbbell else { 612254885Sdumbbell /* no way to read back the next rptr */ 613254885Sdumbbell sx_xunlock(&rdev->ring_lock); 614254885Sdumbbell return 0; 615254885Sdumbbell } 616254885Sdumbbell 617254885Sdumbbell size = ring->wptr + (ring->ring_size / 4); 618254885Sdumbbell size -= ptr; 619254885Sdumbbell size &= ring->ptr_mask; 620254885Sdumbbell if (size == 0) { 621254885Sdumbbell sx_xunlock(&rdev->ring_lock); 622254885Sdumbbell return 0; 623254885Sdumbbell } 624254885Sdumbbell 625254885Sdumbbell /* and then save the content of the ring */ 626254885Sdumbbell *data = malloc(size * sizeof(uint32_t), DRM_MEM_DRIVER, M_WAITOK); 627254885Sdumbbell if (!*data) { 628254885Sdumbbell sx_xunlock(&rdev->ring_lock); 629254885Sdumbbell return 0; 630254885Sdumbbell } 631254885Sdumbbell for (i = 0; i < size; ++i) { 632254885Sdumbbell (*data)[i] = ring->ring[ptr++]; 633254885Sdumbbell ptr &= ring->ptr_mask; 634254885Sdumbbell } 635254885Sdumbbell 636254885Sdumbbell sx_xunlock(&rdev->ring_lock); 637254885Sdumbbell return size; 638254885Sdumbbell} 639254885Sdumbbell 640254885Sdumbbell/** 641254885Sdumbbell * radeon_ring_restore - append saved commands to the ring again 642254885Sdumbbell * 643254885Sdumbbell * @rdev: radeon_device pointer 644254885Sdumbbell * @ring: ring to append commands to 645254885Sdumbbell * @size: number of dwords we want to write 646254885Sdumbbell * @data: saved commands 647254885Sdumbbell * 648254885Sdumbbell * Allocates space on the ring and restore the previously saved commands. 649254885Sdumbbell */ 650254885Sdumbbellint radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring, 651254885Sdumbbell unsigned size, uint32_t *data) 652254885Sdumbbell{ 653254885Sdumbbell int i, r; 654254885Sdumbbell 655254885Sdumbbell if (!size || !data) 656254885Sdumbbell return 0; 657254885Sdumbbell 658254885Sdumbbell /* restore the saved ring content */ 659254885Sdumbbell r = radeon_ring_lock(rdev, ring, size); 660254885Sdumbbell if (r) 661254885Sdumbbell return r; 662254885Sdumbbell 663254885Sdumbbell for (i = 0; i < size; ++i) { 664254885Sdumbbell radeon_ring_write(ring, data[i]); 665254885Sdumbbell } 666254885Sdumbbell 667254885Sdumbbell radeon_ring_unlock_commit(rdev, ring); 668254885Sdumbbell free(data, DRM_MEM_DRIVER); 669254885Sdumbbell return 0; 670254885Sdumbbell} 671254885Sdumbbell 672254885Sdumbbell/** 673254885Sdumbbell * radeon_ring_init - init driver ring struct. 674254885Sdumbbell * 675254885Sdumbbell * @rdev: radeon_device pointer 676254885Sdumbbell * @ring: radeon_ring structure holding ring information 677254885Sdumbbell * @ring_size: size of the ring 678254885Sdumbbell * @rptr_offs: offset of the rptr writeback location in the WB buffer 679254885Sdumbbell * @rptr_reg: MMIO offset of the rptr register 680254885Sdumbbell * @wptr_reg: MMIO offset of the wptr register 681254885Sdumbbell * @ptr_reg_shift: bit offset of the rptr/wptr values 682254885Sdumbbell * @ptr_reg_mask: bit mask of the rptr/wptr values 683254885Sdumbbell * @nop: nop packet for this ring 684254885Sdumbbell * 685254885Sdumbbell * Initialize the driver information for the selected ring (all asics). 686254885Sdumbbell * Returns 0 on success, error on failure. 687254885Sdumbbell */ 688254885Sdumbbellint radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size, 689254885Sdumbbell unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg, 690254885Sdumbbell u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop) 691254885Sdumbbell{ 692254885Sdumbbell int r; 693254885Sdumbbell void *ring_ptr; 694254885Sdumbbell 695254885Sdumbbell ring->ring_size = ring_size; 696254885Sdumbbell ring->rptr_offs = rptr_offs; 697254885Sdumbbell ring->rptr_reg = rptr_reg; 698254885Sdumbbell ring->wptr_reg = wptr_reg; 699254885Sdumbbell ring->ptr_reg_shift = ptr_reg_shift; 700254885Sdumbbell ring->ptr_reg_mask = ptr_reg_mask; 701254885Sdumbbell ring->nop = nop; 702254885Sdumbbell /* Allocate ring buffer */ 703254885Sdumbbell if (ring->ring_obj == NULL) { 704254885Sdumbbell r = radeon_bo_create(rdev, ring->ring_size, PAGE_SIZE, true, 705254885Sdumbbell RADEON_GEM_DOMAIN_GTT, 706254885Sdumbbell NULL, &ring->ring_obj); 707254885Sdumbbell if (r) { 708254885Sdumbbell dev_err(rdev->dev, "(%d) ring create failed\n", r); 709254885Sdumbbell return r; 710254885Sdumbbell } 711254885Sdumbbell r = radeon_bo_reserve(ring->ring_obj, false); 712254885Sdumbbell if (unlikely(r != 0)) { 713254885Sdumbbell radeon_bo_unref(&ring->ring_obj); 714254885Sdumbbell return r; 715254885Sdumbbell } 716254885Sdumbbell r = radeon_bo_pin(ring->ring_obj, RADEON_GEM_DOMAIN_GTT, 717254885Sdumbbell &ring->gpu_addr); 718254885Sdumbbell if (r) { 719254885Sdumbbell radeon_bo_unreserve(ring->ring_obj); 720254885Sdumbbell radeon_bo_unref(&ring->ring_obj); 721254885Sdumbbell dev_err(rdev->dev, "(%d) ring pin failed\n", r); 722254885Sdumbbell return r; 723254885Sdumbbell } 724254885Sdumbbell ring_ptr = &ring->ring; 725254885Sdumbbell r = radeon_bo_kmap(ring->ring_obj, 726254885Sdumbbell ring_ptr); 727254885Sdumbbell radeon_bo_unreserve(ring->ring_obj); 728254885Sdumbbell if (r) { 729254885Sdumbbell dev_err(rdev->dev, "(%d) ring map failed\n", r); 730254885Sdumbbell radeon_bo_unref(&ring->ring_obj); 731254885Sdumbbell return r; 732254885Sdumbbell } 733254885Sdumbbell } 734254885Sdumbbell ring->ptr_mask = (ring->ring_size / 4) - 1; 735254885Sdumbbell ring->ring_free_dw = ring->ring_size / 4; 736254885Sdumbbell if (rdev->wb.enabled) { 737254885Sdumbbell u32 index = RADEON_WB_RING0_NEXT_RPTR + (ring->idx * 4); 738254885Sdumbbell ring->next_rptr_gpu_addr = rdev->wb.gpu_addr + index; 739254885Sdumbbell ring->next_rptr_cpu_addr = &rdev->wb.wb[index/4]; 740254885Sdumbbell } 741254885Sdumbbell#ifdef DUMBBELL_WIP 742254885Sdumbbell if (radeon_debugfs_ring_init(rdev, ring)) { 743254885Sdumbbell DRM_ERROR("Failed to register debugfs file for rings !\n"); 744254885Sdumbbell } 745254885Sdumbbell#endif /* DUMBBELL_WIP */ 746254885Sdumbbell radeon_ring_lockup_update(ring); 747254885Sdumbbell return 0; 748254885Sdumbbell} 749254885Sdumbbell 750254885Sdumbbell/** 751254885Sdumbbell * radeon_ring_fini - tear down the driver ring struct. 752254885Sdumbbell * 753254885Sdumbbell * @rdev: radeon_device pointer 754254885Sdumbbell * @ring: radeon_ring structure holding ring information 755254885Sdumbbell * 756254885Sdumbbell * Tear down the driver information for the selected ring (all asics). 757254885Sdumbbell */ 758254885Sdumbbellvoid radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *ring) 759254885Sdumbbell{ 760254885Sdumbbell int r; 761254885Sdumbbell struct radeon_bo *ring_obj; 762254885Sdumbbell 763254885Sdumbbell sx_xlock(&rdev->ring_lock); 764254885Sdumbbell ring_obj = ring->ring_obj; 765254885Sdumbbell ring->ready = false; 766254885Sdumbbell ring->ring = NULL; 767254885Sdumbbell ring->ring_obj = NULL; 768254885Sdumbbell sx_xunlock(&rdev->ring_lock); 769254885Sdumbbell 770254885Sdumbbell if (ring_obj) { 771254885Sdumbbell r = radeon_bo_reserve(ring_obj, false); 772254885Sdumbbell if (likely(r == 0)) { 773254885Sdumbbell radeon_bo_kunmap(ring_obj); 774254885Sdumbbell radeon_bo_unpin(ring_obj); 775254885Sdumbbell radeon_bo_unreserve(ring_obj); 776254885Sdumbbell } 777254885Sdumbbell radeon_bo_unref(&ring_obj); 778254885Sdumbbell } 779254885Sdumbbell} 780254885Sdumbbell 781254885Sdumbbell/* 782254885Sdumbbell * Debugfs info 783254885Sdumbbell */ 784254885Sdumbbell#if defined(CONFIG_DEBUG_FS) 785254885Sdumbbell 786254885Sdumbbellstatic int radeon_debugfs_ring_info(struct seq_file *m, void *data) 787254885Sdumbbell{ 788254885Sdumbbell struct drm_info_node *node = (struct drm_info_node *) m->private; 789254885Sdumbbell struct drm_device *dev = node->minor->dev; 790254885Sdumbbell struct radeon_device *rdev = dev->dev_private; 791254885Sdumbbell int ridx = *(int*)node->info_ent->data; 792254885Sdumbbell struct radeon_ring *ring = &rdev->ring[ridx]; 793254885Sdumbbell unsigned count, i, j; 794254885Sdumbbell u32 tmp; 795254885Sdumbbell 796254885Sdumbbell radeon_ring_free_size(rdev, ring); 797254885Sdumbbell count = (ring->ring_size / 4) - ring->ring_free_dw; 798254885Sdumbbell tmp = RREG32(ring->wptr_reg) >> ring->ptr_reg_shift; 799254885Sdumbbell seq_printf(m, "wptr(0x%04x): 0x%08x [%5d]\n", ring->wptr_reg, tmp, tmp); 800254885Sdumbbell tmp = RREG32(ring->rptr_reg) >> ring->ptr_reg_shift; 801254885Sdumbbell seq_printf(m, "rptr(0x%04x): 0x%08x [%5d]\n", ring->rptr_reg, tmp, tmp); 802254885Sdumbbell if (ring->rptr_save_reg) { 803254885Sdumbbell seq_printf(m, "rptr next(0x%04x): 0x%08x\n", ring->rptr_save_reg, 804254885Sdumbbell RREG32(ring->rptr_save_reg)); 805254885Sdumbbell } 806254885Sdumbbell seq_printf(m, "driver's copy of the wptr: 0x%08x [%5d]\n", ring->wptr, ring->wptr); 807254885Sdumbbell seq_printf(m, "driver's copy of the rptr: 0x%08x [%5d]\n", ring->rptr, ring->rptr); 808254885Sdumbbell seq_printf(m, "last semaphore signal addr : 0x%016llx\n", ring->last_semaphore_signal_addr); 809254885Sdumbbell seq_printf(m, "last semaphore wait addr : 0x%016llx\n", ring->last_semaphore_wait_addr); 810254885Sdumbbell seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw); 811254885Sdumbbell seq_printf(m, "%u dwords in ring\n", count); 812254885Sdumbbell /* print 8 dw before current rptr as often it's the last executed 813254885Sdumbbell * packet that is the root issue 814254885Sdumbbell */ 815254885Sdumbbell i = (ring->rptr + ring->ptr_mask + 1 - 32) & ring->ptr_mask; 816254885Sdumbbell for (j = 0; j <= (count + 32); j++) { 817254885Sdumbbell seq_printf(m, "r[%5d]=0x%08x\n", i, ring->ring[i]); 818254885Sdumbbell i = (i + 1) & ring->ptr_mask; 819254885Sdumbbell } 820254885Sdumbbell return 0; 821254885Sdumbbell} 822254885Sdumbbell 823254885Sdumbbellstatic int radeon_ring_type_gfx_index = RADEON_RING_TYPE_GFX_INDEX; 824254885Sdumbbellstatic int cayman_ring_type_cp1_index = CAYMAN_RING_TYPE_CP1_INDEX; 825254885Sdumbbellstatic int cayman_ring_type_cp2_index = CAYMAN_RING_TYPE_CP2_INDEX; 826254885Sdumbbellstatic int radeon_ring_type_dma1_index = R600_RING_TYPE_DMA_INDEX; 827254885Sdumbbellstatic int radeon_ring_type_dma2_index = CAYMAN_RING_TYPE_DMA1_INDEX; 828254885Sdumbbell 829254885Sdumbbellstatic struct drm_info_list radeon_debugfs_ring_info_list[] = { 830254885Sdumbbell {"radeon_ring_gfx", radeon_debugfs_ring_info, 0, &radeon_ring_type_gfx_index}, 831254885Sdumbbell {"radeon_ring_cp1", radeon_debugfs_ring_info, 0, &cayman_ring_type_cp1_index}, 832254885Sdumbbell {"radeon_ring_cp2", radeon_debugfs_ring_info, 0, &cayman_ring_type_cp2_index}, 833254885Sdumbbell {"radeon_ring_dma1", radeon_debugfs_ring_info, 0, &radeon_ring_type_dma1_index}, 834254885Sdumbbell {"radeon_ring_dma2", radeon_debugfs_ring_info, 0, &radeon_ring_type_dma2_index}, 835254885Sdumbbell}; 836254885Sdumbbell 837254885Sdumbbellstatic int radeon_debugfs_sa_info(struct seq_file *m, void *data) 838254885Sdumbbell{ 839254885Sdumbbell struct drm_info_node *node = (struct drm_info_node *) m->private; 840254885Sdumbbell struct drm_device *dev = node->minor->dev; 841254885Sdumbbell struct radeon_device *rdev = dev->dev_private; 842254885Sdumbbell 843254885Sdumbbell radeon_sa_bo_dump_debug_info(&rdev->ring_tmp_bo, m); 844254885Sdumbbell 845254885Sdumbbell return 0; 846254885Sdumbbell 847254885Sdumbbell} 848254885Sdumbbell 849254885Sdumbbellstatic struct drm_info_list radeon_debugfs_sa_list[] = { 850254885Sdumbbell {"radeon_sa_info", &radeon_debugfs_sa_info, 0, NULL}, 851254885Sdumbbell}; 852254885Sdumbbell 853254885Sdumbbell#endif 854254885Sdumbbell 855254885Sdumbbell#ifdef DUMBBELL_WIP 856254885Sdumbbellstatic int radeon_debugfs_ring_init(struct radeon_device *rdev, struct radeon_ring *ring) 857254885Sdumbbell{ 858254885Sdumbbell#if defined(CONFIG_DEBUG_FS) 859254885Sdumbbell unsigned i; 860254885Sdumbbell for (i = 0; i < ARRAY_SIZE(radeon_debugfs_ring_info_list); ++i) { 861254885Sdumbbell struct drm_info_list *info = &radeon_debugfs_ring_info_list[i]; 862254885Sdumbbell int ridx = *(int*)radeon_debugfs_ring_info_list[i].data; 863254885Sdumbbell unsigned r; 864254885Sdumbbell 865254885Sdumbbell if (&rdev->ring[ridx] != ring) 866254885Sdumbbell continue; 867254885Sdumbbell 868254885Sdumbbell r = radeon_debugfs_add_files(rdev, info, 1); 869254885Sdumbbell if (r) 870254885Sdumbbell return r; 871254885Sdumbbell } 872254885Sdumbbell#endif 873254885Sdumbbell return 0; 874254885Sdumbbell} 875254885Sdumbbell 876254885Sdumbbellstatic int radeon_debugfs_sa_init(struct radeon_device *rdev) 877254885Sdumbbell{ 878254885Sdumbbell#if defined(CONFIG_DEBUG_FS) 879254885Sdumbbell return radeon_debugfs_add_files(rdev, radeon_debugfs_sa_list, 1); 880254885Sdumbbell#else 881254885Sdumbbell return 0; 882254885Sdumbbell#endif 883254885Sdumbbell} 884254885Sdumbbell#endif /* DUMBBELL_WIP */ 885