1254885Sdumbbell/* 2254885Sdumbbell * Copyright 2008 Advanced Micro Devices, Inc. 3254885Sdumbbell * Copyright 2008 Red Hat Inc. 4254885Sdumbbell * Copyright 2009 Jerome Glisse. 5254885Sdumbbell * 6254885Sdumbbell * Permission is hereby granted, free of charge, to any person obtaining a 7254885Sdumbbell * copy of this software and associated documentation files (the "Software"), 8254885Sdumbbell * to deal in the Software without restriction, including without limitation 9254885Sdumbbell * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10254885Sdumbbell * and/or sell copies of the Software, and to permit persons to whom the 11254885Sdumbbell * Software is furnished to do so, subject to the following conditions: 12254885Sdumbbell * 13254885Sdumbbell * The above copyright notice and this permission notice shall be included in 14254885Sdumbbell * all copies or substantial portions of the Software. 15254885Sdumbbell * 16254885Sdumbbell * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17254885Sdumbbell * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18254885Sdumbbell * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19254885Sdumbbell * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20254885Sdumbbell * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21254885Sdumbbell * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22254885Sdumbbell * OTHER DEALINGS IN THE SOFTWARE. 23254885Sdumbbell * 24254885Sdumbbell * Authors: Dave Airlie 25254885Sdumbbell * Alex Deucher 26254885Sdumbbell * Jerome Glisse 27254885Sdumbbell */ 28254885Sdumbbell 29254885Sdumbbell#include <sys/cdefs.h> 30254885Sdumbbell__FBSDID("$FreeBSD$"); 31254885Sdumbbell 32254885Sdumbbell#ifndef __RADEON_H__ 33254885Sdumbbell#define __RADEON_H__ 34254885Sdumbbell 35254885Sdumbbell/* TODO: Here are things that needs to be done : 36254885Sdumbbell * - surface allocator & initializer : (bit like scratch reg) should 37254885Sdumbbell * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings 38254885Sdumbbell * related to surface 39254885Sdumbbell * - WB : write back stuff (do it bit like scratch reg things) 40254885Sdumbbell * - Vblank : look at Jesse's rework and what we should do 41254885Sdumbbell * - r600/r700: gart & cp 42254885Sdumbbell * - cs : clean cs ioctl use bitmap & things like that. 43254885Sdumbbell * - power management stuff 44254885Sdumbbell * - Barrier in gart code 45254885Sdumbbell * - Unmappabled vram ? 46254885Sdumbbell * - TESTING, TESTING, TESTING 47254885Sdumbbell */ 48254885Sdumbbell 49254885Sdumbbell/* Initialization path: 50254885Sdumbbell * We expect that acceleration initialization might fail for various 51254885Sdumbbell * reasons even thought we work hard to make it works on most 52254885Sdumbbell * configurations. In order to still have a working userspace in such 53254885Sdumbbell * situation the init path must succeed up to the memory controller 54254885Sdumbbell * initialization point. Failure before this point are considered as 55254885Sdumbbell * fatal error. Here is the init callchain : 56254885Sdumbbell * radeon_device_init perform common structure, mutex initialization 57254885Sdumbbell * asic_init setup the GPU memory layout and perform all 58254885Sdumbbell * one time initialization (failure in this 59254885Sdumbbell * function are considered fatal) 60254885Sdumbbell * asic_startup setup the GPU acceleration, in order to 61254885Sdumbbell * follow guideline the first thing this 62254885Sdumbbell * function should do is setting the GPU 63254885Sdumbbell * memory controller (only MC setup failure 64254885Sdumbbell * are considered as fatal) 65254885Sdumbbell */ 66254885Sdumbbell 67254885Sdumbbell#include <sys/cdefs.h> 68254885Sdumbbell__FBSDID("$FreeBSD$"); 69254885Sdumbbell 70254885Sdumbbell#include <sys/param.h> 71254885Sdumbbell#include <sys/systm.h> 72254885Sdumbbell#include <sys/linker.h> 73254885Sdumbbell#include <sys/firmware.h> 74254885Sdumbbell 75254885Sdumbbell#include <contrib/dev/acpica/include/acpi.h> 76254885Sdumbbell#include <dev/acpica/acpivar.h> 77254885Sdumbbell 78254885Sdumbbell#include <dev/drm2/ttm/ttm_bo_api.h> 79254885Sdumbbell#include <dev/drm2/ttm/ttm_bo_driver.h> 80254885Sdumbbell#include <dev/drm2/ttm/ttm_placement.h> 81254885Sdumbbell#include <dev/drm2/ttm/ttm_module.h> 82254885Sdumbbell#include <dev/drm2/ttm/ttm_execbuf_util.h> 83254885Sdumbbell 84254885Sdumbbell#include "radeon_family.h" 85254885Sdumbbell#include "radeon_mode.h" 86254885Sdumbbell#include "radeon_reg.h" 87254885Sdumbbell 88254885Sdumbbell/* 89254885Sdumbbell * Modules parameters. 90254885Sdumbbell */ 91254885Sdumbbellextern int radeon_no_wb; 92254885Sdumbbellextern int radeon_modeset; 93254885Sdumbbellextern int radeon_dynclks; 94254885Sdumbbellextern int radeon_r4xx_atom; 95254885Sdumbbellextern int radeon_agpmode; 96254885Sdumbbellextern int radeon_vram_limit; 97254885Sdumbbellextern int radeon_gart_size; 98254885Sdumbbellextern int radeon_benchmarking; 99254885Sdumbbellextern int radeon_testing; 100254885Sdumbbellextern int radeon_connector_table; 101254885Sdumbbellextern int radeon_tv; 102254885Sdumbbellextern int radeon_audio; 103254885Sdumbbellextern int radeon_disp_priority; 104254885Sdumbbellextern int radeon_hw_i2c; 105254885Sdumbbellextern int radeon_pcie_gen2; 106254885Sdumbbellextern int radeon_msi; 107254885Sdumbbellextern int radeon_lockup_timeout; 108254885Sdumbbell 109254885Sdumbbell/* 110254885Sdumbbell * Copy from radeon_drv.h so we don't have to include both and have conflicting 111254885Sdumbbell * symbol; 112254885Sdumbbell */ 113254885Sdumbbell#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 114254885Sdumbbell#define RADEON_FENCE_JIFFIES_TIMEOUT (DRM_HZ / 2) 115254885Sdumbbell/* RADEON_IB_POOL_SIZE must be a power of 2 */ 116254885Sdumbbell#define RADEON_IB_POOL_SIZE 16 117254885Sdumbbell#define RADEON_DEBUGFS_MAX_COMPONENTS 32 118254885Sdumbbell#define RADEONFB_CONN_LIMIT 4 119254885Sdumbbell#define RADEON_BIOS_NUM_SCRATCH 8 120254885Sdumbbell 121254885Sdumbbell/* max number of rings */ 122254885Sdumbbell#define RADEON_NUM_RINGS 5 123254885Sdumbbell 124254885Sdumbbell/* fence seq are set to this number when signaled */ 125254885Sdumbbell#define RADEON_FENCE_SIGNALED_SEQ 0LL 126254885Sdumbbell 127254885Sdumbbell/* internal ring indices */ 128254885Sdumbbell/* r1xx+ has gfx CP ring */ 129254885Sdumbbell#define RADEON_RING_TYPE_GFX_INDEX 0 130254885Sdumbbell 131254885Sdumbbell/* cayman has 2 compute CP rings */ 132254885Sdumbbell#define CAYMAN_RING_TYPE_CP1_INDEX 1 133254885Sdumbbell#define CAYMAN_RING_TYPE_CP2_INDEX 2 134254885Sdumbbell 135254885Sdumbbell/* R600+ has an async dma ring */ 136254885Sdumbbell#define R600_RING_TYPE_DMA_INDEX 3 137254885Sdumbbell/* cayman add a second async dma ring */ 138254885Sdumbbell#define CAYMAN_RING_TYPE_DMA1_INDEX 4 139254885Sdumbbell 140254885Sdumbbell/* hardcode those limit for now */ 141254885Sdumbbell#define RADEON_VA_IB_OFFSET (1 << 20) 142254885Sdumbbell#define RADEON_VA_RESERVED_SIZE (8 << 20) 143254885Sdumbbell#define RADEON_IB_VM_MAX_SIZE (64 << 10) 144254885Sdumbbell 145254885Sdumbbell/* reset flags */ 146254885Sdumbbell#define RADEON_RESET_GFX (1 << 0) 147254885Sdumbbell#define RADEON_RESET_COMPUTE (1 << 1) 148254885Sdumbbell#define RADEON_RESET_DMA (1 << 2) 149254885Sdumbbell 150254885Sdumbbell/* 151254885Sdumbbell * Errata workarounds. 152254885Sdumbbell */ 153254885Sdumbbellenum radeon_pll_errata { 154254885Sdumbbell CHIP_ERRATA_R300_CG = 0x00000001, 155254885Sdumbbell CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, 156254885Sdumbbell CHIP_ERRATA_PLL_DELAY = 0x00000004 157254885Sdumbbell}; 158254885Sdumbbell 159254885Sdumbbell 160254885Sdumbbellstruct radeon_device; 161254885Sdumbbell 162254885Sdumbbell 163254885Sdumbbell/* 164254885Sdumbbell * BIOS. 165254885Sdumbbell */ 166254885Sdumbbellbool radeon_get_bios(struct radeon_device *rdev); 167254885Sdumbbell 168254885Sdumbbell/* 169254885Sdumbbell * Dummy page 170254885Sdumbbell */ 171254885Sdumbbellstruct radeon_dummy_page { 172254885Sdumbbell drm_dma_handle_t *dmah; 173254885Sdumbbell dma_addr_t addr; 174254885Sdumbbell}; 175254885Sdumbbellint radeon_dummy_page_init(struct radeon_device *rdev); 176254885Sdumbbellvoid radeon_dummy_page_fini(struct radeon_device *rdev); 177254885Sdumbbell 178254885Sdumbbell 179254885Sdumbbell/* 180254885Sdumbbell * Clocks 181254885Sdumbbell */ 182254885Sdumbbellstruct radeon_clock { 183254885Sdumbbell struct radeon_pll p1pll; 184254885Sdumbbell struct radeon_pll p2pll; 185254885Sdumbbell struct radeon_pll dcpll; 186254885Sdumbbell struct radeon_pll spll; 187254885Sdumbbell struct radeon_pll mpll; 188254885Sdumbbell /* 10 Khz units */ 189254885Sdumbbell uint32_t default_mclk; 190254885Sdumbbell uint32_t default_sclk; 191254885Sdumbbell uint32_t default_dispclk; 192254885Sdumbbell uint32_t dp_extclk; 193254885Sdumbbell uint32_t max_pixel_clock; 194254885Sdumbbell}; 195254885Sdumbbell 196254885Sdumbbell/* 197254885Sdumbbell * Power management 198254885Sdumbbell */ 199254885Sdumbbellint radeon_pm_init(struct radeon_device *rdev); 200254885Sdumbbellvoid radeon_pm_fini(struct radeon_device *rdev); 201254885Sdumbbellvoid radeon_pm_compute_clocks(struct radeon_device *rdev); 202254885Sdumbbellvoid radeon_pm_suspend(struct radeon_device *rdev); 203254885Sdumbbellvoid radeon_pm_resume(struct radeon_device *rdev); 204254885Sdumbbellvoid radeon_combios_get_power_modes(struct radeon_device *rdev); 205254885Sdumbbellvoid radeon_atombios_get_power_modes(struct radeon_device *rdev); 206254885Sdumbbellvoid radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type); 207254885Sdumbbellvoid rs690_pm_info(struct radeon_device *rdev); 208254885Sdumbbellextern int rv6xx_get_temp(struct radeon_device *rdev); 209254885Sdumbbellextern int rv770_get_temp(struct radeon_device *rdev); 210254885Sdumbbellextern int evergreen_get_temp(struct radeon_device *rdev); 211254885Sdumbbellextern int sumo_get_temp(struct radeon_device *rdev); 212254885Sdumbbellextern int si_get_temp(struct radeon_device *rdev); 213254885Sdumbbellextern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, 214254885Sdumbbell unsigned *bankh, unsigned *mtaspect, 215254885Sdumbbell unsigned *tile_split); 216254885Sdumbbell 217254885Sdumbbell/* 218254885Sdumbbell * Fences. 219254885Sdumbbell */ 220254885Sdumbbellstruct radeon_fence_driver { 221254885Sdumbbell uint32_t scratch_reg; 222254885Sdumbbell uint64_t gpu_addr; 223254885Sdumbbell volatile uint32_t *cpu_addr; 224254885Sdumbbell /* sync_seq is protected by ring emission lock */ 225254885Sdumbbell uint64_t sync_seq[RADEON_NUM_RINGS]; 226254885Sdumbbell atomic64_t last_seq; 227254885Sdumbbell unsigned long last_activity; 228254885Sdumbbell bool initialized; 229254885Sdumbbell}; 230254885Sdumbbell 231254885Sdumbbellstruct radeon_fence { 232254885Sdumbbell struct radeon_device *rdev; 233254885Sdumbbell unsigned int kref; 234254885Sdumbbell /* protected by radeon_fence.lock */ 235254885Sdumbbell uint64_t seq; 236254885Sdumbbell /* RB, DMA, etc. */ 237254885Sdumbbell unsigned ring; 238254885Sdumbbell}; 239254885Sdumbbell 240254885Sdumbbellint radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring); 241254885Sdumbbellint radeon_fence_driver_init(struct radeon_device *rdev); 242254885Sdumbbellvoid radeon_fence_driver_fini(struct radeon_device *rdev); 243254885Sdumbbellvoid radeon_fence_driver_force_completion(struct radeon_device *rdev); 244254885Sdumbbellint radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring); 245254885Sdumbbellvoid radeon_fence_process(struct radeon_device *rdev, int ring); 246254885Sdumbbellbool radeon_fence_signaled(struct radeon_fence *fence); 247254885Sdumbbellint radeon_fence_wait(struct radeon_fence *fence, bool interruptible); 248254885Sdumbbellint radeon_fence_wait_next_locked(struct radeon_device *rdev, int ring); 249254885Sdumbbellint radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring); 250254885Sdumbbellint radeon_fence_wait_any(struct radeon_device *rdev, 251254885Sdumbbell struct radeon_fence **fences, 252254885Sdumbbell bool intr); 253254885Sdumbbellstruct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); 254254885Sdumbbellvoid radeon_fence_unref(struct radeon_fence **fence); 255254885Sdumbbellunsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring); 256254885Sdumbbellbool radeon_fence_need_sync(struct radeon_fence *fence, int ring); 257254885Sdumbbellvoid radeon_fence_note_sync(struct radeon_fence *fence, int ring); 258254885Sdumbbellstatic inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a, 259254885Sdumbbell struct radeon_fence *b) 260254885Sdumbbell{ 261254885Sdumbbell if (!a) { 262254885Sdumbbell return b; 263254885Sdumbbell } 264254885Sdumbbell 265254885Sdumbbell if (!b) { 266254885Sdumbbell return a; 267254885Sdumbbell } 268254885Sdumbbell 269254885Sdumbbell KASSERT(a->ring == b->ring, ("\"a\" and \"b\" belongs to different rings")); 270254885Sdumbbell 271254885Sdumbbell if (a->seq > b->seq) { 272254885Sdumbbell return a; 273254885Sdumbbell } else { 274254885Sdumbbell return b; 275254885Sdumbbell } 276254885Sdumbbell} 277254885Sdumbbell 278254885Sdumbbellstatic inline bool radeon_fence_is_earlier(struct radeon_fence *a, 279254885Sdumbbell struct radeon_fence *b) 280254885Sdumbbell{ 281254885Sdumbbell if (!a) { 282254885Sdumbbell return false; 283254885Sdumbbell } 284254885Sdumbbell 285254885Sdumbbell if (!b) { 286254885Sdumbbell return true; 287254885Sdumbbell } 288254885Sdumbbell 289254885Sdumbbell KASSERT(a->ring == b->ring, ("\"a\" and \"b\" belongs to different rings")); 290254885Sdumbbell 291254885Sdumbbell return a->seq < b->seq; 292254885Sdumbbell} 293254885Sdumbbell 294254885Sdumbbell/* 295254885Sdumbbell * Tiling registers 296254885Sdumbbell */ 297254885Sdumbbellstruct radeon_surface_reg { 298254885Sdumbbell struct radeon_bo *bo; 299254885Sdumbbell}; 300254885Sdumbbell 301254885Sdumbbell#define RADEON_GEM_MAX_SURFACES 8 302254885Sdumbbell 303254885Sdumbbell/* 304254885Sdumbbell * TTM. 305254885Sdumbbell */ 306254885Sdumbbellstruct radeon_mman { 307254885Sdumbbell struct ttm_bo_global_ref bo_global_ref; 308254885Sdumbbell struct drm_global_reference mem_global_ref; 309254885Sdumbbell struct ttm_bo_device bdev; 310254885Sdumbbell bool mem_global_referenced; 311254885Sdumbbell bool initialized; 312254885Sdumbbell}; 313254885Sdumbbell 314254885Sdumbbell/* bo virtual address in a specific vm */ 315254885Sdumbbellstruct radeon_bo_va { 316254885Sdumbbell /* protected by bo being reserved */ 317254885Sdumbbell struct list_head bo_list; 318254885Sdumbbell uint64_t soffset; 319254885Sdumbbell uint64_t eoffset; 320254885Sdumbbell uint32_t flags; 321254885Sdumbbell bool valid; 322254885Sdumbbell unsigned ref_count; 323254885Sdumbbell 324254885Sdumbbell /* protected by vm mutex */ 325254885Sdumbbell struct list_head vm_list; 326254885Sdumbbell 327254885Sdumbbell /* constant after initialization */ 328254885Sdumbbell struct radeon_vm *vm; 329254885Sdumbbell struct radeon_bo *bo; 330254885Sdumbbell}; 331254885Sdumbbell 332254885Sdumbbellstruct radeon_bo { 333254885Sdumbbell /* Protected by gem.mutex */ 334254885Sdumbbell struct list_head list; 335254885Sdumbbell /* Protected by tbo.reserved */ 336254885Sdumbbell u32 placements[3]; 337254885Sdumbbell struct ttm_placement placement; 338254885Sdumbbell struct ttm_buffer_object tbo; 339254885Sdumbbell struct ttm_bo_kmap_obj kmap; 340254885Sdumbbell unsigned pin_count; 341254885Sdumbbell void *kptr; 342254885Sdumbbell u32 tiling_flags; 343254885Sdumbbell u32 pitch; 344254885Sdumbbell int surface_reg; 345254885Sdumbbell /* list of all virtual address to which this bo 346254885Sdumbbell * is associated to 347254885Sdumbbell */ 348254885Sdumbbell struct list_head va; 349254885Sdumbbell /* Constant after initialization */ 350254885Sdumbbell struct radeon_device *rdev; 351254885Sdumbbell struct drm_gem_object gem_base; 352254885Sdumbbell 353254885Sdumbbell struct ttm_bo_kmap_obj dma_buf_vmap; 354254885Sdumbbell int vmapping_count; 355254885Sdumbbell}; 356254885Sdumbbell#define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base) 357254885Sdumbbell 358254885Sdumbbellstruct radeon_bo_list { 359254885Sdumbbell struct ttm_validate_buffer tv; 360254885Sdumbbell struct radeon_bo *bo; 361254885Sdumbbell uint64_t gpu_offset; 362254885Sdumbbell unsigned rdomain; 363254885Sdumbbell unsigned wdomain; 364254885Sdumbbell u32 tiling_flags; 365254885Sdumbbell}; 366254885Sdumbbell 367254885Sdumbbell/* sub-allocation manager, it has to be protected by another lock. 368254885Sdumbbell * By conception this is an helper for other part of the driver 369254885Sdumbbell * like the indirect buffer or semaphore, which both have their 370254885Sdumbbell * locking. 371254885Sdumbbell * 372254885Sdumbbell * Principe is simple, we keep a list of sub allocation in offset 373254885Sdumbbell * order (first entry has offset == 0, last entry has the highest 374254885Sdumbbell * offset). 375254885Sdumbbell * 376254885Sdumbbell * When allocating new object we first check if there is room at 377254885Sdumbbell * the end total_size - (last_object_offset + last_object_size) >= 378254885Sdumbbell * alloc_size. If so we allocate new object there. 379254885Sdumbbell * 380254885Sdumbbell * When there is not enough room at the end, we start waiting for 381254885Sdumbbell * each sub object until we reach object_offset+object_size >= 382254885Sdumbbell * alloc_size, this object then become the sub object we return. 383254885Sdumbbell * 384254885Sdumbbell * Alignment can't be bigger than page size. 385254885Sdumbbell * 386254885Sdumbbell * Hole are not considered for allocation to keep things simple. 387254885Sdumbbell * Assumption is that there won't be hole (all object on same 388254885Sdumbbell * alignment). 389254885Sdumbbell */ 390254885Sdumbbellstruct radeon_sa_manager { 391254885Sdumbbell struct cv wq; 392254885Sdumbbell struct sx wq_lock; 393254885Sdumbbell struct radeon_bo *bo; 394254885Sdumbbell struct list_head *hole; 395254885Sdumbbell struct list_head flist[RADEON_NUM_RINGS]; 396254885Sdumbbell struct list_head olist; 397254885Sdumbbell unsigned size; 398254885Sdumbbell uint64_t gpu_addr; 399254885Sdumbbell void *cpu_ptr; 400254885Sdumbbell uint32_t domain; 401254885Sdumbbell}; 402254885Sdumbbell 403254885Sdumbbellstruct radeon_sa_bo; 404254885Sdumbbell 405254885Sdumbbell/* sub-allocation buffer */ 406254885Sdumbbellstruct radeon_sa_bo { 407254885Sdumbbell struct list_head olist; 408254885Sdumbbell struct list_head flist; 409254885Sdumbbell struct radeon_sa_manager *manager; 410254885Sdumbbell unsigned soffset; 411254885Sdumbbell unsigned eoffset; 412254885Sdumbbell struct radeon_fence *fence; 413254885Sdumbbell}; 414254885Sdumbbell 415254885Sdumbbell/* 416254885Sdumbbell * GEM objects. 417254885Sdumbbell */ 418254885Sdumbbellstruct radeon_gem { 419254885Sdumbbell struct sx mutex; 420254885Sdumbbell struct list_head objects; 421254885Sdumbbell}; 422254885Sdumbbell 423254885Sdumbbellint radeon_gem_init(struct radeon_device *rdev); 424254885Sdumbbellvoid radeon_gem_fini(struct radeon_device *rdev); 425254885Sdumbbellint radeon_gem_object_create(struct radeon_device *rdev, int size, 426254885Sdumbbell int alignment, int initial_domain, 427254885Sdumbbell bool discardable, bool kernel, 428254885Sdumbbell struct drm_gem_object **obj); 429254885Sdumbbell 430254885Sdumbbellint radeon_mode_dumb_create(struct drm_file *file_priv, 431254885Sdumbbell struct drm_device *dev, 432254885Sdumbbell struct drm_mode_create_dumb *args); 433254885Sdumbbellint radeon_mode_dumb_mmap(struct drm_file *filp, 434254885Sdumbbell struct drm_device *dev, 435254885Sdumbbell uint32_t handle, uint64_t *offset_p); 436254885Sdumbbellint radeon_mode_dumb_destroy(struct drm_file *file_priv, 437254885Sdumbbell struct drm_device *dev, 438254885Sdumbbell uint32_t handle); 439254885Sdumbbell 440254885Sdumbbell/* 441254885Sdumbbell * Semaphores. 442254885Sdumbbell */ 443254885Sdumbbell/* everything here is constant */ 444254885Sdumbbellstruct radeon_semaphore { 445254885Sdumbbell struct radeon_sa_bo *sa_bo; 446254885Sdumbbell signed waiters; 447254885Sdumbbell uint64_t gpu_addr; 448254885Sdumbbell}; 449254885Sdumbbell 450254885Sdumbbellint radeon_semaphore_create(struct radeon_device *rdev, 451254885Sdumbbell struct radeon_semaphore **semaphore); 452254885Sdumbbellvoid radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring, 453254885Sdumbbell struct radeon_semaphore *semaphore); 454254885Sdumbbellvoid radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring, 455254885Sdumbbell struct radeon_semaphore *semaphore); 456254885Sdumbbellint radeon_semaphore_sync_rings(struct radeon_device *rdev, 457254885Sdumbbell struct radeon_semaphore *semaphore, 458254885Sdumbbell int signaler, int waiter); 459254885Sdumbbellvoid radeon_semaphore_free(struct radeon_device *rdev, 460254885Sdumbbell struct radeon_semaphore **semaphore, 461254885Sdumbbell struct radeon_fence *fence); 462254885Sdumbbell 463254885Sdumbbell/* 464254885Sdumbbell * GART structures, functions & helpers 465254885Sdumbbell */ 466254885Sdumbbellstruct radeon_mc; 467254885Sdumbbell 468254885Sdumbbell#define RADEON_GPU_PAGE_SIZE 4096 469254885Sdumbbell#define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1) 470254885Sdumbbell#define RADEON_GPU_PAGE_SHIFT 12 471254885Sdumbbell#define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK) 472254885Sdumbbell 473254885Sdumbbellstruct radeon_gart { 474254885Sdumbbell drm_dma_handle_t *dmah; 475254885Sdumbbell dma_addr_t table_addr; 476254885Sdumbbell struct radeon_bo *robj; 477254885Sdumbbell void *ptr; 478254885Sdumbbell unsigned num_gpu_pages; 479254885Sdumbbell unsigned num_cpu_pages; 480254885Sdumbbell unsigned table_size; 481254885Sdumbbell vm_page_t *pages; 482254885Sdumbbell dma_addr_t *pages_addr; 483254885Sdumbbell bool ready; 484254885Sdumbbell}; 485254885Sdumbbell 486254885Sdumbbellint radeon_gart_table_ram_alloc(struct radeon_device *rdev); 487254885Sdumbbellvoid radeon_gart_table_ram_free(struct radeon_device *rdev); 488254885Sdumbbellint radeon_gart_table_vram_alloc(struct radeon_device *rdev); 489254885Sdumbbellvoid radeon_gart_table_vram_free(struct radeon_device *rdev); 490254885Sdumbbellint radeon_gart_table_vram_pin(struct radeon_device *rdev); 491254885Sdumbbellvoid radeon_gart_table_vram_unpin(struct radeon_device *rdev); 492254885Sdumbbellint radeon_gart_init(struct radeon_device *rdev); 493254885Sdumbbellvoid radeon_gart_fini(struct radeon_device *rdev); 494254885Sdumbbellvoid radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, 495254885Sdumbbell int pages); 496254885Sdumbbellint radeon_gart_bind(struct radeon_device *rdev, unsigned offset, 497254885Sdumbbell int pages, vm_page_t *pagelist, 498254885Sdumbbell dma_addr_t *dma_addr); 499254885Sdumbbellvoid radeon_gart_restore(struct radeon_device *rdev); 500254885Sdumbbell 501254885Sdumbbell 502254885Sdumbbell/* 503254885Sdumbbell * GPU MC structures, functions & helpers 504254885Sdumbbell */ 505254885Sdumbbellstruct radeon_mc { 506254885Sdumbbell resource_size_t aper_size; 507254885Sdumbbell resource_size_t aper_base; 508254885Sdumbbell resource_size_t agp_base; 509254885Sdumbbell /* for some chips with <= 32MB we need to lie 510254885Sdumbbell * about vram size near mc fb location */ 511254885Sdumbbell u64 mc_vram_size; 512254885Sdumbbell u64 visible_vram_size; 513254885Sdumbbell u64 gtt_size; 514254885Sdumbbell u64 gtt_start; 515254885Sdumbbell u64 gtt_end; 516254885Sdumbbell u64 vram_start; 517254885Sdumbbell u64 vram_end; 518254885Sdumbbell unsigned vram_width; 519254885Sdumbbell u64 real_vram_size; 520254885Sdumbbell int vram_mtrr; 521254885Sdumbbell bool vram_is_ddr; 522254885Sdumbbell bool igp_sideport_enabled; 523254885Sdumbbell u64 gtt_base_align; 524254885Sdumbbell}; 525254885Sdumbbell 526254885Sdumbbellbool radeon_combios_sideport_present(struct radeon_device *rdev); 527254885Sdumbbellbool radeon_atombios_sideport_present(struct radeon_device *rdev); 528254885Sdumbbell 529254885Sdumbbell/* 530254885Sdumbbell * GPU scratch registers structures, functions & helpers 531254885Sdumbbell */ 532254885Sdumbbellstruct radeon_scratch { 533254885Sdumbbell unsigned num_reg; 534254885Sdumbbell uint32_t reg_base; 535254885Sdumbbell bool free[32]; 536254885Sdumbbell uint32_t reg[32]; 537254885Sdumbbell}; 538254885Sdumbbell 539254885Sdumbbellint radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); 540254885Sdumbbellvoid radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); 541254885Sdumbbell 542254885Sdumbbell 543254885Sdumbbell/* 544254885Sdumbbell * IRQS. 545254885Sdumbbell */ 546254885Sdumbbell 547254885Sdumbbellstruct radeon_unpin_work { 548254885Sdumbbell struct task work; 549254885Sdumbbell struct radeon_device *rdev; 550254885Sdumbbell int crtc_id; 551254885Sdumbbell struct radeon_fence *fence; 552254885Sdumbbell struct drm_pending_vblank_event *event; 553254885Sdumbbell struct radeon_bo *old_rbo; 554254885Sdumbbell u64 new_crtc_base; 555254885Sdumbbell}; 556254885Sdumbbell 557254885Sdumbbellstruct r500_irq_stat_regs { 558254885Sdumbbell u32 disp_int; 559254885Sdumbbell u32 hdmi0_status; 560254885Sdumbbell}; 561254885Sdumbbell 562254885Sdumbbellstruct r600_irq_stat_regs { 563254885Sdumbbell u32 disp_int; 564254885Sdumbbell u32 disp_int_cont; 565254885Sdumbbell u32 disp_int_cont2; 566254885Sdumbbell u32 d1grph_int; 567254885Sdumbbell u32 d2grph_int; 568254885Sdumbbell u32 hdmi0_status; 569254885Sdumbbell u32 hdmi1_status; 570254885Sdumbbell}; 571254885Sdumbbell 572254885Sdumbbellstruct evergreen_irq_stat_regs { 573254885Sdumbbell u32 disp_int; 574254885Sdumbbell u32 disp_int_cont; 575254885Sdumbbell u32 disp_int_cont2; 576254885Sdumbbell u32 disp_int_cont3; 577254885Sdumbbell u32 disp_int_cont4; 578254885Sdumbbell u32 disp_int_cont5; 579254885Sdumbbell u32 d1grph_int; 580254885Sdumbbell u32 d2grph_int; 581254885Sdumbbell u32 d3grph_int; 582254885Sdumbbell u32 d4grph_int; 583254885Sdumbbell u32 d5grph_int; 584254885Sdumbbell u32 d6grph_int; 585254885Sdumbbell u32 afmt_status1; 586254885Sdumbbell u32 afmt_status2; 587254885Sdumbbell u32 afmt_status3; 588254885Sdumbbell u32 afmt_status4; 589254885Sdumbbell u32 afmt_status5; 590254885Sdumbbell u32 afmt_status6; 591254885Sdumbbell}; 592254885Sdumbbell 593254885Sdumbbellunion radeon_irq_stat_regs { 594254885Sdumbbell struct r500_irq_stat_regs r500; 595254885Sdumbbell struct r600_irq_stat_regs r600; 596254885Sdumbbell struct evergreen_irq_stat_regs evergreen; 597254885Sdumbbell}; 598254885Sdumbbell 599254885Sdumbbell#define RADEON_MAX_HPD_PINS 6 600254885Sdumbbell#define RADEON_MAX_CRTCS 6 601254885Sdumbbell#define RADEON_MAX_AFMT_BLOCKS 6 602254885Sdumbbell 603254885Sdumbbellstruct radeon_irq { 604254885Sdumbbell bool installed; 605254885Sdumbbell struct mtx lock; 606254885Sdumbbell atomic_t ring_int[RADEON_NUM_RINGS]; 607254885Sdumbbell bool crtc_vblank_int[RADEON_MAX_CRTCS]; 608254885Sdumbbell atomic_t pflip[RADEON_MAX_CRTCS]; 609254885Sdumbbell wait_queue_head_t vblank_queue; 610254885Sdumbbell bool hpd[RADEON_MAX_HPD_PINS]; 611254885Sdumbbell bool afmt[RADEON_MAX_AFMT_BLOCKS]; 612254885Sdumbbell union radeon_irq_stat_regs stat_regs; 613254885Sdumbbell}; 614254885Sdumbbell 615254885Sdumbbellint radeon_irq_kms_init(struct radeon_device *rdev); 616254885Sdumbbellvoid radeon_irq_kms_fini(struct radeon_device *rdev); 617254885Sdumbbellvoid radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring); 618254885Sdumbbellvoid radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring); 619254885Sdumbbellvoid radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc); 620254885Sdumbbellvoid radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc); 621254885Sdumbbellvoid radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block); 622254885Sdumbbellvoid radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block); 623254885Sdumbbellvoid radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask); 624254885Sdumbbellvoid radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask); 625254885Sdumbbell 626254885Sdumbbell/* 627254885Sdumbbell * CP & rings. 628254885Sdumbbell */ 629254885Sdumbbell 630254885Sdumbbellstruct radeon_ib { 631254885Sdumbbell struct radeon_sa_bo *sa_bo; 632254885Sdumbbell uint32_t length_dw; 633254885Sdumbbell uint64_t gpu_addr; 634254885Sdumbbell uint32_t *ptr; 635254885Sdumbbell int ring; 636254885Sdumbbell struct radeon_fence *fence; 637254885Sdumbbell struct radeon_vm *vm; 638254885Sdumbbell bool is_const_ib; 639254885Sdumbbell struct radeon_fence *sync_to[RADEON_NUM_RINGS]; 640254885Sdumbbell struct radeon_semaphore *semaphore; 641254885Sdumbbell}; 642254885Sdumbbell 643254885Sdumbbellstruct radeon_ring { 644254885Sdumbbell struct radeon_bo *ring_obj; 645254885Sdumbbell volatile uint32_t *ring; 646254885Sdumbbell unsigned rptr; 647254885Sdumbbell unsigned rptr_offs; 648254885Sdumbbell unsigned rptr_reg; 649254885Sdumbbell unsigned rptr_save_reg; 650254885Sdumbbell u64 next_rptr_gpu_addr; 651254885Sdumbbell volatile u32 *next_rptr_cpu_addr; 652254885Sdumbbell unsigned wptr; 653254885Sdumbbell unsigned wptr_old; 654254885Sdumbbell unsigned wptr_reg; 655254885Sdumbbell unsigned ring_size; 656254885Sdumbbell unsigned ring_free_dw; 657254885Sdumbbell int count_dw; 658254885Sdumbbell unsigned long last_activity; 659254885Sdumbbell unsigned last_rptr; 660254885Sdumbbell uint64_t gpu_addr; 661254885Sdumbbell uint32_t align_mask; 662254885Sdumbbell uint32_t ptr_mask; 663254885Sdumbbell bool ready; 664254885Sdumbbell u32 ptr_reg_shift; 665254885Sdumbbell u32 ptr_reg_mask; 666254885Sdumbbell u32 nop; 667254885Sdumbbell u32 idx; 668254885Sdumbbell u64 last_semaphore_signal_addr; 669254885Sdumbbell u64 last_semaphore_wait_addr; 670254885Sdumbbell}; 671254885Sdumbbell 672254885Sdumbbell/* 673254885Sdumbbell * VM 674254885Sdumbbell */ 675254885Sdumbbell 676254885Sdumbbell/* maximum number of VMIDs */ 677254885Sdumbbell#define RADEON_NUM_VM 16 678254885Sdumbbell 679254885Sdumbbell/* defines number of bits in page table versus page directory, 680254885Sdumbbell * a page is 4KB so we have 12 bits offset, 9 bits in the page 681254885Sdumbbell * table and the remaining 19 bits are in the page directory */ 682254885Sdumbbell#define RADEON_VM_BLOCK_SIZE 9 683254885Sdumbbell 684254885Sdumbbell/* number of entries in page table */ 685254885Sdumbbell#define RADEON_VM_PTE_COUNT (1 << RADEON_VM_BLOCK_SIZE) 686254885Sdumbbell 687254885Sdumbbellstruct radeon_vm { 688254885Sdumbbell struct list_head list; 689254885Sdumbbell struct list_head va; 690254885Sdumbbell unsigned id; 691254885Sdumbbell 692254885Sdumbbell /* contains the page directory */ 693254885Sdumbbell struct radeon_sa_bo *page_directory; 694254885Sdumbbell uint64_t pd_gpu_addr; 695254885Sdumbbell 696254885Sdumbbell /* array of page tables, one for each page directory entry */ 697254885Sdumbbell struct radeon_sa_bo **page_tables; 698254885Sdumbbell 699254885Sdumbbell struct sx mutex; 700254885Sdumbbell /* last fence for cs using this vm */ 701254885Sdumbbell struct radeon_fence *fence; 702254885Sdumbbell /* last flush or NULL if we still need to flush */ 703254885Sdumbbell struct radeon_fence *last_flush; 704254885Sdumbbell}; 705254885Sdumbbell 706254885Sdumbbellstruct radeon_vm_manager { 707254885Sdumbbell struct sx lock; 708254885Sdumbbell struct list_head lru_vm; 709254885Sdumbbell struct radeon_fence *active[RADEON_NUM_VM]; 710254885Sdumbbell struct radeon_sa_manager sa_manager; 711254885Sdumbbell uint32_t max_pfn; 712254885Sdumbbell /* number of VMIDs */ 713254885Sdumbbell unsigned nvm; 714254885Sdumbbell /* vram base address for page table entry */ 715254885Sdumbbell u64 vram_base_offset; 716254885Sdumbbell /* is vm enabled? */ 717254885Sdumbbell bool enabled; 718254885Sdumbbell}; 719254885Sdumbbell 720254885Sdumbbell/* 721254885Sdumbbell * file private structure 722254885Sdumbbell */ 723254885Sdumbbellstruct radeon_fpriv { 724254885Sdumbbell struct radeon_vm vm; 725254885Sdumbbell}; 726254885Sdumbbell 727254885Sdumbbell/* 728254885Sdumbbell * R6xx+ IH ring 729254885Sdumbbell */ 730254885Sdumbbellstruct r600_ih { 731254885Sdumbbell struct radeon_bo *ring_obj; 732254885Sdumbbell volatile uint32_t *ring; 733254885Sdumbbell unsigned rptr; 734254885Sdumbbell unsigned ring_size; 735254885Sdumbbell uint64_t gpu_addr; 736254885Sdumbbell uint32_t ptr_mask; 737254885Sdumbbell atomic_t lock; 738254885Sdumbbell bool enabled; 739254885Sdumbbell}; 740254885Sdumbbell 741254885Sdumbbellstruct r600_blit_cp_primitives { 742254885Sdumbbell void (*set_render_target)(struct radeon_device *rdev, int format, 743254885Sdumbbell int w, int h, u64 gpu_addr); 744254885Sdumbbell void (*cp_set_surface_sync)(struct radeon_device *rdev, 745254885Sdumbbell u32 sync_type, u32 size, 746254885Sdumbbell u64 mc_addr); 747254885Sdumbbell void (*set_shaders)(struct radeon_device *rdev); 748254885Sdumbbell void (*set_vtx_resource)(struct radeon_device *rdev, u64 gpu_addr); 749254885Sdumbbell void (*set_tex_resource)(struct radeon_device *rdev, 750254885Sdumbbell int format, int w, int h, int pitch, 751254885Sdumbbell u64 gpu_addr, u32 size); 752254885Sdumbbell void (*set_scissors)(struct radeon_device *rdev, int x1, int y1, 753254885Sdumbbell int x2, int y2); 754254885Sdumbbell void (*draw_auto)(struct radeon_device *rdev); 755254885Sdumbbell void (*set_default_state)(struct radeon_device *rdev); 756254885Sdumbbell}; 757254885Sdumbbell 758254885Sdumbbellstruct r600_blit { 759254885Sdumbbell struct radeon_bo *shader_obj; 760254885Sdumbbell struct r600_blit_cp_primitives primitives; 761254885Sdumbbell int max_dim; 762254885Sdumbbell int ring_size_common; 763254885Sdumbbell int ring_size_per_loop; 764254885Sdumbbell u64 shader_gpu_addr; 765254885Sdumbbell u32 vs_offset, ps_offset; 766254885Sdumbbell u32 state_offset; 767254885Sdumbbell u32 state_len; 768254885Sdumbbell}; 769254885Sdumbbell 770254885Sdumbbell/* 771254885Sdumbbell * SI RLC stuff 772254885Sdumbbell */ 773254885Sdumbbellstruct si_rlc { 774254885Sdumbbell /* for power gating */ 775254885Sdumbbell struct radeon_bo *save_restore_obj; 776254885Sdumbbell uint64_t save_restore_gpu_addr; 777254885Sdumbbell /* for clear state */ 778254885Sdumbbell struct radeon_bo *clear_state_obj; 779254885Sdumbbell uint64_t clear_state_gpu_addr; 780254885Sdumbbell}; 781254885Sdumbbell 782254885Sdumbbellint radeon_ib_get(struct radeon_device *rdev, int ring, 783254885Sdumbbell struct radeon_ib *ib, struct radeon_vm *vm, 784254885Sdumbbell unsigned size); 785254885Sdumbbellvoid radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib); 786254885Sdumbbellint radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib, 787254885Sdumbbell struct radeon_ib *const_ib); 788254885Sdumbbellint radeon_ib_pool_init(struct radeon_device *rdev); 789254885Sdumbbellvoid radeon_ib_pool_fini(struct radeon_device *rdev); 790254885Sdumbbellint radeon_ib_ring_tests(struct radeon_device *rdev); 791254885Sdumbbell/* Ring access between begin & end cannot sleep */ 792254885Sdumbbellbool radeon_ring_supports_scratch_reg(struct radeon_device *rdev, 793254885Sdumbbell struct radeon_ring *ring); 794254885Sdumbbellvoid radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp); 795254885Sdumbbellint radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); 796254885Sdumbbellint radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); 797254885Sdumbbellvoid radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp); 798254885Sdumbbellvoid radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp); 799254885Sdumbbellvoid radeon_ring_undo(struct radeon_ring *ring); 800254885Sdumbbellvoid radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp); 801254885Sdumbbellint radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); 802254885Sdumbbellvoid radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring); 803254885Sdumbbellvoid radeon_ring_lockup_update(struct radeon_ring *ring); 804254885Sdumbbellbool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 805254885Sdumbbellunsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring, 806254885Sdumbbell uint32_t **data); 807254885Sdumbbellint radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring, 808254885Sdumbbell unsigned size, uint32_t *data); 809254885Sdumbbellint radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size, 810254885Sdumbbell unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg, 811254885Sdumbbell u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop); 812254885Sdumbbellvoid radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp); 813254885Sdumbbell 814254885Sdumbbell 815254885Sdumbbell/* r600 async dma */ 816254885Sdumbbellvoid r600_dma_stop(struct radeon_device *rdev); 817254885Sdumbbellint r600_dma_resume(struct radeon_device *rdev); 818254885Sdumbbellvoid r600_dma_fini(struct radeon_device *rdev); 819254885Sdumbbell 820254885Sdumbbellvoid cayman_dma_stop(struct radeon_device *rdev); 821254885Sdumbbellint cayman_dma_resume(struct radeon_device *rdev); 822254885Sdumbbellvoid cayman_dma_fini(struct radeon_device *rdev); 823254885Sdumbbell 824254885Sdumbbell/* 825254885Sdumbbell * CS. 826254885Sdumbbell */ 827254885Sdumbbellstruct radeon_cs_reloc { 828254885Sdumbbell struct drm_gem_object *gobj; 829254885Sdumbbell struct radeon_bo *robj; 830254885Sdumbbell struct radeon_bo_list lobj; 831254885Sdumbbell uint32_t handle; 832254885Sdumbbell uint32_t flags; 833254885Sdumbbell}; 834254885Sdumbbell 835254885Sdumbbellstruct radeon_cs_chunk { 836254885Sdumbbell uint32_t chunk_id; 837254885Sdumbbell uint32_t length_dw; 838254885Sdumbbell int kpage_idx[2]; 839254885Sdumbbell uint32_t *kpage[2]; 840254885Sdumbbell uint32_t *kdata; 841254885Sdumbbell void __user *user_ptr; 842254885Sdumbbell int last_copied_page; 843254885Sdumbbell int last_page_index; 844254885Sdumbbell}; 845254885Sdumbbell 846254885Sdumbbellstruct radeon_cs_parser { 847254885Sdumbbell device_t dev; 848254885Sdumbbell struct radeon_device *rdev; 849254885Sdumbbell struct drm_file *filp; 850254885Sdumbbell /* chunks */ 851254885Sdumbbell unsigned nchunks; 852254885Sdumbbell struct radeon_cs_chunk *chunks; 853254885Sdumbbell uint64_t *chunks_array; 854254885Sdumbbell /* IB */ 855254885Sdumbbell unsigned idx; 856254885Sdumbbell /* relocations */ 857254885Sdumbbell unsigned nrelocs; 858254885Sdumbbell struct radeon_cs_reloc *relocs; 859254885Sdumbbell struct radeon_cs_reloc **relocs_ptr; 860254885Sdumbbell struct list_head validated; 861254885Sdumbbell unsigned dma_reloc_idx; 862254885Sdumbbell /* indices of various chunks */ 863254885Sdumbbell int chunk_ib_idx; 864254885Sdumbbell int chunk_relocs_idx; 865254885Sdumbbell int chunk_flags_idx; 866254885Sdumbbell int chunk_const_ib_idx; 867254885Sdumbbell struct radeon_ib ib; 868254885Sdumbbell struct radeon_ib const_ib; 869254885Sdumbbell void *track; 870254885Sdumbbell unsigned family; 871254885Sdumbbell int parser_error; 872254885Sdumbbell u32 cs_flags; 873254885Sdumbbell u32 ring; 874254885Sdumbbell s32 priority; 875254885Sdumbbell}; 876254885Sdumbbell 877254885Sdumbbellextern int radeon_cs_finish_pages(struct radeon_cs_parser *p); 878254885Sdumbbellextern u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx); 879254885Sdumbbell 880254885Sdumbbellstruct radeon_cs_packet { 881254885Sdumbbell unsigned idx; 882254885Sdumbbell unsigned type; 883254885Sdumbbell unsigned reg; 884254885Sdumbbell unsigned opcode; 885254885Sdumbbell int count; 886254885Sdumbbell unsigned one_reg_wr; 887254885Sdumbbell}; 888254885Sdumbbell 889254885Sdumbbelltypedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, 890254885Sdumbbell struct radeon_cs_packet *pkt, 891254885Sdumbbell unsigned idx, unsigned reg); 892254885Sdumbbelltypedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, 893254885Sdumbbell struct radeon_cs_packet *pkt); 894254885Sdumbbell 895254885Sdumbbell 896254885Sdumbbell/* 897254885Sdumbbell * AGP 898254885Sdumbbell */ 899254885Sdumbbellint radeon_agp_init(struct radeon_device *rdev); 900254885Sdumbbellvoid radeon_agp_resume(struct radeon_device *rdev); 901254885Sdumbbellvoid radeon_agp_suspend(struct radeon_device *rdev); 902254885Sdumbbellvoid radeon_agp_fini(struct radeon_device *rdev); 903254885Sdumbbell 904254885Sdumbbell 905254885Sdumbbell/* 906254885Sdumbbell * Writeback 907254885Sdumbbell */ 908254885Sdumbbellstruct radeon_wb { 909254885Sdumbbell struct radeon_bo *wb_obj; 910254885Sdumbbell volatile uint32_t *wb; 911254885Sdumbbell uint64_t gpu_addr; 912254885Sdumbbell bool enabled; 913254885Sdumbbell bool use_event; 914254885Sdumbbell}; 915254885Sdumbbell 916254885Sdumbbell#define RADEON_WB_SCRATCH_OFFSET 0 917254885Sdumbbell#define RADEON_WB_RING0_NEXT_RPTR 256 918254885Sdumbbell#define RADEON_WB_CP_RPTR_OFFSET 1024 919254885Sdumbbell#define RADEON_WB_CP1_RPTR_OFFSET 1280 920254885Sdumbbell#define RADEON_WB_CP2_RPTR_OFFSET 1536 921254885Sdumbbell#define R600_WB_DMA_RPTR_OFFSET 1792 922254885Sdumbbell#define R600_WB_IH_WPTR_OFFSET 2048 923254885Sdumbbell#define CAYMAN_WB_DMA1_RPTR_OFFSET 2304 924254885Sdumbbell#define R600_WB_EVENT_OFFSET 3072 925254885Sdumbbell 926254885Sdumbbell/** 927254885Sdumbbell * struct radeon_pm - power management datas 928254885Sdumbbell * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) 929254885Sdumbbell * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) 930254885Sdumbbell * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) 931254885Sdumbbell * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) 932254885Sdumbbell * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) 933254885Sdumbbell * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) 934254885Sdumbbell * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) 935254885Sdumbbell * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) 936254885Sdumbbell * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) 937254885Sdumbbell * @sclk: GPU clock Mhz (core bandwidth depends of this clock) 938254885Sdumbbell * @needed_bandwidth: current bandwidth needs 939254885Sdumbbell * 940254885Sdumbbell * It keeps track of various data needed to take powermanagement decision. 941254885Sdumbbell * Bandwidth need is used to determine minimun clock of the GPU and memory. 942254885Sdumbbell * Equation between gpu/memory clock and available bandwidth is hw dependent 943254885Sdumbbell * (type of memory, bus size, efficiency, ...) 944254885Sdumbbell */ 945254885Sdumbbell 946254885Sdumbbellenum radeon_pm_method { 947254885Sdumbbell PM_METHOD_PROFILE, 948254885Sdumbbell PM_METHOD_DYNPM, 949254885Sdumbbell}; 950254885Sdumbbell 951254885Sdumbbellenum radeon_dynpm_state { 952254885Sdumbbell DYNPM_STATE_DISABLED, 953254885Sdumbbell DYNPM_STATE_MINIMUM, 954254885Sdumbbell DYNPM_STATE_PAUSED, 955254885Sdumbbell DYNPM_STATE_ACTIVE, 956254885Sdumbbell DYNPM_STATE_SUSPENDED, 957254885Sdumbbell}; 958254885Sdumbbellenum radeon_dynpm_action { 959254885Sdumbbell DYNPM_ACTION_NONE, 960254885Sdumbbell DYNPM_ACTION_MINIMUM, 961254885Sdumbbell DYNPM_ACTION_DOWNCLOCK, 962254885Sdumbbell DYNPM_ACTION_UPCLOCK, 963254885Sdumbbell DYNPM_ACTION_DEFAULT 964254885Sdumbbell}; 965254885Sdumbbell 966254885Sdumbbellenum radeon_voltage_type { 967254885Sdumbbell VOLTAGE_NONE = 0, 968254885Sdumbbell VOLTAGE_GPIO, 969254885Sdumbbell VOLTAGE_VDDC, 970254885Sdumbbell VOLTAGE_SW 971254885Sdumbbell}; 972254885Sdumbbell 973254885Sdumbbellenum radeon_pm_state_type { 974254885Sdumbbell POWER_STATE_TYPE_DEFAULT, 975254885Sdumbbell POWER_STATE_TYPE_POWERSAVE, 976254885Sdumbbell POWER_STATE_TYPE_BATTERY, 977254885Sdumbbell POWER_STATE_TYPE_BALANCED, 978254885Sdumbbell POWER_STATE_TYPE_PERFORMANCE, 979254885Sdumbbell}; 980254885Sdumbbell 981254885Sdumbbellenum radeon_pm_profile_type { 982254885Sdumbbell PM_PROFILE_DEFAULT, 983254885Sdumbbell PM_PROFILE_AUTO, 984254885Sdumbbell PM_PROFILE_LOW, 985254885Sdumbbell PM_PROFILE_MID, 986254885Sdumbbell PM_PROFILE_HIGH, 987254885Sdumbbell}; 988254885Sdumbbell 989254885Sdumbbell#define PM_PROFILE_DEFAULT_IDX 0 990254885Sdumbbell#define PM_PROFILE_LOW_SH_IDX 1 991254885Sdumbbell#define PM_PROFILE_MID_SH_IDX 2 992254885Sdumbbell#define PM_PROFILE_HIGH_SH_IDX 3 993254885Sdumbbell#define PM_PROFILE_LOW_MH_IDX 4 994254885Sdumbbell#define PM_PROFILE_MID_MH_IDX 5 995254885Sdumbbell#define PM_PROFILE_HIGH_MH_IDX 6 996254885Sdumbbell#define PM_PROFILE_MAX 7 997254885Sdumbbell 998254885Sdumbbellstruct radeon_pm_profile { 999254885Sdumbbell int dpms_off_ps_idx; 1000254885Sdumbbell int dpms_on_ps_idx; 1001254885Sdumbbell int dpms_off_cm_idx; 1002254885Sdumbbell int dpms_on_cm_idx; 1003254885Sdumbbell}; 1004254885Sdumbbell 1005254885Sdumbbellenum radeon_int_thermal_type { 1006254885Sdumbbell THERMAL_TYPE_NONE, 1007254885Sdumbbell THERMAL_TYPE_RV6XX, 1008254885Sdumbbell THERMAL_TYPE_RV770, 1009254885Sdumbbell THERMAL_TYPE_EVERGREEN, 1010254885Sdumbbell THERMAL_TYPE_SUMO, 1011254885Sdumbbell THERMAL_TYPE_NI, 1012254885Sdumbbell THERMAL_TYPE_SI, 1013254885Sdumbbell}; 1014254885Sdumbbell 1015254885Sdumbbellstruct radeon_voltage { 1016254885Sdumbbell enum radeon_voltage_type type; 1017254885Sdumbbell /* gpio voltage */ 1018254885Sdumbbell struct radeon_gpio_rec gpio; 1019254885Sdumbbell u32 delay; /* delay in usec from voltage drop to sclk change */ 1020254885Sdumbbell bool active_high; /* voltage drop is active when bit is high */ 1021254885Sdumbbell /* VDDC voltage */ 1022254885Sdumbbell u8 vddc_id; /* index into vddc voltage table */ 1023254885Sdumbbell u8 vddci_id; /* index into vddci voltage table */ 1024254885Sdumbbell bool vddci_enabled; 1025254885Sdumbbell /* r6xx+ sw */ 1026254885Sdumbbell u16 voltage; 1027254885Sdumbbell /* evergreen+ vddci */ 1028254885Sdumbbell u16 vddci; 1029254885Sdumbbell}; 1030254885Sdumbbell 1031254885Sdumbbell/* clock mode flags */ 1032254885Sdumbbell#define RADEON_PM_MODE_NO_DISPLAY (1 << 0) 1033254885Sdumbbell 1034254885Sdumbbellstruct radeon_pm_clock_info { 1035254885Sdumbbell /* memory clock */ 1036254885Sdumbbell u32 mclk; 1037254885Sdumbbell /* engine clock */ 1038254885Sdumbbell u32 sclk; 1039254885Sdumbbell /* voltage info */ 1040254885Sdumbbell struct radeon_voltage voltage; 1041254885Sdumbbell /* standardized clock flags */ 1042254885Sdumbbell u32 flags; 1043254885Sdumbbell}; 1044254885Sdumbbell 1045254885Sdumbbell/* state flags */ 1046254885Sdumbbell#define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0) 1047254885Sdumbbell 1048254885Sdumbbellstruct radeon_power_state { 1049254885Sdumbbell enum radeon_pm_state_type type; 1050254885Sdumbbell struct radeon_pm_clock_info *clock_info; 1051254885Sdumbbell /* number of valid clock modes in this power state */ 1052254885Sdumbbell int num_clock_modes; 1053254885Sdumbbell struct radeon_pm_clock_info *default_clock_mode; 1054254885Sdumbbell /* standardized state flags */ 1055254885Sdumbbell u32 flags; 1056254885Sdumbbell u32 misc; /* vbios specific flags */ 1057254885Sdumbbell u32 misc2; /* vbios specific flags */ 1058254885Sdumbbell int pcie_lanes; /* pcie lanes */ 1059254885Sdumbbell}; 1060254885Sdumbbell 1061254885Sdumbbell/* 1062254885Sdumbbell * Some modes are overclocked by very low value, accept them 1063254885Sdumbbell */ 1064254885Sdumbbell#define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */ 1065254885Sdumbbell 1066254885Sdumbbellstruct radeon_pm { 1067254885Sdumbbell struct sx mutex; 1068254885Sdumbbell /* write locked while reprogramming mclk */ 1069254885Sdumbbell struct sx mclk_lock; 1070254885Sdumbbell u32 active_crtcs; 1071254885Sdumbbell int active_crtc_count; 1072254885Sdumbbell int req_vblank; 1073254885Sdumbbell bool vblank_sync; 1074254885Sdumbbell fixed20_12 max_bandwidth; 1075254885Sdumbbell fixed20_12 igp_sideport_mclk; 1076254885Sdumbbell fixed20_12 igp_system_mclk; 1077254885Sdumbbell fixed20_12 igp_ht_link_clk; 1078254885Sdumbbell fixed20_12 igp_ht_link_width; 1079254885Sdumbbell fixed20_12 k8_bandwidth; 1080254885Sdumbbell fixed20_12 sideport_bandwidth; 1081254885Sdumbbell fixed20_12 ht_bandwidth; 1082254885Sdumbbell fixed20_12 core_bandwidth; 1083254885Sdumbbell fixed20_12 sclk; 1084254885Sdumbbell fixed20_12 mclk; 1085254885Sdumbbell fixed20_12 needed_bandwidth; 1086254885Sdumbbell struct radeon_power_state *power_state; 1087254885Sdumbbell /* number of valid power states */ 1088254885Sdumbbell int num_power_states; 1089254885Sdumbbell int current_power_state_index; 1090254885Sdumbbell int current_clock_mode_index; 1091254885Sdumbbell int requested_power_state_index; 1092254885Sdumbbell int requested_clock_mode_index; 1093254885Sdumbbell int default_power_state_index; 1094254885Sdumbbell u32 current_sclk; 1095254885Sdumbbell u32 current_mclk; 1096254885Sdumbbell u16 current_vddc; 1097254885Sdumbbell u16 current_vddci; 1098254885Sdumbbell u32 default_sclk; 1099254885Sdumbbell u32 default_mclk; 1100254885Sdumbbell u16 default_vddc; 1101254885Sdumbbell u16 default_vddci; 1102254885Sdumbbell struct radeon_i2c_chan *i2c_bus; 1103254885Sdumbbell /* selected pm method */ 1104254885Sdumbbell enum radeon_pm_method pm_method; 1105254885Sdumbbell /* dynpm power management */ 1106254885Sdumbbell#ifdef DUMBBELL_WIP 1107254885Sdumbbell struct delayed_work dynpm_idle_work; 1108254885Sdumbbell#endif /* DUMBBELL_WIP */ 1109254885Sdumbbell enum radeon_dynpm_state dynpm_state; 1110254885Sdumbbell enum radeon_dynpm_action dynpm_planned_action; 1111254885Sdumbbell unsigned long dynpm_action_timeout; 1112254885Sdumbbell bool dynpm_can_upclock; 1113254885Sdumbbell bool dynpm_can_downclock; 1114254885Sdumbbell /* profile-based power management */ 1115254885Sdumbbell enum radeon_pm_profile_type profile; 1116254885Sdumbbell int profile_index; 1117254885Sdumbbell struct radeon_pm_profile profiles[PM_PROFILE_MAX]; 1118254885Sdumbbell /* internal thermal controller on rv6xx+ */ 1119254885Sdumbbell enum radeon_int_thermal_type int_thermal_type; 1120254885Sdumbbell#ifdef DUMBBELL_WIP 1121254885Sdumbbell struct device *int_hwmon_dev; 1122254885Sdumbbell#endif /* DUMBBELL_WIP */ 1123254885Sdumbbell}; 1124254885Sdumbbell 1125254885Sdumbbellint radeon_pm_get_type_index(struct radeon_device *rdev, 1126254885Sdumbbell enum radeon_pm_state_type ps_type, 1127254885Sdumbbell int instance); 1128254885Sdumbbell 1129254885Sdumbbellstruct r600_audio { 1130254885Sdumbbell int channels; 1131254885Sdumbbell int rate; 1132254885Sdumbbell int bits_per_sample; 1133254885Sdumbbell u8 status_bits; 1134254885Sdumbbell u8 category_code; 1135254885Sdumbbell}; 1136254885Sdumbbell 1137254885Sdumbbell/* 1138254885Sdumbbell * Benchmarking 1139254885Sdumbbell */ 1140254885Sdumbbellvoid radeon_benchmark(struct radeon_device *rdev, int test_number); 1141254885Sdumbbell 1142254885Sdumbbell 1143254885Sdumbbell/* 1144254885Sdumbbell * Testing 1145254885Sdumbbell */ 1146254885Sdumbbellvoid radeon_test_moves(struct radeon_device *rdev); 1147254885Sdumbbellvoid radeon_test_ring_sync(struct radeon_device *rdev, 1148254885Sdumbbell struct radeon_ring *cpA, 1149254885Sdumbbell struct radeon_ring *cpB); 1150254885Sdumbbellvoid radeon_test_syncing(struct radeon_device *rdev); 1151254885Sdumbbell 1152254885Sdumbbell 1153254885Sdumbbell/* 1154254885Sdumbbell * Debugfs 1155254885Sdumbbell */ 1156254885Sdumbbellstruct radeon_debugfs { 1157254885Sdumbbell struct drm_info_list *files; 1158254885Sdumbbell unsigned num_files; 1159254885Sdumbbell}; 1160254885Sdumbbell 1161254885Sdumbbellint radeon_debugfs_add_files(struct radeon_device *rdev, 1162254885Sdumbbell struct drm_info_list *files, 1163254885Sdumbbell unsigned nfiles); 1164254885Sdumbbellint radeon_debugfs_fence_init(struct radeon_device *rdev); 1165254885Sdumbbell 1166254885Sdumbbell 1167254885Sdumbbell/* 1168254885Sdumbbell * ASIC specific functions. 1169254885Sdumbbell */ 1170254885Sdumbbellstruct radeon_asic { 1171254885Sdumbbell int (*init)(struct radeon_device *rdev); 1172254885Sdumbbell void (*fini)(struct radeon_device *rdev); 1173254885Sdumbbell int (*resume)(struct radeon_device *rdev); 1174254885Sdumbbell int (*suspend)(struct radeon_device *rdev); 1175254885Sdumbbell void (*vga_set_state)(struct radeon_device *rdev, bool state); 1176254885Sdumbbell int (*asic_reset)(struct radeon_device *rdev); 1177254885Sdumbbell /* ioctl hw specific callback. Some hw might want to perform special 1178254885Sdumbbell * operation on specific ioctl. For instance on wait idle some hw 1179254885Sdumbbell * might want to perform and HDP flush through MMIO as it seems that 1180254885Sdumbbell * some R6XX/R7XX hw doesn't take HDP flush into account if programmed 1181254885Sdumbbell * through ring. 1182254885Sdumbbell */ 1183254885Sdumbbell void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo); 1184254885Sdumbbell /* check if 3D engine is idle */ 1185254885Sdumbbell bool (*gui_idle)(struct radeon_device *rdev); 1186254885Sdumbbell /* wait for mc_idle */ 1187254885Sdumbbell int (*mc_wait_for_idle)(struct radeon_device *rdev); 1188254885Sdumbbell /* gart */ 1189254885Sdumbbell struct { 1190254885Sdumbbell void (*tlb_flush)(struct radeon_device *rdev); 1191254885Sdumbbell int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr); 1192254885Sdumbbell } gart; 1193254885Sdumbbell struct { 1194254885Sdumbbell int (*init)(struct radeon_device *rdev); 1195254885Sdumbbell void (*fini)(struct radeon_device *rdev); 1196254885Sdumbbell 1197254885Sdumbbell u32 pt_ring_index; 1198254885Sdumbbell void (*set_page)(struct radeon_device *rdev, uint64_t pe, 1199254885Sdumbbell uint64_t addr, unsigned count, 1200254885Sdumbbell uint32_t incr, uint32_t flags); 1201254885Sdumbbell } vm; 1202254885Sdumbbell /* ring specific callbacks */ 1203254885Sdumbbell struct { 1204254885Sdumbbell void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); 1205254885Sdumbbell int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib); 1206254885Sdumbbell void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence); 1207254885Sdumbbell void (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp, 1208254885Sdumbbell struct radeon_semaphore *semaphore, bool emit_wait); 1209254885Sdumbbell int (*cs_parse)(struct radeon_cs_parser *p); 1210254885Sdumbbell void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp); 1211254885Sdumbbell int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp); 1212254885Sdumbbell int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp); 1213254885Sdumbbell bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp); 1214254885Sdumbbell void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); 1215254885Sdumbbell } ring[RADEON_NUM_RINGS]; 1216254885Sdumbbell /* irqs */ 1217254885Sdumbbell struct { 1218254885Sdumbbell int (*set)(struct radeon_device *rdev); 1219254885Sdumbbell irqreturn_t (*process)(struct radeon_device *rdev); 1220254885Sdumbbell } irq; 1221254885Sdumbbell /* displays */ 1222254885Sdumbbell struct { 1223254885Sdumbbell /* display watermarks */ 1224254885Sdumbbell void (*bandwidth_update)(struct radeon_device *rdev); 1225254885Sdumbbell /* get frame count */ 1226254885Sdumbbell u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); 1227254885Sdumbbell /* wait for vblank */ 1228254885Sdumbbell void (*wait_for_vblank)(struct radeon_device *rdev, int crtc); 1229254885Sdumbbell /* set backlight level */ 1230254885Sdumbbell void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level); 1231254885Sdumbbell /* get backlight level */ 1232254885Sdumbbell u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder); 1233254885Sdumbbell } display; 1234254885Sdumbbell /* copy functions for bo handling */ 1235254885Sdumbbell struct { 1236254885Sdumbbell int (*blit)(struct radeon_device *rdev, 1237254885Sdumbbell uint64_t src_offset, 1238254885Sdumbbell uint64_t dst_offset, 1239254885Sdumbbell unsigned num_gpu_pages, 1240254885Sdumbbell struct radeon_fence **fence); 1241254885Sdumbbell u32 blit_ring_index; 1242254885Sdumbbell int (*dma)(struct radeon_device *rdev, 1243254885Sdumbbell uint64_t src_offset, 1244254885Sdumbbell uint64_t dst_offset, 1245254885Sdumbbell unsigned num_gpu_pages, 1246254885Sdumbbell struct radeon_fence **fence); 1247254885Sdumbbell u32 dma_ring_index; 1248254885Sdumbbell /* method used for bo copy */ 1249254885Sdumbbell int (*copy)(struct radeon_device *rdev, 1250254885Sdumbbell uint64_t src_offset, 1251254885Sdumbbell uint64_t dst_offset, 1252254885Sdumbbell unsigned num_gpu_pages, 1253254885Sdumbbell struct radeon_fence **fence); 1254254885Sdumbbell /* ring used for bo copies */ 1255254885Sdumbbell u32 copy_ring_index; 1256254885Sdumbbell } copy; 1257254885Sdumbbell /* surfaces */ 1258254885Sdumbbell struct { 1259254885Sdumbbell int (*set_reg)(struct radeon_device *rdev, int reg, 1260254885Sdumbbell uint32_t tiling_flags, uint32_t pitch, 1261254885Sdumbbell uint32_t offset, uint32_t obj_size); 1262254885Sdumbbell void (*clear_reg)(struct radeon_device *rdev, int reg); 1263254885Sdumbbell } surface; 1264254885Sdumbbell /* hotplug detect */ 1265254885Sdumbbell struct { 1266254885Sdumbbell void (*init)(struct radeon_device *rdev); 1267254885Sdumbbell void (*fini)(struct radeon_device *rdev); 1268254885Sdumbbell bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 1269254885Sdumbbell void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 1270254885Sdumbbell } hpd; 1271254885Sdumbbell /* power management */ 1272254885Sdumbbell struct { 1273254885Sdumbbell void (*misc)(struct radeon_device *rdev); 1274254885Sdumbbell void (*prepare)(struct radeon_device *rdev); 1275254885Sdumbbell void (*finish)(struct radeon_device *rdev); 1276254885Sdumbbell void (*init_profile)(struct radeon_device *rdev); 1277254885Sdumbbell void (*get_dynpm_state)(struct radeon_device *rdev); 1278254885Sdumbbell uint32_t (*get_engine_clock)(struct radeon_device *rdev); 1279254885Sdumbbell void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); 1280254885Sdumbbell uint32_t (*get_memory_clock)(struct radeon_device *rdev); 1281254885Sdumbbell void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); 1282254885Sdumbbell int (*get_pcie_lanes)(struct radeon_device *rdev); 1283254885Sdumbbell void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); 1284254885Sdumbbell void (*set_clock_gating)(struct radeon_device *rdev, int enable); 1285254885Sdumbbell } pm; 1286254885Sdumbbell /* pageflipping */ 1287254885Sdumbbell struct { 1288254885Sdumbbell void (*pre_page_flip)(struct radeon_device *rdev, int crtc); 1289254885Sdumbbell u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base); 1290254885Sdumbbell void (*post_page_flip)(struct radeon_device *rdev, int crtc); 1291254885Sdumbbell } pflip; 1292254885Sdumbbell}; 1293254885Sdumbbell 1294254885Sdumbbell/* 1295254885Sdumbbell * Asic structures 1296254885Sdumbbell */ 1297254885Sdumbbellstruct r100_asic { 1298254885Sdumbbell const unsigned *reg_safe_bm; 1299254885Sdumbbell unsigned reg_safe_bm_size; 1300254885Sdumbbell u32 hdp_cntl; 1301254885Sdumbbell}; 1302254885Sdumbbell 1303254885Sdumbbellstruct r300_asic { 1304254885Sdumbbell const unsigned *reg_safe_bm; 1305254885Sdumbbell unsigned reg_safe_bm_size; 1306254885Sdumbbell u32 resync_scratch; 1307254885Sdumbbell u32 hdp_cntl; 1308254885Sdumbbell}; 1309254885Sdumbbell 1310254885Sdumbbellstruct r600_asic { 1311254885Sdumbbell unsigned max_pipes; 1312254885Sdumbbell unsigned max_tile_pipes; 1313254885Sdumbbell unsigned max_simds; 1314254885Sdumbbell unsigned max_backends; 1315254885Sdumbbell unsigned max_gprs; 1316254885Sdumbbell unsigned max_threads; 1317254885Sdumbbell unsigned max_stack_entries; 1318254885Sdumbbell unsigned max_hw_contexts; 1319254885Sdumbbell unsigned max_gs_threads; 1320254885Sdumbbell unsigned sx_max_export_size; 1321254885Sdumbbell unsigned sx_max_export_pos_size; 1322254885Sdumbbell unsigned sx_max_export_smx_size; 1323254885Sdumbbell unsigned sq_num_cf_insts; 1324254885Sdumbbell unsigned tiling_nbanks; 1325254885Sdumbbell unsigned tiling_npipes; 1326254885Sdumbbell unsigned tiling_group_size; 1327254885Sdumbbell unsigned tile_config; 1328254885Sdumbbell unsigned backend_map; 1329254885Sdumbbell}; 1330254885Sdumbbell 1331254885Sdumbbellstruct rv770_asic { 1332254885Sdumbbell unsigned max_pipes; 1333254885Sdumbbell unsigned max_tile_pipes; 1334254885Sdumbbell unsigned max_simds; 1335254885Sdumbbell unsigned max_backends; 1336254885Sdumbbell unsigned max_gprs; 1337254885Sdumbbell unsigned max_threads; 1338254885Sdumbbell unsigned max_stack_entries; 1339254885Sdumbbell unsigned max_hw_contexts; 1340254885Sdumbbell unsigned max_gs_threads; 1341254885Sdumbbell unsigned sx_max_export_size; 1342254885Sdumbbell unsigned sx_max_export_pos_size; 1343254885Sdumbbell unsigned sx_max_export_smx_size; 1344254885Sdumbbell unsigned sq_num_cf_insts; 1345254885Sdumbbell unsigned sx_num_of_sets; 1346254885Sdumbbell unsigned sc_prim_fifo_size; 1347254885Sdumbbell unsigned sc_hiz_tile_fifo_size; 1348254885Sdumbbell unsigned sc_earlyz_tile_fifo_fize; 1349254885Sdumbbell unsigned tiling_nbanks; 1350254885Sdumbbell unsigned tiling_npipes; 1351254885Sdumbbell unsigned tiling_group_size; 1352254885Sdumbbell unsigned tile_config; 1353254885Sdumbbell unsigned backend_map; 1354254885Sdumbbell}; 1355254885Sdumbbell 1356254885Sdumbbellstruct evergreen_asic { 1357254885Sdumbbell unsigned num_ses; 1358254885Sdumbbell unsigned max_pipes; 1359254885Sdumbbell unsigned max_tile_pipes; 1360254885Sdumbbell unsigned max_simds; 1361254885Sdumbbell unsigned max_backends; 1362254885Sdumbbell unsigned max_gprs; 1363254885Sdumbbell unsigned max_threads; 1364254885Sdumbbell unsigned max_stack_entries; 1365254885Sdumbbell unsigned max_hw_contexts; 1366254885Sdumbbell unsigned max_gs_threads; 1367254885Sdumbbell unsigned sx_max_export_size; 1368254885Sdumbbell unsigned sx_max_export_pos_size; 1369254885Sdumbbell unsigned sx_max_export_smx_size; 1370254885Sdumbbell unsigned sq_num_cf_insts; 1371254885Sdumbbell unsigned sx_num_of_sets; 1372254885Sdumbbell unsigned sc_prim_fifo_size; 1373254885Sdumbbell unsigned sc_hiz_tile_fifo_size; 1374254885Sdumbbell unsigned sc_earlyz_tile_fifo_size; 1375254885Sdumbbell unsigned tiling_nbanks; 1376254885Sdumbbell unsigned tiling_npipes; 1377254885Sdumbbell unsigned tiling_group_size; 1378254885Sdumbbell unsigned tile_config; 1379254885Sdumbbell unsigned backend_map; 1380254885Sdumbbell}; 1381254885Sdumbbell 1382254885Sdumbbellstruct cayman_asic { 1383254885Sdumbbell unsigned max_shader_engines; 1384254885Sdumbbell unsigned max_pipes_per_simd; 1385254885Sdumbbell unsigned max_tile_pipes; 1386254885Sdumbbell unsigned max_simds_per_se; 1387254885Sdumbbell unsigned max_backends_per_se; 1388254885Sdumbbell unsigned max_texture_channel_caches; 1389254885Sdumbbell unsigned max_gprs; 1390254885Sdumbbell unsigned max_threads; 1391254885Sdumbbell unsigned max_gs_threads; 1392254885Sdumbbell unsigned max_stack_entries; 1393254885Sdumbbell unsigned sx_num_of_sets; 1394254885Sdumbbell unsigned sx_max_export_size; 1395254885Sdumbbell unsigned sx_max_export_pos_size; 1396254885Sdumbbell unsigned sx_max_export_smx_size; 1397254885Sdumbbell unsigned max_hw_contexts; 1398254885Sdumbbell unsigned sq_num_cf_insts; 1399254885Sdumbbell unsigned sc_prim_fifo_size; 1400254885Sdumbbell unsigned sc_hiz_tile_fifo_size; 1401254885Sdumbbell unsigned sc_earlyz_tile_fifo_size; 1402254885Sdumbbell 1403254885Sdumbbell unsigned num_shader_engines; 1404254885Sdumbbell unsigned num_shader_pipes_per_simd; 1405254885Sdumbbell unsigned num_tile_pipes; 1406254885Sdumbbell unsigned num_simds_per_se; 1407254885Sdumbbell unsigned num_backends_per_se; 1408254885Sdumbbell unsigned backend_disable_mask_per_asic; 1409254885Sdumbbell unsigned backend_map; 1410254885Sdumbbell unsigned num_texture_channel_caches; 1411254885Sdumbbell unsigned mem_max_burst_length_bytes; 1412254885Sdumbbell unsigned mem_row_size_in_kb; 1413254885Sdumbbell unsigned shader_engine_tile_size; 1414254885Sdumbbell unsigned num_gpus; 1415254885Sdumbbell unsigned multi_gpu_tile_size; 1416254885Sdumbbell 1417254885Sdumbbell unsigned tile_config; 1418254885Sdumbbell}; 1419254885Sdumbbell 1420254885Sdumbbellstruct si_asic { 1421254885Sdumbbell unsigned max_shader_engines; 1422254885Sdumbbell unsigned max_tile_pipes; 1423254885Sdumbbell unsigned max_cu_per_sh; 1424254885Sdumbbell unsigned max_sh_per_se; 1425254885Sdumbbell unsigned max_backends_per_se; 1426254885Sdumbbell unsigned max_texture_channel_caches; 1427254885Sdumbbell unsigned max_gprs; 1428254885Sdumbbell unsigned max_gs_threads; 1429254885Sdumbbell unsigned max_hw_contexts; 1430254885Sdumbbell unsigned sc_prim_fifo_size_frontend; 1431254885Sdumbbell unsigned sc_prim_fifo_size_backend; 1432254885Sdumbbell unsigned sc_hiz_tile_fifo_size; 1433254885Sdumbbell unsigned sc_earlyz_tile_fifo_size; 1434254885Sdumbbell 1435254885Sdumbbell unsigned num_tile_pipes; 1436254885Sdumbbell unsigned num_backends_per_se; 1437254885Sdumbbell unsigned backend_disable_mask_per_asic; 1438254885Sdumbbell unsigned backend_map; 1439254885Sdumbbell unsigned num_texture_channel_caches; 1440254885Sdumbbell unsigned mem_max_burst_length_bytes; 1441254885Sdumbbell unsigned mem_row_size_in_kb; 1442254885Sdumbbell unsigned shader_engine_tile_size; 1443254885Sdumbbell unsigned num_gpus; 1444254885Sdumbbell unsigned multi_gpu_tile_size; 1445254885Sdumbbell 1446254885Sdumbbell unsigned tile_config; 1447254885Sdumbbell}; 1448254885Sdumbbell 1449254885Sdumbbellunion radeon_asic_config { 1450254885Sdumbbell struct r300_asic r300; 1451254885Sdumbbell struct r100_asic r100; 1452254885Sdumbbell struct r600_asic r600; 1453254885Sdumbbell struct rv770_asic rv770; 1454254885Sdumbbell struct evergreen_asic evergreen; 1455254885Sdumbbell struct cayman_asic cayman; 1456254885Sdumbbell struct si_asic si; 1457254885Sdumbbell}; 1458254885Sdumbbell 1459254885Sdumbbell/* 1460254885Sdumbbell * asic initizalization from radeon_asic.c 1461254885Sdumbbell */ 1462254885Sdumbbellint radeon_asic_init(struct radeon_device *rdev); 1463254885Sdumbbell 1464254885Sdumbbell 1465254885Sdumbbell/* 1466254885Sdumbbell * IOCTL. 1467254885Sdumbbell */ 1468254885Sdumbbellint radeon_gem_info_ioctl(struct drm_device *dev, void *data, 1469254885Sdumbbell struct drm_file *filp); 1470254885Sdumbbellint radeon_gem_create_ioctl(struct drm_device *dev, void *data, 1471254885Sdumbbell struct drm_file *filp); 1472254885Sdumbbellint radeon_gem_pin_ioctl(struct drm_device *dev, void *data, 1473254885Sdumbbell struct drm_file *file_priv); 1474254885Sdumbbellint radeon_gem_unpin_ioctl(struct drm_device *dev, void *data, 1475254885Sdumbbell struct drm_file *file_priv); 1476254885Sdumbbellint radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data, 1477254885Sdumbbell struct drm_file *file_priv); 1478254885Sdumbbellint radeon_gem_pread_ioctl(struct drm_device *dev, void *data, 1479254885Sdumbbell struct drm_file *file_priv); 1480254885Sdumbbellint radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data, 1481254885Sdumbbell struct drm_file *filp); 1482254885Sdumbbellint radeon_gem_mmap_ioctl(struct drm_device *dev, void *data, 1483254885Sdumbbell struct drm_file *filp); 1484254885Sdumbbellint radeon_gem_busy_ioctl(struct drm_device *dev, void *data, 1485254885Sdumbbell struct drm_file *filp); 1486254885Sdumbbellint radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 1487254885Sdumbbell struct drm_file *filp); 1488254885Sdumbbellint radeon_gem_va_ioctl(struct drm_device *dev, void *data, 1489254885Sdumbbell struct drm_file *filp); 1490254885Sdumbbellint radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 1491254885Sdumbbellint radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data, 1492254885Sdumbbell struct drm_file *filp); 1493254885Sdumbbellint radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data, 1494254885Sdumbbell struct drm_file *filp); 1495254885Sdumbbell 1496254885Sdumbbell/* VRAM scratch page for HDP bug, default vram page */ 1497254885Sdumbbellstruct r600_vram_scratch { 1498254885Sdumbbell struct radeon_bo *robj; 1499254885Sdumbbell volatile uint32_t *ptr; 1500254885Sdumbbell u64 gpu_addr; 1501254885Sdumbbell}; 1502254885Sdumbbell 1503254885Sdumbbell/* 1504254885Sdumbbell * ACPI 1505254885Sdumbbell */ 1506254885Sdumbbellstruct radeon_atif_notification_cfg { 1507254885Sdumbbell bool enabled; 1508254885Sdumbbell int command_code; 1509254885Sdumbbell}; 1510254885Sdumbbell 1511254885Sdumbbellstruct radeon_atif_notifications { 1512254885Sdumbbell bool display_switch; 1513254885Sdumbbell bool expansion_mode_change; 1514254885Sdumbbell bool thermal_state; 1515254885Sdumbbell bool forced_power_state; 1516254885Sdumbbell bool system_power_state; 1517254885Sdumbbell bool display_conf_change; 1518254885Sdumbbell bool px_gfx_switch; 1519254885Sdumbbell bool brightness_change; 1520254885Sdumbbell bool dgpu_display_event; 1521254885Sdumbbell}; 1522254885Sdumbbell 1523254885Sdumbbellstruct radeon_atif_functions { 1524254885Sdumbbell bool system_params; 1525254885Sdumbbell bool sbios_requests; 1526254885Sdumbbell bool select_active_disp; 1527254885Sdumbbell bool lid_state; 1528254885Sdumbbell bool get_tv_standard; 1529254885Sdumbbell bool set_tv_standard; 1530254885Sdumbbell bool get_panel_expansion_mode; 1531254885Sdumbbell bool set_panel_expansion_mode; 1532254885Sdumbbell bool temperature_change; 1533254885Sdumbbell bool graphics_device_types; 1534254885Sdumbbell}; 1535254885Sdumbbell 1536254885Sdumbbellstruct radeon_atif { 1537254885Sdumbbell struct radeon_atif_notifications notifications; 1538254885Sdumbbell struct radeon_atif_functions functions; 1539254885Sdumbbell struct radeon_atif_notification_cfg notification_cfg; 1540254885Sdumbbell struct radeon_encoder *encoder_for_bl; 1541254885Sdumbbell}; 1542254885Sdumbbell 1543254885Sdumbbellstruct radeon_atcs_functions { 1544254885Sdumbbell bool get_ext_state; 1545254885Sdumbbell bool pcie_perf_req; 1546254885Sdumbbell bool pcie_dev_rdy; 1547254885Sdumbbell bool pcie_bus_width; 1548254885Sdumbbell}; 1549254885Sdumbbell 1550254885Sdumbbellstruct radeon_atcs { 1551254885Sdumbbell struct radeon_atcs_functions functions; 1552254885Sdumbbell}; 1553254885Sdumbbell 1554254885Sdumbbell/* 1555254885Sdumbbell * Core structure, functions and helpers. 1556254885Sdumbbell */ 1557254885Sdumbbelltypedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); 1558254885Sdumbbelltypedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); 1559254885Sdumbbell 1560254885Sdumbbellstruct radeon_device { 1561254885Sdumbbell device_t dev; 1562254885Sdumbbell struct drm_device *ddev; 1563254885Sdumbbell struct sx exclusive_lock; 1564254885Sdumbbell /* ASIC */ 1565254885Sdumbbell union radeon_asic_config config; 1566254885Sdumbbell enum radeon_family family; 1567254885Sdumbbell unsigned long flags; 1568254885Sdumbbell int usec_timeout; 1569254885Sdumbbell enum radeon_pll_errata pll_errata; 1570254885Sdumbbell int num_gb_pipes; 1571254885Sdumbbell int num_z_pipes; 1572254885Sdumbbell int disp_priority; 1573254885Sdumbbell /* BIOS */ 1574254885Sdumbbell uint8_t *bios; 1575254885Sdumbbell bool is_atom_bios; 1576254885Sdumbbell uint16_t bios_header_start; 1577254885Sdumbbell struct radeon_bo *stollen_vga_memory; 1578254885Sdumbbell /* Register mmio */ 1579254885Sdumbbell resource_size_t rmmio_base; 1580254885Sdumbbell resource_size_t rmmio_size; 1581254885Sdumbbell /* protects concurrent MM_INDEX/DATA based register access */ 1582254885Sdumbbell struct mtx mmio_idx_lock; 1583254885Sdumbbell int rmmio_rid; 1584254885Sdumbbell struct resource *rmmio; 1585254885Sdumbbell radeon_rreg_t mc_rreg; 1586254885Sdumbbell radeon_wreg_t mc_wreg; 1587254885Sdumbbell radeon_rreg_t pll_rreg; 1588254885Sdumbbell radeon_wreg_t pll_wreg; 1589254885Sdumbbell uint32_t pcie_reg_mask; 1590254885Sdumbbell radeon_rreg_t pciep_rreg; 1591254885Sdumbbell radeon_wreg_t pciep_wreg; 1592254885Sdumbbell /* io port */ 1593254885Sdumbbell int rio_rid; 1594254885Sdumbbell struct resource *rio_mem; 1595254885Sdumbbell resource_size_t rio_mem_size; 1596254885Sdumbbell struct radeon_clock clock; 1597254885Sdumbbell struct radeon_mc mc; 1598254885Sdumbbell struct radeon_gart gart; 1599254885Sdumbbell struct radeon_mode_info mode_info; 1600254885Sdumbbell struct radeon_scratch scratch; 1601254885Sdumbbell struct radeon_mman mman; 1602254885Sdumbbell struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS]; 1603254885Sdumbbell struct cv fence_queue; 1604254885Sdumbbell struct mtx fence_queue_mtx; 1605254885Sdumbbell struct sx ring_lock; 1606254885Sdumbbell struct radeon_ring ring[RADEON_NUM_RINGS]; 1607254885Sdumbbell bool ib_pool_ready; 1608254885Sdumbbell struct radeon_sa_manager ring_tmp_bo; 1609254885Sdumbbell struct radeon_irq irq; 1610254885Sdumbbell struct radeon_asic *asic; 1611254885Sdumbbell struct radeon_gem gem; 1612254885Sdumbbell struct radeon_pm pm; 1613254885Sdumbbell uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; 1614254885Sdumbbell struct radeon_wb wb; 1615254885Sdumbbell struct radeon_dummy_page dummy_page; 1616254885Sdumbbell bool shutdown; 1617254885Sdumbbell bool suspend; 1618254885Sdumbbell bool need_dma32; 1619254885Sdumbbell bool accel_working; 1620254885Sdumbbell bool fictitious_range_registered; 1621254885Sdumbbell struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; 1622254885Sdumbbell const struct firmware *me_fw; /* all family ME firmware */ 1623254885Sdumbbell const struct firmware *pfp_fw; /* r6/700 PFP firmware */ 1624254885Sdumbbell const struct firmware *rlc_fw; /* r6/700 RLC firmware */ 1625254885Sdumbbell const struct firmware *mc_fw; /* NI MC firmware */ 1626254885Sdumbbell const struct firmware *ce_fw; /* SI CE firmware */ 1627254885Sdumbbell struct r600_blit r600_blit; 1628254885Sdumbbell struct r600_vram_scratch vram_scratch; 1629254885Sdumbbell int msi_enabled; /* msi enabled */ 1630254885Sdumbbell struct r600_ih ih; /* r6/700 interrupt ring */ 1631254885Sdumbbell struct si_rlc rlc; 1632254885Sdumbbell struct taskqueue *tq; 1633254885Sdumbbell struct task hotplug_work; 1634254885Sdumbbell struct task audio_work; 1635254885Sdumbbell int num_crtc; /* number of crtcs */ 1636254885Sdumbbell struct sx dc_hw_i2c_mutex; /* display controller hw i2c mutex */ 1637254885Sdumbbell bool audio_enabled; 1638254885Sdumbbell struct r600_audio audio_status; /* audio stuff */ 1639254885Sdumbbell struct { 1640254885Sdumbbell ACPI_HANDLE handle; 1641254885Sdumbbell ACPI_NOTIFY_HANDLER notifier_call; 1642254885Sdumbbell } acpi; 1643254885Sdumbbell /* only one userspace can use Hyperz features or CMASK at a time */ 1644254885Sdumbbell struct drm_file *hyperz_filp; 1645254885Sdumbbell struct drm_file *cmask_filp; 1646254885Sdumbbell /* i2c buses */ 1647254885Sdumbbell struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS]; 1648254885Sdumbbell /* debugfs */ 1649254885Sdumbbell struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS]; 1650254885Sdumbbell unsigned debugfs_count; 1651254885Sdumbbell /* virtual memory */ 1652254885Sdumbbell struct radeon_vm_manager vm_manager; 1653254885Sdumbbell struct sx gpu_clock_mutex; 1654254885Sdumbbell /* ACPI interface */ 1655254885Sdumbbell struct radeon_atif atif; 1656254885Sdumbbell struct radeon_atcs atcs; 1657254885Sdumbbell}; 1658254885Sdumbbell 1659254885Sdumbbellint radeon_device_init(struct radeon_device *rdev, 1660254885Sdumbbell struct drm_device *ddev, 1661254885Sdumbbell uint32_t flags); 1662254885Sdumbbellvoid radeon_device_fini(struct radeon_device *rdev); 1663254885Sdumbbellint radeon_gpu_wait_for_idle(struct radeon_device *rdev); 1664254885Sdumbbell 1665254885Sdumbbelluint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg, 1666254885Sdumbbell bool always_indirect); 1667254885Sdumbbellvoid r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v, 1668254885Sdumbbell bool always_indirect); 1669254885Sdumbbellu32 r100_io_rreg(struct radeon_device *rdev, u32 reg); 1670254885Sdumbbellvoid r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v); 1671254885Sdumbbell 1672254885Sdumbbell/* 1673254885Sdumbbell * Cast helper 1674254885Sdumbbell */ 1675254885Sdumbbell#define to_radeon_fence(p) ((struct radeon_fence *)(p)) 1676254885Sdumbbell 1677254885Sdumbbell/* 1678254885Sdumbbell * Registers read & write functions. 1679254885Sdumbbell */ 1680254885Sdumbbell#define RREG8(reg) bus_read_1((rdev->rmmio), (reg)) 1681254885Sdumbbell#define WREG8(reg, v) bus_write_1((rdev->rmmio), (reg), v) 1682254885Sdumbbell#define RREG16(reg) bus_read_2((rdev->rmmio), (reg)) 1683254885Sdumbbell#define WREG16(reg, v) bus_write_2((rdev->rmmio), (reg), v) 1684254885Sdumbbell#define RREG32(reg) r100_mm_rreg(rdev, (reg), false) 1685254885Sdumbbell#define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true) 1686254885Sdumbbell#define DREG32(reg) DRM_INFO("REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg))) 1687254885Sdumbbell#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false) 1688254885Sdumbbell#define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true) 1689254885Sdumbbell#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1690254885Sdumbbell#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1691254885Sdumbbell#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) 1692254885Sdumbbell#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) 1693254885Sdumbbell#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) 1694254885Sdumbbell#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) 1695254885Sdumbbell#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) 1696254885Sdumbbell#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) 1697254885Sdumbbell#define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg)) 1698254885Sdumbbell#define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v)) 1699254885Sdumbbell#define WREG32_P(reg, val, mask) \ 1700254885Sdumbbell do { \ 1701254885Sdumbbell uint32_t tmp_ = RREG32(reg); \ 1702254885Sdumbbell tmp_ &= (mask); \ 1703254885Sdumbbell tmp_ |= ((val) & ~(mask)); \ 1704254885Sdumbbell WREG32(reg, tmp_); \ 1705254885Sdumbbell } while (0) 1706254885Sdumbbell#define WREG32_PLL_P(reg, val, mask) \ 1707254885Sdumbbell do { \ 1708254885Sdumbbell uint32_t tmp_ = RREG32_PLL(reg); \ 1709254885Sdumbbell tmp_ &= (mask); \ 1710254885Sdumbbell tmp_ |= ((val) & ~(mask)); \ 1711254885Sdumbbell WREG32_PLL(reg, tmp_); \ 1712254885Sdumbbell } while (0) 1713254885Sdumbbell#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false)) 1714254885Sdumbbell#define RREG32_IO(reg) r100_io_rreg(rdev, (reg)) 1715254885Sdumbbell#define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v)) 1716254885Sdumbbell 1717254885Sdumbbell/* 1718254885Sdumbbell * Indirect registers accessor 1719254885Sdumbbell */ 1720254885Sdumbbellstatic inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg) 1721254885Sdumbbell{ 1722254885Sdumbbell uint32_t r; 1723254885Sdumbbell 1724254885Sdumbbell WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); 1725254885Sdumbbell r = RREG32(RADEON_PCIE_DATA); 1726254885Sdumbbell return r; 1727254885Sdumbbell} 1728254885Sdumbbell 1729254885Sdumbbellstatic inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 1730254885Sdumbbell{ 1731254885Sdumbbell WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); 1732254885Sdumbbell WREG32(RADEON_PCIE_DATA, (v)); 1733254885Sdumbbell} 1734254885Sdumbbell 1735254885Sdumbbellvoid r100_pll_errata_after_index(struct radeon_device *rdev); 1736254885Sdumbbell 1737254885Sdumbbell 1738254885Sdumbbell/* 1739254885Sdumbbell * ASICs helpers. 1740254885Sdumbbell */ 1741254885Sdumbbell#define ASIC_IS_RN50(rdev) ((rdev->ddev->pci_device == 0x515e) || \ 1742254885Sdumbbell (rdev->ddev->pci_device == 0x5969)) 1743254885Sdumbbell#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ 1744254885Sdumbbell (rdev->family == CHIP_RV200) || \ 1745254885Sdumbbell (rdev->family == CHIP_RS100) || \ 1746254885Sdumbbell (rdev->family == CHIP_RS200) || \ 1747254885Sdumbbell (rdev->family == CHIP_RV250) || \ 1748254885Sdumbbell (rdev->family == CHIP_RV280) || \ 1749254885Sdumbbell (rdev->family == CHIP_RS300)) 1750254885Sdumbbell#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ 1751254885Sdumbbell (rdev->family == CHIP_RV350) || \ 1752254885Sdumbbell (rdev->family == CHIP_R350) || \ 1753254885Sdumbbell (rdev->family == CHIP_RV380) || \ 1754254885Sdumbbell (rdev->family == CHIP_R420) || \ 1755254885Sdumbbell (rdev->family == CHIP_R423) || \ 1756254885Sdumbbell (rdev->family == CHIP_RV410) || \ 1757254885Sdumbbell (rdev->family == CHIP_RS400) || \ 1758254885Sdumbbell (rdev->family == CHIP_RS480)) 1759254885Sdumbbell#define ASIC_IS_X2(rdev) ((rdev->ddev->pci_device == 0x9441) || \ 1760254885Sdumbbell (rdev->ddev->pci_device == 0x9443) || \ 1761254885Sdumbbell (rdev->ddev->pci_device == 0x944B) || \ 1762254885Sdumbbell (rdev->ddev->pci_device == 0x9506) || \ 1763254885Sdumbbell (rdev->ddev->pci_device == 0x9509) || \ 1764254885Sdumbbell (rdev->ddev->pci_device == 0x950F) || \ 1765254885Sdumbbell (rdev->ddev->pci_device == 0x689C) || \ 1766254885Sdumbbell (rdev->ddev->pci_device == 0x689D)) 1767254885Sdumbbell#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) 1768254885Sdumbbell#define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \ 1769254885Sdumbbell (rdev->family == CHIP_RS690) || \ 1770254885Sdumbbell (rdev->family == CHIP_RS740) || \ 1771254885Sdumbbell (rdev->family >= CHIP_R600)) 1772254885Sdumbbell#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) 1773254885Sdumbbell#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) 1774254885Sdumbbell#define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR)) 1775254885Sdumbbell#define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \ 1776254885Sdumbbell (rdev->flags & RADEON_IS_IGP)) 1777254885Sdumbbell#define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS)) 1778254885Sdumbbell#define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA)) 1779254885Sdumbbell#define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \ 1780254885Sdumbbell (rdev->flags & RADEON_IS_IGP)) 1781254885Sdumbbell 1782254885Sdumbbell/* 1783254885Sdumbbell * BIOS helpers. 1784254885Sdumbbell */ 1785254885Sdumbbell#define RBIOS8(i) (rdev->bios[i]) 1786254885Sdumbbell#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1787254885Sdumbbell#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1788254885Sdumbbell 1789254885Sdumbbellint radeon_combios_init(struct radeon_device *rdev); 1790254885Sdumbbellvoid radeon_combios_fini(struct radeon_device *rdev); 1791254885Sdumbbellint radeon_atombios_init(struct radeon_device *rdev); 1792254885Sdumbbellvoid radeon_atombios_fini(struct radeon_device *rdev); 1793254885Sdumbbell 1794254885Sdumbbell 1795254885Sdumbbell/* 1796254885Sdumbbell * RING helpers. 1797254885Sdumbbell */ 1798254885Sdumbbell#if !defined(DRM_DEBUG_CODE) || DRM_DEBUG_CODE == 0 1799254885Sdumbbellstatic inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v) 1800254885Sdumbbell{ 1801254885Sdumbbell ring->ring[ring->wptr++] = v; 1802254885Sdumbbell ring->wptr &= ring->ptr_mask; 1803254885Sdumbbell ring->count_dw--; 1804254885Sdumbbell ring->ring_free_dw--; 1805254885Sdumbbell} 1806254885Sdumbbell#else 1807254885Sdumbbell/* With debugging this is just too big to inline */ 1808254885Sdumbbellvoid radeon_ring_write(struct radeon_ring *ring, uint32_t v); 1809254885Sdumbbell#endif 1810254885Sdumbbell 1811254885Sdumbbell/* 1812254885Sdumbbell * ASICs macro. 1813254885Sdumbbell */ 1814254885Sdumbbell#define radeon_init(rdev) (rdev)->asic->init((rdev)) 1815254885Sdumbbell#define radeon_fini(rdev) (rdev)->asic->fini((rdev)) 1816254885Sdumbbell#define radeon_resume(rdev) (rdev)->asic->resume((rdev)) 1817254885Sdumbbell#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) 1818254885Sdumbbell#define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)].cs_parse((p)) 1819254885Sdumbbell#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) 1820254885Sdumbbell#define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev)) 1821254885Sdumbbell#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev)) 1822254885Sdumbbell#define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p)) 1823254885Sdumbbell#define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev)) 1824254885Sdumbbell#define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev)) 1825254885Sdumbbell#define radeon_asic_vm_set_page(rdev, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (pe), (addr), (count), (incr), (flags))) 1826254885Sdumbbell#define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)].ring_start((rdev), (cp)) 1827254885Sdumbbell#define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)].ring_test((rdev), (cp)) 1828254885Sdumbbell#define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)].ib_test((rdev), (cp)) 1829254885Sdumbbell#define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)].ib_execute((rdev), (ib)) 1830254885Sdumbbell#define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)].ib_parse((rdev), (ib)) 1831254885Sdumbbell#define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)].is_lockup((rdev), (cp)) 1832254885Sdumbbell#define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)].vm_flush((rdev), (r), (vm)) 1833254885Sdumbbell#define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev)) 1834254885Sdumbbell#define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev)) 1835254885Sdumbbell#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc)) 1836254885Sdumbbell#define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l)) 1837254885Sdumbbell#define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e)) 1838254885Sdumbbell#define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)].emit_fence((rdev), (fence)) 1839254885Sdumbbell#define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)].emit_semaphore((rdev), (cp), (semaphore), (emit_wait)) 1840254885Sdumbbell#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f)) 1841254885Sdumbbell#define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f)) 1842254885Sdumbbell#define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f)) 1843254885Sdumbbell#define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index 1844254885Sdumbbell#define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index 1845254885Sdumbbell#define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index 1846254885Sdumbbell#define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev)) 1847254885Sdumbbell#define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e)) 1848254885Sdumbbell#define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev)) 1849254885Sdumbbell#define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e)) 1850254885Sdumbbell#define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev)) 1851254885Sdumbbell#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l)) 1852254885Sdumbbell#define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e)) 1853254885Sdumbbell#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s))) 1854254885Sdumbbell#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r))) 1855254885Sdumbbell#define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev)) 1856254885Sdumbbell#define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev)) 1857254885Sdumbbell#define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev)) 1858254885Sdumbbell#define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h)) 1859254885Sdumbbell#define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h)) 1860254885Sdumbbell#define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev)) 1861254885Sdumbbell#define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev)) 1862254885Sdumbbell#define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev)) 1863254885Sdumbbell#define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev)) 1864254885Sdumbbell#define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev)) 1865254885Sdumbbell#define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev)) 1866254885Sdumbbell#define radeon_pre_page_flip(rdev, crtc) (rdev)->asic->pflip.pre_page_flip((rdev), (crtc)) 1867254885Sdumbbell#define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base)) 1868254885Sdumbbell#define radeon_post_page_flip(rdev, crtc) (rdev)->asic->pflip.post_page_flip((rdev), (crtc)) 1869254885Sdumbbell#define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc)) 1870254885Sdumbbell#define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev)) 1871254885Sdumbbell 1872254885Sdumbbell/* Common functions */ 1873254885Sdumbbell/* AGP */ 1874254885Sdumbbellextern int radeon_gpu_reset(struct radeon_device *rdev); 1875254885Sdumbbellextern void radeon_agp_disable(struct radeon_device *rdev); 1876254885Sdumbbellextern int radeon_modeset_init(struct radeon_device *rdev); 1877254885Sdumbbellextern void radeon_modeset_fini(struct radeon_device *rdev); 1878254885Sdumbbellextern bool radeon_card_posted(struct radeon_device *rdev); 1879254885Sdumbbellextern void radeon_update_bandwidth_info(struct radeon_device *rdev); 1880254885Sdumbbellextern void radeon_update_display_priority(struct radeon_device *rdev); 1881254885Sdumbbellextern bool radeon_boot_test_post_card(struct radeon_device *rdev); 1882254885Sdumbbellextern void radeon_scratch_init(struct radeon_device *rdev); 1883254885Sdumbbellextern void radeon_wb_fini(struct radeon_device *rdev); 1884254885Sdumbbellextern int radeon_wb_init(struct radeon_device *rdev); 1885254885Sdumbbellextern void radeon_wb_disable(struct radeon_device *rdev); 1886254885Sdumbbellextern void radeon_surface_init(struct radeon_device *rdev); 1887254885Sdumbbellextern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); 1888254885Sdumbbellextern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); 1889254885Sdumbbellextern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo); 1890254885Sdumbbellextern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base); 1891254885Sdumbbellextern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); 1892254885Sdumbbellextern int radeon_resume_kms(struct drm_device *dev); 1893254885Sdumbbellextern int radeon_suspend_kms(struct drm_device *dev); 1894254885Sdumbbellextern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size); 1895254885Sdumbbell 1896254885Sdumbbell/* 1897254885Sdumbbell * vm 1898254885Sdumbbell */ 1899254885Sdumbbellint radeon_vm_manager_init(struct radeon_device *rdev); 1900254885Sdumbbellvoid radeon_vm_manager_fini(struct radeon_device *rdev); 1901254885Sdumbbellvoid radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm); 1902254885Sdumbbellvoid radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm); 1903254885Sdumbbellint radeon_vm_alloc_pt(struct radeon_device *rdev, struct radeon_vm *vm); 1904254885Sdumbbellvoid radeon_vm_add_to_lru(struct radeon_device *rdev, struct radeon_vm *vm); 1905254885Sdumbbellstruct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev, 1906254885Sdumbbell struct radeon_vm *vm, int ring); 1907254885Sdumbbellvoid radeon_vm_fence(struct radeon_device *rdev, 1908254885Sdumbbell struct radeon_vm *vm, 1909254885Sdumbbell struct radeon_fence *fence); 1910254885Sdumbbelluint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr); 1911254885Sdumbbellint radeon_vm_bo_update_pte(struct radeon_device *rdev, 1912254885Sdumbbell struct radeon_vm *vm, 1913254885Sdumbbell struct radeon_bo *bo, 1914254885Sdumbbell struct ttm_mem_reg *mem); 1915254885Sdumbbellvoid radeon_vm_bo_invalidate(struct radeon_device *rdev, 1916254885Sdumbbell struct radeon_bo *bo); 1917254885Sdumbbellstruct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm, 1918254885Sdumbbell struct radeon_bo *bo); 1919254885Sdumbbellstruct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev, 1920254885Sdumbbell struct radeon_vm *vm, 1921254885Sdumbbell struct radeon_bo *bo); 1922254885Sdumbbellint radeon_vm_bo_set_addr(struct radeon_device *rdev, 1923254885Sdumbbell struct radeon_bo_va *bo_va, 1924254885Sdumbbell uint64_t offset, 1925254885Sdumbbell uint32_t flags); 1926254885Sdumbbellint radeon_vm_bo_rmv(struct radeon_device *rdev, 1927254885Sdumbbell struct radeon_bo_va *bo_va); 1928254885Sdumbbell 1929254885Sdumbbell/* audio */ 1930254885Sdumbbellvoid r600_audio_update_hdmi(void *arg, int pending); 1931254885Sdumbbell 1932254885Sdumbbell/* 1933254885Sdumbbell * R600 vram scratch functions 1934254885Sdumbbell */ 1935254885Sdumbbellint r600_vram_scratch_init(struct radeon_device *rdev); 1936254885Sdumbbellvoid r600_vram_scratch_fini(struct radeon_device *rdev); 1937254885Sdumbbell 1938254885Sdumbbell/* 1939254885Sdumbbell * r600 cs checking helper 1940254885Sdumbbell */ 1941254885Sdumbbellunsigned r600_mip_minify(unsigned size, unsigned level); 1942254885Sdumbbellbool r600_fmt_is_valid_color(u32 format); 1943254885Sdumbbellbool r600_fmt_is_valid_texture(u32 format, enum radeon_family family); 1944254885Sdumbbellint r600_fmt_get_blocksize(u32 format); 1945254885Sdumbbellint r600_fmt_get_nblocksx(u32 format, u32 w); 1946254885Sdumbbellint r600_fmt_get_nblocksy(u32 format, u32 h); 1947254885Sdumbbell 1948254885Sdumbbell/* 1949254885Sdumbbell * r600 functions used by radeon_encoder.c 1950254885Sdumbbell */ 1951254885Sdumbbellstruct radeon_hdmi_acr { 1952254885Sdumbbell u32 clock; 1953254885Sdumbbell 1954254885Sdumbbell int n_32khz; 1955254885Sdumbbell int cts_32khz; 1956254885Sdumbbell 1957254885Sdumbbell int n_44_1khz; 1958254885Sdumbbell int cts_44_1khz; 1959254885Sdumbbell 1960254885Sdumbbell int n_48khz; 1961254885Sdumbbell int cts_48khz; 1962254885Sdumbbell 1963254885Sdumbbell}; 1964254885Sdumbbell 1965254885Sdumbbellextern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock); 1966254885Sdumbbell 1967254885Sdumbbellextern void r600_hdmi_enable(struct drm_encoder *encoder); 1968254885Sdumbbellextern void r600_hdmi_disable(struct drm_encoder *encoder); 1969254885Sdumbbellextern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode); 1970254885Sdumbbellextern u32 r6xx_remap_render_backend(struct radeon_device *rdev, 1971254885Sdumbbell u32 tiling_pipe_num, 1972254885Sdumbbell u32 max_rb_num, 1973254885Sdumbbell u32 total_max_rb_num, 1974254885Sdumbbell u32 enabled_rb_mask); 1975254885Sdumbbell 1976254885Sdumbbell/* 1977254885Sdumbbell * evergreen functions used by radeon_encoder.c 1978254885Sdumbbell */ 1979254885Sdumbbell 1980254885Sdumbbellextern void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode); 1981254885Sdumbbell 1982254885Sdumbbellextern int ni_init_microcode(struct radeon_device *rdev); 1983254885Sdumbbellextern int ni_mc_load_microcode(struct radeon_device *rdev); 1984254885Sdumbbellextern void ni_fini_microcode(struct radeon_device *rdev); 1985254885Sdumbbell 1986254885Sdumbbell/* radeon_acpi.c */ 1987254885Sdumbbellextern int radeon_acpi_init(struct radeon_device *rdev); 1988254885Sdumbbellextern void radeon_acpi_fini(struct radeon_device *rdev); 1989254885Sdumbbell 1990254885Sdumbbell/* Prototypes added by @dumbbell. */ 1991254885Sdumbbell 1992254885Sdumbbell/* atombios_encoders.c */ 1993254885Sdumbbellvoid radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder, 1994254885Sdumbbell struct drm_connector *drm_connector); 1995254885Sdumbbellvoid radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum, 1996254885Sdumbbell uint32_t supported_device, u16 caps); 1997254885Sdumbbell 1998254885Sdumbbell/* radeon_atombios.c */ 1999254885Sdumbbellbool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index, 2000254885Sdumbbell struct drm_display_mode *mode); 2001254885Sdumbbell 2002254885Sdumbbell/* radeon_combios.c */ 2003254885Sdumbbellvoid radeon_combios_connected_scratch_regs(struct drm_connector *connector, 2004254885Sdumbbell struct drm_encoder *encoder, bool connected); 2005254885Sdumbbell 2006254885Sdumbbell/* radeon_connectors.c */ 2007254885Sdumbbellvoid radeon_atombios_connected_scratch_regs(struct drm_connector *connector, 2008254885Sdumbbell struct drm_encoder *encoder, bool connected); 2009254885Sdumbbellvoid radeon_add_legacy_connector(struct drm_device *dev, 2010254885Sdumbbell uint32_t connector_id, 2011254885Sdumbbell uint32_t supported_device, 2012254885Sdumbbell int connector_type, 2013254885Sdumbbell struct radeon_i2c_bus_rec *i2c_bus, 2014254885Sdumbbell uint16_t connector_object_id, 2015254885Sdumbbell struct radeon_hpd *hpd); 2016254885Sdumbbellvoid radeon_add_atom_connector(struct drm_device *dev, 2017254885Sdumbbell uint32_t connector_id, 2018254885Sdumbbell uint32_t supported_device, 2019254885Sdumbbell int connector_type, 2020254885Sdumbbell struct radeon_i2c_bus_rec *i2c_bus, 2021254885Sdumbbell uint32_t igp_lane_info, 2022254885Sdumbbell uint16_t connector_object_id, 2023254885Sdumbbell struct radeon_hpd *hpd, 2024254885Sdumbbell struct radeon_router *router); 2025254885Sdumbbell 2026254885Sdumbbell/* radeon_encoders.c */ 2027254885Sdumbbelluint32_t radeon_get_encoder_enum(struct drm_device *dev, 2028254885Sdumbbell uint32_t supported_device, uint8_t dac); 2029254885Sdumbbellvoid radeon_link_encoder_connector(struct drm_device *dev); 2030254885Sdumbbell 2031254885Sdumbbell/* radeon_legacy_encoders.c */ 2032254885Sdumbbellvoid radeon_add_legacy_encoder(struct drm_device *dev, 2033254885Sdumbbell uint32_t encoder_enum, uint32_t supported_device); 2034254885Sdumbbellvoid radeon_legacy_backlight_init(struct radeon_encoder *radeon_encoder, 2035254885Sdumbbell struct drm_connector *drm_connector); 2036254885Sdumbbell 2037254885Sdumbbell/* radeon_pm.c */ 2038254885Sdumbbellvoid radeon_pm_acpi_event_handler(struct radeon_device *rdev); 2039254885Sdumbbell 2040254885Sdumbbell/* radeon_ttm.c */ 2041254885Sdumbbellint radeon_ttm_init(struct radeon_device *rdev); 2042254885Sdumbbellvoid radeon_ttm_fini(struct radeon_device *rdev); 2043254885Sdumbbell 2044262861Sjhb/* radeon_fb.c */ 2045262861Sjhbstruct fb_info * radeon_fb_helper_getinfo(device_t kdev); 2046262861Sjhb 2047254885Sdumbbell/* r600.c */ 2048254885Sdumbbellint r600_ih_ring_alloc(struct radeon_device *rdev); 2049254885Sdumbbellvoid r600_ih_ring_fini(struct radeon_device *rdev); 2050254885Sdumbbell 2051254885Sdumbbell#include "radeon_object.h" 2052254885Sdumbbell 2053254885Sdumbbell#endif 2054