intel_iic.c revision 235783
1/* 2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright �� 2006-2008,2010 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 23 * DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: 26 * Eric Anholt <eric@anholt.net> 27 * Chris Wilson <chris@chris-wilson.co.uk> 28 * 29 * Copyright (c) 2011 The FreeBSD Foundation 30 * All rights reserved. 31 * 32 * This software was developed by Konstantin Belousov under sponsorship from 33 * the FreeBSD Foundation. 34 * 35 * Redistribution and use in source and binary forms, with or without 36 * modification, are permitted provided that the following conditions 37 * are met: 38 * 1. Redistributions of source code must retain the above copyright 39 * notice, this list of conditions and the following disclaimer. 40 * 2. Redistributions in binary form must reproduce the above copyright 41 * notice, this list of conditions and the following disclaimer in the 42 * documentation and/or other materials provided with the distribution. 43 * 44 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 45 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 46 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 47 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 48 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 49 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 50 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 51 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 52 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 53 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 54 * SUCH DAMAGE. 55 */ 56#include <sys/cdefs.h> 57__FBSDID("$FreeBSD: head/sys/dev/drm2/i915/intel_iic.c 235783 2012-05-22 11:07:44Z kib $"); 58 59#include <dev/drm2/drmP.h> 60#include <dev/drm2/drm.h> 61#include <dev/drm2/i915/i915_drm.h> 62#include <dev/drm2/i915/i915_drv.h> 63#include <dev/drm2/i915/intel_drv.h> 64#include <dev/iicbus/iic.h> 65#include <dev/iicbus/iiconf.h> 66#include <dev/iicbus/iicbus.h> 67#include "iicbus_if.h" 68#include "iicbb_if.h" 69 70static int intel_iic_quirk_xfer(device_t idev, struct iic_msg *msgs, int nmsgs); 71static void intel_teardown_gmbus_m(struct drm_device *dev, int m); 72 73/* Intel GPIO access functions */ 74 75#define I2C_RISEFALL_TIME 10 76 77struct intel_iic_softc { 78 struct drm_device *drm_dev; 79 device_t iic_dev; 80 bool force_bit_dev; 81 char name[32]; 82 uint32_t reg; 83 uint32_t reg0; 84}; 85 86static void 87intel_iic_quirk_set(struct drm_i915_private *dev_priv, bool enable) 88{ 89 u32 val; 90 91 /* When using bit bashing for I2C, this bit needs to be set to 1 */ 92 if (!IS_PINEVIEW(dev_priv->dev)) 93 return; 94 95 val = I915_READ(DSPCLK_GATE_D); 96 if (enable) 97 val |= DPCUNIT_CLOCK_GATE_DISABLE; 98 else 99 val &= ~DPCUNIT_CLOCK_GATE_DISABLE; 100 I915_WRITE(DSPCLK_GATE_D, val); 101} 102 103static u32 104intel_iic_get_reserved(device_t idev) 105{ 106 struct intel_iic_softc *sc; 107 struct drm_device *dev; 108 struct drm_i915_private *dev_priv; 109 u32 reserved; 110 111 sc = device_get_softc(idev); 112 dev = sc->drm_dev; 113 dev_priv = dev->dev_private; 114 115 if (!IS_I830(dev) && !IS_845G(dev)) { 116 reserved = I915_READ_NOTRACE(sc->reg) & 117 (GPIO_DATA_PULLUP_DISABLE | GPIO_CLOCK_PULLUP_DISABLE); 118 } else { 119 reserved = 0; 120 } 121 122 return (reserved); 123} 124 125void 126intel_iic_reset(struct drm_device *dev) 127{ 128 struct drm_i915_private *dev_priv; 129 130 dev_priv = dev->dev_private; 131 if (HAS_PCH_SPLIT(dev)) 132 I915_WRITE(PCH_GMBUS0, 0); 133 else 134 I915_WRITE(GMBUS0, 0); 135} 136 137static int 138intel_iicbus_reset(device_t idev, u_char speed, u_char addr, u_char *oldaddr) 139{ 140 struct intel_iic_softc *sc; 141 struct drm_device *dev; 142 143 sc = device_get_softc(idev); 144 dev = sc->drm_dev; 145 146 intel_iic_reset(dev); 147 return (0); 148} 149 150static void 151intel_iicbb_setsda(device_t idev, int val) 152{ 153 struct intel_iic_softc *sc; 154 struct drm_i915_private *dev_priv; 155 u32 reserved; 156 u32 data_bits; 157 158 sc = device_get_softc(idev); 159 dev_priv = sc->drm_dev->dev_private; 160 161 reserved = intel_iic_get_reserved(idev); 162 if (val) 163 data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK; 164 else 165 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK | 166 GPIO_DATA_VAL_MASK; 167 168 I915_WRITE_NOTRACE(sc->reg, reserved | data_bits); 169 POSTING_READ(sc->reg); 170} 171 172static void 173intel_iicbb_setscl(device_t idev, int val) 174{ 175 struct intel_iic_softc *sc; 176 struct drm_i915_private *dev_priv; 177 u32 clock_bits, reserved; 178 179 sc = device_get_softc(idev); 180 dev_priv = sc->drm_dev->dev_private; 181 182 reserved = intel_iic_get_reserved(idev); 183 if (val) 184 clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK; 185 else 186 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK | 187 GPIO_CLOCK_VAL_MASK; 188 189 I915_WRITE_NOTRACE(sc->reg, reserved | clock_bits); 190 POSTING_READ(sc->reg); 191} 192 193static int 194intel_iicbb_getsda(device_t idev) 195{ 196 struct intel_iic_softc *sc; 197 struct drm_i915_private *dev_priv; 198 u32 reserved; 199 200 sc = device_get_softc(idev); 201 dev_priv = sc->drm_dev->dev_private; 202 203 reserved = intel_iic_get_reserved(idev); 204 205 I915_WRITE_NOTRACE(sc->reg, reserved | GPIO_DATA_DIR_MASK); 206 I915_WRITE_NOTRACE(sc->reg, reserved); 207 return ((I915_READ_NOTRACE(sc->reg) & GPIO_DATA_VAL_IN) != 0); 208} 209 210static int 211intel_iicbb_getscl(device_t idev) 212{ 213 struct intel_iic_softc *sc; 214 struct drm_i915_private *dev_priv; 215 u32 reserved; 216 217 sc = device_get_softc(idev); 218 dev_priv = sc->drm_dev->dev_private; 219 220 reserved = intel_iic_get_reserved(idev); 221 222 I915_WRITE_NOTRACE(sc->reg, reserved | GPIO_CLOCK_DIR_MASK); 223 I915_WRITE_NOTRACE(sc->reg, reserved); 224 return ((I915_READ_NOTRACE(sc->reg) & GPIO_CLOCK_VAL_IN) != 0); 225} 226 227static int 228intel_gmbus_transfer(device_t idev, struct iic_msg *msgs, uint32_t nmsgs) 229{ 230 struct intel_iic_softc *sc; 231 struct drm_i915_private *dev_priv; 232 u8 *buf; 233 int error, i, reg_offset, unit; 234 u32 val, loop; 235 u16 len; 236 237 sc = device_get_softc(idev); 238 dev_priv = sc->drm_dev->dev_private; 239 unit = device_get_unit(idev); 240 241 sx_xlock(&dev_priv->gmbus_sx); 242 if (sc->force_bit_dev) { 243 error = intel_iic_quirk_xfer(dev_priv->bbbus[unit], msgs, nmsgs); 244 goto out; 245 } 246 247 reg_offset = HAS_PCH_SPLIT(dev_priv->dev) ? PCH_GMBUS0 - GMBUS0 : 0; 248 249 I915_WRITE(GMBUS0 + reg_offset, sc->reg0); 250 251 for (i = 0; i < nmsgs; i++) { 252 len = msgs[i].len; 253 buf = msgs[i].buf; 254 255 if ((msgs[i].flags & IIC_M_RD) != 0) { 256 I915_WRITE(GMBUS1 + reg_offset, GMBUS_CYCLE_WAIT | 257 (i + 1 == nmsgs ? GMBUS_CYCLE_STOP : 0) | 258 (len << GMBUS_BYTE_COUNT_SHIFT) | 259 (msgs[i].slave << GMBUS_SLAVE_ADDR_SHIFT) | 260 GMBUS_SLAVE_READ | GMBUS_SW_RDY); 261 POSTING_READ(GMBUS2 + reg_offset); 262 do { 263 loop = 0; 264 265 if (_intel_wait_for(sc->drm_dev, 266 (I915_READ(GMBUS2 + reg_offset) & 267 (GMBUS_SATOER | GMBUS_HW_RDY)) != 0, 268 50, 1, "915gbr")) 269 goto timeout; 270 if ((I915_READ(GMBUS2 + reg_offset) & 271 GMBUS_SATOER) != 0) 272 goto clear_err; 273 274 val = I915_READ(GMBUS3 + reg_offset); 275 do { 276 *buf++ = val & 0xff; 277 val >>= 8; 278 } while (--len != 0 && ++loop < 4); 279 } while (len != 0); 280 } else { 281 val = loop = 0; 282 do { 283 val |= *buf++ << (8 * loop); 284 } while (--len != 0 && ++loop < 4); 285 286 I915_WRITE(GMBUS3 + reg_offset, val); 287 I915_WRITE(GMBUS1 + reg_offset, GMBUS_CYCLE_WAIT | 288 (i + 1 == nmsgs ? GMBUS_CYCLE_STOP : 0) | 289 (msgs[i].len << GMBUS_BYTE_COUNT_SHIFT) | 290 (msgs[i].slave << GMBUS_SLAVE_ADDR_SHIFT) | 291 GMBUS_SLAVE_WRITE | GMBUS_SW_RDY); 292 POSTING_READ(GMBUS2+reg_offset); 293 294 while (len != 0) { 295 if (_intel_wait_for(sc->drm_dev, 296 (I915_READ(GMBUS2 + reg_offset) & 297 (GMBUS_SATOER | GMBUS_HW_RDY)) != 0, 298 50, 1, "915gbw")) 299 goto timeout; 300 if (I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER) 301 goto clear_err; 302 303 val = loop = 0; 304 do { 305 val |= *buf++ << (8 * loop); 306 } while (--len != 0 && ++loop < 4); 307 308 I915_WRITE(GMBUS3 + reg_offset, val); 309 POSTING_READ(GMBUS2 + reg_offset); 310 } 311 } 312 313 if (i + 1 < nmsgs && _intel_wait_for(sc->drm_dev, 314 (I915_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | 315 GMBUS_HW_WAIT_PHASE)) != 0, 316 50, 1, "915gbh")) 317 goto timeout; 318 if ((I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER) != 0) 319 goto clear_err; 320 } 321 322 error = 0; 323done: 324 /* Mark the GMBUS interface as disabled after waiting for idle. 325 * We will re-enable it at the start of the next xfer, 326 * till then let it sleep. 327 */ 328 if (_intel_wait_for(dev, 329 (I915_READ(GMBUS2 + reg_offset) & GMBUS_ACTIVE) == 0, 330 10, 1, "915gbu")) 331 DRM_INFO("GMBUS timed out waiting for idle\n"); 332 I915_WRITE(GMBUS0 + reg_offset, 0); 333out: 334 sx_xunlock(&dev_priv->gmbus_sx); 335 return (error); 336 337clear_err: 338 /* Toggle the Software Clear Interrupt bit. This has the effect 339 * of resetting the GMBUS controller and so clearing the 340 * BUS_ERROR raised by the slave's NAK. 341 */ 342 I915_WRITE(GMBUS1 + reg_offset, GMBUS_SW_CLR_INT); 343 I915_WRITE(GMBUS1 + reg_offset, 0); 344 error = EIO; 345 goto done; 346 347timeout: 348 DRM_INFO("GMBUS timed out, falling back to bit banging on pin %d [%s]\n", 349 sc->reg0 & 0xff, sc->name); 350 I915_WRITE(GMBUS0 + reg_offset, 0); 351 352 /* 353 * Hardware may not support GMBUS over these pins? 354 * Try GPIO bitbanging instead. 355 */ 356 sc->force_bit_dev = true; 357 358 error = intel_iic_quirk_xfer(dev_priv->bbbus[unit], msgs, nmsgs); 359 goto out; 360} 361 362void 363intel_gmbus_set_speed(device_t idev, int speed) 364{ 365 struct intel_iic_softc *sc; 366 367 sc = device_get_softc(device_get_parent(idev)); 368 369 sc->reg0 = (sc->reg0 & ~(0x3 << 8)) | speed; 370} 371 372void 373intel_gmbus_force_bit(device_t idev, bool force_bit) 374{ 375 struct intel_iic_softc *sc; 376 377 sc = device_get_softc(device_get_parent(idev)); 378 sc->force_bit_dev = force_bit; 379} 380 381static int 382intel_iic_quirk_xfer(device_t idev, struct iic_msg *msgs, int nmsgs) 383{ 384 device_t bridge_dev; 385 struct intel_iic_softc *sc; 386 struct drm_i915_private *dev_priv; 387 int ret; 388 int i; 389 390 bridge_dev = device_get_parent(device_get_parent(idev)); 391 sc = device_get_softc(bridge_dev); 392 dev_priv = sc->drm_dev->dev_private; 393 394 intel_iic_reset(sc->drm_dev); 395 intel_iic_quirk_set(dev_priv, true); 396 IICBB_SETSDA(bridge_dev, 1); 397 IICBB_SETSCL(bridge_dev, 1); 398 DELAY(I2C_RISEFALL_TIME); 399 400 /* convert slave addresses to format expected by iicbb */ 401 for (i = 0; i < nmsgs; i++) { 402 msgs[i].slave <<= 1; 403 /* force use of repeated start instead of default stop+start */ 404 if (i != (nmsgs - 1)) 405 msgs[i].flags |= IIC_M_NOSTOP; 406 } 407 ret = iicbus_transfer(idev, msgs, nmsgs); 408 /* restore the addresses */ 409 for (i = 0; i < nmsgs; i++) 410 msgs[i].slave >>= 1; 411 IICBB_SETSDA(bridge_dev, 1); 412 IICBB_SETSCL(bridge_dev, 1); 413 intel_iic_quirk_set(dev_priv, false); 414 415 return (ret); 416} 417 418static const char *gpio_names[GMBUS_NUM_PORTS] = { 419 "disabled", 420 "ssc", 421 "vga", 422 "panel", 423 "dpc", 424 "dpb", 425 "reserved", 426 "dpd", 427}; 428 429static int 430intel_gmbus_probe(device_t dev) 431{ 432 433 return (BUS_PROBE_SPECIFIC); 434} 435 436static int 437intel_gmbus_attach(device_t idev) 438{ 439 struct drm_i915_private *dev_priv; 440 struct intel_iic_softc *sc; 441 int pin; 442 443 sc = device_get_softc(idev); 444 sc->drm_dev = device_get_softc(device_get_parent(idev)); 445 dev_priv = sc->drm_dev->dev_private; 446 pin = device_get_unit(idev); 447 448 snprintf(sc->name, sizeof(sc->name), "gmbus bus %s", gpio_names[pin]); 449 device_set_desc(idev, sc->name); 450 451 /* By default use a conservative clock rate */ 452 sc->reg0 = pin | GMBUS_RATE_100KHZ; 453 454 /* XXX force bit banging until GMBUS is fully debugged */ 455 if (IS_GEN2(sc->drm_dev)) { 456 sc->force_bit_dev = true; 457 } 458 459 /* add bus interface device */ 460 sc->iic_dev = device_add_child(idev, "iicbus", -1); 461 if (sc->iic_dev == NULL) 462 return (ENXIO); 463 device_quiet(sc->iic_dev); 464 bus_generic_attach(idev); 465 466 return (0); 467} 468 469static int 470intel_gmbus_detach(device_t idev) 471{ 472 struct intel_iic_softc *sc; 473 struct drm_i915_private *dev_priv; 474 device_t child; 475 int u; 476 477 sc = device_get_softc(idev); 478 u = device_get_unit(idev); 479 dev_priv = sc->drm_dev->dev_private; 480 481 child = sc->iic_dev; 482 bus_generic_detach(idev); 483 if (child != NULL) 484 device_delete_child(idev, child); 485 486 return (0); 487} 488 489static int 490intel_iicbb_probe(device_t dev) 491{ 492 493 return (BUS_PROBE_DEFAULT); 494} 495 496static int 497intel_iicbb_attach(device_t idev) 498{ 499 static const int map_pin_to_reg[] = { 500 0, 501 GPIOB, 502 GPIOA, 503 GPIOC, 504 GPIOD, 505 GPIOE, 506 0, 507 GPIOF 508 }; 509 510 struct intel_iic_softc *sc; 511 struct drm_i915_private *dev_priv; 512 int pin; 513 514 sc = device_get_softc(idev); 515 sc->drm_dev = device_get_softc(device_get_parent(idev)); 516 dev_priv = sc->drm_dev->dev_private; 517 pin = device_get_unit(idev); 518 519 snprintf(sc->name, sizeof(sc->name), "i915 iicbb %s", gpio_names[pin]); 520 device_set_desc(idev, sc->name); 521 522 sc->reg0 = pin | GMBUS_RATE_100KHZ; 523 sc->reg = map_pin_to_reg[pin]; 524 if (HAS_PCH_SPLIT(dev_priv->dev)) 525 sc->reg += PCH_GPIOA - GPIOA; 526 527 /* add generic bit-banging code */ 528 sc->iic_dev = device_add_child(idev, "iicbb", -1); 529 if (sc->iic_dev == NULL) 530 return (ENXIO); 531 device_quiet(sc->iic_dev); 532 bus_generic_attach(idev); 533 534 return (0); 535} 536 537static int 538intel_iicbb_detach(device_t idev) 539{ 540 struct intel_iic_softc *sc; 541 device_t child; 542 543 sc = device_get_softc(idev); 544 child = sc->iic_dev; 545 bus_generic_detach(idev); 546 if (child) 547 device_delete_child(idev, child); 548 return (0); 549} 550 551static device_method_t intel_gmbus_methods[] = { 552 DEVMETHOD(device_probe, intel_gmbus_probe), 553 DEVMETHOD(device_attach, intel_gmbus_attach), 554 DEVMETHOD(device_detach, intel_gmbus_detach), 555 DEVMETHOD(iicbus_reset, intel_iicbus_reset), 556 DEVMETHOD(iicbus_transfer, intel_gmbus_transfer), 557 DEVMETHOD_END 558}; 559static driver_t intel_gmbus_driver = { 560 "intel_gmbus", 561 intel_gmbus_methods, 562 sizeof(struct intel_iic_softc) 563}; 564static devclass_t intel_gmbus_devclass; 565DRIVER_MODULE_ORDERED(intel_gmbus, drmn, intel_gmbus_driver, 566 intel_gmbus_devclass, 0, 0, SI_ORDER_FIRST); 567DRIVER_MODULE(iicbus, intel_gmbus, iicbus_driver, iicbus_devclass, 0, 0); 568 569static device_method_t intel_iicbb_methods[] = { 570 DEVMETHOD(device_probe, intel_iicbb_probe), 571 DEVMETHOD(device_attach, intel_iicbb_attach), 572 DEVMETHOD(device_detach, intel_iicbb_detach), 573 574 DEVMETHOD(bus_add_child, bus_generic_add_child), 575 DEVMETHOD(bus_print_child, bus_generic_print_child), 576 577 DEVMETHOD(iicbb_callback, iicbus_null_callback), 578 DEVMETHOD(iicbb_reset, intel_iicbus_reset), 579 DEVMETHOD(iicbb_setsda, intel_iicbb_setsda), 580 DEVMETHOD(iicbb_setscl, intel_iicbb_setscl), 581 DEVMETHOD(iicbb_getsda, intel_iicbb_getsda), 582 DEVMETHOD(iicbb_getscl, intel_iicbb_getscl), 583 DEVMETHOD_END 584}; 585static driver_t intel_iicbb_driver = { 586 "intel_iicbb", 587 intel_iicbb_methods, 588 sizeof(struct intel_iic_softc) 589}; 590static devclass_t intel_iicbb_devclass; 591DRIVER_MODULE_ORDERED(intel_iicbb, drmn, intel_iicbb_driver, 592 intel_iicbb_devclass, 0, 0, SI_ORDER_FIRST); 593DRIVER_MODULE(iicbb, intel_iicbb, iicbb_driver, iicbb_devclass, 0, 0); 594 595int 596intel_setup_gmbus(struct drm_device *dev) 597{ 598 struct drm_i915_private *dev_priv; 599 device_t iic_dev; 600 int i, ret; 601 602 dev_priv = dev->dev_private; 603 sx_init(&dev_priv->gmbus_sx, "gmbus"); 604 dev_priv->gmbus_bridge = malloc(sizeof(device_t) * GMBUS_NUM_PORTS, 605 DRM_MEM_DRIVER, M_WAITOK | M_ZERO); 606 dev_priv->bbbus_bridge = malloc(sizeof(device_t) * GMBUS_NUM_PORTS, 607 DRM_MEM_DRIVER, M_WAITOK | M_ZERO); 608 dev_priv->gmbus = malloc(sizeof(device_t) * GMBUS_NUM_PORTS, 609 DRM_MEM_DRIVER, M_WAITOK | M_ZERO); 610 dev_priv->bbbus = malloc(sizeof(device_t) * GMBUS_NUM_PORTS, 611 DRM_MEM_DRIVER, M_WAITOK | M_ZERO); 612 613 /* 614 * The Giant there is recursed, most likely. Normally, the 615 * intel_setup_gmbus() is called from the attach method of the 616 * driver. 617 */ 618 mtx_lock(&Giant); 619 for (i = 0; i < GMBUS_NUM_PORTS; i++) { 620 /* 621 * Initialized bbbus_bridge before gmbus_bridge, since 622 * gmbus may decide to force quirk transfer in the 623 * attachment code. 624 */ 625 dev_priv->bbbus_bridge[i] = device_add_child(dev->device, 626 "intel_iicbb", i); 627 if (dev_priv->bbbus_bridge[i] == NULL) { 628 DRM_ERROR("bbbus bridge %d creation failed\n", i); 629 ret = ENXIO; 630 goto err; 631 } 632 device_quiet(dev_priv->bbbus_bridge[i]); 633 ret = device_probe_and_attach(dev_priv->bbbus_bridge[i]); 634 if (ret != 0) { 635 DRM_ERROR("bbbus bridge %d attach failed, %d\n", i, 636 ret); 637 goto err; 638 } 639 640 iic_dev = device_find_child(dev_priv->bbbus_bridge[i], "iicbb", 641 -1); 642 if (iic_dev == NULL) { 643 DRM_ERROR("bbbus bridge doesn't have iicbb child\n"); 644 goto err; 645 } 646 iic_dev = device_find_child(iic_dev, "iicbus", -1); 647 if (iic_dev == NULL) { 648 DRM_ERROR( 649 "bbbus bridge doesn't have iicbus grandchild\n"); 650 goto err; 651 } 652 653 dev_priv->bbbus[i] = iic_dev; 654 655 dev_priv->gmbus_bridge[i] = device_add_child(dev->device, 656 "intel_gmbus", i); 657 if (dev_priv->gmbus_bridge[i] == NULL) { 658 DRM_ERROR("gmbus bridge %d creation failed\n", i); 659 ret = ENXIO; 660 goto err; 661 } 662 device_quiet(dev_priv->gmbus_bridge[i]); 663 ret = device_probe_and_attach(dev_priv->gmbus_bridge[i]); 664 if (ret != 0) { 665 DRM_ERROR("gmbus bridge %d attach failed, %d\n", i, 666 ret); 667 ret = ENXIO; 668 goto err; 669 } 670 671 iic_dev = device_find_child(dev_priv->gmbus_bridge[i], 672 "iicbus", -1); 673 if (iic_dev == NULL) { 674 DRM_ERROR("gmbus bridge doesn't have iicbus child\n"); 675 goto err; 676 } 677 dev_priv->gmbus[i] = iic_dev; 678 679 intel_iic_reset(dev); 680 } 681 682 mtx_unlock(&Giant); 683 return (0); 684 685err: 686 intel_teardown_gmbus_m(dev, i); 687 mtx_unlock(&Giant); 688 return (ret); 689} 690 691static void 692intel_teardown_gmbus_m(struct drm_device *dev, int m) 693{ 694 struct drm_i915_private *dev_priv; 695 696 dev_priv = dev->dev_private; 697 698 free(dev_priv->gmbus, DRM_MEM_DRIVER); 699 dev_priv->gmbus = NULL; 700 free(dev_priv->bbbus, DRM_MEM_DRIVER); 701 dev_priv->bbbus = NULL; 702 free(dev_priv->gmbus_bridge, DRM_MEM_DRIVER); 703 dev_priv->gmbus_bridge = NULL; 704 free(dev_priv->bbbus_bridge, DRM_MEM_DRIVER); 705 dev_priv->bbbus_bridge = NULL; 706 sx_destroy(&dev_priv->gmbus_sx); 707} 708 709void 710intel_teardown_gmbus(struct drm_device *dev) 711{ 712 713 mtx_lock(&Giant); 714 intel_teardown_gmbus_m(dev, GMBUS_NUM_PORTS); 715 mtx_unlock(&Giant); 716} 717