1181624Skmacy/* 2181624Skmacy * Copyright �� 2006 Intel Corporation 3181624Skmacy * 4181624Skmacy * Permission is hereby granted, free of charge, to any person obtaining a 5181624Skmacy * copy of this software and associated documentation files (the "Software"), 6181624Skmacy * to deal in the Software without restriction, including without limitation 7181624Skmacy * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8181624Skmacy * and/or sell copies of the Software, and to permit persons to whom the 9181624Skmacy * Software is furnished to do so, subject to the following conditions: 10181624Skmacy * 11181624Skmacy * The above copyright notice and this permission notice (including the next 12181624Skmacy * paragraph) shall be included in all copies or substantial portions of the 13181624Skmacy * Software. 14181624Skmacy * 15181624Skmacy * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16181624Skmacy * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17181624Skmacy * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18181624Skmacy * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19181624Skmacy * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20181624Skmacy * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21181624Skmacy * SOFTWARE. 22181624Skmacy * 23181624Skmacy * Authors: 24181624Skmacy * Eric Anholt <eric@anholt.net> 25181624Skmacy * 26181624Skmacy * $FreeBSD$ 27181624Skmacy */ 28181624Skmacy 29181624Skmacy#ifndef _I830_BIOS_H_ 30251767Sgibbs#define _I830_BIOS_H_ 31251767Sgibbs 32181624Skmacy#include <dev/drm2/drmP.h> 33181624Skmacy 34181624Skmacystruct vbt_header { 35181624Skmacy u8 signature[20]; /**< Always starts with 'VBT$' */ 36181624Skmacy u16 version; /**< decimal */ 37181624Skmacy u16 header_size; /**< in bytes */ 38181624Skmacy u16 vbt_size; /**< in bytes */ 39181624Skmacy u8 vbt_checksum; 40183375Skmacy u8 reserved0; 41183375Skmacy u32 bdb_offset; /**< from beginning of VBT */ 42183375Skmacy u32 aim_offset[4]; /**< from beginning of VBT */ 43183375Skmacy} __attribute__((packed)); 44183375Skmacy 45183375Skmacystruct bdb_header { 46183375Skmacy u8 signature[16]; /**< Always 'BIOS_DATA_BLOCK' */ 47183375Skmacy u16 version; /**< decimal */ 48183375Skmacy u16 header_size; /**< in bytes */ 49183375Skmacy u16 bdb_size; /**< in bytes */ 50183375Skmacy}; 51183375Skmacy 52183375Skmacy/* strictly speaking, this is a "skip" block, but it has interesting info */ 53251767Sgibbsstruct vbios_data { 54251767Sgibbs u8 type; /* 0 == desktop, 1 == mobile */ 55251767Sgibbs u8 relstage; 56251767Sgibbs u8 chipset; 57251767Sgibbs u8 lvds_present:1; 58183375Skmacy u8 tv_present:1; 59183375Skmacy u8 rsvd2:6; /* finish byte */ 60181624Skmacy u8 rsvd3[4]; 61181624Skmacy u8 signon[155]; 62181624Skmacy u8 copyright[61]; 63181624Skmacy u16 code_segment; 64181624Skmacy u8 dos_boot_mode; 65181624Skmacy u8 bandwidth_percent; 66181624Skmacy u8 rsvd4; /* popup memory size */ 67181624Skmacy u8 resize_pci_bios; 68181624Skmacy u8 rsvd5; /* is crt already on ddc2 */ 69181624Skmacy} __attribute__((packed)); 70181624Skmacy 71181624Skmacy/* 72183375Skmacy * There are several types of BIOS data blocks (BDBs), each block has 73181624Skmacy * an ID and size in the first 3 bytes (ID in first, size in next 2). 74181624Skmacy * Known types are listed below. 75181624Skmacy */ 76181624Skmacy#define BDB_GENERAL_FEATURES 1 77181624Skmacy#define BDB_GENERAL_DEFINITIONS 2 78183375Skmacy#define BDB_OLD_TOGGLE_LIST 3 79183375Skmacy#define BDB_MODE_SUPPORT_LIST 4 80183375Skmacy#define BDB_GENERIC_MODE_TABLE 5 81183375Skmacy#define BDB_EXT_MMIO_REGS 6 82181624Skmacy#define BDB_SWF_IO 7 83183375Skmacy#define BDB_SWF_MMIO 8 84181624Skmacy#define BDB_DOT_CLOCK_TABLE 9 85181624Skmacy#define BDB_MODE_REMOVAL_TABLE 10 86181624Skmacy#define BDB_CHILD_DEVICE_TABLE 11 87181624Skmacy#define BDB_DRIVER_FEATURES 12 88181624Skmacy#define BDB_DRIVER_PERSISTENCE 13 89181624Skmacy#define BDB_EXT_TABLE_PTRS 14 90181624Skmacy#define BDB_DOT_CLOCK_OVERRIDE 15 91181624Skmacy#define BDB_DISPLAY_SELECT 16 92181624Skmacy/* 17 rsvd */ 93181624Skmacy#define BDB_DRIVER_ROTATION 18 94181624Skmacy#define BDB_DISPLAY_REMOVE 19 95181624Skmacy#define BDB_OEM_CUSTOM 20 96181624Skmacy#define BDB_EFP_LIST 21 /* workarounds for VGA hsync/vsync */ 97181624Skmacy#define BDB_SDVO_LVDS_OPTIONS 22 98181624Skmacy#define BDB_SDVO_PANEL_DTDS 23 99181624Skmacy#define BDB_SDVO_LVDS_PNP_IDS 24 100181624Skmacy#define BDB_SDVO_LVDS_POWER_SEQ 25 101181624Skmacy#define BDB_TV_OPTIONS 26 102181624Skmacy#define BDB_EDP 27 103181624Skmacy#define BDB_LVDS_OPTIONS 40 104181624Skmacy#define BDB_LVDS_LFP_DATA_PTRS 41 105181624Skmacy#define BDB_LVDS_LFP_DATA 42 106181624Skmacy#define BDB_LVDS_BACKLIGHT 43 107181624Skmacy#define BDB_LVDS_POWER 44 108181624Skmacy#define BDB_SKIP 254 /* VBIOS private block, ignore */ 109181624Skmacy 110181624Skmacystruct bdb_general_features { 111181624Skmacy /* bits 1 */ 112181624Skmacy u8 panel_fitting:2; 113181624Skmacy u8 flexaim:1; 114181624Skmacy u8 msg_enable:1; 115181624Skmacy u8 clear_screen:3; 116181624Skmacy u8 color_flip:1; 117181624Skmacy 118181624Skmacy /* bits 2 */ 119181624Skmacy u8 download_ext_vbt:1; 120181624Skmacy u8 enable_ssc:1; 121181624Skmacy u8 ssc_freq:1; 122181624Skmacy u8 enable_lfp_on_override:1; 123181624Skmacy u8 disable_ssc_ddt:1; 124181624Skmacy u8 rsvd7:1; 125181624Skmacy u8 display_clock_mode:1; 126181624Skmacy u8 rsvd8:1; /* finish byte */ 127181624Skmacy 128181624Skmacy /* bits 3 */ 129181624Skmacy u8 disable_smooth_vision:1; 130181624Skmacy u8 single_dvi:1; 131181624Skmacy u8 rsvd9:6; /* finish byte */ 132181624Skmacy 133181624Skmacy /* bits 4 */ 134181624Skmacy u8 legacy_monitor_detect; 135181624Skmacy 136181624Skmacy /* bits 5 */ 137181624Skmacy u8 int_crt_support:1; 138181624Skmacy u8 int_tv_support:1; 139181624Skmacy u8 int_efp_support:1; 140181624Skmacy u8 dp_ssc_enb:1; /* PCH attached eDP supports SSC */ 141181624Skmacy u8 dp_ssc_freq:1; /* SSC freq for PCH attached eDP */ 142181624Skmacy u8 rsvd11:3; /* finish byte */ 143181624Skmacy} __attribute__((packed)); 144181624Skmacy 145181624Skmacy/* pre-915 */ 146181624Skmacy#define GPIO_PIN_DVI_LVDS 0x03 /* "DVI/LVDS DDC GPIO pins" */ 147181624Skmacy#define GPIO_PIN_ADD_I2C 0x05 /* "ADDCARD I2C GPIO pins" */ 148181624Skmacy#define GPIO_PIN_ADD_DDC 0x04 /* "ADDCARD DDC GPIO pins" */ 149181624Skmacy#define GPIO_PIN_ADD_DDC_I2C 0x06 /* "ADDCARD DDC/I2C GPIO pins" */ 150181624Skmacy 151181624Skmacy/* Pre 915 */ 152181624Skmacy#define DEVICE_TYPE_NONE 0x00 153181624Skmacy#define DEVICE_TYPE_CRT 0x01 154181624Skmacy#define DEVICE_TYPE_TV 0x09 155181624Skmacy#define DEVICE_TYPE_EFP 0x12 156181624Skmacy#define DEVICE_TYPE_LFP 0x22 157181624Skmacy/* On 915+ */ 158181624Skmacy#define DEVICE_TYPE_CRT_DPMS 0x6001 159181624Skmacy#define DEVICE_TYPE_CRT_DPMS_HOTPLUG 0x4001 160181624Skmacy#define DEVICE_TYPE_TV_COMPOSITE 0x0209 161181624Skmacy#define DEVICE_TYPE_TV_MACROVISION 0x0289 162181624Skmacy#define DEVICE_TYPE_TV_RF_COMPOSITE 0x020c 163181624Skmacy#define DEVICE_TYPE_TV_SVIDEO_COMPOSITE 0x0609 164181624Skmacy#define DEVICE_TYPE_TV_SCART 0x0209 165181624Skmacy#define DEVICE_TYPE_TV_CODEC_HOTPLUG_PWR 0x6009 166181624Skmacy#define DEVICE_TYPE_EFP_HOTPLUG_PWR 0x6012 167181624Skmacy#define DEVICE_TYPE_EFP_DVI_HOTPLUG_PWR 0x6052 168181624Skmacy#define DEVICE_TYPE_EFP_DVI_I 0x6053 169181624Skmacy#define DEVICE_TYPE_EFP_DVI_D_DUAL 0x6152 170181624Skmacy#define DEVICE_TYPE_EFP_DVI_D_HDCP 0x60d2 171181624Skmacy#define DEVICE_TYPE_OPENLDI_HOTPLUG_PWR 0x6062 172181624Skmacy#define DEVICE_TYPE_OPENLDI_DUALPIX 0x6162 173181624Skmacy#define DEVICE_TYPE_LFP_PANELLINK 0x5012 174181624Skmacy#define DEVICE_TYPE_LFP_CMOS_PWR 0x5042 175181624Skmacy#define DEVICE_TYPE_LFP_LVDS_PWR 0x5062 176183375Skmacy#define DEVICE_TYPE_LFP_LVDS_DUAL 0x5162 177181624Skmacy#define DEVICE_TYPE_LFP_LVDS_DUAL_HDCP 0x51e2 178181624Skmacy 179181624Skmacy#define DEVICE_CFG_NONE 0x00 180181624Skmacy#define DEVICE_CFG_12BIT_DVOB 0x01 181181624Skmacy#define DEVICE_CFG_12BIT_DVOC 0x02 182181624Skmacy#define DEVICE_CFG_24BIT_DVOBC 0x09 183181624Skmacy#define DEVICE_CFG_24BIT_DVOCB 0x0a 184181624Skmacy#define DEVICE_CFG_DUAL_DVOB 0x11 185181624Skmacy#define DEVICE_CFG_DUAL_DVOC 0x12 186181624Skmacy#define DEVICE_CFG_DUAL_DVOBC 0x13 187181624Skmacy#define DEVICE_CFG_DUAL_LINK_DVOBC 0x19 188181624Skmacy#define DEVICE_CFG_DUAL_LINK_DVOCB 0x1a 189181624Skmacy 190181624Skmacy#define DEVICE_WIRE_NONE 0x00 191181624Skmacy#define DEVICE_WIRE_DVOB 0x01 192181624Skmacy#define DEVICE_WIRE_DVOC 0x02 193181624Skmacy#define DEVICE_WIRE_DVOBC 0x03 194181624Skmacy#define DEVICE_WIRE_DVOBB 0x05 195181624Skmacy#define DEVICE_WIRE_DVOCC 0x06 196181624Skmacy#define DEVICE_WIRE_DVOB_MASTER 0x0d 197181624Skmacy#define DEVICE_WIRE_DVOC_MASTER 0x0e 198181624Skmacy 199181624Skmacy#define DEVICE_PORT_DVOA 0x00 /* none on 845+ */ 200181624Skmacy#define DEVICE_PORT_DVOB 0x01 201181624Skmacy#define DEVICE_PORT_DVOC 0x02 202181624Skmacy 203181624Skmacystruct child_device_config { 204181624Skmacy u16 handle; 205181624Skmacy u16 device_type; 206181624Skmacy u8 device_id[10]; /* ascii string */ 207181624Skmacy u16 addin_offset; 208181624Skmacy u8 dvo_port; /* See Device_PORT_* above */ 209181624Skmacy u8 i2c_pin; 210181624Skmacy u8 slave_addr; 211251767Sgibbs u8 ddc_pin; 212251767Sgibbs u16 edid_ptr; 213251767Sgibbs u8 dvo_cfg; /* See DEVICE_CFG_* above */ 214181624Skmacy u8 dvo2_port; 215181624Skmacy u8 i2c2_pin; 216181624Skmacy u8 slave2_addr; 217251767Sgibbs u8 ddc2_pin; 218251767Sgibbs u8 capabilities; 219181624Skmacy u8 dvo_wiring;/* See DEVICE_WIRE_* above */ 220181624Skmacy u8 dvo2_wiring; 221251767Sgibbs u16 extended_type; 222251767Sgibbs u8 dvo_function; 223181624Skmacy} __attribute__((packed)); 224181624Skmacy 225181624Skmacystruct bdb_general_definitions { 226181624Skmacy /* DDC GPIO */ 227181624Skmacy u8 crt_ddc_gmbus_pin; 228181624Skmacy 229181624Skmacy /* DPMS bits */ 230181624Skmacy u8 dpms_acpi:1; 231181624Skmacy u8 skip_boot_crt_detect:1; 232181624Skmacy u8 dpms_aim:1; 233183375Skmacy u8 rsvd1:5; /* finish byte */ 234183375Skmacy 235183375Skmacy /* boot device bits */ 236183375Skmacy u8 boot_display[2]; 237183375Skmacy u8 child_dev_size; 238183375Skmacy 239183375Skmacy /* 240183375Skmacy * Device info: 241183375Skmacy * If TV is present, it'll be at devices[0]. 242183375Skmacy * LVDS will be next, either devices[0] or [1], if present. 243183375Skmacy * On some platforms the number of device is 6. But could be as few as 244183375Skmacy * 4 if both TV and LVDS are missing. 245183375Skmacy * And the device num is related with the size of general definition 246183375Skmacy * block. It is obtained by using the following formula: 247183375Skmacy * number = (block_size - sizeof(bdb_general_definitions))/ 248251767Sgibbs * sizeof(child_device_config); 249251767Sgibbs */ 250181624Skmacy struct child_device_config devices[0]; 251181624Skmacy} __attribute__((packed)); 252181624Skmacy 253181624Skmacystruct bdb_lvds_options { 254181624Skmacy u8 panel_type; 255181624Skmacy u8 rsvd1; 256181624Skmacy /* LVDS capabilities, stored in a dword */ 257181624Skmacy u8 pfit_mode:2; 258181624Skmacy u8 pfit_text_mode_enhanced:1; 259181624Skmacy u8 pfit_gfx_mode_enhanced:1; 260181624Skmacy u8 pfit_ratio_auto:1; 261181624Skmacy u8 pixel_dither:1; 262181624Skmacy u8 lvds_edid:1; 263181624Skmacy u8 rsvd2:1; 264181624Skmacy u8 rsvd4; 265181624Skmacy} __attribute__((packed)); 266181624Skmacy 267181624Skmacy/* LFP pointer table contains entries to the struct below */ 268181624Skmacystruct bdb_lvds_lfp_data_ptr { 269183375Skmacy u16 fp_timing_offset; /* offsets are from start of bdb */ 270181624Skmacy u8 fp_table_size; 271181624Skmacy u16 dvo_timing_offset; 272181624Skmacy u8 dvo_table_size; 273181624Skmacy u16 panel_pnp_id_offset; 274181624Skmacy u8 pnp_table_size; 275181624Skmacy} __attribute__((packed)); 276181624Skmacy 277181624Skmacystruct bdb_lvds_lfp_data_ptrs { 278181624Skmacy u8 lvds_entries; /* followed by one or more lvds_data_ptr structs */ 279181624Skmacy struct bdb_lvds_lfp_data_ptr ptr[16]; 280181624Skmacy} __attribute__((packed)); 281181624Skmacy 282181624Skmacy/* LFP data has 3 blocks per entry */ 283181624Skmacystruct lvds_fp_timing { 284181624Skmacy u16 x_res; 285181624Skmacy u16 y_res; 286181624Skmacy u32 lvds_reg; 287181624Skmacy u32 lvds_reg_val; 288181624Skmacy u32 pp_on_reg; 289181624Skmacy u32 pp_on_reg_val; 290181624Skmacy u32 pp_off_reg; 291181624Skmacy u32 pp_off_reg_val; 292181624Skmacy u32 pp_cycle_reg; 293181624Skmacy u32 pp_cycle_reg_val; 294251767Sgibbs u32 pfit_reg; 295251767Sgibbs u32 pfit_reg_val; 296251767Sgibbs u16 terminator; 297251767Sgibbs} __attribute__((packed)); 298251767Sgibbs 299251767Sgibbsstruct lvds_dvo_timing { 300251767Sgibbs u16 clock; /**< In 10khz */ 301251767Sgibbs u8 hactive_lo; 302251767Sgibbs u8 hblank_lo; 303251767Sgibbs u8 hblank_hi:4; 304251767Sgibbs u8 hactive_hi:4; 305251767Sgibbs u8 vactive_lo; 306251767Sgibbs u8 vblank_lo; 307251767Sgibbs u8 vblank_hi:4; 308251767Sgibbs u8 vactive_hi:4; 309251767Sgibbs u8 hsync_off_lo; 310251767Sgibbs u8 hsync_pulse_width; 311251767Sgibbs u8 vsync_pulse_width:4; 312251767Sgibbs u8 vsync_off:4; 313251767Sgibbs u8 rsvd0:6; 314251767Sgibbs u8 hsync_off_hi:2; 315251767Sgibbs u8 h_image; 316251767Sgibbs u8 v_image; 317251767Sgibbs u8 max_hv; 318251767Sgibbs u8 h_border; 319251767Sgibbs u8 v_border; 320251767Sgibbs u8 rsvd1:3; 321251767Sgibbs u8 digital:2; 322251767Sgibbs u8 vsync_positive:1; 323251767Sgibbs u8 hsync_positive:1; 324251767Sgibbs u8 rsvd2:1; 325251767Sgibbs} __attribute__((packed)); 326251767Sgibbs 327251767Sgibbsstruct lvds_pnp_id { 328251767Sgibbs u16 mfg_name; 329251767Sgibbs u16 product_code; 330251767Sgibbs u32 serial; 331251767Sgibbs u8 mfg_week; 332251767Sgibbs u8 mfg_year; 333251767Sgibbs} __attribute__((packed)); 334251767Sgibbs 335251767Sgibbsstruct bdb_lvds_lfp_data_entry { 336251767Sgibbs struct lvds_fp_timing fp_timing; 337251767Sgibbs struct lvds_dvo_timing dvo_timing; 338251767Sgibbs struct lvds_pnp_id pnp_id; 339251767Sgibbs} __attribute__((packed)); 340251767Sgibbs 341251767Sgibbsstruct bdb_lvds_lfp_data { 342251767Sgibbs struct bdb_lvds_lfp_data_entry data[16]; 343251767Sgibbs} __attribute__((packed)); 344251767Sgibbs 345251767Sgibbsstruct aimdb_header { 346251767Sgibbs char signature[16]; 347251767Sgibbs char oem_device[20]; 348251767Sgibbs u16 aimdb_version; 349251767Sgibbs u16 aimdb_header_size; 350251767Sgibbs u16 aimdb_size; 351251767Sgibbs} __attribute__((packed)); 352251767Sgibbs 353251767Sgibbsstruct aimdb_block { 354251767Sgibbs u8 aimdb_id; 355251767Sgibbs u16 aimdb_size; 356251767Sgibbs} __attribute__((packed)); 357251767Sgibbs 358251767Sgibbsstruct vch_panel_data { 359251767Sgibbs u16 fp_timing_offset; 360251767Sgibbs u8 fp_timing_size; 361251767Sgibbs u16 dvo_timing_offset; 362251767Sgibbs u8 dvo_timing_size; 363251767Sgibbs u16 text_fitting_offset; 364251767Sgibbs u8 text_fitting_size; 365251767Sgibbs u16 graphics_fitting_offset; 366251767Sgibbs u8 graphics_fitting_size; 367251767Sgibbs} __attribute__((packed)); 368251767Sgibbs 369251767Sgibbsstruct vch_bdb_22 { 370251767Sgibbs struct aimdb_block aimdb_block; 371251767Sgibbs struct vch_panel_data panels[16]; 372251767Sgibbs} __attribute__((packed)); 373251767Sgibbs 374251767Sgibbsstruct bdb_sdvo_lvds_options { 375251767Sgibbs u8 panel_backlight; 376251767Sgibbs u8 h40_set_panel_type; 377251767Sgibbs u8 panel_type; 378251767Sgibbs u8 ssc_clk_freq; 379251767Sgibbs u16 als_low_trip; 380251767Sgibbs u16 als_high_trip; 381251767Sgibbs u8 sclalarcoeff_tab_row_num; 382251767Sgibbs u8 sclalarcoeff_tab_row_size; 383251767Sgibbs u8 coefficient[8]; 384251767Sgibbs u8 panel_misc_bits_1; 385251767Sgibbs u8 panel_misc_bits_2; 386251767Sgibbs u8 panel_misc_bits_3; 387251767Sgibbs u8 panel_misc_bits_4; 388251767Sgibbs} __attribute__((packed)); 389251767Sgibbs 390251767Sgibbs 391251767Sgibbs#define BDB_DRIVER_FEATURE_NO_LVDS 0 392251767Sgibbs#define BDB_DRIVER_FEATURE_INT_LVDS 1 393251767Sgibbs#define BDB_DRIVER_FEATURE_SDVO_LVDS 2 394251767Sgibbs#define BDB_DRIVER_FEATURE_EDP 3 395251767Sgibbs 396251767Sgibbsstruct bdb_driver_features { 397251767Sgibbs u8 boot_dev_algorithm:1; 398251767Sgibbs u8 block_display_switch:1; 399251767Sgibbs u8 allow_display_switch:1; 400251767Sgibbs u8 hotplug_dvo:1; 401251767Sgibbs u8 dual_view_zoom:1; 402181624Skmacy u8 int15h_hook:1; 403181624Skmacy u8 sprite_in_clone:1; 404181624Skmacy u8 primary_lfp_id:1; 405181624Skmacy 406181624Skmacy u16 boot_mode_x; 407181624Skmacy u16 boot_mode_y; 408181624Skmacy u8 boot_mode_bpp; 409181624Skmacy u8 boot_mode_refresh; 410181624Skmacy 411181624Skmacy u16 enable_lfp_primary:1; 412181624Skmacy u16 selective_mode_pruning:1; 413 u16 dual_frequency:1; 414 u16 render_clock_freq:1; /* 0: high freq; 1: low freq */ 415 u16 nt_clone_support:1; 416 u16 power_scheme_ui:1; /* 0: CUI; 1: 3rd party */ 417 u16 sprite_display_assign:1; /* 0: secondary; 1: primary */ 418 u16 cui_aspect_scaling:1; 419 u16 preserve_aspect_ratio:1; 420 u16 sdvo_device_power_down:1; 421 u16 crt_hotplug:1; 422 u16 lvds_config:2; 423 u16 tv_hotplug:1; 424 u16 hdmi_config:2; 425 426 u8 static_display:1; 427 u8 reserved2:7; 428 u16 legacy_crt_max_x; 429 u16 legacy_crt_max_y; 430 u8 legacy_crt_max_refresh; 431 432 u8 hdmi_termination; 433 u8 custom_vbt_version; 434} __attribute__((packed)); 435 436#define EDP_18BPP 0 437#define EDP_24BPP 1 438#define EDP_30BPP 2 439#define EDP_RATE_1_62 0 440#define EDP_RATE_2_7 1 441#define EDP_LANE_1 0 442#define EDP_LANE_2 1 443#define EDP_LANE_4 3 444#define EDP_PREEMPHASIS_NONE 0 445#define EDP_PREEMPHASIS_3_5dB 1 446#define EDP_PREEMPHASIS_6dB 2 447#define EDP_PREEMPHASIS_9_5dB 3 448#define EDP_VSWING_0_4V 0 449#define EDP_VSWING_0_6V 1 450#define EDP_VSWING_0_8V 2 451#define EDP_VSWING_1_2V 3 452 453struct edp_power_seq { 454 u16 t1_t3; 455 u16 t8; 456 u16 t9; 457 u16 t10; 458 u16 t11_t12; 459} __attribute__ ((packed)); 460 461struct edp_link_params { 462 u8 rate:4; 463 u8 lanes:4; 464 u8 preemphasis:4; 465 u8 vswing:4; 466} __attribute__ ((packed)); 467 468struct bdb_edp { 469 struct edp_power_seq power_seqs[16]; 470 u32 color_depth; 471 struct edp_link_params link_params[16]; 472 u32 sdrrs_msa_timing_delay; 473 474 /* ith bit indicates enabled/disabled for (i+1)th panel */ 475 u16 edp_s3d_feature; 476 u16 edp_t3_optimization; 477} __attribute__ ((packed)); 478 479void intel_setup_bios(struct drm_device *dev); 480bool intel_parse_bios(struct drm_device *dev); 481 482/* 483 * Driver<->VBIOS interaction occurs through scratch bits in 484 * GR18 & SWF*. 485 */ 486 487/* GR18 bits are set on display switch and hotkey events */ 488#define GR18_DRIVER_SWITCH_EN (1<<7) /* 0: VBIOS control, 1: driver control */ 489#define GR18_HOTKEY_MASK 0x78 /* See also SWF4 15:0 */ 490#define GR18_HK_NONE (0x0<<3) 491#define GR18_HK_LFP_STRETCH (0x1<<3) 492#define GR18_HK_TOGGLE_DISP (0x2<<3) 493#define GR18_HK_DISP_SWITCH (0x4<<3) /* see SWF14 15:0 for what to enable */ 494#define GR18_HK_POPUP_DISABLED (0x6<<3) 495#define GR18_HK_POPUP_ENABLED (0x7<<3) 496#define GR18_HK_PFIT (0x8<<3) 497#define GR18_HK_APM_CHANGE (0xa<<3) 498#define GR18_HK_MULTIPLE (0xc<<3) 499#define GR18_USER_INT_EN (1<<2) 500#define GR18_A0000_FLUSH_EN (1<<1) 501#define GR18_SMM_EN (1<<0) 502 503/* Set by driver, cleared by VBIOS */ 504#define SWF00_YRES_SHIFT 16 505#define SWF00_XRES_SHIFT 0 506#define SWF00_RES_MASK 0xffff 507 508/* Set by VBIOS at boot time and driver at runtime */ 509#define SWF01_TV2_FORMAT_SHIFT 8 510#define SWF01_TV1_FORMAT_SHIFT 0 511#define SWF01_TV_FORMAT_MASK 0xffff 512 513#define SWF10_VBIOS_BLC_I2C_EN (1<<29) 514#define SWF10_GTT_OVERRIDE_EN (1<<28) 515#define SWF10_LFP_DPMS_OVR (1<<27) /* override DPMS on display switch */ 516#define SWF10_ACTIVE_TOGGLE_LIST_MASK (7<<24) 517#define SWF10_OLD_TOGGLE 0x0 518#define SWF10_TOGGLE_LIST_1 0x1 519#define SWF10_TOGGLE_LIST_2 0x2 520#define SWF10_TOGGLE_LIST_3 0x3 521#define SWF10_TOGGLE_LIST_4 0x4 522#define SWF10_PANNING_EN (1<<23) 523#define SWF10_DRIVER_LOADED (1<<22) 524#define SWF10_EXTENDED_DESKTOP (1<<21) 525#define SWF10_EXCLUSIVE_MODE (1<<20) 526#define SWF10_OVERLAY_EN (1<<19) 527#define SWF10_PLANEB_HOLDOFF (1<<18) 528#define SWF10_PLANEA_HOLDOFF (1<<17) 529#define SWF10_VGA_HOLDOFF (1<<16) 530#define SWF10_ACTIVE_DISP_MASK 0xffff 531#define SWF10_PIPEB_LFP2 (1<<15) 532#define SWF10_PIPEB_EFP2 (1<<14) 533#define SWF10_PIPEB_TV2 (1<<13) 534#define SWF10_PIPEB_CRT2 (1<<12) 535#define SWF10_PIPEB_LFP (1<<11) 536#define SWF10_PIPEB_EFP (1<<10) 537#define SWF10_PIPEB_TV (1<<9) 538#define SWF10_PIPEB_CRT (1<<8) 539#define SWF10_PIPEA_LFP2 (1<<7) 540#define SWF10_PIPEA_EFP2 (1<<6) 541#define SWF10_PIPEA_TV2 (1<<5) 542#define SWF10_PIPEA_CRT2 (1<<4) 543#define SWF10_PIPEA_LFP (1<<3) 544#define SWF10_PIPEA_EFP (1<<2) 545#define SWF10_PIPEA_TV (1<<1) 546#define SWF10_PIPEA_CRT (1<<0) 547 548#define SWF11_MEMORY_SIZE_SHIFT 16 549#define SWF11_SV_TEST_EN (1<<15) 550#define SWF11_IS_AGP (1<<14) 551#define SWF11_DISPLAY_HOLDOFF (1<<13) 552#define SWF11_DPMS_REDUCED (1<<12) 553#define SWF11_IS_VBE_MODE (1<<11) 554#define SWF11_PIPEB_ACCESS (1<<10) /* 0 here means pipe a */ 555#define SWF11_DPMS_MASK 0x07 556#define SWF11_DPMS_OFF (1<<2) 557#define SWF11_DPMS_SUSPEND (1<<1) 558#define SWF11_DPMS_STANDBY (1<<0) 559#define SWF11_DPMS_ON 0 560 561#define SWF14_GFX_PFIT_EN (1<<31) 562#define SWF14_TEXT_PFIT_EN (1<<30) 563#define SWF14_LID_STATUS_CLOSED (1<<29) /* 0 here means open */ 564#define SWF14_POPUP_EN (1<<28) 565#define SWF14_DISPLAY_HOLDOFF (1<<27) 566#define SWF14_DISP_DETECT_EN (1<<26) 567#define SWF14_DOCKING_STATUS_DOCKED (1<<25) /* 0 here means undocked */ 568#define SWF14_DRIVER_STATUS (1<<24) 569#define SWF14_OS_TYPE_WIN9X (1<<23) 570#define SWF14_OS_TYPE_WINNT (1<<22) 571/* 21:19 rsvd */ 572#define SWF14_PM_TYPE_MASK 0x00070000 573#define SWF14_PM_ACPI_VIDEO (0x4 << 16) 574#define SWF14_PM_ACPI (0x3 << 16) 575#define SWF14_PM_APM_12 (0x2 << 16) 576#define SWF14_PM_APM_11 (0x1 << 16) 577#define SWF14_HK_REQUEST_MASK 0x0000ffff /* see GR18 6:3 for event type */ 578 /* if GR18 indicates a display switch */ 579#define SWF14_DS_PIPEB_LFP2_EN (1<<15) 580#define SWF14_DS_PIPEB_EFP2_EN (1<<14) 581#define SWF14_DS_PIPEB_TV2_EN (1<<13) 582#define SWF14_DS_PIPEB_CRT2_EN (1<<12) 583#define SWF14_DS_PIPEB_LFP_EN (1<<11) 584#define SWF14_DS_PIPEB_EFP_EN (1<<10) 585#define SWF14_DS_PIPEB_TV_EN (1<<9) 586#define SWF14_DS_PIPEB_CRT_EN (1<<8) 587#define SWF14_DS_PIPEA_LFP2_EN (1<<7) 588#define SWF14_DS_PIPEA_EFP2_EN (1<<6) 589#define SWF14_DS_PIPEA_TV2_EN (1<<5) 590#define SWF14_DS_PIPEA_CRT2_EN (1<<4) 591#define SWF14_DS_PIPEA_LFP_EN (1<<3) 592#define SWF14_DS_PIPEA_EFP_EN (1<<2) 593#define SWF14_DS_PIPEA_TV_EN (1<<1) 594#define SWF14_DS_PIPEA_CRT_EN (1<<0) 595 /* if GR18 indicates a panel fitting request */ 596#define SWF14_PFIT_EN (1<<0) /* 0 means disable */ 597 /* if GR18 indicates an APM change request */ 598#define SWF14_APM_HIBERNATE 0x4 599#define SWF14_APM_SUSPEND 0x3 600#define SWF14_APM_STANDBY 0x1 601#define SWF14_APM_RESTORE 0x0 602 603/* Add the device class for LFP, TV, HDMI */ 604#define DEVICE_TYPE_INT_LFP 0x1022 605#define DEVICE_TYPE_INT_TV 0x1009 606#define DEVICE_TYPE_HDMI 0x60D2 607#define DEVICE_TYPE_DP 0x68C6 608#define DEVICE_TYPE_eDP 0x78C6 609 610/* define the DVO port for HDMI output type */ 611#define DVO_B 1 612#define DVO_C 2 613#define DVO_D 3 614 615/* define the PORT for DP output type */ 616#define PORT_IDPB 7 617#define PORT_IDPC 8 618#define PORT_IDPD 9 619 620#endif /* _I830_BIOS_H_ */ 621