drm_mode.h revision 272461
1321936Shselasky/* 2321936Shselasky * Copyright (c) 2007 Dave Airlie <airlied@linux.ie> 3321936Shselasky * Copyright (c) 2007 Jakob Bornecrantz <wallbraker@gmail.com> 4321936Shselasky * Copyright (c) 2008 Red Hat Inc. 5321936Shselasky * Copyright (c) 2007-2008 Tungsten Graphics, Inc., Cedar Park, TX., USA 6321936Shselasky * Copyright (c) 2007-2008 Intel Corporation 7321936Shselasky * 8321936Shselasky * Permission is hereby granted, free of charge, to any person obtaining a 9321936Shselasky * copy of this software and associated documentation files (the "Software"), 10321936Shselasky * to deal in the Software without restriction, including without limitation 11321936Shselasky * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12321936Shselasky * and/or sell copies of the Software, and to permit persons to whom the 13321936Shselasky * Software is furnished to do so, subject to the following conditions: 14321936Shselasky * 15321936Shselasky * The above copyright notice and this permission notice shall be included in 16321936Shselasky * all copies or substantial portions of the Software. 17321936Shselasky * 18321936Shselasky * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19321936Shselasky * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20321936Shselasky * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 21321936Shselasky * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22321936Shselasky * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 23321936Shselasky * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 24321936Shselasky * IN THE SOFTWARE. 25321936Shselasky * 26321936Shselasky * $FreeBSD: releng/10.1/sys/dev/drm2/drm_mode.h 235783 2012-05-22 11:07:44Z kib $ 27321936Shselasky */ 28321936Shselasky 29321936Shselasky#ifndef _DRM_MODE_H 30321936Shselasky#define _DRM_MODE_H 31321936Shselasky 32321936Shselasky#define DRM_DISPLAY_INFO_LEN 32 33321936Shselasky#define DRM_CONNECTOR_NAME_LEN 32 34321936Shselasky#define DRM_DISPLAY_MODE_LEN 32 35321936Shselasky#define DRM_PROP_NAME_LEN 32 36321936Shselasky 37321936Shselasky#define DRM_MODE_TYPE_BUILTIN (1<<0) 38321936Shselasky#define DRM_MODE_TYPE_CLOCK_C ((1<<1) | DRM_MODE_TYPE_BUILTIN) 39321936Shselasky#define DRM_MODE_TYPE_CRTC_C ((1<<2) | DRM_MODE_TYPE_BUILTIN) 40321936Shselasky#define DRM_MODE_TYPE_PREFERRED (1<<3) 41321936Shselasky#define DRM_MODE_TYPE_DEFAULT (1<<4) 42321936Shselasky#define DRM_MODE_TYPE_USERDEF (1<<5) 43321936Shselasky#define DRM_MODE_TYPE_DRIVER (1<<6) 44321936Shselasky 45321936Shselasky/* Video mode flags */ 46321936Shselasky/* bit compatible with the xorg definitions. */ 47321936Shselasky#define DRM_MODE_FLAG_PHSYNC (1<<0) 48321936Shselasky#define DRM_MODE_FLAG_NHSYNC (1<<1) 49321936Shselasky#define DRM_MODE_FLAG_PVSYNC (1<<2) 50321936Shselasky#define DRM_MODE_FLAG_NVSYNC (1<<3) 51321936Shselasky#define DRM_MODE_FLAG_INTERLACE (1<<4) 52321936Shselasky#define DRM_MODE_FLAG_DBLSCAN (1<<5) 53321936Shselasky#define DRM_MODE_FLAG_CSYNC (1<<6) 54321936Shselasky#define DRM_MODE_FLAG_PCSYNC (1<<7) 55321936Shselasky#define DRM_MODE_FLAG_NCSYNC (1<<8) 56321936Shselasky#define DRM_MODE_FLAG_HSKEW (1<<9) /* hskew provided */ 57321936Shselasky#define DRM_MODE_FLAG_BCAST (1<<10) 58321936Shselasky#define DRM_MODE_FLAG_PIXMUX (1<<11) 59321936Shselasky#define DRM_MODE_FLAG_DBLCLK (1<<12) 60321936Shselasky#define DRM_MODE_FLAG_CLKDIV2 (1<<13) 61321936Shselasky 62321936Shselasky/* DPMS flags */ 63321936Shselasky/* bit compatible with the xorg definitions. */ 64321936Shselasky#define DRM_MODE_DPMS_ON 0 65321936Shselasky#define DRM_MODE_DPMS_STANDBY 1 66321936Shselasky#define DRM_MODE_DPMS_SUSPEND 2 67321936Shselasky#define DRM_MODE_DPMS_OFF 3 68321936Shselasky 69321936Shselasky/* Scaling mode options */ 70321936Shselasky#define DRM_MODE_SCALE_NONE 0 /* Unmodified timing (display or 71321936Shselasky software can still scale) */ 72321936Shselasky#define DRM_MODE_SCALE_FULLSCREEN 1 /* Full screen, ignore aspect */ 73321936Shselasky#define DRM_MODE_SCALE_CENTER 2 /* Centered, no scaling */ 74321936Shselasky#define DRM_MODE_SCALE_ASPECT 3 /* Full screen, preserve aspect */ 75321936Shselasky 76321936Shselasky/* Dithering mode options */ 77321936Shselasky#define DRM_MODE_DITHERING_OFF 0 78321936Shselasky#define DRM_MODE_DITHERING_ON 1 79321936Shselasky#define DRM_MODE_DITHERING_AUTO 2 80321936Shselasky 81321936Shselasky/* Dirty info options */ 82321936Shselasky#define DRM_MODE_DIRTY_OFF 0 83321936Shselasky#define DRM_MODE_DIRTY_ON 1 84321936Shselasky#define DRM_MODE_DIRTY_ANNOTATE 2 85321936Shselasky 86321936Shselaskystruct drm_mode_modeinfo { 87321936Shselasky uint32_t clock; 88321936Shselasky uint16_t hdisplay, hsync_start, hsync_end, htotal, hskew; 89321936Shselasky uint16_t vdisplay, vsync_start, vsync_end, vtotal, vscan; 90321936Shselasky 91321936Shselasky uint32_t vrefresh; 92321936Shselasky 93321936Shselasky uint32_t flags; 94321936Shselasky uint32_t type; 95321936Shselasky char name[DRM_DISPLAY_MODE_LEN]; 96321936Shselasky}; 97321936Shselasky 98321936Shselaskystruct drm_mode_card_res { 99321936Shselasky uint64_t fb_id_ptr; 100321936Shselasky uint64_t crtc_id_ptr; 101321936Shselasky uint64_t connector_id_ptr; 102321936Shselasky uint64_t encoder_id_ptr; 103321936Shselasky uint32_t count_fbs; 104321936Shselasky uint32_t count_crtcs; 105321936Shselasky uint32_t count_connectors; 106321936Shselasky uint32_t count_encoders; 107321936Shselasky uint32_t min_width, max_width; 108321936Shselasky uint32_t min_height, max_height; 109321936Shselasky}; 110321936Shselasky 111321936Shselaskystruct drm_mode_crtc { 112321936Shselasky uint64_t set_connectors_ptr; 113321936Shselasky uint32_t count_connectors; 114321936Shselasky 115321936Shselasky uint32_t crtc_id; /**< Id */ 116321936Shselasky uint32_t fb_id; /**< Id of framebuffer */ 117321936Shselasky 118321936Shselasky uint32_t x, y; /**< Position on the frameuffer */ 119321936Shselasky 120321936Shselasky uint32_t gamma_size; 121321936Shselasky uint32_t mode_valid; 122321936Shselasky struct drm_mode_modeinfo mode; 123321936Shselasky}; 124321936Shselasky 125321936Shselasky#define DRM_MODE_PRESENT_TOP_FIELD (1<<0) 126321936Shselasky#define DRM_MODE_PRESENT_BOTTOM_FIELD (1<<1) 127321936Shselasky 128321936Shselasky/* Planes blend with or override other bits on the CRTC */ 129321936Shselaskystruct drm_mode_set_plane { 130321936Shselasky uint32_t plane_id; 131321936Shselasky uint32_t crtc_id; 132321936Shselasky uint32_t fb_id; /* fb object contains surface format type */ 133321936Shselasky uint32_t flags; /* see above flags */ 134321936Shselasky 135321936Shselasky /* Signed dest location allows it to be partially off screen */ 136321936Shselasky int32_t crtc_x, crtc_y; 137321936Shselasky uint32_t crtc_w, crtc_h; 138321936Shselasky 139321936Shselasky /* Source values are 16.16 fixed point */ 140321936Shselasky uint32_t src_x, src_y; 141321936Shselasky uint32_t src_h, src_w; 142321936Shselasky}; 143321936Shselasky 144321936Shselaskystruct drm_mode_get_plane { 145321936Shselasky uint32_t plane_id; 146321936Shselasky 147321936Shselasky uint32_t crtc_id; 148321936Shselasky uint32_t fb_id; 149321936Shselasky 150321936Shselasky uint32_t possible_crtcs; 151321936Shselasky uint32_t gamma_size; 152321936Shselasky 153321936Shselasky uint32_t count_format_types; 154321936Shselasky uint64_t format_type_ptr; 155321936Shselasky}; 156321936Shselasky 157321936Shselaskystruct drm_mode_get_plane_res { 158321936Shselasky uint64_t plane_id_ptr; 159321936Shselasky uint32_t count_planes; 160321936Shselasky}; 161321936Shselasky 162321936Shselasky#define DRM_MODE_ENCODER_NONE 0 163321936Shselasky#define DRM_MODE_ENCODER_DAC 1 164321936Shselasky#define DRM_MODE_ENCODER_TMDS 2 165321936Shselasky#define DRM_MODE_ENCODER_LVDS 3 166321936Shselasky#define DRM_MODE_ENCODER_TVDAC 4 167321936Shselasky 168321936Shselaskystruct drm_mode_get_encoder { 169321936Shselasky uint32_t encoder_id; 170321936Shselasky uint32_t encoder_type; 171321936Shselasky 172321936Shselasky uint32_t crtc_id; /**< Id of crtc */ 173321936Shselasky 174321936Shselasky uint32_t possible_crtcs; 175321936Shselasky uint32_t possible_clones; 176321936Shselasky}; 177321936Shselasky 178321936Shselasky/* This is for connectors with multiple signal types. */ 179321936Shselasky/* Try to match DRM_MODE_CONNECTOR_X as closely as possible. */ 180321936Shselasky#define DRM_MODE_SUBCONNECTOR_Automatic 0 181321936Shselasky#define DRM_MODE_SUBCONNECTOR_Unknown 0 182321936Shselasky#define DRM_MODE_SUBCONNECTOR_DVID 3 183321936Shselasky#define DRM_MODE_SUBCONNECTOR_DVIA 4 184321936Shselasky#define DRM_MODE_SUBCONNECTOR_Composite 5 185321936Shselasky#define DRM_MODE_SUBCONNECTOR_SVIDEO 6 186321936Shselasky#define DRM_MODE_SUBCONNECTOR_Component 8 187321936Shselasky#define DRM_MODE_SUBCONNECTOR_SCART 9 188321936Shselasky 189321936Shselasky#define DRM_MODE_CONNECTOR_Unknown 0 190321936Shselasky#define DRM_MODE_CONNECTOR_VGA 1 191321936Shselasky#define DRM_MODE_CONNECTOR_DVII 2 192321936Shselasky#define DRM_MODE_CONNECTOR_DVID 3 193321936Shselasky#define DRM_MODE_CONNECTOR_DVIA 4 194321936Shselasky#define DRM_MODE_CONNECTOR_Composite 5 195321936Shselasky#define DRM_MODE_CONNECTOR_SVIDEO 6 196321936Shselasky#define DRM_MODE_CONNECTOR_LVDS 7 197321936Shselasky#define DRM_MODE_CONNECTOR_Component 8 198321936Shselasky#define DRM_MODE_CONNECTOR_9PinDIN 9 199321936Shselasky#define DRM_MODE_CONNECTOR_DisplayPort 10 200321936Shselasky#define DRM_MODE_CONNECTOR_HDMIA 11 201321936Shselasky#define DRM_MODE_CONNECTOR_HDMIB 12 202321936Shselasky#define DRM_MODE_CONNECTOR_TV 13 203321936Shselasky#define DRM_MODE_CONNECTOR_eDP 14 204321936Shselasky 205321936Shselaskystruct drm_mode_get_connector { 206321936Shselasky 207321936Shselasky uint64_t encoders_ptr; 208321936Shselasky uint64_t modes_ptr; 209321936Shselasky uint64_t props_ptr; 210321936Shselasky uint64_t prop_values_ptr; 211321936Shselasky 212321936Shselasky uint32_t count_modes; 213321936Shselasky uint32_t count_props; 214321936Shselasky uint32_t count_encoders; 215321936Shselasky 216321936Shselasky uint32_t encoder_id; /**< Current Encoder */ 217321936Shselasky uint32_t connector_id; /**< Id */ 218321936Shselasky uint32_t connector_type; 219321936Shselasky uint32_t connector_type_id; 220321936Shselasky 221321936Shselasky uint32_t connection; 222321936Shselasky uint32_t mm_width, mm_height; /**< HxW in millimeters */ 223321936Shselasky uint32_t subpixel; 224321936Shselasky}; 225321936Shselasky 226321936Shselasky#define DRM_MODE_PROP_PENDING (1<<0) 227321936Shselasky#define DRM_MODE_PROP_RANGE (1<<1) 228321936Shselasky#define DRM_MODE_PROP_IMMUTABLE (1<<2) 229321936Shselasky#define DRM_MODE_PROP_ENUM (1<<3) /* enumerated type with text strings */ 230321936Shselasky#define DRM_MODE_PROP_BLOB (1<<4) 231321936Shselasky 232321936Shselaskystruct drm_mode_property_enum { 233321936Shselasky uint64_t value; 234321936Shselasky char name[DRM_PROP_NAME_LEN]; 235321936Shselasky}; 236321936Shselasky 237321936Shselaskystruct drm_mode_get_property { 238321936Shselasky uint64_t values_ptr; /* values and blob lengths */ 239321936Shselasky uint64_t enum_blob_ptr; /* enum and blob id ptrs */ 240321936Shselasky 241321936Shselasky uint32_t prop_id; 242321936Shselasky uint32_t flags; 243321936Shselasky char name[DRM_PROP_NAME_LEN]; 244321936Shselasky 245321936Shselasky uint32_t count_values; 246321936Shselasky uint32_t count_enum_blobs; 247321936Shselasky}; 248321936Shselasky 249321936Shselaskystruct drm_mode_connector_set_property { 250321936Shselasky uint64_t value; 251321936Shselasky uint32_t prop_id; 252321936Shselasky uint32_t connector_id; 253321936Shselasky}; 254321936Shselasky 255321936Shselaskystruct drm_mode_get_blob { 256321936Shselasky uint32_t blob_id; 257321936Shselasky uint32_t length; 258321936Shselasky uint64_t data; 259321936Shselasky}; 260321936Shselasky 261321936Shselaskystruct drm_mode_fb_cmd { 262321936Shselasky uint32_t fb_id; 263321936Shselasky uint32_t width, height; 264321936Shselasky uint32_t pitch; 265321936Shselasky uint32_t bpp; 266321936Shselasky uint32_t depth; 267321936Shselasky /* driver specific handle */ 268321936Shselasky uint32_t handle; 269321936Shselasky}; 270321936Shselasky 271321936Shselasky#define DRM_MODE_FB_INTERLACED (1<<0 /* for interlaced framebuffers */ 272321936Shselasky 273321936Shselaskystruct drm_mode_fb_cmd2 { 274321936Shselasky uint32_t fb_id; 275321936Shselasky uint32_t width, height; 276321936Shselasky uint32_t pixel_format; /* fourcc code from drm_fourcc.h */ 277321936Shselasky uint32_t flags; /* see above flags */ 278321936Shselasky 279321936Shselasky /* 280321936Shselasky * In case of planar formats, this ioctl allows up to 4 281321936Shselasky * buffer objects with offets and pitches per plane. 282321936Shselasky * The pitch and offset order is dictated by the fourcc, 283321936Shselasky * e.g. NV12 (http://fourcc.org/yuv.php#NV12) is described as: 284321936Shselasky * 285321936Shselasky * YUV 4:2:0 image with a plane of 8 bit Y samples 286321936Shselasky * followed by an interleaved U/V plane containing 287321936Shselasky * 8 bit 2x2 subsampled colour difference samples. 288321936Shselasky * 289321936Shselasky * So it would consist of Y as offset[0] and UV as 290321936Shselasky * offeset[1]. Note that offset[0] will generally 291321936Shselasky * be 0. 292321936Shselasky */ 293321936Shselasky uint32_t handles[4]; 294321936Shselasky uint32_t pitches[4]; /* pitch for each plane */ 295321936Shselasky uint32_t offsets[4]; /* offset of each plane */ 296321936Shselasky}; 297321936Shselasky 298321936Shselasky#define DRM_MODE_FB_DIRTY_ANNOTATE_COPY 0x01 299321936Shselasky#define DRM_MODE_FB_DIRTY_ANNOTATE_FILL 0x02 300321936Shselasky#define DRM_MODE_FB_DIRTY_FLAGS 0x03 301321936Shselasky 302321936Shselasky#define DRM_MODE_FB_DIRTY_MAX_CLIPS 256 303321936Shselasky 304321936Shselasky/* 305321936Shselasky * Mark a region of a framebuffer as dirty. 306321936Shselasky * 307321936Shselasky * Some hardware does not automatically update display contents 308321936Shselasky * as a hardware or software draw to a framebuffer. This ioctl 309321936Shselasky * allows userspace to tell the kernel and the hardware what 310321936Shselasky * regions of the framebuffer have changed. 311321936Shselasky * 312321936Shselasky * The kernel or hardware is free to update more then just the 313321936Shselasky * region specified by the clip rects. The kernel or hardware 314321936Shselasky * may also delay and/or coalesce several calls to dirty into a 315321936Shselasky * single update. 316321936Shselasky * 317321936Shselasky * Userspace may annotate the updates, the annotates are a 318321936Shselasky * promise made by the caller that the change is either a copy 319321936Shselasky * of pixels or a fill of a single color in the region specified. 320321936Shselasky * 321321936Shselasky * If the DRM_MODE_FB_DIRTY_ANNOTATE_COPY flag is given then 322321936Shselasky * the number of updated regions are half of num_clips given, 323321936Shselasky * where the clip rects are paired in src and dst. The width and 324321936Shselasky * height of each one of the pairs must match. 325321936Shselasky * 326321936Shselasky * If the DRM_MODE_FB_DIRTY_ANNOTATE_FILL flag is given the caller 327321936Shselasky * promises that the region specified of the clip rects is filled 328321936Shselasky * completely with a single color as given in the color argument. 329321936Shselasky */ 330321936Shselasky 331321936Shselaskystruct drm_mode_fb_dirty_cmd { 332321936Shselasky uint32_t fb_id; 333321936Shselasky uint32_t flags; 334321936Shselasky uint32_t color; 335321936Shselasky uint32_t num_clips; 336321936Shselasky uint64_t clips_ptr; 337321936Shselasky}; 338321936Shselasky 339321936Shselaskystruct drm_mode_mode_cmd { 340321936Shselasky uint32_t connector_id; 341321936Shselasky struct drm_mode_modeinfo mode; 342321936Shselasky}; 343321936Shselasky 344321936Shselasky#define DRM_MODE_CURSOR_BO (1<<0) 345321936Shselasky#define DRM_MODE_CURSOR_MOVE (1<<1) 346321936Shselasky 347321936Shselasky/* 348321936Shselasky * depending on the value in flags diffrent members are used. 349321936Shselasky * 350321936Shselasky * CURSOR_BO uses 351321936Shselasky * crtc 352321936Shselasky * width 353321936Shselasky * height 354321936Shselasky * handle - if 0 turns the cursor of 355321936Shselasky * 356321936Shselasky * CURSOR_MOVE uses 357321936Shselasky * crtc 358321936Shselasky * x 359321936Shselasky * y 360321936Shselasky */ 361321936Shselaskystruct drm_mode_cursor { 362321936Shselasky uint32_t flags; 363321936Shselasky uint32_t crtc_id; 364321936Shselasky int32_t x; 365321936Shselasky int32_t y; 366321936Shselasky uint32_t width; 367321936Shselasky uint32_t height; 368321936Shselasky /* driver specific handle */ 369321936Shselasky uint32_t handle; 370321936Shselasky}; 371321936Shselasky 372321936Shselaskystruct drm_mode_crtc_lut { 373321936Shselasky uint32_t crtc_id; 374321936Shselasky uint32_t gamma_size; 375321936Shselasky 376321936Shselasky /* pointers to arrays */ 377321936Shselasky uint64_t red; 378321936Shselasky uint64_t green; 379321936Shselasky uint64_t blue; 380321936Shselasky}; 381321936Shselasky 382321936Shselasky#define DRM_MODE_PAGE_FLIP_EVENT 0x01 383321936Shselasky#define DRM_MODE_PAGE_FLIP_FLAGS DRM_MODE_PAGE_FLIP_EVENT 384321936Shselasky 385321936Shselasky/* 386321936Shselasky * Request a page flip on the specified crtc. 387321936Shselasky * 388321936Shselasky * This ioctl will ask KMS to schedule a page flip for the specified 389321936Shselasky * crtc. Once any pending rendering targeting the specified fb (as of 390321936Shselasky * ioctl time) has completed, the crtc will be reprogrammed to display 391321936Shselasky * that fb after the next vertical refresh. The ioctl returns 392321936Shselasky * immediately, but subsequent rendering to the current fb will block 393321936Shselasky * in the execbuffer ioctl until the page flip happens. If a page 394321936Shselasky * flip is already pending as the ioctl is called, EBUSY will be 395321936Shselasky * returned. 396321936Shselasky * 397321936Shselasky * The ioctl supports one flag, DRM_MODE_PAGE_FLIP_EVENT, which will 398321936Shselasky * request that drm sends back a vblank event (see drm.h: struct 399321936Shselasky * drm_event_vblank) when the page flip is done. The user_data field 400321936Shselasky * passed in with this ioctl will be returned as the user_data field 401321936Shselasky * in the vblank event struct. 402321936Shselasky * 403321936Shselasky * The reserved field must be zero until we figure out something 404321936Shselasky * clever to use it for. 405321936Shselasky */ 406321936Shselasky 407321936Shselaskystruct drm_mode_crtc_page_flip { 408321936Shselasky uint32_t crtc_id; 409321936Shselasky uint32_t fb_id; 410321936Shselasky uint32_t flags; 411321936Shselasky uint32_t reserved; 412321936Shselasky uint64_t user_data; 413321936Shselasky}; 414321936Shselasky 415321936Shselasky/* create a dumb scanout buffer */ 416321936Shselaskystruct drm_mode_create_dumb { 417321936Shselasky uint32_t height; 418321936Shselasky uint32_t width; 419321936Shselasky uint32_t bpp; 420321936Shselasky uint32_t flags; 421321936Shselasky /* handle, pitch, size will be returned */ 422321936Shselasky uint32_t handle; 423321936Shselasky uint32_t pitch; 424321936Shselasky uint64_t size; 425321936Shselasky}; 426321936Shselasky 427321936Shselasky/* set up for mmap of a dumb scanout buffer */ 428321936Shselaskystruct drm_mode_map_dumb { 429321936Shselasky /** Handle for the object being mapped. */ 430321936Shselasky uint32_t handle; 431321936Shselasky uint32_t pad; 432321936Shselasky /** 433321936Shselasky * Fake offset to use for subsequent mmap call 434321936Shselasky * 435321936Shselasky * This is a fixed-size type for 32/64 compatibility. 436321936Shselasky */ 437321936Shselasky uint64_t offset; 438321936Shselasky}; 439321936Shselasky 440321936Shselaskystruct drm_mode_destroy_dumb { 441321936Shselasky uint32_t handle; 442321936Shselasky}; 443321936Shselasky 444321936Shselasky#endif 445321936Shselasky