radeon_irq.c revision 152909 
1/* radeon_irq.c -- IRQ handling for radeon -*- linux-c -*- */
2/*-
3 * Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
4 *
5 * The Weather Channel (TM) funded Tungsten Graphics to develop the
6 * initial release of the Radeon 8500 driver under the XFree86 license.
7 * This notice must be preserved.
8 *
9 * Permission is hereby granted, free of charge, to any person obtaining a
10 * copy of this software and associated documentation files (the "Software"),
11 * to deal in the Software without restriction, including without limitation
12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
13 * and/or sell copies of the Software, and to permit persons to whom the
14 * Software is furnished to do so, subject to the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the next
17 * paragraph) shall be included in all copies or substantial portions of the
18 * Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
23 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
24 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
25 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
26 * DEALINGS IN THE SOFTWARE.
27 *
28 * Authors:
29 *    Keith Whitwell <keith@tungstengraphics.com>
30 *    Michel D���zer <michel@daenzer.net>
31 */
32
33#include <sys/cdefs.h>
34__FBSDID("$FreeBSD: head/sys/dev/drm/radeon_irq.c 152909 2005-11-28 23:13:57Z anholt $");
35
36#include "dev/drm/drmP.h"
37#include "dev/drm/drm.h"
38#include "dev/drm/radeon_drm.h"
39#include "dev/drm/radeon_drv.h"
40
41static __inline__ u32 radeon_acknowledge_irqs(drm_radeon_private_t * dev_priv,
42					      u32 mask)
43{
44	u32 irqs = RADEON_READ(RADEON_GEN_INT_STATUS) & mask;
45	if (irqs)
46		RADEON_WRITE(RADEON_GEN_INT_STATUS, irqs);
47	return irqs;
48}
49
50/* Interrupts - Used for device synchronization and flushing in the
51 * following circumstances:
52 *
53 * - Exclusive FB access with hw idle:
54 *    - Wait for GUI Idle (?) interrupt, then do normal flush.
55 *
56 * - Frame throttling, NV_fence:
57 *    - Drop marker irq's into command stream ahead of time.
58 *    - Wait on irq's with lock *not held*
59 *    - Check each for termination condition
60 *
61 * - Internally in cp_getbuffer, etc:
62 *    - as above, but wait with lock held???
63 *
64 * NOTE: These functions are misleadingly named -- the irq's aren't
65 * tied to dma at all, this is just a hangover from dri prehistory.
66 */
67
68irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS)
69{
70	drm_device_t *dev = (drm_device_t *) arg;
71	drm_radeon_private_t *dev_priv =
72	    (drm_radeon_private_t *) dev->dev_private;
73	u32 stat;
74
75	/* Only consider the bits we're interested in - others could be used
76	 * outside the DRM
77	 */
78	stat = radeon_acknowledge_irqs(dev_priv, (RADEON_SW_INT_TEST_ACK |
79						  RADEON_CRTC_VBLANK_STAT));
80	if (!stat)
81		return IRQ_NONE;
82
83	/* SW interrupt */
84	if (stat & RADEON_SW_INT_TEST) {
85		DRM_WAKEUP(&dev_priv->swi_queue);
86	}
87
88	/* VBLANK interrupt */
89	if (stat & RADEON_CRTC_VBLANK_STAT) {
90		atomic_inc(&dev->vbl_received);
91		DRM_WAKEUP(&dev->vbl_queue);
92		drm_vbl_send_signals(dev);
93	}
94
95	return IRQ_HANDLED;
96}
97
98static int radeon_emit_irq(drm_device_t * dev)
99{
100	drm_radeon_private_t *dev_priv = dev->dev_private;
101	unsigned int ret;
102	RING_LOCALS;
103
104	atomic_inc(&dev_priv->swi_emitted);
105	ret = atomic_read(&dev_priv->swi_emitted);
106
107	BEGIN_RING(4);
108	OUT_RING_REG(RADEON_LAST_SWI_REG, ret);
109	OUT_RING_REG(RADEON_GEN_INT_STATUS, RADEON_SW_INT_FIRE);
110	ADVANCE_RING();
111	COMMIT_RING();
112
113	return ret;
114}
115
116static int radeon_wait_irq(drm_device_t * dev, int swi_nr)
117{
118	drm_radeon_private_t *dev_priv =
119	    (drm_radeon_private_t *) dev->dev_private;
120	int ret = 0;
121
122	if (RADEON_READ(RADEON_LAST_SWI_REG) >= swi_nr)
123		return 0;
124
125	dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
126
127	DRM_WAIT_ON(ret, dev_priv->swi_queue, 3 * DRM_HZ,
128		    RADEON_READ(RADEON_LAST_SWI_REG) >= swi_nr);
129
130	return ret;
131}
132
133int radeon_driver_vblank_wait(drm_device_t * dev, unsigned int *sequence)
134{
135	drm_radeon_private_t *dev_priv =
136	    (drm_radeon_private_t *) dev->dev_private;
137	unsigned int cur_vblank;
138	int ret = 0;
139
140	if (!dev_priv) {
141		DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
142		return DRM_ERR(EINVAL);
143	}
144
145	radeon_acknowledge_irqs(dev_priv, RADEON_CRTC_VBLANK_STAT);
146
147	dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
148
149	/* Assume that the user has missed the current sequence number
150	 * by about a day rather than she wants to wait for years
151	 * using vertical blanks...
152	 */
153	DRM_WAIT_ON(ret, dev->vbl_queue, 3 * DRM_HZ,
154		    (((cur_vblank = atomic_read(&dev->vbl_received))
155		      - *sequence) <= (1 << 23)));
156
157	*sequence = cur_vblank;
158
159	return ret;
160}
161
162/* Needs the lock as it touches the ring.
163 */
164int radeon_irq_emit(DRM_IOCTL_ARGS)
165{
166	DRM_DEVICE;
167	drm_radeon_private_t *dev_priv = dev->dev_private;
168	drm_radeon_irq_emit_t emit;
169	int result;
170
171	LOCK_TEST_WITH_RETURN(dev, filp);
172
173	if (!dev_priv) {
174		DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
175		return DRM_ERR(EINVAL);
176	}
177
178	DRM_COPY_FROM_USER_IOCTL(emit, (drm_radeon_irq_emit_t __user *) data,
179				 sizeof(emit));
180
181	result = radeon_emit_irq(dev);
182
183	if (DRM_COPY_TO_USER(emit.irq_seq, &result, sizeof(int))) {
184		DRM_ERROR("copy_to_user\n");
185		return DRM_ERR(EFAULT);
186	}
187
188	return 0;
189}
190
191/* Doesn't need the hardware lock.
192 */
193int radeon_irq_wait(DRM_IOCTL_ARGS)
194{
195	DRM_DEVICE;
196	drm_radeon_private_t *dev_priv = dev->dev_private;
197	drm_radeon_irq_wait_t irqwait;
198
199	if (!dev_priv) {
200		DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
201		return DRM_ERR(EINVAL);
202	}
203
204	DRM_COPY_FROM_USER_IOCTL(irqwait, (drm_radeon_irq_wait_t __user *) data,
205				 sizeof(irqwait));
206
207	return radeon_wait_irq(dev, irqwait.irq_seq);
208}
209
210/* drm_dma.h hooks
211*/
212void radeon_driver_irq_preinstall(drm_device_t * dev)
213{
214	drm_radeon_private_t *dev_priv =
215	    (drm_radeon_private_t *) dev->dev_private;
216
217	/* Disable *all* interrupts */
218	RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
219
220	/* Clear bits if they're already high */
221	radeon_acknowledge_irqs(dev_priv, (RADEON_SW_INT_TEST_ACK |
222					   RADEON_CRTC_VBLANK_STAT));
223}
224
225void radeon_driver_irq_postinstall(drm_device_t * dev)
226{
227	drm_radeon_private_t *dev_priv =
228	    (drm_radeon_private_t *) dev->dev_private;
229
230	atomic_set(&dev_priv->swi_emitted, 0);
231	DRM_INIT_WAITQUEUE(&dev_priv->swi_queue);
232
233	/* Turn on SW and VBL ints */
234	RADEON_WRITE(RADEON_GEN_INT_CNTL,
235		     RADEON_CRTC_VBLANK_MASK | RADEON_SW_INT_ENABLE);
236}
237
238void radeon_driver_irq_uninstall(drm_device_t * dev)
239{
240	drm_radeon_private_t *dev_priv =
241	    (drm_radeon_private_t *) dev->dev_private;
242	if (!dev_priv)
243		return;
244
245	/* Disable *all* interrupts */
246	RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
247}
248