1183573Srnoland/* i915_suspend.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*- 2183573Srnoland */ 3183573Srnoland/* 4182080Srnoland * 5182080Srnoland * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6182080Srnoland * All Rights Reserved. 7182080Srnoland * 8182080Srnoland * Permission is hereby granted, free of charge, to any person obtaining a 9182080Srnoland * copy of this software and associated documentation files (the 10182080Srnoland * "Software"), to deal in the Software without restriction, including 11182080Srnoland * without limitation the rights to use, copy, modify, merge, publish, 12182080Srnoland * distribute, sub license, and/or sell copies of the Software, and to 13182080Srnoland * permit persons to whom the Software is furnished to do so, subject to 14182080Srnoland * the following conditions: 15182080Srnoland * 16182080Srnoland * The above copyright notice and this permission notice (including the 17182080Srnoland * next paragraph) shall be included in all copies or substantial portions 18182080Srnoland * of the Software. 19182080Srnoland * 20182080Srnoland * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21182080Srnoland * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22182080Srnoland * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23182080Srnoland * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24182080Srnoland * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25182080Srnoland * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26182080Srnoland * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27182080Srnoland * 28182080Srnoland */ 29182080Srnoland 30182080Srnoland#include <sys/cdefs.h> 31182080Srnoland__FBSDID("$FreeBSD$"); 32182080Srnoland 33182080Srnoland#include "dev/drm/drmP.h" 34182080Srnoland#include "dev/drm/drm.h" 35182080Srnoland#include "dev/drm/i915_drm.h" 36182080Srnoland#include "dev/drm/i915_drv.h" 37182080Srnoland 38182080Srnolandstatic bool i915_pipe_enabled(struct drm_device *dev, enum pipe pipe) 39182080Srnoland{ 40182080Srnoland struct drm_i915_private *dev_priv = dev->dev_private; 41182080Srnoland 42182080Srnoland if (pipe == PIPE_A) 43182080Srnoland return (I915_READ(DPLL_A) & DPLL_VCO_ENABLE); 44182080Srnoland else 45182080Srnoland return (I915_READ(DPLL_B) & DPLL_VCO_ENABLE); 46182080Srnoland} 47182080Srnoland 48182080Srnolandstatic void i915_save_palette(struct drm_device *dev, enum pipe pipe) 49182080Srnoland{ 50182080Srnoland struct drm_i915_private *dev_priv = dev->dev_private; 51182080Srnoland unsigned long reg = (pipe == PIPE_A ? PALETTE_A : PALETTE_B); 52182080Srnoland u32 *array; 53182080Srnoland int i; 54182080Srnoland 55182080Srnoland if (!i915_pipe_enabled(dev, pipe)) 56182080Srnoland return; 57182080Srnoland 58182080Srnoland if (pipe == PIPE_A) 59182080Srnoland array = dev_priv->save_palette_a; 60182080Srnoland else 61182080Srnoland array = dev_priv->save_palette_b; 62182080Srnoland 63182080Srnoland for(i = 0; i < 256; i++) 64182080Srnoland array[i] = I915_READ(reg + (i << 2)); 65182080Srnoland} 66182080Srnoland 67182080Srnolandstatic void i915_restore_palette(struct drm_device *dev, enum pipe pipe) 68182080Srnoland{ 69182080Srnoland struct drm_i915_private *dev_priv = dev->dev_private; 70182080Srnoland unsigned long reg = (pipe == PIPE_A ? PALETTE_A : PALETTE_B); 71182080Srnoland u32 *array; 72182080Srnoland int i; 73182080Srnoland 74182080Srnoland if (!i915_pipe_enabled(dev, pipe)) 75182080Srnoland return; 76182080Srnoland 77182080Srnoland if (pipe == PIPE_A) 78182080Srnoland array = dev_priv->save_palette_a; 79182080Srnoland else 80182080Srnoland array = dev_priv->save_palette_b; 81182080Srnoland 82182080Srnoland for(i = 0; i < 256; i++) 83182080Srnoland I915_WRITE(reg + (i << 2), array[i]); 84182080Srnoland} 85182080Srnoland 86182080Srnolandstatic u8 i915_read_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg) 87182080Srnoland{ 88182080Srnoland struct drm_i915_private *dev_priv = dev->dev_private; 89182080Srnoland 90182080Srnoland I915_WRITE8(index_port, reg); 91182080Srnoland return I915_READ8(data_port); 92182080Srnoland} 93182080Srnoland 94182080Srnolandstatic u8 i915_read_ar(struct drm_device *dev, u16 st01, u8 reg, u16 palette_enable) 95182080Srnoland{ 96182080Srnoland struct drm_i915_private *dev_priv = dev->dev_private; 97182080Srnoland 98182080Srnoland I915_READ8(st01); 99182080Srnoland I915_WRITE8(VGA_AR_INDEX, palette_enable | reg); 100182080Srnoland return I915_READ8(VGA_AR_DATA_READ); 101182080Srnoland} 102182080Srnoland 103182080Srnolandstatic void i915_write_ar(struct drm_device *dev, u16 st01, u8 reg, u8 val, u16 palette_enable) 104182080Srnoland{ 105182080Srnoland struct drm_i915_private *dev_priv = dev->dev_private; 106182080Srnoland 107182080Srnoland I915_READ8(st01); 108182080Srnoland I915_WRITE8(VGA_AR_INDEX, palette_enable | reg); 109182080Srnoland I915_WRITE8(VGA_AR_DATA_WRITE, val); 110182080Srnoland} 111182080Srnoland 112182080Srnolandstatic void i915_write_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg, u8 val) 113182080Srnoland{ 114182080Srnoland struct drm_i915_private *dev_priv = dev->dev_private; 115182080Srnoland 116182080Srnoland I915_WRITE8(index_port, reg); 117182080Srnoland I915_WRITE8(data_port, val); 118182080Srnoland} 119182080Srnoland 120182080Srnolandstatic void i915_save_vga(struct drm_device *dev) 121182080Srnoland{ 122182080Srnoland struct drm_i915_private *dev_priv = dev->dev_private; 123182080Srnoland int i; 124182080Srnoland u16 cr_index, cr_data, st01; 125182080Srnoland 126182080Srnoland /* VGA color palette registers */ 127182080Srnoland dev_priv->saveDACMASK = I915_READ8(VGA_DACMASK); 128182080Srnoland 129182080Srnoland /* MSR bits */ 130182080Srnoland dev_priv->saveMSR = I915_READ8(VGA_MSR_READ); 131182080Srnoland if (dev_priv->saveMSR & VGA_MSR_CGA_MODE) { 132182080Srnoland cr_index = VGA_CR_INDEX_CGA; 133182080Srnoland cr_data = VGA_CR_DATA_CGA; 134182080Srnoland st01 = VGA_ST01_CGA; 135182080Srnoland } else { 136182080Srnoland cr_index = VGA_CR_INDEX_MDA; 137182080Srnoland cr_data = VGA_CR_DATA_MDA; 138182080Srnoland st01 = VGA_ST01_MDA; 139182080Srnoland } 140182080Srnoland 141182080Srnoland /* CRT controller regs */ 142182080Srnoland i915_write_indexed(dev, cr_index, cr_data, 0x11, 143182080Srnoland i915_read_indexed(dev, cr_index, cr_data, 0x11) & 144182080Srnoland (~0x80)); 145182080Srnoland for (i = 0; i <= 0x24; i++) 146182080Srnoland dev_priv->saveCR[i] = 147182080Srnoland i915_read_indexed(dev, cr_index, cr_data, i); 148182080Srnoland /* Make sure we don't turn off CR group 0 writes */ 149182080Srnoland dev_priv->saveCR[0x11] &= ~0x80; 150182080Srnoland 151182080Srnoland /* Attribute controller registers */ 152182080Srnoland I915_READ8(st01); 153182080Srnoland dev_priv->saveAR_INDEX = I915_READ8(VGA_AR_INDEX); 154182080Srnoland for (i = 0; i <= 0x14; i++) 155182080Srnoland dev_priv->saveAR[i] = i915_read_ar(dev, st01, i, 0); 156182080Srnoland I915_READ8(st01); 157182080Srnoland I915_WRITE8(VGA_AR_INDEX, dev_priv->saveAR_INDEX); 158182080Srnoland I915_READ8(st01); 159182080Srnoland 160182080Srnoland /* Graphics controller registers */ 161182080Srnoland for (i = 0; i < 9; i++) 162182080Srnoland dev_priv->saveGR[i] = 163182080Srnoland i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i); 164182080Srnoland 165182080Srnoland dev_priv->saveGR[0x10] = 166182080Srnoland i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10); 167182080Srnoland dev_priv->saveGR[0x11] = 168182080Srnoland i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11); 169182080Srnoland dev_priv->saveGR[0x18] = 170182080Srnoland i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18); 171182080Srnoland 172182080Srnoland /* Sequencer registers */ 173182080Srnoland for (i = 0; i < 8; i++) 174182080Srnoland dev_priv->saveSR[i] = 175182080Srnoland i915_read_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i); 176182080Srnoland} 177182080Srnoland 178182080Srnolandstatic void i915_restore_vga(struct drm_device *dev) 179182080Srnoland{ 180182080Srnoland struct drm_i915_private *dev_priv = dev->dev_private; 181182080Srnoland int i; 182182080Srnoland u16 cr_index, cr_data, st01; 183182080Srnoland 184182080Srnoland /* MSR bits */ 185182080Srnoland I915_WRITE8(VGA_MSR_WRITE, dev_priv->saveMSR); 186182080Srnoland if (dev_priv->saveMSR & VGA_MSR_CGA_MODE) { 187182080Srnoland cr_index = VGA_CR_INDEX_CGA; 188182080Srnoland cr_data = VGA_CR_DATA_CGA; 189182080Srnoland st01 = VGA_ST01_CGA; 190182080Srnoland } else { 191182080Srnoland cr_index = VGA_CR_INDEX_MDA; 192182080Srnoland cr_data = VGA_CR_DATA_MDA; 193182080Srnoland st01 = VGA_ST01_MDA; 194182080Srnoland } 195182080Srnoland 196182080Srnoland /* Sequencer registers, don't write SR07 */ 197182080Srnoland for (i = 0; i < 7; i++) 198182080Srnoland i915_write_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i, 199182080Srnoland dev_priv->saveSR[i]); 200182080Srnoland 201182080Srnoland /* CRT controller regs */ 202182080Srnoland /* Enable CR group 0 writes */ 203182080Srnoland i915_write_indexed(dev, cr_index, cr_data, 0x11, dev_priv->saveCR[0x11]); 204182080Srnoland for (i = 0; i <= 0x24; i++) 205182080Srnoland i915_write_indexed(dev, cr_index, cr_data, i, dev_priv->saveCR[i]); 206182080Srnoland 207182080Srnoland /* Graphics controller regs */ 208182080Srnoland for (i = 0; i < 9; i++) 209182080Srnoland i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i, 210182080Srnoland dev_priv->saveGR[i]); 211182080Srnoland 212182080Srnoland i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10, 213182080Srnoland dev_priv->saveGR[0x10]); 214182080Srnoland i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11, 215182080Srnoland dev_priv->saveGR[0x11]); 216182080Srnoland i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18, 217182080Srnoland dev_priv->saveGR[0x18]); 218182080Srnoland 219182080Srnoland /* Attribute controller registers */ 220182080Srnoland I915_READ8(st01); /* switch back to index mode */ 221182080Srnoland for (i = 0; i <= 0x14; i++) 222182080Srnoland i915_write_ar(dev, st01, i, dev_priv->saveAR[i], 0); 223182080Srnoland I915_READ8(st01); /* switch back to index mode */ 224182080Srnoland I915_WRITE8(VGA_AR_INDEX, dev_priv->saveAR_INDEX | 0x20); 225182080Srnoland I915_READ8(st01); 226182080Srnoland 227182080Srnoland /* VGA color palette registers */ 228182080Srnoland I915_WRITE8(VGA_DACMASK, dev_priv->saveDACMASK); 229182080Srnoland} 230182080Srnoland 231182080Srnolandint i915_save_state(struct drm_device *dev) 232182080Srnoland{ 233182080Srnoland struct drm_i915_private *dev_priv = dev->dev_private; 234182080Srnoland int i; 235182080Srnoland 236182080Srnoland#if defined(__FreeBSD__) 237182080Srnoland dev_priv->saveLBB = (u8) pci_read_config(dev->device, LBB, 1); 238182080Srnoland#else 239182080Srnoland pci_read_config_byte(dev->pdev, LBB, &dev_priv->saveLBB); 240182080Srnoland#endif 241182080Srnoland 242190020Srnoland /* Render Standby */ 243190020Srnoland if (IS_I965G(dev) && IS_MOBILE(dev)) 244190020Srnoland dev_priv->saveRENDERSTANDBY = I915_READ(MCHBAR_RENDER_STANDBY); 245190020Srnoland 246190020Srnoland /* Hardware status page */ 247190020Srnoland dev_priv->saveHWS = I915_READ(HWS_PGA); 248190020Srnoland 249182080Srnoland /* Display arbitration control */ 250182080Srnoland dev_priv->saveDSPARB = I915_READ(DSPARB); 251182080Srnoland 252182080Srnoland /* Pipe & plane A info */ 253182080Srnoland dev_priv->savePIPEACONF = I915_READ(PIPEACONF); 254182080Srnoland dev_priv->savePIPEASRC = I915_READ(PIPEASRC); 255182080Srnoland dev_priv->saveFPA0 = I915_READ(FPA0); 256182080Srnoland dev_priv->saveFPA1 = I915_READ(FPA1); 257182080Srnoland dev_priv->saveDPLL_A = I915_READ(DPLL_A); 258182080Srnoland if (IS_I965G(dev)) 259182080Srnoland dev_priv->saveDPLL_A_MD = I915_READ(DPLL_A_MD); 260182080Srnoland dev_priv->saveHTOTAL_A = I915_READ(HTOTAL_A); 261182080Srnoland dev_priv->saveHBLANK_A = I915_READ(HBLANK_A); 262182080Srnoland dev_priv->saveHSYNC_A = I915_READ(HSYNC_A); 263182080Srnoland dev_priv->saveVTOTAL_A = I915_READ(VTOTAL_A); 264182080Srnoland dev_priv->saveVBLANK_A = I915_READ(VBLANK_A); 265182080Srnoland dev_priv->saveVSYNC_A = I915_READ(VSYNC_A); 266182080Srnoland dev_priv->saveBCLRPAT_A = I915_READ(BCLRPAT_A); 267182080Srnoland 268182080Srnoland dev_priv->saveDSPACNTR = I915_READ(DSPACNTR); 269182080Srnoland dev_priv->saveDSPASTRIDE = I915_READ(DSPASTRIDE); 270182080Srnoland dev_priv->saveDSPASIZE = I915_READ(DSPASIZE); 271182080Srnoland dev_priv->saveDSPAPOS = I915_READ(DSPAPOS); 272182080Srnoland dev_priv->saveDSPAADDR = I915_READ(DSPAADDR); 273182080Srnoland if (IS_I965G(dev)) { 274182080Srnoland dev_priv->saveDSPASURF = I915_READ(DSPASURF); 275182080Srnoland dev_priv->saveDSPATILEOFF = I915_READ(DSPATILEOFF); 276182080Srnoland } 277182080Srnoland i915_save_palette(dev, PIPE_A); 278182080Srnoland dev_priv->savePIPEASTAT = I915_READ(PIPEASTAT); 279182080Srnoland 280182080Srnoland /* Pipe & plane B info */ 281182080Srnoland dev_priv->savePIPEBCONF = I915_READ(PIPEBCONF); 282182080Srnoland dev_priv->savePIPEBSRC = I915_READ(PIPEBSRC); 283182080Srnoland dev_priv->saveFPB0 = I915_READ(FPB0); 284182080Srnoland dev_priv->saveFPB1 = I915_READ(FPB1); 285182080Srnoland dev_priv->saveDPLL_B = I915_READ(DPLL_B); 286182080Srnoland if (IS_I965G(dev)) 287182080Srnoland dev_priv->saveDPLL_B_MD = I915_READ(DPLL_B_MD); 288182080Srnoland dev_priv->saveHTOTAL_B = I915_READ(HTOTAL_B); 289182080Srnoland dev_priv->saveHBLANK_B = I915_READ(HBLANK_B); 290182080Srnoland dev_priv->saveHSYNC_B = I915_READ(HSYNC_B); 291182080Srnoland dev_priv->saveVTOTAL_B = I915_READ(VTOTAL_B); 292182080Srnoland dev_priv->saveVBLANK_B = I915_READ(VBLANK_B); 293182080Srnoland dev_priv->saveVSYNC_B = I915_READ(VSYNC_B); 294182080Srnoland dev_priv->saveBCLRPAT_A = I915_READ(BCLRPAT_A); 295182080Srnoland 296182080Srnoland dev_priv->saveDSPBCNTR = I915_READ(DSPBCNTR); 297182080Srnoland dev_priv->saveDSPBSTRIDE = I915_READ(DSPBSTRIDE); 298182080Srnoland dev_priv->saveDSPBSIZE = I915_READ(DSPBSIZE); 299182080Srnoland dev_priv->saveDSPBPOS = I915_READ(DSPBPOS); 300182080Srnoland dev_priv->saveDSPBADDR = I915_READ(DSPBADDR); 301182080Srnoland if (IS_I965GM(dev) || IS_GM45(dev)) { 302182080Srnoland dev_priv->saveDSPBSURF = I915_READ(DSPBSURF); 303182080Srnoland dev_priv->saveDSPBTILEOFF = I915_READ(DSPBTILEOFF); 304182080Srnoland } 305182080Srnoland i915_save_palette(dev, PIPE_B); 306182080Srnoland dev_priv->savePIPEBSTAT = I915_READ(PIPEBSTAT); 307182080Srnoland 308182080Srnoland /* CRT state */ 309182080Srnoland dev_priv->saveADPA = I915_READ(ADPA); 310182080Srnoland 311182080Srnoland /* LVDS state */ 312182080Srnoland dev_priv->savePP_CONTROL = I915_READ(PP_CONTROL); 313182080Srnoland dev_priv->savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS); 314182080Srnoland dev_priv->saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL); 315182080Srnoland if (IS_I965G(dev)) 316182080Srnoland dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2); 317182080Srnoland if (IS_MOBILE(dev) && !IS_I830(dev)) 318182080Srnoland dev_priv->saveLVDS = I915_READ(LVDS); 319182080Srnoland if (!IS_I830(dev) && !IS_845G(dev)) 320182080Srnoland dev_priv->savePFIT_CONTROL = I915_READ(PFIT_CONTROL); 321182080Srnoland dev_priv->savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS); 322182080Srnoland dev_priv->savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS); 323182080Srnoland dev_priv->savePP_DIVISOR = I915_READ(PP_DIVISOR); 324182080Srnoland 325182080Srnoland /* FIXME: save TV & SDVO state */ 326182080Srnoland 327182080Srnoland /* FBC state */ 328182080Srnoland dev_priv->saveFBC_CFB_BASE = I915_READ(FBC_CFB_BASE); 329182080Srnoland dev_priv->saveFBC_LL_BASE = I915_READ(FBC_LL_BASE); 330182080Srnoland dev_priv->saveFBC_CONTROL2 = I915_READ(FBC_CONTROL2); 331182080Srnoland dev_priv->saveFBC_CONTROL = I915_READ(FBC_CONTROL); 332182080Srnoland 333182080Srnoland /* Interrupt state */ 334182080Srnoland dev_priv->saveIIR = I915_READ(IIR); 335182080Srnoland dev_priv->saveIER = I915_READ(IER); 336182080Srnoland dev_priv->saveIMR = I915_READ(IMR); 337182080Srnoland 338182080Srnoland /* VGA state */ 339182080Srnoland dev_priv->saveVGA0 = I915_READ(VGA0); 340182080Srnoland dev_priv->saveVGA1 = I915_READ(VGA1); 341182080Srnoland dev_priv->saveVGA_PD = I915_READ(VGA_PD); 342182080Srnoland dev_priv->saveVGACNTRL = I915_READ(VGACNTRL); 343182080Srnoland 344182080Srnoland /* Clock gating state */ 345182080Srnoland dev_priv->saveD_STATE = I915_READ(D_STATE); 346182080Srnoland dev_priv->saveCG_2D_DIS = I915_READ(CG_2D_DIS); 347182080Srnoland 348182080Srnoland /* Cache mode state */ 349182080Srnoland dev_priv->saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0); 350182080Srnoland 351182080Srnoland /* Memory Arbitration state */ 352182080Srnoland dev_priv->saveMI_ARB_STATE = I915_READ(MI_ARB_STATE); 353182080Srnoland 354182080Srnoland /* Scratch space */ 355182080Srnoland for (i = 0; i < 16; i++) { 356182080Srnoland dev_priv->saveSWF0[i] = I915_READ(SWF00 + (i << 2)); 357182080Srnoland dev_priv->saveSWF1[i] = I915_READ(SWF10 + (i << 2)); 358182080Srnoland } 359182080Srnoland for (i = 0; i < 3; i++) 360182080Srnoland dev_priv->saveSWF2[i] = I915_READ(SWF30 + (i << 2)); 361182080Srnoland 362182080Srnoland i915_save_vga(dev); 363182080Srnoland 364182080Srnoland return 0; 365182080Srnoland} 366182080Srnoland 367182080Srnolandint i915_restore_state(struct drm_device *dev) 368182080Srnoland{ 369182080Srnoland struct drm_i915_private *dev_priv = dev->dev_private; 370182080Srnoland int i; 371182080Srnoland 372182080Srnoland#if defined(__FreeBSD__) 373182080Srnoland pci_write_config(dev->device, LBB, dev_priv->saveLBB, 1); 374182080Srnoland#else 375182080Srnoland pci_write_config_byte(dev->pdev, LBB, dev_priv->saveLBB); 376182080Srnoland#endif 377182080Srnoland 378190020Srnoland /* Render Standby */ 379190020Srnoland if (IS_I965G(dev) && IS_MOBILE(dev)) 380190020Srnoland I915_WRITE(MCHBAR_RENDER_STANDBY, dev_priv->saveRENDERSTANDBY); 381190020Srnoland 382190020Srnoland /* Hardware status page */ 383190020Srnoland I915_WRITE(HWS_PGA, dev_priv->saveHWS); 384190020Srnoland 385190020Srnoland /* Display arbitration */ 386182080Srnoland I915_WRITE(DSPARB, dev_priv->saveDSPARB); 387182080Srnoland 388182080Srnoland /* Pipe & plane A info */ 389182080Srnoland /* Prime the clock */ 390182080Srnoland if (dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) { 391182080Srnoland I915_WRITE(DPLL_A, dev_priv->saveDPLL_A & 392182080Srnoland ~DPLL_VCO_ENABLE); 393182080Srnoland DRM_UDELAY(150); 394182080Srnoland } 395182080Srnoland I915_WRITE(FPA0, dev_priv->saveFPA0); 396182080Srnoland I915_WRITE(FPA1, dev_priv->saveFPA1); 397182080Srnoland /* Actually enable it */ 398182080Srnoland I915_WRITE(DPLL_A, dev_priv->saveDPLL_A); 399182080Srnoland DRM_UDELAY(150); 400182080Srnoland if (IS_I965G(dev)) 401182080Srnoland I915_WRITE(DPLL_A_MD, dev_priv->saveDPLL_A_MD); 402182080Srnoland DRM_UDELAY(150); 403182080Srnoland 404182080Srnoland /* Restore mode */ 405182080Srnoland I915_WRITE(HTOTAL_A, dev_priv->saveHTOTAL_A); 406182080Srnoland I915_WRITE(HBLANK_A, dev_priv->saveHBLANK_A); 407182080Srnoland I915_WRITE(HSYNC_A, dev_priv->saveHSYNC_A); 408182080Srnoland I915_WRITE(VTOTAL_A, dev_priv->saveVTOTAL_A); 409182080Srnoland I915_WRITE(VBLANK_A, dev_priv->saveVBLANK_A); 410182080Srnoland I915_WRITE(VSYNC_A, dev_priv->saveVSYNC_A); 411182080Srnoland I915_WRITE(BCLRPAT_A, dev_priv->saveBCLRPAT_A); 412182080Srnoland 413182080Srnoland /* Restore plane info */ 414182080Srnoland I915_WRITE(DSPASIZE, dev_priv->saveDSPASIZE); 415182080Srnoland I915_WRITE(DSPAPOS, dev_priv->saveDSPAPOS); 416182080Srnoland I915_WRITE(PIPEASRC, dev_priv->savePIPEASRC); 417182080Srnoland I915_WRITE(DSPAADDR, dev_priv->saveDSPAADDR); 418182080Srnoland I915_WRITE(DSPASTRIDE, dev_priv->saveDSPASTRIDE); 419182080Srnoland if (IS_I965G(dev)) { 420182080Srnoland I915_WRITE(DSPASURF, dev_priv->saveDSPASURF); 421182080Srnoland I915_WRITE(DSPATILEOFF, dev_priv->saveDSPATILEOFF); 422182080Srnoland } 423182080Srnoland 424182080Srnoland I915_WRITE(PIPEACONF, dev_priv->savePIPEACONF); 425182080Srnoland 426182080Srnoland i915_restore_palette(dev, PIPE_A); 427182080Srnoland /* Enable the plane */ 428182080Srnoland I915_WRITE(DSPACNTR, dev_priv->saveDSPACNTR); 429182080Srnoland I915_WRITE(DSPAADDR, I915_READ(DSPAADDR)); 430182080Srnoland 431182080Srnoland /* Pipe & plane B info */ 432182080Srnoland if (dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) { 433182080Srnoland I915_WRITE(DPLL_B, dev_priv->saveDPLL_B & 434182080Srnoland ~DPLL_VCO_ENABLE); 435182080Srnoland DRM_UDELAY(150); 436182080Srnoland } 437182080Srnoland I915_WRITE(FPB0, dev_priv->saveFPB0); 438182080Srnoland I915_WRITE(FPB1, dev_priv->saveFPB1); 439182080Srnoland /* Actually enable it */ 440182080Srnoland I915_WRITE(DPLL_B, dev_priv->saveDPLL_B); 441182080Srnoland DRM_UDELAY(150); 442182080Srnoland if (IS_I965G(dev)) 443182080Srnoland I915_WRITE(DPLL_B_MD, dev_priv->saveDPLL_B_MD); 444182080Srnoland DRM_UDELAY(150); 445182080Srnoland 446182080Srnoland /* Restore mode */ 447182080Srnoland I915_WRITE(HTOTAL_B, dev_priv->saveHTOTAL_B); 448182080Srnoland I915_WRITE(HBLANK_B, dev_priv->saveHBLANK_B); 449182080Srnoland I915_WRITE(HSYNC_B, dev_priv->saveHSYNC_B); 450182080Srnoland I915_WRITE(VTOTAL_B, dev_priv->saveVTOTAL_B); 451182080Srnoland I915_WRITE(VBLANK_B, dev_priv->saveVBLANK_B); 452182080Srnoland I915_WRITE(VSYNC_B, dev_priv->saveVSYNC_B); 453182080Srnoland I915_WRITE(BCLRPAT_B, dev_priv->saveBCLRPAT_B); 454182080Srnoland 455182080Srnoland /* Restore plane info */ 456182080Srnoland I915_WRITE(DSPBSIZE, dev_priv->saveDSPBSIZE); 457182080Srnoland I915_WRITE(DSPBPOS, dev_priv->saveDSPBPOS); 458182080Srnoland I915_WRITE(PIPEBSRC, dev_priv->savePIPEBSRC); 459182080Srnoland I915_WRITE(DSPBADDR, dev_priv->saveDSPBADDR); 460182080Srnoland I915_WRITE(DSPBSTRIDE, dev_priv->saveDSPBSTRIDE); 461182080Srnoland if (IS_I965G(dev)) { 462182080Srnoland I915_WRITE(DSPBSURF, dev_priv->saveDSPBSURF); 463182080Srnoland I915_WRITE(DSPBTILEOFF, dev_priv->saveDSPBTILEOFF); 464182080Srnoland } 465182080Srnoland 466182080Srnoland I915_WRITE(PIPEBCONF, dev_priv->savePIPEBCONF); 467182080Srnoland 468182080Srnoland i915_restore_palette(dev, PIPE_B); 469182080Srnoland /* Enable the plane */ 470182080Srnoland I915_WRITE(DSPBCNTR, dev_priv->saveDSPBCNTR); 471182080Srnoland I915_WRITE(DSPBADDR, I915_READ(DSPBADDR)); 472182080Srnoland 473182080Srnoland /* CRT state */ 474182080Srnoland I915_WRITE(ADPA, dev_priv->saveADPA); 475182080Srnoland 476182080Srnoland /* LVDS state */ 477182080Srnoland if (IS_I965G(dev)) 478182080Srnoland I915_WRITE(BLC_PWM_CTL2, dev_priv->saveBLC_PWM_CTL2); 479182080Srnoland if (IS_MOBILE(dev) && !IS_I830(dev)) 480182080Srnoland I915_WRITE(LVDS, dev_priv->saveLVDS); 481182080Srnoland if (!IS_I830(dev) && !IS_845G(dev)) 482182080Srnoland I915_WRITE(PFIT_CONTROL, dev_priv->savePFIT_CONTROL); 483182080Srnoland 484182080Srnoland I915_WRITE(PFIT_PGM_RATIOS, dev_priv->savePFIT_PGM_RATIOS); 485182080Srnoland I915_WRITE(BLC_PWM_CTL, dev_priv->saveBLC_PWM_CTL); 486182080Srnoland I915_WRITE(PP_ON_DELAYS, dev_priv->savePP_ON_DELAYS); 487182080Srnoland I915_WRITE(PP_OFF_DELAYS, dev_priv->savePP_OFF_DELAYS); 488182080Srnoland I915_WRITE(PP_DIVISOR, dev_priv->savePP_DIVISOR); 489182080Srnoland I915_WRITE(PP_CONTROL, dev_priv->savePP_CONTROL); 490182080Srnoland 491182080Srnoland /* FIXME: restore TV & SDVO state */ 492182080Srnoland 493182080Srnoland /* FBC info */ 494182080Srnoland I915_WRITE(FBC_CFB_BASE, dev_priv->saveFBC_CFB_BASE); 495182080Srnoland I915_WRITE(FBC_LL_BASE, dev_priv->saveFBC_LL_BASE); 496182080Srnoland I915_WRITE(FBC_CONTROL2, dev_priv->saveFBC_CONTROL2); 497182080Srnoland I915_WRITE(FBC_CONTROL, dev_priv->saveFBC_CONTROL); 498182080Srnoland 499182080Srnoland /* VGA state */ 500182080Srnoland I915_WRITE(VGACNTRL, dev_priv->saveVGACNTRL); 501182080Srnoland I915_WRITE(VGA0, dev_priv->saveVGA0); 502182080Srnoland I915_WRITE(VGA1, dev_priv->saveVGA1); 503182080Srnoland I915_WRITE(VGA_PD, dev_priv->saveVGA_PD); 504182080Srnoland DRM_UDELAY(150); 505182080Srnoland 506182080Srnoland /* Clock gating state */ 507182080Srnoland I915_WRITE (D_STATE, dev_priv->saveD_STATE); 508182080Srnoland I915_WRITE (CG_2D_DIS, dev_priv->saveCG_2D_DIS); 509182080Srnoland 510182080Srnoland /* Cache mode state */ 511182080Srnoland I915_WRITE (CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000); 512182080Srnoland 513182080Srnoland /* Memory arbitration state */ 514182080Srnoland I915_WRITE (MI_ARB_STATE, dev_priv->saveMI_ARB_STATE | 0xffff0000); 515182080Srnoland 516182080Srnoland for (i = 0; i < 16; i++) { 517182080Srnoland I915_WRITE(SWF00 + (i << 2), dev_priv->saveSWF0[i]); 518190164Srnoland I915_WRITE(SWF10 + (i << 2), dev_priv->saveSWF1[i]); 519182080Srnoland } 520182080Srnoland for (i = 0; i < 3; i++) 521182080Srnoland I915_WRITE(SWF30 + (i << 2), dev_priv->saveSWF2[i]); 522182080Srnoland 523182080Srnoland i915_restore_vga(dev); 524182080Srnoland 525182080Srnoland return 0; 526182080Srnoland} 527182080Srnoland 528