1256694Snp/* 2256694Snp * Copyright (c) 2009-2013 Chelsio, Inc. All rights reserved. 3256694Snp * 4256694Snp * This software is available to you under a choice of one of two 5256694Snp * licenses. You may choose to be licensed under the terms of the GNU 6256694Snp * General Public License (GPL) Version 2, available from the file 7256694Snp * COPYING in the main directory of this source tree, or the 8256694Snp * OpenIB.org BSD license below: 9256694Snp * 10256694Snp * Redistribution and use in source and binary forms, with or 11256694Snp * without modification, are permitted provided that the following 12256694Snp * conditions are met: 13256694Snp * 14256694Snp * - Redistributions of source code must retain the above 15256694Snp * copyright notice, this list of conditions and the following 16256694Snp * disclaimer. 17256694Snp * - Redistributions in binary form must reproduce the above 18256694Snp * copyright notice, this list of conditions and the following 19256694Snp * disclaimer in the documentation and/or other materials 20256694Snp * provided with the distribution. 21256694Snp * 22256694Snp * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 23256694Snp * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 24256694Snp * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 25256694Snp * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 26256694Snp * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 27256694Snp * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 28256694Snp * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 29256694Snp * SOFTWARE. 30256694Snp * 31256694Snp * $FreeBSD$ 32256694Snp */ 33256694Snp#ifndef __T4_H__ 34256694Snp#define __T4_H__ 35256694Snp 36256694Snp/* 37256694Snp * Fixme: Adding missing defines 38256694Snp */ 39256694Snp#define SGE_PF_KDOORBELL 0x0 40256694Snp#define QID_MASK 0xffff8000U 41256694Snp#define QID_SHIFT 15 42256694Snp#define QID(x) ((x) << QID_SHIFT) 43256694Snp#define DBPRIO 0x00004000U 44256694Snp#define PIDX_MASK 0x00003fffU 45256694Snp#define PIDX_SHIFT 0 46256694Snp#define PIDX(x) ((x) << PIDX_SHIFT) 47256694Snp 48256694Snp#define SGE_PF_GTS 0x4 49256694Snp#define INGRESSQID_MASK 0xffff0000U 50256694Snp#define INGRESSQID_SHIFT 16 51256694Snp#define INGRESSQID(x) ((x) << INGRESSQID_SHIFT) 52256694Snp#define TIMERREG_MASK 0x0000e000U 53256694Snp#define TIMERREG_SHIFT 13 54256694Snp#define TIMERREG(x) ((x) << TIMERREG_SHIFT) 55256694Snp#define SEINTARM_MASK 0x00001000U 56256694Snp#define SEINTARM_SHIFT 12 57256694Snp#define SEINTARM(x) ((x) << SEINTARM_SHIFT) 58256694Snp#define CIDXINC_MASK 0x00000fffU 59256694Snp#define CIDXINC_SHIFT 0 60256694Snp#define CIDXINC(x) ((x) << CIDXINC_SHIFT) 61256694Snp 62256694Snp#define T4_MAX_NUM_QP (1<<16) 63256694Snp#define T4_MAX_NUM_CQ (1<<15) 64256694Snp#define T4_MAX_NUM_PD (1<<15) 65256694Snp#define T4_EQ_STATUS_ENTRIES (L1_CACHE_BYTES > 64 ? 2 : 1) 66256694Snp#define T4_MAX_EQ_SIZE (65520 - T4_EQ_STATUS_ENTRIES) 67256694Snp#define T4_MAX_IQ_SIZE (65520 - 1) 68256694Snp#define T4_MAX_RQ_SIZE (8192 - T4_EQ_STATUS_ENTRIES) 69256694Snp#define T4_MAX_SQ_SIZE (T4_MAX_EQ_SIZE - 1) 70256694Snp#define T4_MAX_QP_DEPTH (T4_MAX_RQ_SIZE - 1) 71256694Snp#define T4_MAX_CQ_DEPTH (T4_MAX_IQ_SIZE - 1) 72256694Snp#define T4_MAX_NUM_STAG (1<<15) 73256694Snp#define T4_MAX_MR_SIZE (~0ULL - 1) 74256694Snp#define T4_PAGESIZE_MASK 0xffff000 /* 4KB-128MB */ 75256694Snp#define T4_STAG_UNSET 0xffffffff 76256694Snp#define T4_FW_MAJ 0 77256694Snp#define T4_EQ_STATUS_ENTRIES (L1_CACHE_BYTES > 64 ? 2 : 1) 78256694Snp#define A_PCIE_MA_SYNC 0x30b4 79256694Snp 80256694Snpstruct t4_status_page { 81256694Snp __be32 rsvd1; /* flit 0 - hw owns */ 82256694Snp __be16 rsvd2; 83256694Snp __be16 qid; 84256694Snp __be16 cidx; 85256694Snp __be16 pidx; 86256694Snp u8 qp_err; /* flit 1 - sw owns */ 87256694Snp u8 db_off; 88256694Snp u8 pad; 89256694Snp u16 host_wq_pidx; 90256694Snp u16 host_cidx; 91256694Snp u16 host_pidx; 92256694Snp}; 93256694Snp 94256694Snp#define T4_EQ_ENTRY_SIZE 64 95256694Snp 96256694Snp#define T4_SQ_NUM_SLOTS 5 97256694Snp#define T4_SQ_NUM_BYTES (T4_EQ_ENTRY_SIZE * T4_SQ_NUM_SLOTS) 98256694Snp#define T4_MAX_SEND_SGE ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_send_wr) - \ 99256694Snp sizeof(struct fw_ri_isgl)) / sizeof(struct fw_ri_sge)) 100256694Snp#define T4_MAX_SEND_INLINE ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_send_wr) - \ 101256694Snp sizeof(struct fw_ri_immd))) 102256694Snp#define T4_MAX_WRITE_INLINE ((T4_SQ_NUM_BYTES - \ 103256694Snp sizeof(struct fw_ri_rdma_write_wr) - \ 104256694Snp sizeof(struct fw_ri_immd))) 105256694Snp#define T4_MAX_WRITE_SGE ((T4_SQ_NUM_BYTES - \ 106256694Snp sizeof(struct fw_ri_rdma_write_wr) - \ 107256694Snp sizeof(struct fw_ri_isgl)) / sizeof(struct fw_ri_sge)) 108256694Snp#define T4_MAX_FR_IMMD ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_fr_nsmr_wr) - \ 109256694Snp sizeof(struct fw_ri_immd)) & ~31UL) 110256694Snp#define T4_MAX_FR_DEPTH (T4_MAX_FR_IMMD / sizeof(u64)) 111256694Snp 112256694Snp#define T4_RQ_NUM_SLOTS 2 113256694Snp#define T4_RQ_NUM_BYTES (T4_EQ_ENTRY_SIZE * T4_RQ_NUM_SLOTS) 114256694Snp#define T4_MAX_RECV_SGE 4 115256694Snp 116256694Snpunion t4_wr { 117256694Snp struct fw_ri_res_wr res; 118256694Snp struct fw_ri_wr ri; 119256694Snp struct fw_ri_rdma_write_wr write; 120256694Snp struct fw_ri_send_wr send; 121256694Snp struct fw_ri_rdma_read_wr read; 122256694Snp struct fw_ri_bind_mw_wr bind; 123256694Snp struct fw_ri_fr_nsmr_wr fr; 124256694Snp struct fw_ri_inv_lstag_wr inv; 125256694Snp struct t4_status_page status; 126256694Snp __be64 flits[T4_EQ_ENTRY_SIZE / sizeof(__be64) * T4_SQ_NUM_SLOTS]; 127256694Snp}; 128256694Snp 129256694Snpunion t4_recv_wr { 130256694Snp struct fw_ri_recv_wr recv; 131256694Snp struct t4_status_page status; 132256694Snp __be64 flits[T4_EQ_ENTRY_SIZE / sizeof(__be64) * T4_RQ_NUM_SLOTS]; 133256694Snp}; 134256694Snp 135256694Snpstatic inline void init_wr_hdr(union t4_wr *wqe, u16 wrid, 136256694Snp enum fw_wr_opcodes opcode, u8 flags, u8 len16) 137256694Snp{ 138256694Snp wqe->send.opcode = (u8)opcode; 139256694Snp wqe->send.flags = flags; 140256694Snp wqe->send.wrid = wrid; 141256694Snp wqe->send.r1[0] = 0; 142256694Snp wqe->send.r1[1] = 0; 143256694Snp wqe->send.r1[2] = 0; 144256694Snp wqe->send.len16 = len16; 145256694Snp} 146256694Snp 147256694Snp/* CQE/AE status codes */ 148256694Snp#define T4_ERR_SUCCESS 0x0 149256694Snp#define T4_ERR_STAG 0x1 /* STAG invalid: either the */ 150256694Snp /* STAG is offlimt, being 0, */ 151256694Snp /* or STAG_key mismatch */ 152256694Snp#define T4_ERR_PDID 0x2 /* PDID mismatch */ 153256694Snp#define T4_ERR_QPID 0x3 /* QPID mismatch */ 154256694Snp#define T4_ERR_ACCESS 0x4 /* Invalid access right */ 155256694Snp#define T4_ERR_WRAP 0x5 /* Wrap error */ 156256694Snp#define T4_ERR_BOUND 0x6 /* base and bounds voilation */ 157256694Snp#define T4_ERR_INVALIDATE_SHARED_MR 0x7 /* attempt to invalidate a */ 158256694Snp /* shared memory region */ 159256694Snp#define T4_ERR_INVALIDATE_MR_WITH_MW_BOUND 0x8 /* attempt to invalidate a */ 160256694Snp /* shared memory region */ 161256694Snp#define T4_ERR_ECC 0x9 /* ECC error detected */ 162256694Snp#define T4_ERR_ECC_PSTAG 0xA /* ECC error detected when */ 163256694Snp /* reading PSTAG for a MW */ 164256694Snp /* Invalidate */ 165256694Snp#define T4_ERR_PBL_ADDR_BOUND 0xB /* pbl addr out of bounds: */ 166256694Snp /* software error */ 167256694Snp#define T4_ERR_SWFLUSH 0xC /* SW FLUSHED */ 168256694Snp#define T4_ERR_CRC 0x10 /* CRC error */ 169256694Snp#define T4_ERR_MARKER 0x11 /* Marker error */ 170256694Snp#define T4_ERR_PDU_LEN_ERR 0x12 /* invalid PDU length */ 171256694Snp#define T4_ERR_OUT_OF_RQE 0x13 /* out of RQE */ 172256694Snp#define T4_ERR_DDP_VERSION 0x14 /* wrong DDP version */ 173256694Snp#define T4_ERR_RDMA_VERSION 0x15 /* wrong RDMA version */ 174256694Snp#define T4_ERR_OPCODE 0x16 /* invalid rdma opcode */ 175256694Snp#define T4_ERR_DDP_QUEUE_NUM 0x17 /* invalid ddp queue number */ 176256694Snp#define T4_ERR_MSN 0x18 /* MSN error */ 177256694Snp#define T4_ERR_TBIT 0x19 /* tag bit not set correctly */ 178256694Snp#define T4_ERR_MO 0x1A /* MO not 0 for TERMINATE */ 179256694Snp /* or READ_REQ */ 180256694Snp#define T4_ERR_MSN_GAP 0x1B 181256694Snp#define T4_ERR_MSN_RANGE 0x1C 182256694Snp#define T4_ERR_IRD_OVERFLOW 0x1D 183256694Snp#define T4_ERR_RQE_ADDR_BOUND 0x1E /* RQE addr out of bounds: */ 184256694Snp /* software error */ 185256694Snp#define T4_ERR_INTERNAL_ERR 0x1F /* internal error (opcode */ 186256694Snp /* mismatch) */ 187256694Snp/* 188256694Snp * CQE defs 189256694Snp */ 190256694Snpstruct t4_cqe { 191256694Snp __be32 header; 192256694Snp __be32 len; 193256694Snp union { 194256694Snp struct { 195256694Snp __be32 stag; 196256694Snp __be32 msn; 197256694Snp } rcqe; 198256694Snp struct { 199256694Snp u32 nada1; 200256694Snp u16 nada2; 201256694Snp u16 cidx; 202256694Snp } scqe; 203256694Snp struct { 204256694Snp __be32 wrid_hi; 205256694Snp __be32 wrid_low; 206256694Snp } gen; 207256694Snp } u; 208256694Snp __be64 reserved; 209256694Snp __be64 bits_type_ts; 210256694Snp}; 211256694Snp 212256694Snp/* macros for flit 0 of the cqe */ 213256694Snp 214256694Snp#define S_CQE_QPID 12 215256694Snp#define M_CQE_QPID 0xFFFFF 216256694Snp#define G_CQE_QPID(x) ((((x) >> S_CQE_QPID)) & M_CQE_QPID) 217256694Snp#define V_CQE_QPID(x) ((x)<<S_CQE_QPID) 218256694Snp 219256694Snp#define S_CQE_SWCQE 11 220256694Snp#define M_CQE_SWCQE 0x1 221256694Snp#define G_CQE_SWCQE(x) ((((x) >> S_CQE_SWCQE)) & M_CQE_SWCQE) 222256694Snp#define V_CQE_SWCQE(x) ((x)<<S_CQE_SWCQE) 223256694Snp 224256694Snp#define S_CQE_STATUS 5 225256694Snp#define M_CQE_STATUS 0x1F 226256694Snp#define G_CQE_STATUS(x) ((((x) >> S_CQE_STATUS)) & M_CQE_STATUS) 227256694Snp#define V_CQE_STATUS(x) ((x)<<S_CQE_STATUS) 228256694Snp 229256694Snp#define S_CQE_TYPE 4 230256694Snp#define M_CQE_TYPE 0x1 231256694Snp#define G_CQE_TYPE(x) ((((x) >> S_CQE_TYPE)) & M_CQE_TYPE) 232256694Snp#define V_CQE_TYPE(x) ((x)<<S_CQE_TYPE) 233256694Snp 234256694Snp#define S_CQE_OPCODE 0 235256694Snp#define M_CQE_OPCODE 0xF 236256694Snp#define G_CQE_OPCODE(x) ((((x) >> S_CQE_OPCODE)) & M_CQE_OPCODE) 237256694Snp#define V_CQE_OPCODE(x) ((x)<<S_CQE_OPCODE) 238256694Snp 239256694Snp#define SW_CQE(x) (G_CQE_SWCQE(be32_to_cpu((x)->header))) 240256694Snp#define CQE_QPID(x) (G_CQE_QPID(be32_to_cpu((x)->header))) 241256694Snp#define CQE_TYPE(x) (G_CQE_TYPE(be32_to_cpu((x)->header))) 242256694Snp#define SQ_TYPE(x) (CQE_TYPE((x))) 243256694Snp#define RQ_TYPE(x) (!CQE_TYPE((x))) 244256694Snp#define CQE_STATUS(x) (G_CQE_STATUS(be32_to_cpu((x)->header))) 245256694Snp#define CQE_OPCODE(x) (G_CQE_OPCODE(be32_to_cpu((x)->header))) 246256694Snp 247256694Snp#define CQE_SEND_OPCODE(x)(\ 248256694Snp (G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND) || \ 249256694Snp (G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_SE) || \ 250256694Snp (G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_INV) || \ 251256694Snp (G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_SE_INV)) 252256694Snp 253256694Snp#define CQE_LEN(x) (be32_to_cpu((x)->len)) 254256694Snp 255256694Snp/* used for RQ completion processing */ 256256694Snp#define CQE_WRID_STAG(x) (be32_to_cpu((x)->u.rcqe.stag)) 257256694Snp#define CQE_WRID_MSN(x) (be32_to_cpu((x)->u.rcqe.msn)) 258256694Snp 259256694Snp/* used for SQ completion processing */ 260256694Snp#define CQE_WRID_SQ_IDX(x) ((x)->u.scqe.cidx) 261256694Snp 262256694Snp/* generic accessor macros */ 263256694Snp#define CQE_WRID_HI(x) ((x)->u.gen.wrid_hi) 264256694Snp#define CQE_WRID_LOW(x) ((x)->u.gen.wrid_low) 265256694Snp 266256694Snp/* macros for flit 3 of the cqe */ 267256694Snp#define S_CQE_GENBIT 63 268256694Snp#define M_CQE_GENBIT 0x1 269256694Snp#define G_CQE_GENBIT(x) (((x) >> S_CQE_GENBIT) & M_CQE_GENBIT) 270256694Snp#define V_CQE_GENBIT(x) ((x)<<S_CQE_GENBIT) 271256694Snp 272256694Snp#define S_CQE_OVFBIT 62 273256694Snp#define M_CQE_OVFBIT 0x1 274256694Snp#define G_CQE_OVFBIT(x) ((((x) >> S_CQE_OVFBIT)) & M_CQE_OVFBIT) 275256694Snp 276256694Snp#define S_CQE_IQTYPE 60 277256694Snp#define M_CQE_IQTYPE 0x3 278256694Snp#define G_CQE_IQTYPE(x) ((((x) >> S_CQE_IQTYPE)) & M_CQE_IQTYPE) 279256694Snp 280256694Snp#define M_CQE_TS 0x0fffffffffffffffULL 281256694Snp#define G_CQE_TS(x) ((x) & M_CQE_TS) 282256694Snp 283256694Snp#define CQE_OVFBIT(x) ((unsigned)G_CQE_OVFBIT(be64_to_cpu((x)->bits_type_ts))) 284256694Snp#define CQE_GENBIT(x) ((unsigned)G_CQE_GENBIT(be64_to_cpu((x)->bits_type_ts))) 285256694Snp#define CQE_TS(x) (G_CQE_TS(be64_to_cpu((x)->bits_type_ts))) 286256694Snp 287256694Snpstruct t4_swsqe { 288256694Snp u64 wr_id; 289256694Snp struct t4_cqe cqe; 290256694Snp int read_len; 291256694Snp int opcode; 292256694Snp int complete; 293256694Snp int signaled; 294256694Snp u16 idx; 295256694Snp}; 296256694Snp 297256694Snpstruct t4_sq { 298256694Snp union t4_wr *queue; 299256694Snp bus_addr_t dma_addr; 300256694Snp DECLARE_PCI_UNMAP_ADDR(mapping); 301256694Snp unsigned long phys_addr; 302256694Snp struct t4_swsqe *sw_sq; 303256694Snp struct t4_swsqe *oldest_read; 304256694Snp u64 udb; 305256694Snp size_t memsize; 306256694Snp u32 qid; 307256694Snp u16 in_use; 308256694Snp u16 size; 309256694Snp u16 cidx; 310256694Snp u16 pidx; 311256694Snp u16 wq_pidx; 312256694Snp u16 flags; 313256694Snp}; 314256694Snp 315256694Snpstruct t4_swrqe { 316256694Snp u64 wr_id; 317256694Snp}; 318256694Snp 319256694Snpstruct t4_rq { 320256694Snp union t4_recv_wr *queue; 321256694Snp bus_addr_t dma_addr; 322256694Snp DECLARE_PCI_UNMAP_ADDR(mapping); 323256694Snp struct t4_swrqe *sw_rq; 324256694Snp u64 udb; 325256694Snp size_t memsize; 326256694Snp u32 qid; 327256694Snp u32 msn; 328256694Snp u32 rqt_hwaddr; 329256694Snp u16 rqt_size; 330256694Snp u16 in_use; 331256694Snp u16 size; 332256694Snp u16 cidx; 333256694Snp u16 pidx; 334256694Snp u16 wq_pidx; 335256694Snp}; 336256694Snp 337256694Snpstruct t4_wq { 338256694Snp struct t4_sq sq; 339256694Snp struct t4_rq rq; 340256694Snp void __iomem *db; 341256694Snp void __iomem *gts; 342256694Snp struct c4iw_rdev *rdev; 343256694Snp}; 344256694Snp 345256694Snpstatic inline int t4_rqes_posted(struct t4_wq *wq) 346256694Snp{ 347256694Snp return wq->rq.in_use; 348256694Snp} 349256694Snp 350256694Snpstatic inline int t4_rq_empty(struct t4_wq *wq) 351256694Snp{ 352256694Snp return wq->rq.in_use == 0; 353256694Snp} 354256694Snp 355256694Snpstatic inline int t4_rq_full(struct t4_wq *wq) 356256694Snp{ 357256694Snp return wq->rq.in_use == (wq->rq.size - 1); 358256694Snp} 359256694Snp 360256694Snpstatic inline u32 t4_rq_avail(struct t4_wq *wq) 361256694Snp{ 362256694Snp return wq->rq.size - 1 - wq->rq.in_use; 363256694Snp} 364256694Snp 365256694Snpstatic inline void t4_rq_produce(struct t4_wq *wq, u8 len16) 366256694Snp{ 367256694Snp wq->rq.in_use++; 368256694Snp if (++wq->rq.pidx == wq->rq.size) 369256694Snp wq->rq.pidx = 0; 370256694Snp wq->rq.wq_pidx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE); 371256694Snp if (wq->rq.wq_pidx >= wq->rq.size * T4_RQ_NUM_SLOTS) 372256694Snp wq->rq.wq_pidx %= wq->rq.size * T4_RQ_NUM_SLOTS; 373256694Snp} 374256694Snp 375256694Snpstatic inline void t4_rq_consume(struct t4_wq *wq) 376256694Snp{ 377256694Snp wq->rq.in_use--; 378256694Snp wq->rq.msn++; 379256694Snp if (++wq->rq.cidx == wq->rq.size) 380256694Snp wq->rq.cidx = 0; 381256694Snp} 382256694Snp 383256694Snpstatic inline u16 t4_rq_host_wq_pidx(struct t4_wq *wq) 384256694Snp{ 385256694Snp return wq->rq.queue[wq->rq.size].status.host_wq_pidx; 386256694Snp} 387256694Snp 388256694Snpstatic inline u16 t4_rq_wq_size(struct t4_wq *wq) 389256694Snp{ 390256694Snp return wq->rq.size * T4_RQ_NUM_SLOTS; 391256694Snp} 392256694Snp 393256694Snpstatic inline int t4_sq_empty(struct t4_wq *wq) 394256694Snp{ 395256694Snp return wq->sq.in_use == 0; 396256694Snp} 397256694Snp 398256694Snpstatic inline int t4_sq_full(struct t4_wq *wq) 399256694Snp{ 400256694Snp return wq->sq.in_use == (wq->sq.size - 1); 401256694Snp} 402256694Snp 403256694Snpstatic inline u32 t4_sq_avail(struct t4_wq *wq) 404256694Snp{ 405256694Snp return wq->sq.size - 1 - wq->sq.in_use; 406256694Snp} 407256694Snp 408256694Snpstatic inline void t4_sq_produce(struct t4_wq *wq, u8 len16) 409256694Snp{ 410256694Snp wq->sq.in_use++; 411256694Snp if (++wq->sq.pidx == wq->sq.size) 412256694Snp wq->sq.pidx = 0; 413256694Snp wq->sq.wq_pidx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE); 414256694Snp if (wq->sq.wq_pidx >= wq->sq.size * T4_SQ_NUM_SLOTS) 415256694Snp wq->sq.wq_pidx %= wq->sq.size * T4_SQ_NUM_SLOTS; 416256694Snp} 417256694Snp 418256694Snpstatic inline void t4_sq_consume(struct t4_wq *wq) 419256694Snp{ 420256694Snp wq->sq.in_use--; 421256694Snp if (++wq->sq.cidx == wq->sq.size) 422256694Snp wq->sq.cidx = 0; 423256694Snp} 424256694Snp 425256694Snpstatic inline u16 t4_sq_host_wq_pidx(struct t4_wq *wq) 426256694Snp{ 427256694Snp return wq->sq.queue[wq->sq.size].status.host_wq_pidx; 428256694Snp} 429256694Snp 430256694Snpstatic inline u16 t4_sq_wq_size(struct t4_wq *wq) 431256694Snp{ 432256694Snp return wq->sq.size * T4_SQ_NUM_SLOTS; 433256694Snp} 434256694Snp 435256694Snpstatic inline void t4_ring_sq_db(struct t4_wq *wq, u16 inc) 436256694Snp{ 437256694Snp wmb(); 438256694Snp writel(QID(wq->sq.qid) | PIDX(inc), wq->db); 439256694Snp} 440256694Snp 441256694Snpstatic inline void t4_ring_rq_db(struct t4_wq *wq, u16 inc) 442256694Snp{ 443256694Snp wmb(); 444256694Snp writel(QID(wq->rq.qid) | PIDX(inc), wq->db); 445256694Snp} 446256694Snp 447256694Snpstatic inline int t4_wq_in_error(struct t4_wq *wq) 448256694Snp{ 449256694Snp return wq->rq.queue[wq->rq.size].status.qp_err; 450256694Snp} 451256694Snp 452256694Snpstatic inline void t4_set_wq_in_error(struct t4_wq *wq) 453256694Snp{ 454256694Snp wq->rq.queue[wq->rq.size].status.qp_err = 1; 455256694Snp} 456256694Snp 457256694Snpstatic inline void t4_disable_wq_db(struct t4_wq *wq) 458256694Snp{ 459256694Snp wq->rq.queue[wq->rq.size].status.db_off = 1; 460256694Snp} 461256694Snp 462256694Snpstatic inline void t4_enable_wq_db(struct t4_wq *wq) 463256694Snp{ 464256694Snp wq->rq.queue[wq->rq.size].status.db_off = 0; 465256694Snp} 466256694Snp 467256694Snpstatic inline int t4_wq_db_enabled(struct t4_wq *wq) 468256694Snp{ 469256694Snp return !wq->rq.queue[wq->rq.size].status.db_off; 470256694Snp} 471256694Snp 472256694Snpstruct t4_cq { 473256694Snp struct t4_cqe *queue; 474256694Snp bus_addr_t dma_addr; 475256694Snp DECLARE_PCI_UNMAP_ADDR(mapping); 476256694Snp struct t4_cqe *sw_queue; 477256694Snp void __iomem *gts; 478256694Snp struct c4iw_rdev *rdev; 479256694Snp u64 ugts; 480256694Snp size_t memsize; 481256694Snp __be64 bits_type_ts; 482256694Snp u32 cqid; 483256694Snp u16 size; /* including status page */ 484256694Snp u16 cidx; 485256694Snp u16 sw_pidx; 486256694Snp u16 sw_cidx; 487256694Snp u16 sw_in_use; 488256694Snp u16 cidx_inc; 489256694Snp u8 gen; 490256694Snp u8 error; 491256694Snp}; 492256694Snp 493256694Snpstatic inline int t4_arm_cq(struct t4_cq *cq, int se) 494256694Snp{ 495256694Snp u32 val; 496256694Snp 497256694Snp while (cq->cidx_inc > CIDXINC_MASK) { 498256694Snp val = SEINTARM(0) | CIDXINC(CIDXINC_MASK) | TIMERREG(7) | 499256694Snp INGRESSQID(cq->cqid); 500256694Snp writel(val, cq->gts); 501256694Snp cq->cidx_inc -= CIDXINC_MASK; 502256694Snp } 503256694Snp val = SEINTARM(se) | CIDXINC(cq->cidx_inc) | TIMERREG(6) | 504256694Snp INGRESSQID(cq->cqid); 505256694Snp writel(val, cq->gts); 506256694Snp cq->cidx_inc = 0; 507256694Snp return 0; 508256694Snp} 509256694Snp 510256694Snpstatic inline void t4_swcq_produce(struct t4_cq *cq) 511256694Snp{ 512256694Snp cq->sw_in_use++; 513256694Snp if (++cq->sw_pidx == cq->size) 514256694Snp cq->sw_pidx = 0; 515256694Snp} 516256694Snp 517256694Snpstatic inline void t4_swcq_consume(struct t4_cq *cq) 518256694Snp{ 519256694Snp cq->sw_in_use--; 520256694Snp if (++cq->sw_cidx == cq->size) 521256694Snp cq->sw_cidx = 0; 522256694Snp} 523256694Snp 524256694Snpstatic inline void t4_hwcq_consume(struct t4_cq *cq) 525256694Snp{ 526256694Snp cq->bits_type_ts = cq->queue[cq->cidx].bits_type_ts; 527256694Snp if (++cq->cidx_inc == (cq->size >> 4)) { 528256694Snp u32 val; 529256694Snp 530256694Snp val = SEINTARM(0) | CIDXINC(cq->cidx_inc) | TIMERREG(7) | 531256694Snp INGRESSQID(cq->cqid); 532256694Snp writel(val, cq->gts); 533256694Snp cq->cidx_inc = 0; 534256694Snp } 535256694Snp if (++cq->cidx == cq->size) { 536256694Snp cq->cidx = 0; 537256694Snp cq->gen ^= 1; 538256694Snp } 539256694Snp} 540256694Snp 541256694Snpstatic inline int t4_valid_cqe(struct t4_cq *cq, struct t4_cqe *cqe) 542256694Snp{ 543256694Snp return (CQE_GENBIT(cqe) == cq->gen); 544256694Snp} 545256694Snp 546256694Snpstatic inline int t4_next_hw_cqe(struct t4_cq *cq, struct t4_cqe **cqe) 547256694Snp{ 548256694Snp int ret; 549256694Snp u16 prev_cidx; 550256694Snp 551256694Snp if (cq->cidx == 0) 552256694Snp prev_cidx = cq->size - 1; 553256694Snp else 554256694Snp prev_cidx = cq->cidx - 1; 555256694Snp 556256694Snp if (cq->queue[prev_cidx].bits_type_ts != cq->bits_type_ts) { 557256694Snp ret = -EOVERFLOW; 558256694Snp cq->error = 1; 559256694Snp printk(KERN_ERR MOD "cq overflow cqid %u\n", cq->cqid); 560256694Snp } else if (t4_valid_cqe(cq, &cq->queue[cq->cidx])) { 561256694Snp *cqe = &cq->queue[cq->cidx]; 562256694Snp ret = 0; 563256694Snp } else 564256694Snp ret = -ENODATA; 565256694Snp return ret; 566256694Snp} 567256694Snp 568256694Snpstatic inline struct t4_cqe *t4_next_sw_cqe(struct t4_cq *cq) 569256694Snp{ 570256694Snp if (cq->sw_in_use) 571256694Snp return &cq->sw_queue[cq->sw_cidx]; 572256694Snp return NULL; 573256694Snp} 574256694Snp 575256694Snpstatic inline int t4_next_cqe(struct t4_cq *cq, struct t4_cqe **cqe) 576256694Snp{ 577256694Snp int ret = 0; 578256694Snp 579256694Snp if (cq->error) 580256694Snp ret = -ENODATA; 581256694Snp else if (cq->sw_in_use) 582256694Snp *cqe = &cq->sw_queue[cq->sw_cidx]; 583256694Snp else 584256694Snp ret = t4_next_hw_cqe(cq, cqe); 585256694Snp return ret; 586256694Snp} 587256694Snp 588256694Snpstatic inline int t4_cq_in_error(struct t4_cq *cq) 589256694Snp{ 590256694Snp return ((struct t4_status_page *)&cq->queue[cq->size])->qp_err; 591256694Snp} 592256694Snp 593256694Snpstatic inline void t4_set_cq_in_error(struct t4_cq *cq) 594256694Snp{ 595256694Snp ((struct t4_status_page *)&cq->queue[cq->size])->qp_err = 1; 596256694Snp} 597256694Snp#endif 598