adapter.h revision 269356
1/*- 2 * Copyright (c) 2011 Chelsio Communications, Inc. 3 * All rights reserved. 4 * Written by: Navdeep Parhar <np@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD: stable/10/sys/dev/cxgbe/adapter.h 269356 2014-07-31 23:04:41Z np $ 28 * 29 */ 30 31#ifndef __T4_ADAPTER_H__ 32#define __T4_ADAPTER_H__ 33 34#include <sys/kernel.h> 35#include <sys/bus.h> 36#include <sys/rman.h> 37#include <sys/types.h> 38#include <sys/malloc.h> 39#include <dev/pci/pcivar.h> 40#include <dev/pci/pcireg.h> 41#include <machine/bus.h> 42#include <sys/socket.h> 43#include <sys/sysctl.h> 44#include <net/ethernet.h> 45#include <net/if.h> 46#include <net/if_media.h> 47#include <netinet/in.h> 48#include <netinet/tcp_lro.h> 49 50#include "offload.h" 51#include "firmware/t4fw_interface.h" 52 53MALLOC_DECLARE(M_CXGBE); 54#define CXGBE_UNIMPLEMENTED(s) \ 55 panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__) 56 57#if defined(__i386__) || defined(__amd64__) 58static __inline void 59prefetch(void *x) 60{ 61 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 62} 63#else 64#define prefetch(x) 65#endif 66 67#ifndef SYSCTL_ADD_UQUAD 68#define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD 69#define sysctl_handle_64 sysctl_handle_quad 70#define CTLTYPE_U64 CTLTYPE_QUAD 71#endif 72 73#if (__FreeBSD_version >= 900030) || \ 74 ((__FreeBSD_version >= 802507) && (__FreeBSD_version < 900000)) 75#define SBUF_DRAIN 1 76#endif 77 78#ifdef __amd64__ 79/* XXX: need systemwide bus_space_read_8/bus_space_write_8 */ 80static __inline uint64_t 81t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle, 82 bus_size_t offset) 83{ 84 KASSERT(tag == X86_BUS_SPACE_MEM, 85 ("%s: can only handle mem space", __func__)); 86 87 return (*(volatile uint64_t *)(handle + offset)); 88} 89 90static __inline void 91t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh, 92 bus_size_t offset, uint64_t value) 93{ 94 KASSERT(tag == X86_BUS_SPACE_MEM, 95 ("%s: can only handle mem space", __func__)); 96 97 *(volatile uint64_t *)(bsh + offset) = value; 98} 99#else 100static __inline uint64_t 101t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle, 102 bus_size_t offset) 103{ 104 return (uint64_t)bus_space_read_4(tag, handle, offset) + 105 ((uint64_t)bus_space_read_4(tag, handle, offset + 4) << 32); 106} 107 108static __inline void 109t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh, 110 bus_size_t offset, uint64_t value) 111{ 112 bus_space_write_4(tag, bsh, offset, value); 113 bus_space_write_4(tag, bsh, offset + 4, value >> 32); 114} 115#endif 116 117struct adapter; 118typedef struct adapter adapter_t; 119 120enum { 121 FW_IQ_QSIZE = 256, 122 FW_IQ_ESIZE = 64, /* At least 64 mandated by the firmware spec */ 123 124 RX_IQ_QSIZE = 1024, 125 RX_IQ_ESIZE = 64, /* At least 64 so CPL_RX_PKT will fit */ 126 127 EQ_ESIZE = 64, /* All egress queues use this entry size */ 128 129 RX_FL_ESIZE = EQ_ESIZE, /* 8 64bit addresses */ 130#if MJUMPAGESIZE != MCLBYTES 131 SW_ZONE_SIZES = 4, /* cluster, jumbop, jumbo9k, jumbo16k */ 132#else 133 SW_ZONE_SIZES = 3, /* cluster, jumbo9k, jumbo16k */ 134#endif 135 CL_METADATA_SIZE = CACHE_LINE_SIZE, 136 137 CTRL_EQ_QSIZE = 128, 138 139 TX_EQ_QSIZE = 1024, 140 TX_SGL_SEGS = 36, 141 TX_WR_FLITS = SGE_MAX_WR_LEN / 8 142}; 143 144enum { 145 /* adapter intr_type */ 146 INTR_INTX = (1 << 0), 147 INTR_MSI = (1 << 1), 148 INTR_MSIX = (1 << 2) 149}; 150 151enum { 152 /* flags understood by begin_synchronized_op */ 153 HOLD_LOCK = (1 << 0), 154 SLEEP_OK = (1 << 1), 155 INTR_OK = (1 << 2), 156 157 /* flags understood by end_synchronized_op */ 158 LOCK_HELD = HOLD_LOCK, 159}; 160 161enum { 162 /* adapter flags */ 163 FULL_INIT_DONE = (1 << 0), 164 FW_OK = (1 << 1), 165 INTR_DIRECT = (1 << 2), /* direct interrupts for everything */ 166 MASTER_PF = (1 << 3), 167 ADAP_SYSCTL_CTX = (1 << 4), 168 TOM_INIT_DONE = (1 << 5), 169 BUF_PACKING_OK = (1 << 6), 170 171 CXGBE_BUSY = (1 << 9), 172 173 /* port flags */ 174 DOOMED = (1 << 0), 175 PORT_INIT_DONE = (1 << 1), 176 PORT_SYSCTL_CTX = (1 << 2), 177 HAS_TRACEQ = (1 << 3), 178}; 179 180#define IS_DOOMED(pi) ((pi)->flags & DOOMED) 181#define SET_DOOMED(pi) do {(pi)->flags |= DOOMED;} while (0) 182#define IS_BUSY(sc) ((sc)->flags & CXGBE_BUSY) 183#define SET_BUSY(sc) do {(sc)->flags |= CXGBE_BUSY;} while (0) 184#define CLR_BUSY(sc) do {(sc)->flags &= ~CXGBE_BUSY;} while (0) 185 186struct port_info { 187 device_t dev; 188 struct adapter *adapter; 189 190 struct ifnet *ifp; 191 struct ifmedia media; 192 193 struct mtx pi_lock; 194 char lockname[16]; 195 unsigned long flags; 196 int if_flags; 197 198 uint16_t *rss; 199 uint16_t viid; 200 int16_t xact_addr_filt;/* index of exact MAC address filter */ 201 uint16_t rss_size; /* size of VI's RSS table slice */ 202 uint8_t lport; /* associated offload logical port */ 203 int8_t mdio_addr; 204 uint8_t port_type; 205 uint8_t mod_type; 206 uint8_t port_id; 207 uint8_t tx_chan; 208 uint8_t rx_chan_map; /* rx MPS channel bitmap */ 209 210 /* These need to be int as they are used in sysctl */ 211 int ntxq; /* # of tx queues */ 212 int first_txq; /* index of first tx queue */ 213 int rsrv_noflowq; /* Reserve queue 0 for non-flowid packets */ 214 int nrxq; /* # of rx queues */ 215 int first_rxq; /* index of first rx queue */ 216#ifdef TCP_OFFLOAD 217 int nofldtxq; /* # of offload tx queues */ 218 int first_ofld_txq; /* index of first offload tx queue */ 219 int nofldrxq; /* # of offload rx queues */ 220 int first_ofld_rxq; /* index of first offload rx queue */ 221#endif 222 int tmr_idx; 223 int pktc_idx; 224 int qsize_rxq; 225 int qsize_txq; 226 227 int linkdnrc; 228 struct link_config link_cfg; 229 struct port_stats stats; 230 231 eventhandler_tag vlan_c; 232 233 struct callout tick; 234 struct sysctl_ctx_list ctx; /* from ifconfig up to driver detach */ 235 236 uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */ 237}; 238 239/* Where the cluster came from, how it has been carved up. */ 240struct cluster_layout { 241 int8_t zidx; 242 int8_t hwidx; 243 uint16_t region1; /* mbufs laid out within this region */ 244 /* region2 is the DMA region */ 245 uint16_t region3; /* cluster_metadata within this region */ 246}; 247 248struct cluster_metadata { 249 u_int refcount; 250#ifdef INVARIANTS 251 struct fl_sdesc *sd; /* For debug only. Could easily be stale */ 252#endif 253}; 254 255struct fl_sdesc { 256 caddr_t cl; 257 uint16_t nmbuf; /* # of driver originated mbufs with ref on cluster */ 258 struct cluster_layout cll; 259}; 260 261struct tx_desc { 262 __be64 flit[8]; 263}; 264 265struct tx_map { 266 struct mbuf *m; 267 bus_dmamap_t map; 268}; 269 270/* DMA maps used for tx */ 271struct tx_maps { 272 struct tx_map *maps; 273 uint32_t map_total; /* # of DMA maps */ 274 uint32_t map_pidx; /* next map to be used */ 275 uint32_t map_cidx; /* reclaimed up to this index */ 276 uint32_t map_avail; /* # of available maps */ 277}; 278 279struct tx_sdesc { 280 uint8_t desc_used; /* # of hardware descriptors used by the WR */ 281 uint8_t credits; /* NIC txq: # of frames sent out in the WR */ 282}; 283 284enum { 285 /* iq flags */ 286 IQ_ALLOCATED = (1 << 0), /* firmware resources allocated */ 287 IQ_HAS_FL = (1 << 1), /* iq associated with a freelist */ 288 IQ_INTR = (1 << 2), /* iq takes direct interrupt */ 289 IQ_LRO_ENABLED = (1 << 3), /* iq is an eth rxq with LRO enabled */ 290 291 /* iq state */ 292 IQS_DISABLED = 0, 293 IQS_BUSY = 1, 294 IQS_IDLE = 2, 295}; 296 297/* 298 * Ingress Queue: T4 is producer, driver is consumer. 299 */ 300struct sge_iq { 301 bus_dma_tag_t desc_tag; 302 bus_dmamap_t desc_map; 303 bus_addr_t ba; /* bus address of descriptor ring */ 304 uint32_t flags; 305 uint16_t abs_id; /* absolute SGE id for the iq */ 306 int8_t intr_pktc_idx; /* packet count threshold index */ 307 int8_t pad0; 308 __be64 *desc; /* KVA of descriptor ring */ 309 310 volatile int state; 311 struct adapter *adapter; 312 const __be64 *cdesc; /* current descriptor */ 313 uint8_t gen; /* generation bit */ 314 uint8_t intr_params; /* interrupt holdoff parameters */ 315 uint8_t intr_next; /* XXX: holdoff for next interrupt */ 316 uint8_t esize; /* size (bytes) of each entry in the queue */ 317 uint16_t qsize; /* size (# of entries) of the queue */ 318 uint16_t cidx; /* consumer index */ 319 uint16_t cntxt_id; /* SGE context id for the iq */ 320 321 STAILQ_ENTRY(sge_iq) link; 322}; 323 324enum { 325 EQ_CTRL = 1, 326 EQ_ETH = 2, 327#ifdef TCP_OFFLOAD 328 EQ_OFLD = 3, 329#endif 330 331 /* eq flags */ 332 EQ_TYPEMASK = 7, /* 3 lsbits hold the type */ 333 EQ_ALLOCATED = (1 << 3), /* firmware resources allocated */ 334 EQ_DOOMED = (1 << 4), /* about to be destroyed */ 335 EQ_CRFLUSHED = (1 << 5), /* expecting an update from SGE */ 336 EQ_STALLED = (1 << 6), /* out of hw descriptors or dmamaps */ 337}; 338 339/* Listed in order of preference. Update t4_sysctls too if you change these */ 340enum {DOORBELL_UDB, DOORBELL_WCWR, DOORBELL_UDBWC, DOORBELL_KDB}; 341 342/* 343 * Egress Queue: driver is producer, T4 is consumer. 344 * 345 * Note: A free list is an egress queue (driver produces the buffers and T4 346 * consumes them) but it's special enough to have its own struct (see sge_fl). 347 */ 348struct sge_eq { 349 unsigned int flags; /* MUST be first */ 350 unsigned int cntxt_id; /* SGE context id for the eq */ 351 bus_dma_tag_t desc_tag; 352 bus_dmamap_t desc_map; 353 char lockname[16]; 354 struct mtx eq_lock; 355 356 struct tx_desc *desc; /* KVA of descriptor ring */ 357 bus_addr_t ba; /* bus address of descriptor ring */ 358 struct sge_qstat *spg; /* status page, for convenience */ 359 int doorbells; 360 volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */ 361 u_int udb_qid; /* relative qid within the doorbell page */ 362 uint16_t cap; /* max # of desc, for convenience */ 363 uint16_t avail; /* available descriptors, for convenience */ 364 uint16_t qsize; /* size (# of entries) of the queue */ 365 uint16_t cidx; /* consumer idx (desc idx) */ 366 uint16_t pidx; /* producer idx (desc idx) */ 367 uint16_t pending; /* # of descriptors used since last doorbell */ 368 uint16_t iqid; /* iq that gets egr_update for the eq */ 369 uint8_t tx_chan; /* tx channel used by the eq */ 370 struct task tx_task; 371 struct callout tx_callout; 372 373 /* stats */ 374 375 uint32_t egr_update; /* # of SGE_EGR_UPDATE notifications for eq */ 376 uint32_t unstalled; /* recovered from stall */ 377}; 378 379struct sw_zone_info { 380 uma_zone_t zone; /* zone that this cluster comes from */ 381 int size; /* size of cluster: 2K, 4K, 9K, 16K, etc. */ 382 int type; /* EXT_xxx type of the cluster */ 383 int8_t head_hwidx; 384 int8_t tail_hwidx; 385}; 386 387struct hw_buf_info { 388 int8_t zidx; /* backpointer to zone; -ve means unused */ 389 int8_t next; /* next hwidx for this zone; -1 means no more */ 390 int size; 391}; 392 393enum { 394 FL_STARVING = (1 << 0), /* on the adapter's list of starving fl's */ 395 FL_DOOMED = (1 << 1), /* about to be destroyed */ 396 FL_BUF_PACKING = (1 << 2), /* buffer packing enabled */ 397}; 398 399#define FL_RUNNING_LOW(fl) (fl->cap - fl->needed <= fl->lowat) 400#define FL_NOT_RUNNING_LOW(fl) (fl->cap - fl->needed >= 2 * fl->lowat) 401 402struct sge_fl { 403 bus_dma_tag_t desc_tag; 404 bus_dmamap_t desc_map; 405 struct cluster_layout cll_def; /* default refill zone, layout */ 406 struct cluster_layout cll_alt; /* alternate refill zone, layout */ 407 struct mtx fl_lock; 408 char lockname[16]; 409 int flags; 410 411 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */ 412 bus_addr_t ba; /* bus address of descriptor ring */ 413 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */ 414 uint32_t cap; /* max # of buffers, for convenience */ 415 uint16_t qsize; /* size (# of entries) of the queue */ 416 uint16_t cntxt_id; /* SGE context id for the freelist */ 417 uint32_t cidx; /* consumer idx (buffer idx, NOT hw desc idx) */ 418 uint32_t rx_offset; /* offset in fl buf (when buffer packing) */ 419 uint32_t pidx; /* producer idx (buffer idx, NOT hw desc idx) */ 420 uint32_t needed; /* # of buffers needed to fill up fl. */ 421 uint32_t lowat; /* # of buffers <= this means fl needs help */ 422 uint32_t pending; /* # of bufs allocated since last doorbell */ 423 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */ 424 425 struct mbuf *m0; 426 struct mbuf **pnext; 427 u_int remaining; 428 429 uint64_t mbuf_allocated;/* # of mbuf allocated from zone_mbuf */ 430 uint64_t mbuf_inlined; /* # of mbuf created within clusters */ 431 uint64_t cl_allocated; /* # of clusters allocated */ 432 uint64_t cl_recycled; /* # of clusters recycled */ 433 uint64_t cl_fast_recycled; /* # of clusters recycled (fast) */ 434}; 435 436/* txq: SGE egress queue + what's needed for Ethernet NIC */ 437struct sge_txq { 438 struct sge_eq eq; /* MUST be first */ 439 440 struct ifnet *ifp; /* the interface this txq belongs to */ 441 bus_dma_tag_t tx_tag; /* tag for transmit buffers */ 442 struct buf_ring *br; /* tx buffer ring */ 443 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */ 444 struct mbuf *m; /* held up due to temporary resource shortage */ 445 446 struct tx_maps txmaps; 447 448 /* stats for common events first */ 449 450 uint64_t txcsum; /* # of times hardware assisted with checksum */ 451 uint64_t tso_wrs; /* # of TSO work requests */ 452 uint64_t vlan_insertion;/* # of times VLAN tag was inserted */ 453 uint64_t imm_wrs; /* # of work requests with immediate data */ 454 uint64_t sgl_wrs; /* # of work requests with direct SGL */ 455 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */ 456 uint64_t txpkts_wrs; /* # of coalesced tx work requests */ 457 uint64_t txpkts_pkts; /* # of frames in coalesced tx work requests */ 458 459 /* stats for not-that-common events */ 460 461 uint32_t no_dmamap; /* no DMA map to load the mbuf */ 462 uint32_t no_desc; /* out of hardware descriptors */ 463} __aligned(CACHE_LINE_SIZE); 464 465/* rxq: SGE ingress queue + SGE free list + miscellaneous items */ 466struct sge_rxq { 467 struct sge_iq iq; /* MUST be first */ 468 struct sge_fl fl; /* MUST follow iq */ 469 470 struct ifnet *ifp; /* the interface this rxq belongs to */ 471#if defined(INET) || defined(INET6) 472 struct lro_ctrl lro; /* LRO state */ 473#endif 474 475 /* stats for common events first */ 476 477 uint64_t rxcsum; /* # of times hardware assisted with checksum */ 478 uint64_t vlan_extraction;/* # of times VLAN tag was extracted */ 479 480 /* stats for not-that-common events */ 481 482} __aligned(CACHE_LINE_SIZE); 483 484static inline struct sge_rxq * 485iq_to_rxq(struct sge_iq *iq) 486{ 487 488 return (__containerof(iq, struct sge_rxq, iq)); 489} 490 491 492#ifdef TCP_OFFLOAD 493/* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */ 494struct sge_ofld_rxq { 495 struct sge_iq iq; /* MUST be first */ 496 struct sge_fl fl; /* MUST follow iq */ 497} __aligned(CACHE_LINE_SIZE); 498 499static inline struct sge_ofld_rxq * 500iq_to_ofld_rxq(struct sge_iq *iq) 501{ 502 503 return (__containerof(iq, struct sge_ofld_rxq, iq)); 504} 505#endif 506 507struct wrqe { 508 STAILQ_ENTRY(wrqe) link; 509 struct sge_wrq *wrq; 510 int wr_len; 511 uint64_t wr[] __aligned(16); 512}; 513 514/* 515 * wrq: SGE egress queue that is given prebuilt work requests. Both the control 516 * and offload tx queues are of this type. 517 */ 518struct sge_wrq { 519 struct sge_eq eq; /* MUST be first */ 520 521 struct adapter *adapter; 522 523 /* List of WRs held up due to lack of tx descriptors */ 524 STAILQ_HEAD(, wrqe) wr_list; 525 526 /* stats for common events first */ 527 528 uint64_t tx_wrs; /* # of tx work requests */ 529 530 /* stats for not-that-common events */ 531 532 uint32_t no_desc; /* out of hardware descriptors */ 533} __aligned(CACHE_LINE_SIZE); 534 535struct sge { 536 int timer_val[SGE_NTIMERS]; 537 int counter_val[SGE_NCOUNTERS]; 538 int fl_starve_threshold; 539 int fl_starve_threshold2; 540 int eq_s_qpp; 541 int iq_s_qpp; 542 543 int nrxq; /* total # of Ethernet rx queues */ 544 int ntxq; /* total # of Ethernet tx tx queues */ 545#ifdef TCP_OFFLOAD 546 int nofldrxq; /* total # of TOE rx queues */ 547 int nofldtxq; /* total # of TOE tx queues */ 548#endif 549 int niq; /* total # of ingress queues */ 550 int neq; /* total # of egress queues */ 551 552 struct sge_iq fwq; /* Firmware event queue */ 553 struct sge_wrq mgmtq; /* Management queue (control queue) */ 554 struct sge_wrq *ctrlq; /* Control queues */ 555 struct sge_txq *txq; /* NIC tx queues */ 556 struct sge_rxq *rxq; /* NIC rx queues */ 557#ifdef TCP_OFFLOAD 558 struct sge_wrq *ofld_txq; /* TOE tx queues */ 559 struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */ 560#endif 561 562 uint16_t iq_start; 563 int eq_start; 564 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */ 565 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */ 566 567 int pack_boundary; 568 int8_t safe_hwidx1; /* may not have room for metadata */ 569 int8_t safe_hwidx2; /* with room for metadata and maybe more */ 570 struct sw_zone_info sw_zone_info[SW_ZONE_SIZES]; 571 struct hw_buf_info hw_buf_info[SGE_FLBUF_SIZES]; 572}; 573 574struct rss_header; 575typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *, 576 struct mbuf *); 577typedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *); 578typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *); 579 580struct adapter { 581 SLIST_ENTRY(adapter) link; 582 device_t dev; 583 struct cdev *cdev; 584 585 /* PCIe register resources */ 586 int regs_rid; 587 struct resource *regs_res; 588 int msix_rid; 589 struct resource *msix_res; 590 bus_space_handle_t bh; 591 bus_space_tag_t bt; 592 bus_size_t mmio_len; 593 int udbs_rid; 594 struct resource *udbs_res; 595 volatile uint8_t *udbs_base; 596 597 unsigned int pf; 598 unsigned int mbox; 599 600 /* Interrupt information */ 601 int intr_type; 602 int intr_count; 603 struct irq { 604 struct resource *res; 605 int rid; 606 void *tag; 607 } *irq; 608 609 bus_dma_tag_t dmat; /* Parent DMA tag */ 610 611 struct sge sge; 612 int lro_timeout; 613 614 struct taskqueue *tq[NCHAN]; /* taskqueues that flush data out */ 615 struct port_info *port[MAX_NPORTS]; 616 uint8_t chan_map[NCHAN]; 617 618#ifdef TCP_OFFLOAD 619 void *tom_softc; /* (struct tom_data *) */ 620 struct tom_tunables tt; 621 void *iwarp_softc; /* (struct c4iw_dev *) */ 622#endif 623 struct l2t_data *l2t; /* L2 table */ 624 struct tid_info tids; 625 626 int doorbells; 627 int open_device_map; 628#ifdef TCP_OFFLOAD 629 int offload_map; 630#endif 631 int flags; 632 633 char ifp_lockname[16]; 634 struct mtx ifp_lock; 635 struct ifnet *ifp; /* tracer ifp */ 636 struct ifmedia media; 637 int traceq; /* iq used by all tracers, -1 if none */ 638 int tracer_valid; /* bitmap of valid tracers */ 639 int tracer_enabled; /* bitmap of enabled tracers */ 640 641 char fw_version[32]; 642 char cfg_file[32]; 643 u_int cfcsum; 644 struct adapter_params params; 645 struct t4_virt_res vres; 646 647 uint16_t linkcaps; 648 uint16_t niccaps; 649 uint16_t toecaps; 650 uint16_t rdmacaps; 651 uint16_t iscsicaps; 652 uint16_t fcoecaps; 653 654 struct sysctl_ctx_list ctx; /* from adapter_full_init to full_uninit */ 655 656 struct mtx sc_lock; 657 char lockname[16]; 658 659 /* Starving free lists */ 660 struct mtx sfl_lock; /* same cache-line as sc_lock? but that's ok */ 661 TAILQ_HEAD(, sge_fl) sfl; 662 struct callout sfl_callout; 663 664 an_handler_t an_handler __aligned(CACHE_LINE_SIZE); 665 fw_msg_handler_t fw_msg_handler[5]; /* NUM_FW6_TYPES */ 666 cpl_handler_t cpl_handler[0xef]; /* NUM_CPL_CMDS */ 667 668#ifdef INVARIANTS 669 const char *last_op; 670 const void *last_op_thr; 671#endif 672 673 int sc_do_rxcopy; 674}; 675 676#define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock) 677#define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock) 678#define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED) 679#define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED) 680 681/* XXX: not bulletproof, but much better than nothing */ 682#define ASSERT_SYNCHRONIZED_OP(sc) \ 683 KASSERT(IS_BUSY(sc) && \ 684 (mtx_owned(&(sc)->sc_lock) || sc->last_op_thr == curthread), \ 685 ("%s: operation not synchronized.", __func__)) 686 687#define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock) 688#define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock) 689#define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED) 690#define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED) 691 692#define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock) 693#define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock) 694#define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock) 695#define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED) 696#define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED) 697 698#define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl) 699#define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl) 700#define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl) 701#define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl) 702 703#define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock) 704#define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock) 705#define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock) 706#define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED) 707#define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED) 708 709#define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq) 710#define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq) 711#define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq) 712#define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq) 713#define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq) 714 715#define for_each_txq(pi, iter, q) \ 716 for (q = &pi->adapter->sge.txq[pi->first_txq], iter = 0; \ 717 iter < pi->ntxq; ++iter, ++q) 718#define for_each_rxq(pi, iter, q) \ 719 for (q = &pi->adapter->sge.rxq[pi->first_rxq], iter = 0; \ 720 iter < pi->nrxq; ++iter, ++q) 721#define for_each_ofld_txq(pi, iter, q) \ 722 for (q = &pi->adapter->sge.ofld_txq[pi->first_ofld_txq], iter = 0; \ 723 iter < pi->nofldtxq; ++iter, ++q) 724#define for_each_ofld_rxq(pi, iter, q) \ 725 for (q = &pi->adapter->sge.ofld_rxq[pi->first_ofld_rxq], iter = 0; \ 726 iter < pi->nofldrxq; ++iter, ++q) 727 728/* One for errors, one for firmware events */ 729#define T4_EXTRA_INTR 2 730 731static inline uint32_t 732t4_read_reg(struct adapter *sc, uint32_t reg) 733{ 734 735 return bus_space_read_4(sc->bt, sc->bh, reg); 736} 737 738static inline void 739t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val) 740{ 741 742 bus_space_write_4(sc->bt, sc->bh, reg, val); 743} 744 745static inline uint64_t 746t4_read_reg64(struct adapter *sc, uint32_t reg) 747{ 748 749 return t4_bus_space_read_8(sc->bt, sc->bh, reg); 750} 751 752static inline void 753t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val) 754{ 755 756 t4_bus_space_write_8(sc->bt, sc->bh, reg, val); 757} 758 759static inline void 760t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val) 761{ 762 763 *val = pci_read_config(sc->dev, reg, 1); 764} 765 766static inline void 767t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val) 768{ 769 770 pci_write_config(sc->dev, reg, val, 1); 771} 772 773static inline void 774t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val) 775{ 776 777 *val = pci_read_config(sc->dev, reg, 2); 778} 779 780static inline void 781t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val) 782{ 783 784 pci_write_config(sc->dev, reg, val, 2); 785} 786 787static inline void 788t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val) 789{ 790 791 *val = pci_read_config(sc->dev, reg, 4); 792} 793 794static inline void 795t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val) 796{ 797 798 pci_write_config(sc->dev, reg, val, 4); 799} 800 801static inline struct port_info * 802adap2pinfo(struct adapter *sc, int idx) 803{ 804 805 return (sc->port[idx]); 806} 807 808static inline void 809t4_os_set_hw_addr(struct adapter *sc, int idx, uint8_t hw_addr[]) 810{ 811 812 bcopy(hw_addr, sc->port[idx]->hw_addr, ETHER_ADDR_LEN); 813} 814 815static inline bool 816is_10G_port(const struct port_info *pi) 817{ 818 819 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) != 0); 820} 821 822static inline bool 823is_40G_port(const struct port_info *pi) 824{ 825 826 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G) != 0); 827} 828 829static inline int 830tx_resume_threshold(struct sge_eq *eq) 831{ 832 833 return (eq->qsize / 4); 834} 835 836/* t4_main.c */ 837void t4_tx_task(void *, int); 838void t4_tx_callout(void *); 839int t4_os_find_pci_capability(struct adapter *, int); 840int t4_os_pci_save_state(struct adapter *); 841int t4_os_pci_restore_state(struct adapter *); 842void t4_os_portmod_changed(const struct adapter *, int); 843void t4_os_link_changed(struct adapter *, int, int, int); 844void t4_iterate(void (*)(struct adapter *, void *), void *); 845int t4_register_cpl_handler(struct adapter *, int, cpl_handler_t); 846int t4_register_an_handler(struct adapter *, an_handler_t); 847int t4_register_fw_msg_handler(struct adapter *, int, fw_msg_handler_t); 848int t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 849int begin_synchronized_op(struct adapter *, struct port_info *, int, char *); 850void end_synchronized_op(struct adapter *, int); 851 852/* t4_sge.c */ 853void t4_sge_modload(void); 854void t4_sge_modunload(void); 855uint64_t t4_sge_extfree_refs(void); 856void t4_init_sge_cpl_handlers(struct adapter *); 857void t4_tweak_chip_settings(struct adapter *); 858int t4_read_chip_settings(struct adapter *); 859int t4_create_dma_tag(struct adapter *); 860void t4_sge_sysctls(struct adapter *, struct sysctl_ctx_list *, 861 struct sysctl_oid_list *); 862int t4_destroy_dma_tag(struct adapter *); 863int t4_setup_adapter_queues(struct adapter *); 864int t4_teardown_adapter_queues(struct adapter *); 865int t4_setup_port_queues(struct port_info *); 866int t4_teardown_port_queues(struct port_info *); 867int t4_alloc_tx_maps(struct tx_maps *, bus_dma_tag_t, int, int); 868void t4_free_tx_maps(struct tx_maps *, bus_dma_tag_t); 869void t4_intr_all(void *); 870void t4_intr(void *); 871void t4_intr_err(void *); 872void t4_intr_evt(void *); 873void t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct wrqe *); 874int t4_eth_tx(struct ifnet *, struct sge_txq *, struct mbuf *); 875void t4_update_fl_bufsize(struct ifnet *); 876int can_resume_tx(struct sge_eq *); 877 878/* t4_tracer.c */ 879struct t4_tracer; 880void t4_tracer_modload(void); 881void t4_tracer_modunload(void); 882void t4_tracer_port_detach(struct adapter *); 883int t4_get_tracer(struct adapter *, struct t4_tracer *); 884int t4_set_tracer(struct adapter *, struct t4_tracer *); 885int t4_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 886int t5_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 887 888static inline struct wrqe * 889alloc_wrqe(int wr_len, struct sge_wrq *wrq) 890{ 891 int len = offsetof(struct wrqe, wr) + wr_len; 892 struct wrqe *wr; 893 894 wr = malloc(len, M_CXGBE, M_NOWAIT); 895 if (__predict_false(wr == NULL)) 896 return (NULL); 897 wr->wr_len = wr_len; 898 wr->wrq = wrq; 899 return (wr); 900} 901 902static inline void * 903wrtod(struct wrqe *wr) 904{ 905 return (&wr->wr[0]); 906} 907 908static inline void 909free_wrqe(struct wrqe *wr) 910{ 911 free(wr, M_CXGBE); 912} 913 914static inline void 915t4_wrq_tx(struct adapter *sc, struct wrqe *wr) 916{ 917 struct sge_wrq *wrq = wr->wrq; 918 919 TXQ_LOCK(wrq); 920 t4_wrq_tx_locked(sc, wrq, wr); 921 TXQ_UNLOCK(wrq); 922} 923 924#endif 925