adapter.h revision 256794
1249259Sdim/*- 2249259Sdim * Copyright (c) 2011 Chelsio Communications, Inc. 3249259Sdim * All rights reserved. 4249259Sdim * Written by: Navdeep Parhar <np@FreeBSD.org> 5249259Sdim * 6249259Sdim * Redistribution and use in source and binary forms, with or without 7249259Sdim * modification, are permitted provided that the following conditions 8249259Sdim * are met: 9249259Sdim * 1. Redistributions of source code must retain the above copyright 10249259Sdim * notice, this list of conditions and the following disclaimer. 11249259Sdim * 2. Redistributions in binary form must reproduce the above copyright 12249259Sdim * notice, this list of conditions and the following disclaimer in the 13249259Sdim * documentation and/or other materials provided with the distribution. 14249259Sdim * 15249259Sdim * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16249259Sdim * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17249259Sdim * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18249259Sdim * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19249259Sdim * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20249259Sdim * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21249259Sdim * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22249259Sdim * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23249259Sdim * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24249259Sdim * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25249259Sdim * SUCH DAMAGE. 26249259Sdim * 27249259Sdim * $FreeBSD: stable/10/sys/dev/cxgbe/adapter.h 256794 2013-10-20 16:45:01Z np $ 28249259Sdim * 29249259Sdim */ 30249259Sdim 31249259Sdim#ifndef __T4_ADAPTER_H__ 32249259Sdim#define __T4_ADAPTER_H__ 33249259Sdim 34249259Sdim#include <sys/kernel.h> 35249259Sdim#include <sys/bus.h> 36249259Sdim#include <sys/rman.h> 37249259Sdim#include <sys/types.h> 38249259Sdim#include <sys/malloc.h> 39249259Sdim#include <dev/pci/pcivar.h> 40249259Sdim#include <dev/pci/pcireg.h> 41249259Sdim#include <machine/bus.h> 42249259Sdim#include <sys/socket.h> 43249259Sdim#include <sys/sysctl.h> 44249259Sdim#include <net/ethernet.h> 45249259Sdim#include <net/if.h> 46249259Sdim#include <net/if_media.h> 47249259Sdim#include <netinet/in.h> 48249259Sdim#include <netinet/tcp_lro.h> 49249259Sdim 50249259Sdim#include "offload.h" 51249259Sdim#include "firmware/t4fw_interface.h" 52249259Sdim 53249259SdimMALLOC_DECLARE(M_CXGBE); 54249259Sdim#define CXGBE_UNIMPLEMENTED(s) \ 55249259Sdim panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__) 56249259Sdim 57249259Sdim#if defined(__i386__) || defined(__amd64__) 58249259Sdimstatic __inline void 59249259Sdimprefetch(void *x) 60249259Sdim{ 61249259Sdim __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 62249259Sdim} 63249259Sdim#else 64249259Sdim#define prefetch(x) 65249259Sdim#endif 66249259Sdim 67249259Sdim#ifndef SYSCTL_ADD_UQUAD 68249259Sdim#define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD 69249259Sdim#define sysctl_handle_64 sysctl_handle_quad 70249259Sdim#define CTLTYPE_U64 CTLTYPE_QUAD 71249259Sdim#endif 72249259Sdim 73249259Sdim#if (__FreeBSD_version >= 900030) || \ 74249259Sdim ((__FreeBSD_version >= 802507) && (__FreeBSD_version < 900000)) 75249259Sdim#define SBUF_DRAIN 1 76249259Sdim#endif 77249259Sdim 78249259Sdim#ifdef __amd64__ 79249259Sdim/* XXX: need systemwide bus_space_read_8/bus_space_write_8 */ 80249259Sdimstatic __inline uint64_t 81249259Sdimt4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle, 82249259Sdim bus_size_t offset) 83249259Sdim{ 84249259Sdim KASSERT(tag == X86_BUS_SPACE_MEM, 85249259Sdim ("%s: can only handle mem space", __func__)); 86249259Sdim 87249259Sdim return (*(volatile uint64_t *)(handle + offset)); 88249259Sdim} 89249259Sdim 90249259Sdimstatic __inline void 91249259Sdimt4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh, 92249259Sdim bus_size_t offset, uint64_t value) 93249259Sdim{ 94249259Sdim KASSERT(tag == X86_BUS_SPACE_MEM, 95249259Sdim ("%s: can only handle mem space", __func__)); 96249259Sdim 97249259Sdim *(volatile uint64_t *)(bsh + offset) = value; 98249259Sdim} 99249259Sdim#else 100249259Sdimstatic __inline uint64_t 101249259Sdimt4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle, 102249259Sdim bus_size_t offset) 103249259Sdim{ 104249259Sdim return (uint64_t)bus_space_read_4(tag, handle, offset) + 105249259Sdim ((uint64_t)bus_space_read_4(tag, handle, offset + 4) << 32); 106249259Sdim} 107249259Sdim 108249259Sdimstatic __inline void 109249259Sdimt4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh, 110249259Sdim bus_size_t offset, uint64_t value) 111249259Sdim{ 112249259Sdim bus_space_write_4(tag, bsh, offset, value); 113249259Sdim bus_space_write_4(tag, bsh, offset + 4, value >> 32); 114249259Sdim} 115249259Sdim#endif 116249259Sdim 117249259Sdimstruct adapter; 118249259Sdimtypedef struct adapter adapter_t; 119249259Sdim 120249259Sdimenum { 121249259Sdim FW_IQ_QSIZE = 256, 122249259Sdim FW_IQ_ESIZE = 64, /* At least 64 mandated by the firmware spec */ 123249259Sdim 124249259Sdim RX_IQ_QSIZE = 1024, 125249259Sdim RX_IQ_ESIZE = 64, /* At least 64 so CPL_RX_PKT will fit */ 126249259Sdim 127251662Sdim EQ_ESIZE = 64, /* All egress queues use this entry size */ 128251662Sdim 129251662Sdim RX_FL_ESIZE = EQ_ESIZE, /* 8 64bit addresses */ 130251662Sdim#if MJUMPAGESIZE != MCLBYTES 131251662Sdim FL_BUF_SIZES_MAX = 5, /* cluster, jumbop, jumbo9k, jumbo16k, extra */ 132251662Sdim#else 133251662Sdim FL_BUF_SIZES_MAX = 4, /* cluster, jumbo9k, jumbo16k, extra */ 134263508Sdim#endif 135263508Sdim 136263508Sdim CTRL_EQ_QSIZE = 128, 137263508Sdim 138263508Sdim TX_EQ_QSIZE = 1024, 139263508Sdim TX_SGL_SEGS = 36, 140263508Sdim TX_WR_FLITS = SGE_MAX_WR_LEN / 8 141263508Sdim}; 142263508Sdim 143249259Sdimenum { 144249259Sdim /* adapter intr_type */ 145249259Sdim INTR_INTX = (1 << 0), 146249259Sdim INTR_MSI = (1 << 1), 147249259Sdim INTR_MSIX = (1 << 2) 148249259Sdim}; 149249259Sdim 150249259Sdimenum { 151249259Sdim /* flags understood by begin_synchronized_op */ 152249259Sdim HOLD_LOCK = (1 << 0), 153249259Sdim SLEEP_OK = (1 << 1), 154249259Sdim INTR_OK = (1 << 2), 155249259Sdim 156249259Sdim /* flags understood by end_synchronized_op */ 157249259Sdim LOCK_HELD = HOLD_LOCK, 158249259Sdim}; 159249259Sdim 160249259Sdimenum { 161249259Sdim /* adapter flags */ 162249259Sdim FULL_INIT_DONE = (1 << 0), 163249259Sdim FW_OK = (1 << 1), 164249259Sdim INTR_DIRECT = (1 << 2), /* direct interrupts for everything */ 165249259Sdim MASTER_PF = (1 << 3), 166249259Sdim ADAP_SYSCTL_CTX = (1 << 4), 167249259Sdim TOM_INIT_DONE = (1 << 5), 168249259Sdim BUF_PACKING_OK = (1 << 6), 169249259Sdim 170249259Sdim CXGBE_BUSY = (1 << 9), 171249259Sdim 172249259Sdim /* port flags */ 173249259Sdim DOOMED = (1 << 0), 174249259Sdim PORT_INIT_DONE = (1 << 1), 175249259Sdim PORT_SYSCTL_CTX = (1 << 2), 176249259Sdim HAS_TRACEQ = (1 << 3), 177249259Sdim}; 178249259Sdim 179249259Sdim#define IS_DOOMED(pi) ((pi)->flags & DOOMED) 180249259Sdim#define SET_DOOMED(pi) do {(pi)->flags |= DOOMED;} while (0) 181249259Sdim#define IS_BUSY(sc) ((sc)->flags & CXGBE_BUSY) 182249259Sdim#define SET_BUSY(sc) do {(sc)->flags |= CXGBE_BUSY;} while (0) 183249259Sdim#define CLR_BUSY(sc) do {(sc)->flags &= ~CXGBE_BUSY;} while (0) 184249259Sdim 185249259Sdimstruct port_info { 186249259Sdim device_t dev; 187249259Sdim struct adapter *adapter; 188249259Sdim 189249259Sdim struct ifnet *ifp; 190249259Sdim struct ifmedia media; 191249259Sdim 192249259Sdim struct mtx pi_lock; 193249259Sdim char lockname[16]; 194249259Sdim unsigned long flags; 195249259Sdim int if_flags; 196249259Sdim 197249259Sdim uint16_t viid; 198249259Sdim int16_t xact_addr_filt;/* index of exact MAC address filter */ 199249259Sdim uint16_t rss_size; /* size of VI's RSS table slice */ 200249259Sdim uint8_t lport; /* associated offload logical port */ 201249259Sdim int8_t mdio_addr; 202249259Sdim uint8_t port_type; 203249259Sdim uint8_t mod_type; 204249259Sdim uint8_t port_id; 205249259Sdim uint8_t tx_chan; 206249259Sdim 207249259Sdim /* These need to be int as they are used in sysctl */ 208249259Sdim int ntxq; /* # of tx queues */ 209249259Sdim int first_txq; /* index of first tx queue */ 210249259Sdim int nrxq; /* # of rx queues */ 211249259Sdim int first_rxq; /* index of first rx queue */ 212249259Sdim#ifdef TCP_OFFLOAD 213249259Sdim int nofldtxq; /* # of offload tx queues */ 214249259Sdim int first_ofld_txq; /* index of first offload tx queue */ 215249259Sdim int nofldrxq; /* # of offload rx queues */ 216249259Sdim int first_ofld_rxq; /* index of first offload rx queue */ 217249259Sdim#endif 218249259Sdim int tmr_idx; 219249259Sdim int pktc_idx; 220249259Sdim int qsize_rxq; 221249259Sdim int qsize_txq; 222249259Sdim 223249259Sdim int linkdnrc; 224249259Sdim struct link_config link_cfg; 225249259Sdim struct port_stats stats; 226249259Sdim 227249259Sdim eventhandler_tag vlan_c; 228249259Sdim 229249259Sdim struct callout tick; 230249259Sdim struct sysctl_ctx_list ctx; /* from ifconfig up to driver detach */ 231249259Sdim 232249259Sdim uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */ 233249259Sdim}; 234249259Sdim 235249259Sdimstruct fl_sdesc { 236249259Sdim bus_dmamap_t map; 237249259Sdim caddr_t cl; 238249259Sdim uint8_t tag_idx; /* the fl->tag entry this map comes from */ 239249259Sdim#ifdef INVARIANTS 240249259Sdim __be64 ba_hwtag; 241249259Sdim#endif 242249259Sdim}; 243249259Sdim 244249259Sdimstruct tx_desc { 245249259Sdim __be64 flit[8]; 246249259Sdim}; 247249259Sdim 248249259Sdimstruct tx_map { 249249259Sdim struct mbuf *m; 250249259Sdim bus_dmamap_t map; 251249259Sdim}; 252249259Sdim 253249259Sdim/* DMA maps used for tx */ 254249259Sdimstruct tx_maps { 255249259Sdim struct tx_map *maps; 256249259Sdim uint32_t map_total; /* # of DMA maps */ 257249259Sdim uint32_t map_pidx; /* next map to be used */ 258249259Sdim uint32_t map_cidx; /* reclaimed up to this index */ 259249259Sdim uint32_t map_avail; /* # of available maps */ 260249259Sdim}; 261249259Sdim 262249259Sdimstruct tx_sdesc { 263249259Sdim uint8_t desc_used; /* # of hardware descriptors used by the WR */ 264249259Sdim uint8_t credits; /* NIC txq: # of frames sent out in the WR */ 265249259Sdim}; 266249259Sdim 267249259Sdimenum { 268249259Sdim /* iq flags */ 269249259Sdim IQ_ALLOCATED = (1 << 0), /* firmware resources allocated */ 270249259Sdim IQ_HAS_FL = (1 << 1), /* iq associated with a freelist */ 271249259Sdim IQ_INTR = (1 << 2), /* iq takes direct interrupt */ 272249259Sdim IQ_LRO_ENABLED = (1 << 3), /* iq is an eth rxq with LRO enabled */ 273249259Sdim 274249259Sdim /* iq state */ 275249259Sdim IQS_DISABLED = 0, 276249259Sdim IQS_BUSY = 1, 277249259Sdim IQS_IDLE = 2, 278249259Sdim}; 279263508Sdim 280263508Sdim/* 281263508Sdim * Ingress Queue: T4 is producer, driver is consumer. 282249259Sdim */ 283249259Sdimstruct sge_iq { 284249259Sdim bus_dma_tag_t desc_tag; 285249259Sdim bus_dmamap_t desc_map; 286249259Sdim bus_addr_t ba; /* bus address of descriptor ring */ 287249259Sdim uint32_t flags; 288249259Sdim uint16_t abs_id; /* absolute SGE id for the iq */ 289249259Sdim int8_t intr_pktc_idx; /* packet count threshold index */ 290249259Sdim int8_t pad0; 291249259Sdim __be64 *desc; /* KVA of descriptor ring */ 292249259Sdim 293249259Sdim volatile int state; 294249259Sdim struct adapter *adapter; 295249259Sdim const __be64 *cdesc; /* current descriptor */ 296249259Sdim uint8_t gen; /* generation bit */ 297249259Sdim uint8_t intr_params; /* interrupt holdoff parameters */ 298249259Sdim uint8_t intr_next; /* XXX: holdoff for next interrupt */ 299249259Sdim uint8_t esize; /* size (bytes) of each entry in the queue */ 300249259Sdim uint16_t qsize; /* size (# of entries) of the queue */ 301249259Sdim uint16_t cidx; /* consumer index */ 302249259Sdim uint16_t cntxt_id; /* SGE context id for the iq */ 303249259Sdim 304249259Sdim STAILQ_ENTRY(sge_iq) link; 305249259Sdim}; 306249259Sdim 307249259Sdimenum { 308249259Sdim EQ_CTRL = 1, 309249259Sdim EQ_ETH = 2, 310249259Sdim#ifdef TCP_OFFLOAD 311249259Sdim EQ_OFLD = 3, 312249259Sdim#endif 313249259Sdim 314249259Sdim /* eq flags */ 315249259Sdim EQ_TYPEMASK = 7, /* 3 lsbits hold the type */ 316249259Sdim EQ_ALLOCATED = (1 << 3), /* firmware resources allocated */ 317249259Sdim EQ_DOOMED = (1 << 4), /* about to be destroyed */ 318249259Sdim EQ_CRFLUSHED = (1 << 5), /* expecting an update from SGE */ 319249259Sdim EQ_STALLED = (1 << 6), /* out of hw descriptors or dmamaps */ 320249259Sdim}; 321249259Sdim 322249259Sdim/* Listed in order of preference. Update t4_sysctls too if you change these */ 323249259Sdimenum {DOORBELL_UDB, DOORBELL_WCWR, DOORBELL_UDBWC, DOORBELL_KDB}; 324249259Sdim 325249259Sdim/* 326249259Sdim * Egress Queue: driver is producer, T4 is consumer. 327249259Sdim * 328249259Sdim * Note: A free list is an egress queue (driver produces the buffers and T4 329249259Sdim * consumes them) but it's special enough to have its own struct (see sge_fl). 330249259Sdim */ 331249259Sdimstruct sge_eq { 332249259Sdim unsigned int flags; /* MUST be first */ 333249259Sdim unsigned int cntxt_id; /* SGE context id for the eq */ 334249259Sdim bus_dma_tag_t desc_tag; 335249259Sdim bus_dmamap_t desc_map; 336249259Sdim char lockname[16]; 337249259Sdim struct mtx eq_lock; 338249259Sdim 339249259Sdim struct tx_desc *desc; /* KVA of descriptor ring */ 340249259Sdim bus_addr_t ba; /* bus address of descriptor ring */ 341249259Sdim struct sge_qstat *spg; /* status page, for convenience */ 342249259Sdim int doorbells; 343249259Sdim volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */ 344249259Sdim u_int udb_qid; /* relative qid within the doorbell page */ 345249259Sdim uint16_t cap; /* max # of desc, for convenience */ 346249259Sdim uint16_t avail; /* available descriptors, for convenience */ 347249259Sdim uint16_t qsize; /* size (# of entries) of the queue */ 348249259Sdim uint16_t cidx; /* consumer idx (desc idx) */ 349249259Sdim uint16_t pidx; /* producer idx (desc idx) */ 350249259Sdim uint16_t pending; /* # of descriptors used since last doorbell */ 351249259Sdim uint16_t iqid; /* iq that gets egr_update for the eq */ 352249259Sdim uint8_t tx_chan; /* tx channel used by the eq */ 353249259Sdim struct task tx_task; 354249259Sdim struct callout tx_callout; 355249259Sdim 356249259Sdim /* stats */ 357263508Sdim 358263508Sdim uint32_t egr_update; /* # of SGE_EGR_UPDATE notifications for eq */ 359263508Sdim uint32_t unstalled; /* recovered from stall */ 360263508Sdim}; 361249259Sdim 362249259Sdimstruct fl_buf_info { 363249259Sdim u_int size; 364249259Sdim int type; 365249259Sdim int hwtag:4; /* tag in low 4 bits of the pa. */ 366249259Sdim uma_zone_t zone; 367249259Sdim}; 368249259Sdim#define FL_BUF_SIZES(sc) (sc->sge.fl_buf_sizes) 369249259Sdim#define FL_BUF_SIZE(sc, x) (sc->sge.fl_buf_info[x].size) 370249259Sdim#define FL_BUF_TYPE(sc, x) (sc->sge.fl_buf_info[x].type) 371249259Sdim#define FL_BUF_HWTAG(sc, x) (sc->sge.fl_buf_info[x].hwtag) 372249259Sdim#define FL_BUF_ZONE(sc, x) (sc->sge.fl_buf_info[x].zone) 373249259Sdim 374249259Sdimenum { 375249259Sdim FL_STARVING = (1 << 0), /* on the adapter's list of starving fl's */ 376249259Sdim FL_DOOMED = (1 << 1), /* about to be destroyed */ 377249259Sdim FL_BUF_PACKING = (1 << 2), /* buffer packing enabled */ 378249259Sdim}; 379249259Sdim 380249259Sdim#define FL_RUNNING_LOW(fl) (fl->cap - fl->needed <= fl->lowat) 381249259Sdim#define FL_NOT_RUNNING_LOW(fl) (fl->cap - fl->needed >= 2 * fl->lowat) 382249259Sdim 383249259Sdimstruct sge_fl { 384249259Sdim bus_dma_tag_t desc_tag; 385249259Sdim bus_dmamap_t desc_map; 386249259Sdim bus_dma_tag_t tag[FL_BUF_SIZES_MAX]; /* only first FL_BUF_SIZES(sc) are 387249259Sdim valid */ 388249259Sdim uint8_t tag_idx; 389249259Sdim struct mtx fl_lock; 390249259Sdim char lockname[16]; 391249259Sdim int flags; 392249259Sdim 393249259Sdim __be64 *desc; /* KVA of descriptor ring, ptr to addresses */ 394249259Sdim bus_addr_t ba; /* bus address of descriptor ring */ 395249259Sdim struct fl_sdesc *sdesc; /* KVA of software descriptor ring */ 396249259Sdim uint32_t cap; /* max # of buffers, for convenience */ 397249259Sdim uint16_t qsize; /* size (# of entries) of the queue */ 398249259Sdim uint16_t cntxt_id; /* SGE context id for the freelist */ 399249259Sdim uint32_t cidx; /* consumer idx (buffer idx, NOT hw desc idx) */ 400249259Sdim uint32_t rx_offset; /* offset in fl buf (when buffer packing) */ 401249259Sdim uint32_t pidx; /* producer idx (buffer idx, NOT hw desc idx) */ 402249259Sdim uint32_t needed; /* # of buffers needed to fill up fl. */ 403249259Sdim uint32_t lowat; /* # of buffers <= this means fl needs help */ 404249259Sdim uint32_t pending; /* # of bufs allocated since last doorbell */ 405249259Sdim u_int dmamap_failed; 406249259Sdim struct mbuf *mstash[8]; 407249259Sdim TAILQ_ENTRY(sge_fl) link; /* All starving freelists */ 408249259Sdim}; 409249259Sdim 410249259Sdim/* txq: SGE egress queue + what's needed for Ethernet NIC */ 411249259Sdimstruct sge_txq { 412249259Sdim struct sge_eq eq; /* MUST be first */ 413249259Sdim 414249259Sdim struct ifnet *ifp; /* the interface this txq belongs to */ 415249259Sdim bus_dma_tag_t tx_tag; /* tag for transmit buffers */ 416249259Sdim struct buf_ring *br; /* tx buffer ring */ 417249259Sdim struct tx_sdesc *sdesc; /* KVA of software descriptor ring */ 418249259Sdim struct mbuf *m; /* held up due to temporary resource shortage */ 419249259Sdim 420249259Sdim struct tx_maps txmaps; 421249259Sdim 422249259Sdim /* stats for common events first */ 423249259Sdim 424249259Sdim uint64_t txcsum; /* # of times hardware assisted with checksum */ 425249259Sdim uint64_t tso_wrs; /* # of TSO work requests */ 426249259Sdim uint64_t vlan_insertion;/* # of times VLAN tag was inserted */ 427249259Sdim uint64_t imm_wrs; /* # of work requests with immediate data */ 428249259Sdim uint64_t sgl_wrs; /* # of work requests with direct SGL */ 429249259Sdim uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */ 430249259Sdim uint64_t txpkts_wrs; /* # of coalesced tx work requests */ 431249259Sdim uint64_t txpkts_pkts; /* # of frames in coalesced tx work requests */ 432249259Sdim 433249259Sdim /* stats for not-that-common events */ 434249259Sdim 435249259Sdim uint32_t no_dmamap; /* no DMA map to load the mbuf */ 436249259Sdim uint32_t no_desc; /* out of hardware descriptors */ 437249259Sdim} __aligned(CACHE_LINE_SIZE); 438249259Sdim 439249259Sdim/* rxq: SGE ingress queue + SGE free list + miscellaneous items */ 440249259Sdimstruct sge_rxq { 441249259Sdim struct sge_iq iq; /* MUST be first */ 442249259Sdim struct sge_fl fl; /* MUST follow iq */ 443249259Sdim 444249259Sdim struct ifnet *ifp; /* the interface this rxq belongs to */ 445249259Sdim#if defined(INET) || defined(INET6) 446249259Sdim struct lro_ctrl lro; /* LRO state */ 447249259Sdim#endif 448249259Sdim 449249259Sdim /* stats for common events first */ 450249259Sdim 451249259Sdim uint64_t rxcsum; /* # of times hardware assisted with checksum */ 452249259Sdim uint64_t vlan_extraction;/* # of times VLAN tag was extracted */ 453249259Sdim 454249259Sdim /* stats for not-that-common events */ 455249259Sdim 456263508Sdim} __aligned(CACHE_LINE_SIZE); 457263508Sdim 458263508Sdimstatic inline struct sge_rxq * 459249259Sdimiq_to_rxq(struct sge_iq *iq) 460249259Sdim{ 461249259Sdim 462249259Sdim return (__containerof(iq, struct sge_rxq, iq)); 463249259Sdim} 464249259Sdim 465249259Sdim 466249259Sdim#ifdef TCP_OFFLOAD 467249259Sdim/* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */ 468249259Sdimstruct sge_ofld_rxq { 469249259Sdim struct sge_iq iq; /* MUST be first */ 470249259Sdim struct sge_fl fl; /* MUST follow iq */ 471249259Sdim} __aligned(CACHE_LINE_SIZE); 472263508Sdim 473263508Sdimstatic inline struct sge_ofld_rxq * 474263508Sdimiq_to_ofld_rxq(struct sge_iq *iq) 475249259Sdim{ 476249259Sdim 477249259Sdim return (__containerof(iq, struct sge_ofld_rxq, iq)); 478249259Sdim} 479249259Sdim#endif 480249259Sdim 481249259Sdimstruct wrqe { 482249259Sdim STAILQ_ENTRY(wrqe) link; 483249259Sdim struct sge_wrq *wrq; 484249259Sdim int wr_len; 485249259Sdim uint64_t wr[] __aligned(16); 486249259Sdim}; 487249259Sdim 488249259Sdim/* 489249259Sdim * wrq: SGE egress queue that is given prebuilt work requests. Both the control 490249259Sdim * and offload tx queues are of this type. 491249259Sdim */ 492249259Sdimstruct sge_wrq { 493249259Sdim struct sge_eq eq; /* MUST be first */ 494249259Sdim 495249259Sdim struct adapter *adapter; 496249259Sdim 497249259Sdim /* List of WRs held up due to lack of tx descriptors */ 498249259Sdim STAILQ_HEAD(, wrqe) wr_list; 499249259Sdim 500249259Sdim /* stats for common events first */ 501249259Sdim 502249259Sdim uint64_t tx_wrs; /* # of tx work requests */ 503249259Sdim 504249259Sdim /* stats for not-that-common events */ 505263508Sdim 506263508Sdim uint32_t no_desc; /* out of hardware descriptors */ 507263508Sdim} __aligned(CACHE_LINE_SIZE); 508263508Sdim 509249259Sdimstruct sge { 510249259Sdim int timer_val[SGE_NTIMERS]; 511249259Sdim int counter_val[SGE_NCOUNTERS]; 512249259Sdim int fl_starve_threshold; 513249259Sdim int eq_s_qpp; 514249259Sdim int iq_s_qpp; 515249259Sdim 516249259Sdim int nrxq; /* total # of Ethernet rx queues */ 517249259Sdim int ntxq; /* total # of Ethernet tx tx queues */ 518249259Sdim#ifdef TCP_OFFLOAD 519249259Sdim int nofldrxq; /* total # of TOE rx queues */ 520249259Sdim int nofldtxq; /* total # of TOE tx queues */ 521249259Sdim#endif 522249259Sdim int niq; /* total # of ingress queues */ 523249259Sdim int neq; /* total # of egress queues */ 524249259Sdim 525249259Sdim struct sge_iq fwq; /* Firmware event queue */ 526249259Sdim struct sge_wrq mgmtq; /* Management queue (control queue) */ 527249259Sdim struct sge_wrq *ctrlq; /* Control queues */ 528249259Sdim struct sge_txq *txq; /* NIC tx queues */ 529249259Sdim struct sge_rxq *rxq; /* NIC rx queues */ 530249259Sdim#ifdef TCP_OFFLOAD 531249259Sdim struct sge_wrq *ofld_txq; /* TOE tx queues */ 532249259Sdim struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */ 533249259Sdim#endif 534249259Sdim 535249259Sdim uint16_t iq_start; 536249259Sdim int eq_start; 537249259Sdim struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */ 538249259Sdim struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */ 539249259Sdim 540249259Sdim u_int fl_buf_sizes __aligned(CACHE_LINE_SIZE); 541249259Sdim struct fl_buf_info fl_buf_info[FL_BUF_SIZES_MAX]; 542249259Sdim}; 543249259Sdim 544249259Sdimstruct rss_header; 545249259Sdimtypedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *, 546249259Sdim struct mbuf *); 547249259Sdimtypedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *); 548249259Sdimtypedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *); 549249259Sdim 550249259Sdimstruct adapter { 551249259Sdim SLIST_ENTRY(adapter) link; 552249259Sdim device_t dev; 553249259Sdim struct cdev *cdev; 554249259Sdim 555249259Sdim /* PCIe register resources */ 556249259Sdim int regs_rid; 557249259Sdim struct resource *regs_res; 558249259Sdim int msix_rid; 559249259Sdim struct resource *msix_res; 560249259Sdim bus_space_handle_t bh; 561249259Sdim bus_space_tag_t bt; 562249259Sdim bus_size_t mmio_len; 563249259Sdim int udbs_rid; 564249259Sdim struct resource *udbs_res; 565249259Sdim volatile uint8_t *udbs_base; 566249259Sdim 567249259Sdim unsigned int pf; 568249259Sdim unsigned int mbox; 569249259Sdim 570249259Sdim /* Interrupt information */ 571249259Sdim int intr_type; 572249259Sdim int intr_count; 573249259Sdim struct irq { 574249259Sdim struct resource *res; 575249259Sdim int rid; 576249259Sdim void *tag; 577249259Sdim } *irq; 578249259Sdim 579249259Sdim bus_dma_tag_t dmat; /* Parent DMA tag */ 580249259Sdim 581249259Sdim struct sge sge; 582249259Sdim int lro_timeout; 583249259Sdim 584249259Sdim struct taskqueue *tq[NCHAN]; /* taskqueues that flush data out */ 585249259Sdim struct port_info *port[MAX_NPORTS]; 586249259Sdim uint8_t chan_map[NCHAN]; 587249259Sdim 588249259Sdim#ifdef TCP_OFFLOAD 589249259Sdim void *tom_softc; /* (struct tom_data *) */ 590249259Sdim struct tom_tunables tt; 591249259Sdim void *iwarp_softc; /* (struct c4iw_dev *) */ 592249259Sdim#endif 593249259Sdim struct l2t_data *l2t; /* L2 table */ 594249259Sdim struct tid_info tids; 595249259Sdim 596249259Sdim int doorbells; 597249259Sdim int open_device_map; 598249259Sdim#ifdef TCP_OFFLOAD 599249259Sdim int offload_map; 600249259Sdim#endif 601249259Sdim int flags; 602249259Sdim 603249259Sdim char ifp_lockname[16]; 604249259Sdim struct mtx ifp_lock; 605249259Sdim struct ifnet *ifp; /* tracer ifp */ 606249259Sdim struct ifmedia media; 607249259Sdim int traceq; /* iq used by all tracers, -1 if none */ 608249259Sdim int tracer_valid; /* bitmap of valid tracers */ 609249259Sdim int tracer_enabled; /* bitmap of enabled tracers */ 610249259Sdim 611249259Sdim char fw_version[32]; 612249259Sdim char cfg_file[32]; 613249259Sdim u_int cfcsum; 614249259Sdim struct adapter_params params; 615249259Sdim struct t4_virt_res vres; 616249259Sdim 617249259Sdim uint16_t linkcaps; 618249259Sdim uint16_t niccaps; 619249259Sdim uint16_t toecaps; 620263508Sdim uint16_t rdmacaps; 621249259Sdim uint16_t iscsicaps; 622249259Sdim uint16_t fcoecaps; 623249259Sdim 624249259Sdim struct sysctl_ctx_list ctx; /* from adapter_full_init to full_uninit */ 625249259Sdim 626249259Sdim struct mtx sc_lock; 627249259Sdim char lockname[16]; 628249259Sdim 629249259Sdim /* Starving free lists */ 630249259Sdim struct mtx sfl_lock; /* same cache-line as sc_lock? but that's ok */ 631249259Sdim TAILQ_HEAD(, sge_fl) sfl; 632249259Sdim struct callout sfl_callout; 633249259Sdim 634249259Sdim an_handler_t an_handler __aligned(CACHE_LINE_SIZE); 635249259Sdim fw_msg_handler_t fw_msg_handler[5]; /* NUM_FW6_TYPES */ 636249259Sdim cpl_handler_t cpl_handler[0xef]; /* NUM_CPL_CMDS */ 637249259Sdim 638249259Sdim#ifdef INVARIANTS 639249259Sdim const char *last_op; 640249259Sdim const void *last_op_thr; 641249259Sdim#endif 642249259Sdim}; 643249259Sdim 644249259Sdim#define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock) 645249259Sdim#define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock) 646249259Sdim#define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED) 647249259Sdim#define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED) 648249259Sdim 649249259Sdim/* XXX: not bulletproof, but much better than nothing */ 650249259Sdim#define ASSERT_SYNCHRONIZED_OP(sc) \ 651249259Sdim KASSERT(IS_BUSY(sc) && \ 652249259Sdim (mtx_owned(&(sc)->sc_lock) || sc->last_op_thr == curthread), \ 653249259Sdim ("%s: operation not synchronized.", __func__)) 654249259Sdim 655249259Sdim#define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock) 656249259Sdim#define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock) 657249259Sdim#define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED) 658249259Sdim#define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED) 659249259Sdim 660249259Sdim#define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock) 661249259Sdim#define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock) 662249259Sdim#define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock) 663249259Sdim#define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED) 664249259Sdim#define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED) 665249259Sdim 666249259Sdim#define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl) 667249259Sdim#define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl) 668249259Sdim#define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl) 669249259Sdim#define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl) 670249259Sdim 671249259Sdim#define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock) 672249259Sdim#define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock) 673249259Sdim#define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock) 674249259Sdim#define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED) 675249259Sdim#define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED) 676249259Sdim 677249259Sdim#define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq) 678249259Sdim#define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq) 679249259Sdim#define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq) 680249259Sdim#define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq) 681249259Sdim#define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq) 682249259Sdim 683249259Sdim#define for_each_txq(pi, iter, q) \ 684249259Sdim for (q = &pi->adapter->sge.txq[pi->first_txq], iter = 0; \ 685249259Sdim iter < pi->ntxq; ++iter, ++q) 686249259Sdim#define for_each_rxq(pi, iter, q) \ 687249259Sdim for (q = &pi->adapter->sge.rxq[pi->first_rxq], iter = 0; \ 688249259Sdim iter < pi->nrxq; ++iter, ++q) 689249259Sdim#define for_each_ofld_txq(pi, iter, q) \ 690249259Sdim for (q = &pi->adapter->sge.ofld_txq[pi->first_ofld_txq], iter = 0; \ 691249259Sdim iter < pi->nofldtxq; ++iter, ++q) 692249259Sdim#define for_each_ofld_rxq(pi, iter, q) \ 693249259Sdim for (q = &pi->adapter->sge.ofld_rxq[pi->first_ofld_rxq], iter = 0; \ 694249259Sdim iter < pi->nofldrxq; ++iter, ++q) 695249259Sdim 696249259Sdim/* One for errors, one for firmware events */ 697249259Sdim#define T4_EXTRA_INTR 2 698249259Sdim 699249259Sdimstatic inline uint32_t 700249259Sdimt4_read_reg(struct adapter *sc, uint32_t reg) 701249259Sdim{ 702249259Sdim 703249259Sdim return bus_space_read_4(sc->bt, sc->bh, reg); 704249259Sdim} 705249259Sdim 706249259Sdimstatic inline void 707249259Sdimt4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val) 708249259Sdim{ 709249259Sdim 710249259Sdim bus_space_write_4(sc->bt, sc->bh, reg, val); 711249259Sdim} 712249259Sdim 713249259Sdimstatic inline uint64_t 714249259Sdimt4_read_reg64(struct adapter *sc, uint32_t reg) 715249259Sdim{ 716249259Sdim 717249259Sdim return t4_bus_space_read_8(sc->bt, sc->bh, reg); 718249259Sdim} 719249259Sdim 720249259Sdimstatic inline void 721249259Sdimt4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val) 722249259Sdim{ 723249259Sdim 724249259Sdim t4_bus_space_write_8(sc->bt, sc->bh, reg, val); 725249259Sdim} 726249259Sdim 727249259Sdimstatic inline void 728249259Sdimt4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val) 729249259Sdim{ 730249259Sdim 731249259Sdim *val = pci_read_config(sc->dev, reg, 1); 732249259Sdim} 733249259Sdim 734249259Sdimstatic inline void 735249259Sdimt4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val) 736249259Sdim{ 737249259Sdim 738249259Sdim pci_write_config(sc->dev, reg, val, 1); 739249259Sdim} 740249259Sdim 741263508Sdimstatic inline void 742263508Sdimt4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val) 743263508Sdim{ 744263508Sdim 745263508Sdim *val = pci_read_config(sc->dev, reg, 2); 746263508Sdim} 747263508Sdim 748263508Sdimstatic inline void 749263508Sdimt4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val) 750263508Sdim{ 751263508Sdim 752263508Sdim pci_write_config(sc->dev, reg, val, 2); 753263508Sdim} 754263508Sdim 755263508Sdimstatic inline void 756263508Sdimt4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val) 757263508Sdim{ 758263508Sdim 759263508Sdim *val = pci_read_config(sc->dev, reg, 4); 760263508Sdim} 761263508Sdim 762263508Sdimstatic inline void 763263508Sdimt4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val) 764263508Sdim{ 765263508Sdim 766263508Sdim pci_write_config(sc->dev, reg, val, 4); 767263508Sdim} 768263508Sdim 769static inline struct port_info * 770adap2pinfo(struct adapter *sc, int idx) 771{ 772 773 return (sc->port[idx]); 774} 775 776static inline void 777t4_os_set_hw_addr(struct adapter *sc, int idx, uint8_t hw_addr[]) 778{ 779 780 bcopy(hw_addr, sc->port[idx]->hw_addr, ETHER_ADDR_LEN); 781} 782 783static inline bool 784is_10G_port(const struct port_info *pi) 785{ 786 787 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) != 0); 788} 789 790static inline bool 791is_40G_port(const struct port_info *pi) 792{ 793 794 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G) != 0); 795} 796 797static inline int 798tx_resume_threshold(struct sge_eq *eq) 799{ 800 801 return (eq->qsize / 4); 802} 803 804/* t4_main.c */ 805void t4_tx_task(void *, int); 806void t4_tx_callout(void *); 807int t4_os_find_pci_capability(struct adapter *, int); 808int t4_os_pci_save_state(struct adapter *); 809int t4_os_pci_restore_state(struct adapter *); 810void t4_os_portmod_changed(const struct adapter *, int); 811void t4_os_link_changed(struct adapter *, int, int, int); 812void t4_iterate(void (*)(struct adapter *, void *), void *); 813int t4_register_cpl_handler(struct adapter *, int, cpl_handler_t); 814int t4_register_an_handler(struct adapter *, an_handler_t); 815int t4_register_fw_msg_handler(struct adapter *, int, fw_msg_handler_t); 816int t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 817int begin_synchronized_op(struct adapter *, struct port_info *, int, char *); 818void end_synchronized_op(struct adapter *, int); 819 820/* t4_sge.c */ 821void t4_sge_modload(void); 822void t4_init_sge_cpl_handlers(struct adapter *); 823void t4_tweak_chip_settings(struct adapter *); 824int t4_read_chip_settings(struct adapter *); 825int t4_create_dma_tag(struct adapter *); 826void t4_sge_sysctls(struct adapter *, struct sysctl_ctx_list *, 827 struct sysctl_oid_list *); 828int t4_destroy_dma_tag(struct adapter *); 829int t4_setup_adapter_queues(struct adapter *); 830int t4_teardown_adapter_queues(struct adapter *); 831int t4_setup_port_queues(struct port_info *); 832int t4_teardown_port_queues(struct port_info *); 833int t4_alloc_tx_maps(struct tx_maps *, bus_dma_tag_t, int, int); 834void t4_free_tx_maps(struct tx_maps *, bus_dma_tag_t); 835void t4_intr_all(void *); 836void t4_intr(void *); 837void t4_intr_err(void *); 838void t4_intr_evt(void *); 839void t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct wrqe *); 840int t4_eth_tx(struct ifnet *, struct sge_txq *, struct mbuf *); 841void t4_update_fl_bufsize(struct ifnet *); 842int can_resume_tx(struct sge_eq *); 843 844/* t4_tracer.c */ 845struct t4_tracer; 846void t4_tracer_modload(void); 847void t4_tracer_modunload(void); 848void t4_tracer_port_detach(struct adapter *); 849int t4_get_tracer(struct adapter *, struct t4_tracer *); 850int t4_set_tracer(struct adapter *, struct t4_tracer *); 851int t4_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 852int t5_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 853 854static inline struct wrqe * 855alloc_wrqe(int wr_len, struct sge_wrq *wrq) 856{ 857 int len = offsetof(struct wrqe, wr) + wr_len; 858 struct wrqe *wr; 859 860 wr = malloc(len, M_CXGBE, M_NOWAIT); 861 if (__predict_false(wr == NULL)) 862 return (NULL); 863 wr->wr_len = wr_len; 864 wr->wrq = wrq; 865 return (wr); 866} 867 868static inline void * 869wrtod(struct wrqe *wr) 870{ 871 return (&wr->wr[0]); 872} 873 874static inline void 875free_wrqe(struct wrqe *wr) 876{ 877 free(wr, M_CXGBE); 878} 879 880static inline void 881t4_wrq_tx(struct adapter *sc, struct wrqe *wr) 882{ 883 struct sge_wrq *wrq = wr->wrq; 884 885 TXQ_LOCK(wrq); 886 t4_wrq_tx_locked(sc, wrq, wr); 887 TXQ_UNLOCK(wrq); 888} 889 890#endif 891