1255736Sdavidch/*- 2265797Sdavidcs * Copyright (c) 2007-2014 QLogic Corporation. All rights reserved. 3255736Sdavidch * 4255736Sdavidch * Redistribution and use in source and binary forms, with or without 5255736Sdavidch * modification, are permitted provided that the following conditions 6255736Sdavidch * are met: 7255736Sdavidch * 8255736Sdavidch * 1. Redistributions of source code must retain the above copyright 9255736Sdavidch * notice, this list of conditions and the following disclaimer. 10255736Sdavidch * 2. Redistributions in binary form must reproduce the above copyright 11255736Sdavidch * notice, this list of conditions and the following disclaimer in the 12255736Sdavidch * documentation and/or other materials provided with the distribution. 13255736Sdavidch * 14255736Sdavidch * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 15255736Sdavidch * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16255736Sdavidch * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17255736Sdavidch * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 18255736Sdavidch * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 19255736Sdavidch * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 20255736Sdavidch * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 21255736Sdavidch * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 22255736Sdavidch * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 23255736Sdavidch * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 24255736Sdavidch * THE POSSIBILITY OF SUCH DAMAGE. 25255736Sdavidch */ 26255736Sdavidch 27255736Sdavidch#include <sys/cdefs.h> 28255736Sdavidch__FBSDID("$FreeBSD$"); 29255736Sdavidch 30255736Sdavidch#ifndef ECORE_FW_DEFS_H 31255736Sdavidch#define ECORE_FW_DEFS_H 32255736Sdavidch 33255736Sdavidch 34255736Sdavidch#define CSTORM_ASSERT_LIST_INDEX_OFFSET (IRO[148].base) 35255736Sdavidch#define CSTORM_ASSERT_LIST_OFFSET(assertListEntry) \ 36255736Sdavidch (IRO[147].base + ((assertListEntry) * IRO[147].m1)) 37255736Sdavidch#define CSTORM_EVENT_RING_DATA_OFFSET(pfId) \ 38255736Sdavidch (IRO[153].base + (((pfId)>>1) * IRO[153].m1) + (((pfId)&1) * \ 39255736Sdavidch IRO[153].m2)) 40255736Sdavidch#define CSTORM_EVENT_RING_PROD_OFFSET(pfId) \ 41255736Sdavidch (IRO[154].base + (((pfId)>>1) * IRO[154].m1) + (((pfId)&1) * \ 42255736Sdavidch IRO[154].m2)) 43255736Sdavidch#define CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(funcId) \ 44255736Sdavidch (IRO[159].base + ((funcId) * IRO[159].m1)) 45255736Sdavidch#define CSTORM_FUNC_EN_OFFSET(funcId) \ 46255736Sdavidch (IRO[149].base + ((funcId) * IRO[149].m1)) 47255736Sdavidch#define CSTORM_HC_SYNC_LINE_INDEX_E1X_OFFSET(hcIndex, sbId) \ 48255736Sdavidch (IRO[139].base + ((hcIndex) * IRO[139].m1) + ((sbId) * IRO[139].m2)) 49255736Sdavidch#define CSTORM_HC_SYNC_LINE_INDEX_E2_OFFSET(hcIndex, sbId) \ 50255736Sdavidch (IRO[138].base + (((hcIndex)>>2) * IRO[138].m1) + (((hcIndex)&3) \ 51255736Sdavidch * IRO[138].m2) + ((sbId) * IRO[138].m3)) 52255736Sdavidch#define CSTORM_IGU_MODE_OFFSET (IRO[157].base) 53255736Sdavidch#define CSTORM_ISCSI_CQ_SIZE_OFFSET(pfId) \ 54255736Sdavidch (IRO[317].base + ((pfId) * IRO[317].m1)) 55255736Sdavidch#define CSTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfId) \ 56255736Sdavidch (IRO[318].base + ((pfId) * IRO[318].m1)) 57255736Sdavidch#define CSTORM_ISCSI_EQ_CONS_OFFSET(pfId, iscsiEqId) \ 58255736Sdavidch (IRO[310].base + ((pfId) * IRO[310].m1) + ((iscsiEqId) * IRO[310].m2)) 59255736Sdavidch#define CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfId, iscsiEqId) \ 60255736Sdavidch (IRO[312].base + ((pfId) * IRO[312].m1) + ((iscsiEqId) * IRO[312].m2)) 61255736Sdavidch#define CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfId, iscsiEqId) \ 62255736Sdavidch (IRO[311].base + ((pfId) * IRO[311].m1) + ((iscsiEqId) * IRO[311].m2)) 63255736Sdavidch#define CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_VALID_OFFSET(pfId, iscsiEqId) \ 64255736Sdavidch (IRO[313].base + ((pfId) * IRO[313].m1) + ((iscsiEqId) * IRO[313].m2)) 65255736Sdavidch#define CSTORM_ISCSI_EQ_PROD_OFFSET(pfId, iscsiEqId) \ 66255736Sdavidch (IRO[309].base + ((pfId) * IRO[309].m1) + ((iscsiEqId) * IRO[309].m2)) 67255736Sdavidch#define CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(pfId, iscsiEqId) \ 68255736Sdavidch (IRO[315].base + ((pfId) * IRO[315].m1) + ((iscsiEqId) * IRO[315].m2)) 69255736Sdavidch#define CSTORM_ISCSI_EQ_SB_NUM_OFFSET(pfId, iscsiEqId) \ 70255736Sdavidch (IRO[314].base + ((pfId) * IRO[314].m1) + ((iscsiEqId) * IRO[314].m2)) 71255736Sdavidch#define CSTORM_ISCSI_HQ_SIZE_OFFSET(pfId) \ 72255736Sdavidch (IRO[316].base + ((pfId) * IRO[316].m1)) 73255736Sdavidch#define CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \ 74255736Sdavidch (IRO[308].base + ((pfId) * IRO[308].m1)) 75255736Sdavidch#define CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \ 76255736Sdavidch (IRO[307].base + ((pfId) * IRO[307].m1)) 77255736Sdavidch#define CSTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \ 78255736Sdavidch (IRO[306].base + ((pfId) * IRO[306].m1)) 79255736Sdavidch#define CSTORM_RECORD_SLOW_PATH_OFFSET(funcId) \ 80255736Sdavidch (IRO[151].base + ((funcId) * IRO[151].m1)) 81255736Sdavidch#define CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(pfId) \ 82255736Sdavidch (IRO[142].base + ((pfId) * IRO[142].m1)) 83255736Sdavidch#define CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(pfId) \ 84255736Sdavidch (IRO[143].base + ((pfId) * IRO[143].m1)) 85255736Sdavidch#define CSTORM_SP_STATUS_BLOCK_OFFSET(pfId) \ 86255736Sdavidch (IRO[141].base + ((pfId) * IRO[141].m1)) 87255736Sdavidch#define CSTORM_SP_STATUS_BLOCK_SIZE (IRO[141].size) 88255736Sdavidch#define CSTORM_SP_SYNC_BLOCK_OFFSET(pfId) \ 89255736Sdavidch (IRO[144].base + ((pfId) * IRO[144].m1)) 90255736Sdavidch#define CSTORM_SP_SYNC_BLOCK_SIZE (IRO[144].size) 91255736Sdavidch#define CSTORM_STATUS_BLOCK_DATA_FLAGS_OFFSET(sbId, hcIndex) \ 92255736Sdavidch (IRO[136].base + ((sbId) * IRO[136].m1) + ((hcIndex) * IRO[136].m2)) 93255736Sdavidch#define CSTORM_STATUS_BLOCK_DATA_OFFSET(sbId) \ 94255736Sdavidch (IRO[133].base + ((sbId) * IRO[133].m1)) 95255736Sdavidch#define CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(sbId) \ 96255736Sdavidch (IRO[134].base + ((sbId) * IRO[134].m1)) 97255736Sdavidch#define CSTORM_STATUS_BLOCK_DATA_TIMEOUT_OFFSET(sbId, hcIndex) \ 98255736Sdavidch (IRO[135].base + ((sbId) * IRO[135].m1) + ((hcIndex) * IRO[135].m2)) 99255736Sdavidch#define CSTORM_STATUS_BLOCK_OFFSET(sbId) \ 100255736Sdavidch (IRO[132].base + ((sbId) * IRO[132].m1)) 101255736Sdavidch#define CSTORM_STATUS_BLOCK_SIZE (IRO[132].size) 102255736Sdavidch#define CSTORM_SYNC_BLOCK_OFFSET(sbId) \ 103255736Sdavidch (IRO[137].base + ((sbId) * IRO[137].m1)) 104255736Sdavidch#define CSTORM_SYNC_BLOCK_SIZE (IRO[137].size) 105255736Sdavidch#define CSTORM_VF_TO_PF_OFFSET(funcId) \ 106255736Sdavidch (IRO[150].base + ((funcId) * IRO[150].m1)) 107255736Sdavidch#define TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET (IRO[204].base) 108255736Sdavidch#define TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(pfId) \ 109255736Sdavidch (IRO[203].base + ((pfId) * IRO[203].m1)) 110255736Sdavidch#define TSTORM_ASSERT_LIST_INDEX_OFFSET (IRO[102].base) 111255736Sdavidch#define TSTORM_ASSERT_LIST_OFFSET(assertListEntry) \ 112255736Sdavidch (IRO[101].base + ((assertListEntry) * IRO[101].m1)) 113255736Sdavidch#define TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(pfId) \ 114255736Sdavidch (IRO[201].base + ((pfId) * IRO[201].m1)) 115255736Sdavidch#define TSTORM_FUNC_EN_OFFSET(funcId) \ 116255736Sdavidch (IRO[103].base + ((funcId) * IRO[103].m1)) 117255736Sdavidch#define TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfId) \ 118255736Sdavidch (IRO[272].base + ((pfId) * IRO[272].m1)) 119255736Sdavidch#define TSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \ 120255736Sdavidch (IRO[271].base + ((pfId) * IRO[271].m1)) 121255736Sdavidch#define TSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \ 122255736Sdavidch (IRO[270].base + ((pfId) * IRO[270].m1)) 123255736Sdavidch#define TSTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \ 124255736Sdavidch (IRO[269].base + ((pfId) * IRO[269].m1)) 125255736Sdavidch#define TSTORM_ISCSI_RQ_SIZE_OFFSET(pfId) \ 126255736Sdavidch (IRO[268].base + ((pfId) * IRO[268].m1)) 127255736Sdavidch#define TSTORM_ISCSI_TCP_LOCAL_ADV_WND_OFFSET(pfId) \ 128255736Sdavidch (IRO[278].base + ((pfId) * IRO[278].m1)) 129255736Sdavidch#define TSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(pfId) \ 130255736Sdavidch (IRO[264].base + ((pfId) * IRO[264].m1)) 131255736Sdavidch#define TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfId) \ 132255736Sdavidch (IRO[265].base + ((pfId) * IRO[265].m1)) 133255736Sdavidch#define TSTORM_ISCSI_TCP_VARS_MID_LOCAL_MAC_ADDR_OFFSET(pfId) \ 134255736Sdavidch (IRO[266].base + ((pfId) * IRO[266].m1)) 135255736Sdavidch#define TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfId) \ 136255736Sdavidch (IRO[267].base + ((pfId) * IRO[267].m1)) 137255736Sdavidch#define TSTORM_MAC_FILTER_CONFIG_OFFSET(pfId) \ 138255736Sdavidch (IRO[202].base + ((pfId) * IRO[202].m1)) 139255736Sdavidch#define TSTORM_RECORD_SLOW_PATH_OFFSET(funcId) \ 140255736Sdavidch (IRO[105].base + ((funcId) * IRO[105].m1)) 141255736Sdavidch#define TSTORM_TCP_MAX_CWND_OFFSET(pfId) \ 142255736Sdavidch (IRO[217].base + ((pfId) * IRO[217].m1)) 143255736Sdavidch#define TSTORM_VF_TO_PF_OFFSET(funcId) \ 144255736Sdavidch (IRO[104].base + ((funcId) * IRO[104].m1)) 145255736Sdavidch#define USTORM_AGG_DATA_OFFSET (IRO[206].base) 146255736Sdavidch#define USTORM_AGG_DATA_SIZE (IRO[206].size) 147255736Sdavidch#define USTORM_ASSERT_LIST_INDEX_OFFSET (IRO[177].base) 148255736Sdavidch#define USTORM_ASSERT_LIST_OFFSET(assertListEntry) \ 149255736Sdavidch (IRO[176].base + ((assertListEntry) * IRO[176].m1)) 150255736Sdavidch#define USTORM_ETH_PAUSE_ENABLED_OFFSET(portId) \ 151255736Sdavidch (IRO[183].base + ((portId) * IRO[183].m1)) 152255736Sdavidch#define USTORM_FCOE_EQ_PROD_OFFSET(pfId) \ 153255736Sdavidch (IRO[319].base + ((pfId) * IRO[319].m1)) 154255736Sdavidch#define USTORM_FUNC_EN_OFFSET(funcId) \ 155255736Sdavidch (IRO[178].base + ((funcId) * IRO[178].m1)) 156255736Sdavidch#define USTORM_ISCSI_CQ_SIZE_OFFSET(pfId) \ 157255736Sdavidch (IRO[283].base + ((pfId) * IRO[283].m1)) 158255736Sdavidch#define USTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfId) \ 159255736Sdavidch (IRO[284].base + ((pfId) * IRO[284].m1)) 160255736Sdavidch#define USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfId) \ 161255736Sdavidch (IRO[288].base + ((pfId) * IRO[288].m1)) 162255736Sdavidch#define USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfId) \ 163255736Sdavidch (IRO[285].base + ((pfId) * IRO[285].m1)) 164255736Sdavidch#define USTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \ 165255736Sdavidch (IRO[281].base + ((pfId) * IRO[281].m1)) 166255736Sdavidch#define USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \ 167255736Sdavidch (IRO[280].base + ((pfId) * IRO[280].m1)) 168255736Sdavidch#define USTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \ 169255736Sdavidch (IRO[279].base + ((pfId) * IRO[279].m1)) 170255736Sdavidch#define USTORM_ISCSI_R2TQ_SIZE_OFFSET(pfId) \ 171255736Sdavidch (IRO[282].base + ((pfId) * IRO[282].m1)) 172255736Sdavidch#define USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(pfId) \ 173255736Sdavidch (IRO[286].base + ((pfId) * IRO[286].m1)) 174255736Sdavidch#define USTORM_ISCSI_RQ_SIZE_OFFSET(pfId) \ 175255736Sdavidch (IRO[287].base + ((pfId) * IRO[287].m1)) 176255736Sdavidch#define USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(pfId) \ 177255736Sdavidch (IRO[182].base + ((pfId) * IRO[182].m1)) 178255736Sdavidch#define USTORM_RECORD_SLOW_PATH_OFFSET(funcId) \ 179255736Sdavidch (IRO[180].base + ((funcId) * IRO[180].m1)) 180255736Sdavidch#define USTORM_RX_PRODS_E1X_OFFSET(portId, clientId) \ 181255736Sdavidch (IRO[209].base + ((portId) * IRO[209].m1) + ((clientId) * \ 182255736Sdavidch IRO[209].m2)) 183255736Sdavidch#define USTORM_RX_PRODS_E2_OFFSET(qzoneId) \ 184255736Sdavidch (IRO[210].base + ((qzoneId) * IRO[210].m1)) 185255736Sdavidch#define USTORM_TPA_BTR_OFFSET (IRO[207].base) 186255736Sdavidch#define USTORM_TPA_BTR_SIZE (IRO[207].size) 187255736Sdavidch#define USTORM_VF_TO_PF_OFFSET(funcId) \ 188255736Sdavidch (IRO[179].base + ((funcId) * IRO[179].m1)) 189255736Sdavidch#define XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE (IRO[67].base) 190255736Sdavidch#define XSTORM_AGG_INT_FINAL_CLEANUP_INDEX (IRO[66].base) 191255736Sdavidch#define XSTORM_ASSERT_LIST_INDEX_OFFSET (IRO[51].base) 192255736Sdavidch#define XSTORM_ASSERT_LIST_OFFSET(assertListEntry) \ 193255736Sdavidch (IRO[50].base + ((assertListEntry) * IRO[50].m1)) 194255736Sdavidch#define XSTORM_CMNG_PER_PORT_VARS_OFFSET(portId) \ 195255736Sdavidch (IRO[43].base + ((portId) * IRO[43].m1)) 196255736Sdavidch#define XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(pfId) \ 197255736Sdavidch (IRO[45].base + ((pfId) * IRO[45].m1)) 198255736Sdavidch#define XSTORM_FUNC_EN_OFFSET(funcId) \ 199255736Sdavidch (IRO[47].base + ((funcId) * IRO[47].m1)) 200255736Sdavidch#define XSTORM_ISCSI_HQ_SIZE_OFFSET(pfId) \ 201255736Sdavidch (IRO[296].base + ((pfId) * IRO[296].m1)) 202255736Sdavidch#define XSTORM_ISCSI_LOCAL_MAC_ADDR0_OFFSET(pfId) \ 203255736Sdavidch (IRO[299].base + ((pfId) * IRO[299].m1)) 204255736Sdavidch#define XSTORM_ISCSI_LOCAL_MAC_ADDR1_OFFSET(pfId) \ 205255736Sdavidch (IRO[300].base + ((pfId) * IRO[300].m1)) 206255736Sdavidch#define XSTORM_ISCSI_LOCAL_MAC_ADDR2_OFFSET(pfId) \ 207255736Sdavidch (IRO[301].base + ((pfId) * IRO[301].m1)) 208255736Sdavidch#define XSTORM_ISCSI_LOCAL_MAC_ADDR3_OFFSET(pfId) \ 209255736Sdavidch (IRO[302].base + ((pfId) * IRO[302].m1)) 210255736Sdavidch#define XSTORM_ISCSI_LOCAL_MAC_ADDR4_OFFSET(pfId) \ 211255736Sdavidch (IRO[303].base + ((pfId) * IRO[303].m1)) 212255736Sdavidch#define XSTORM_ISCSI_LOCAL_MAC_ADDR5_OFFSET(pfId) \ 213255736Sdavidch (IRO[304].base + ((pfId) * IRO[304].m1)) 214255736Sdavidch#define XSTORM_ISCSI_LOCAL_VLAN_OFFSET(pfId) \ 215255736Sdavidch (IRO[305].base + ((pfId) * IRO[305].m1)) 216255736Sdavidch#define XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \ 217255736Sdavidch (IRO[295].base + ((pfId) * IRO[295].m1)) 218255736Sdavidch#define XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \ 219255736Sdavidch (IRO[294].base + ((pfId) * IRO[294].m1)) 220255736Sdavidch#define XSTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \ 221255736Sdavidch (IRO[293].base + ((pfId) * IRO[293].m1)) 222255736Sdavidch#define XSTORM_ISCSI_R2TQ_SIZE_OFFSET(pfId) \ 223255736Sdavidch (IRO[298].base + ((pfId) * IRO[298].m1)) 224255736Sdavidch#define XSTORM_ISCSI_SQ_SIZE_OFFSET(pfId) \ 225255736Sdavidch (IRO[297].base + ((pfId) * IRO[297].m1)) 226255736Sdavidch#define XSTORM_ISCSI_TCP_VARS_ADV_WND_SCL_OFFSET(pfId) \ 227255736Sdavidch (IRO[292].base + ((pfId) * IRO[292].m1)) 228255736Sdavidch#define XSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(pfId) \ 229255736Sdavidch (IRO[291].base + ((pfId) * IRO[291].m1)) 230255736Sdavidch#define XSTORM_ISCSI_TCP_VARS_TOS_OFFSET(pfId) \ 231255736Sdavidch (IRO[290].base + ((pfId) * IRO[290].m1)) 232255736Sdavidch#define XSTORM_ISCSI_TCP_VARS_TTL_OFFSET(pfId) \ 233255736Sdavidch (IRO[289].base + ((pfId) * IRO[289].m1)) 234255736Sdavidch#define XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(pfId) \ 235255736Sdavidch (IRO[44].base + ((pfId) * IRO[44].m1)) 236255736Sdavidch#define XSTORM_RECORD_SLOW_PATH_OFFSET(funcId) \ 237255736Sdavidch (IRO[49].base + ((funcId) * IRO[49].m1)) 238255736Sdavidch#define XSTORM_SPQ_DATA_OFFSET(funcId) \ 239255736Sdavidch (IRO[32].base + ((funcId) * IRO[32].m1)) 240255736Sdavidch#define XSTORM_SPQ_DATA_SIZE (IRO[32].size) 241255736Sdavidch#define XSTORM_SPQ_PAGE_BASE_OFFSET(funcId) \ 242255736Sdavidch (IRO[30].base + ((funcId) * IRO[30].m1)) 243255736Sdavidch#define XSTORM_SPQ_PROD_OFFSET(funcId) \ 244255736Sdavidch (IRO[31].base + ((funcId) * IRO[31].m1)) 245255736Sdavidch#define XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_ENABLED_OFFSET(portId) \ 246255736Sdavidch (IRO[211].base + ((portId) * IRO[211].m1)) 247255736Sdavidch#define XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_MAX_COUNT_OFFSET(portId) \ 248255736Sdavidch (IRO[212].base + ((portId) * IRO[212].m1)) 249255736Sdavidch#define XSTORM_TCP_TX_SWS_TIMER_VAL_OFFSET(pfId) \ 250255736Sdavidch (IRO[214].base + (((pfId)>>1) * IRO[214].m1) + (((pfId)&1) * \ 251255736Sdavidch IRO[214].m2)) 252255736Sdavidch#define XSTORM_VF_TO_PF_OFFSET(funcId) \ 253255736Sdavidch (IRO[48].base + ((funcId) * IRO[48].m1)) 254255736Sdavidch#define COMMON_ASM_INVALID_ASSERT_OPCODE (IRO[7].base) 255255736Sdavidch 256255736Sdavidch 257255736Sdavidch/* Ethernet Ring parameters */ 258255736Sdavidch#define X_ETH_LOCAL_RING_SIZE 13 259255736Sdavidch#define FIRST_BD_IN_PKT 0 260255736Sdavidch#define PARSE_BD_INDEX 1 261255736Sdavidch#define NUM_OF_ETH_BDS_IN_PAGE ((PAGE_SIZE)/(STRUCT_SIZE(eth_tx_bd)/8)) 262255736Sdavidch#define U_ETH_NUM_OF_SGES_TO_FETCH 8 263255736Sdavidch#define U_ETH_MAX_SGES_FOR_PACKET 3 264255736Sdavidch 265255736Sdavidch/* Rx ring params */ 266255736Sdavidch#define U_ETH_LOCAL_BD_RING_SIZE 8 267255736Sdavidch#define U_ETH_LOCAL_SGE_RING_SIZE 10 268255736Sdavidch#define U_ETH_SGL_SIZE 8 269255736Sdavidch /* The fw will padd the buffer with this value, so the IP header \ 270255736Sdavidch will be align to 4 Byte */ 271255736Sdavidch#define IP_HEADER_ALIGNMENT_PADDING 2 272255736Sdavidch 273255736Sdavidch#define U_ETH_SGES_PER_PAGE_INVERSE_MASK \ 274255736Sdavidch (0xFFFF - ((PAGE_SIZE/((STRUCT_SIZE(eth_rx_sge))/8))-1)) 275255736Sdavidch 276255736Sdavidch#define TU_ETH_CQES_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_cqe)/8)) 277255736Sdavidch#define U_ETH_BDS_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_bd)/8)) 278255736Sdavidch#define U_ETH_SGES_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_sge)/8)) 279255736Sdavidch 280255736Sdavidch#define U_ETH_BDS_PER_PAGE_MASK (U_ETH_BDS_PER_PAGE-1) 281255736Sdavidch#define U_ETH_CQE_PER_PAGE_MASK (TU_ETH_CQES_PER_PAGE-1) 282255736Sdavidch#define U_ETH_SGES_PER_PAGE_MASK (U_ETH_SGES_PER_PAGE-1) 283255736Sdavidch 284255736Sdavidch#define U_ETH_UNDEFINED_Q 0xFF 285255736Sdavidch 286255736Sdavidch#define T_ETH_INDIRECTION_TABLE_SIZE 128 287255736Sdavidch#define T_ETH_RSS_KEY 10 288255736Sdavidch#define ETH_NUM_OF_RSS_ENGINES_E2 72 289255736Sdavidch 290255736Sdavidch#define FILTER_RULES_COUNT 16 291255736Sdavidch#define MULTICAST_RULES_COUNT 16 292255736Sdavidch#define CLASSIFY_RULES_COUNT 16 293255736Sdavidch 294255736Sdavidch/*The CRC32 seed, that is used for the hash(reduction) multicast address */ 295255736Sdavidch#define ETH_CRC32_HASH_SEED 0x00000000 296255736Sdavidch 297255736Sdavidch#define ETH_CRC32_HASH_BIT_SIZE (8) 298255736Sdavidch#define ETH_CRC32_HASH_MASK EVAL((1<<ETH_CRC32_HASH_BIT_SIZE)-1) 299255736Sdavidch 300255736Sdavidch/* Maximal L2 clients supported */ 301255736Sdavidch#define ETH_MAX_RX_CLIENTS_E1 18 302255736Sdavidch#define ETH_MAX_RX_CLIENTS_E1H 28 303255736Sdavidch#define ETH_MAX_RX_CLIENTS_E2 152 304255736Sdavidch 305255736Sdavidch/* Maximal statistics client Ids */ 306255736Sdavidch#define MAX_STAT_COUNTER_ID_E1 36 307255736Sdavidch#define MAX_STAT_COUNTER_ID_E1H 56 308255736Sdavidch#define MAX_STAT_COUNTER_ID_E2 140 309255736Sdavidch 310255736Sdavidch#define MAX_MAC_CREDIT_E1 192 /* Per Chip */ 311255736Sdavidch#define MAX_MAC_CREDIT_E1H 256 /* Per Chip */ 312255736Sdavidch#define MAX_MAC_CREDIT_E2 272 /* Per Path */ 313255736Sdavidch#define MAX_VLAN_CREDIT_E1 0 /* Per Chip */ 314255736Sdavidch#define MAX_VLAN_CREDIT_E1H 0 /* Per Chip */ 315255736Sdavidch#define MAX_VLAN_CREDIT_E2 272 /* Per Path */ 316255736Sdavidch 317255736Sdavidch 318255736Sdavidch/* Maximal aggregation queues supported */ 319255736Sdavidch#define ETH_MAX_AGGREGATION_QUEUES_E1 32 320255736Sdavidch#define ETH_MAX_AGGREGATION_QUEUES_E1H_E2 64 321255736Sdavidch 322255736Sdavidch 323255736Sdavidch#define ETH_NUM_OF_MCAST_BINS 256 324255736Sdavidch#define ETH_NUM_OF_MCAST_ENGINES_E2 72 325255736Sdavidch 326255736Sdavidch#define ETH_MIN_RX_CQES_WITHOUT_TPA (MAX_RAMRODS_PER_PORT + 3) 327255736Sdavidch#define ETH_MIN_RX_CQES_WITH_TPA_E1 \ 328255736Sdavidch (ETH_MAX_AGGREGATION_QUEUES_E1 + ETH_MIN_RX_CQES_WITHOUT_TPA) 329255736Sdavidch#define ETH_MIN_RX_CQES_WITH_TPA_E1H_E2 \ 330255736Sdavidch (ETH_MAX_AGGREGATION_QUEUES_E1H_E2 + ETH_MIN_RX_CQES_WITHOUT_TPA) 331255736Sdavidch 332255736Sdavidch#define DISABLE_STATISTIC_COUNTER_ID_VALUE 0 333255736Sdavidch 334255736Sdavidch 335255736Sdavidch/* This file defines HSI constants common to all microcode flows */ 336255736Sdavidch 337255736Sdavidch/* offset in bits of protocol in the state context parameter */ 338255736Sdavidch#define PROTOCOL_STATE_BIT_OFFSET 6 339255736Sdavidch 340255736Sdavidch#define ETH_STATE (ETH_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET) 341255736Sdavidch#define TOE_STATE (TOE_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET) 342255736Sdavidch#define RDMA_STATE (RDMA_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET) 343255736Sdavidch 344255736Sdavidch/* microcode fixed page page size 4K (chains and ring segments) */ 345255736Sdavidch#define MC_PAGE_SIZE 4096 346255736Sdavidch 347255736Sdavidch/* Number of indices per slow-path SB */ 348255736Sdavidch#define HC_SP_SB_MAX_INDICES 16 /* The Maximum of all */ 349255736Sdavidch 350255736Sdavidch/* Number of indices per SB */ 351255736Sdavidch#define HC_SB_MAX_INDICES_E1X 8 /* Multiple of 4 */ 352255736Sdavidch#define HC_SB_MAX_INDICES_E2 8 /* Multiple of 4 */ 353255736Sdavidch 354255736Sdavidch/* Number of SB */ 355255736Sdavidch#define HC_SB_MAX_SB_E1X 32 356255736Sdavidch#define HC_SB_MAX_SB_E2 136 /* include PF */ 357255736Sdavidch 358255736Sdavidch/* ID of slow path status block */ 359255736Sdavidch#define HC_SP_SB_ID 0xde 360255736Sdavidch 361255736Sdavidch/* Num of State machines */ 362255736Sdavidch#define HC_SB_MAX_SM 2 /* Fixed */ 363255736Sdavidch 364255736Sdavidch/* Num of dynamic indices */ 365255736Sdavidch#define HC_SB_MAX_DYNAMIC_INDICES 4 /* 0..3 fixed */ 366255736Sdavidch 367255736Sdavidch/* max number of slow path commands per port */ 368255736Sdavidch#define MAX_RAMRODS_PER_PORT 8 369255736Sdavidch 370255736Sdavidch 371255736Sdavidch/**** DEFINES FOR TIMERS/CLOCKS RESOLUTIONS ****/ 372255736Sdavidch 373255736Sdavidch/* chip timers frequency constants */ 374255736Sdavidch#define TIMERS_TICK_SIZE_CHIP (1e-3) 375255736Sdavidch 376255736Sdavidch/* used in toe: TsRecentAge, MaxRt, and temporarily RTT */ 377255736Sdavidch#define TSEMI_CLK1_RESUL_CHIP (1e-3) 378255736Sdavidch 379255736Sdavidch/* temporarily used for RTT */ 380255736Sdavidch#define XSEMI_CLK1_RESUL_CHIP (1e-3) 381255736Sdavidch 382255736Sdavidch/* used for Host Coallescing */ 383255736Sdavidch#define SDM_TIMER_TICK_RESUL_CHIP (4 * (1e-6)) 384255736Sdavidch 385255736Sdavidch/**** END DEFINES FOR TIMERS/CLOCKS RESOLUTIONS ****/ 386255736Sdavidch 387255736Sdavidch#define XSTORM_IP_ID_ROLL_HALF 0x8000 388255736Sdavidch#define XSTORM_IP_ID_ROLL_ALL 0 389255736Sdavidch 390255736Sdavidch/* assert list: number of entries */ 391255736Sdavidch#define FW_LOG_LIST_SIZE 50 392255736Sdavidch 393255736Sdavidch#define NUM_OF_SAFC_BITS 16 394255736Sdavidch#define MAX_COS_NUMBER 4 395255736Sdavidch#define MAX_TRAFFIC_TYPES 8 396255736Sdavidch#define MAX_PFC_PRIORITIES 8 397255736Sdavidch 398255736Sdavidch /* used by array traffic_type_to_priority[] to mark traffic type \ 399255736Sdavidch that is not mapped to priority*/ 400255736Sdavidch#define LLFC_TRAFFIC_TYPE_TO_PRIORITY_UNMAPPED 0xFF 401255736Sdavidch 402255736Sdavidch/* Event Ring definitions */ 403255736Sdavidch#define C_ERES_PER_PAGE \ 404255736Sdavidch (PAGE_SIZE / BITS_TO_BYTES(STRUCT_SIZE(event_ring_elem))) 405255736Sdavidch#define C_ERE_PER_PAGE_MASK (C_ERES_PER_PAGE - 1) 406255736Sdavidch 407255736Sdavidch/* number of statistic command */ 408255736Sdavidch#define STATS_QUERY_CMD_COUNT 16 409255736Sdavidch 410255736Sdavidch/* niv list table size */ 411255736Sdavidch#define AFEX_LIST_TABLE_SIZE 4096 412255736Sdavidch 413255736Sdavidch/* invalid VNIC Id. used in VNIC classification */ 414255736Sdavidch#define INVALID_VNIC_ID 0xFF 415255736Sdavidch 416255736Sdavidch/* used for indicating an undefined RAM offset in the IRO arrays */ 417255736Sdavidch#define UNDEF_IRO 0x80000000 418255736Sdavidch 419255736Sdavidch/* used for defining the amount of FCoE tasks supported for PF */ 420255736Sdavidch#define MAX_FCOE_FUNCS_PER_ENGINE 2 421255736Sdavidch#define MAX_NUM_FCOE_TASKS_PER_ENGINE \ 422255736Sdavidch 4096 /*Each port can have at max 1 function*/ 423255736Sdavidch 424255736Sdavidch 425255736Sdavidch#endif /* ECORE_FW_DEFS_H */ 426255736Sdavidch 427