if_bgereg.h revision 241983
1/*- 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2001 4 * Bill Paul <wpaul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD: head/sys/dev/bge/if_bgereg.h 241983 2012-10-24 05:00:56Z yongari $ 34 */ 35 36/* 37 * BCM570x memory map. The internal memory layout varies somewhat 38 * depending on whether or not we have external SSRAM attached. 39 * The BCM5700 can have up to 16MB of external memory. The BCM5701 40 * is apparently not designed to use external SSRAM. The mappings 41 * up to the first 4 send rings are the same for both internal and 42 * external memory configurations. Note that mini RX ring space is 43 * only available with external SSRAM configurations, which means 44 * the mini RX ring is not supported on the BCM5701. 45 * 46 * The NIC's memory can be accessed by the host in one of 3 ways: 47 * 48 * 1) Indirect register access. The MEMWIN_BASEADDR and MEMWIN_DATA 49 * registers in PCI config space can be used to read any 32-bit 50 * address within the NIC's memory. 51 * 52 * 2) Memory window access. The MEMWIN_BASEADDR register in PCI config 53 * space can be used in conjunction with the memory window in the 54 * device register space at offset 0x8000 to read any 32K chunk 55 * of NIC memory. 56 * 57 * 3) Flat mode. If the 'flat mode' bit in the PCI state register is 58 * set, the device I/O mapping consumes 32MB of host address space, 59 * allowing all of the registers and internal NIC memory to be 60 * accessed directly. NIC memory addresses are offset by 0x01000000. 61 * Flat mode consumes so much host address space that it is not 62 * recommended. 63 */ 64#define BGE_PAGE_ZERO 0x00000000 65#define BGE_PAGE_ZERO_END 0x000000FF 66#define BGE_SEND_RING_RCB 0x00000100 67#define BGE_SEND_RING_RCB_END 0x000001FF 68#define BGE_RX_RETURN_RING_RCB 0x00000200 69#define BGE_RX_RETURN_RING_RCB_END 0x000002FF 70#define BGE_STATS_BLOCK 0x00000300 71#define BGE_STATS_BLOCK_END 0x00000AFF 72#define BGE_STATUS_BLOCK 0x00000B00 73#define BGE_STATUS_BLOCK_END 0x00000B4F 74#define BGE_SRAM_FW_MB 0x00000B50 75#define BGE_SRAM_DATA_SIG 0x00000B54 76#define BGE_SRAM_DATA_CFG 0x00000B58 77#define BGE_SRAM_FW_CMD_MB 0x00000B78 78#define BGE_SRAM_FW_CMD_LEN_MB 0x00000B7C 79#define BGE_SRAM_FW_CMD_DATA_MB 0x00000B80 80#define BGE_SRAM_FW_DRV_STATE_MB 0x00000C04 81#define BGE_SRAM_MAC_ADDR_HIGH_MB 0x00000C14 82#define BGE_SRAM_MAC_ADDR_LOW_MB 0x00000C18 83#define BGE_SOFTWARE_GENCOMM_END 0x00000FFF 84#define BGE_UNMAPPED 0x00001000 85#define BGE_UNMAPPED_END 0x00001FFF 86#define BGE_DMA_DESCRIPTORS 0x00002000 87#define BGE_DMA_DESCRIPTORS_END 0x00003FFF 88#define BGE_SEND_RING_5717 0x00004000 89#define BGE_SEND_RING_1_TO_4 0x00004000 90#define BGE_SEND_RING_1_TO_4_END 0x00005FFF 91 92/* Firmware interface */ 93#define BGE_SRAM_DATA_SIG_MAGIC 0x4B657654 /* 'KevT' */ 94 95#define BGE_FW_CMD_DRV_ALIVE 0x00000001 96#define BGE_FW_CMD_PAUSE 0x00000002 97#define BGE_FW_CMD_IPV4_ADDR_CHANGE 0x00000003 98#define BGE_FW_CMD_IPV6_ADDR_CHANGE 0x00000004 99#define BGE_FW_CMD_LINK_UPDATE 0x0000000C 100#define BGE_FW_CMD_DRV_ALIVE2 0x0000000D 101#define BGE_FW_CMD_DRV_ALIVE3 0x0000000E 102 103#define BGE_FW_HB_TIMEOUT_SEC 3 104 105#define BGE_FW_DRV_STATE_START 0x00000001 106#define BGE_FW_DRV_STATE_START_DONE 0x80000001 107#define BGE_FW_DRV_STATE_UNLOAD 0x00000002 108#define BGE_FW_DRV_STATE_UNLOAD_DONE 0x80000002 109#define BGE_FW_DRV_STATE_WOL 0x00000003 110#define BGE_FW_DRV_STATE_SUSPEND 0x00000004 111 112/* Mappings for internal memory configuration */ 113#define BGE_STD_RX_RINGS 0x00006000 114#define BGE_STD_RX_RINGS_END 0x00006FFF 115#define BGE_JUMBO_RX_RINGS 0x00007000 116#define BGE_JUMBO_RX_RINGS_END 0x00007FFF 117#define BGE_BUFFPOOL_1 0x00008000 118#define BGE_BUFFPOOL_1_END 0x0000FFFF 119#define BGE_BUFFPOOL_2 0x00010000 /* or expansion ROM */ 120#define BGE_BUFFPOOL_2_END 0x00017FFF 121#define BGE_BUFFPOOL_3 0x00018000 /* or expansion ROM */ 122#define BGE_BUFFPOOL_3_END 0x0001FFFF 123#define BGE_STD_RX_RINGS_5717 0x00040000 124#define BGE_JUMBO_RX_RINGS_5717 0x00044400 125 126/* Mappings for external SSRAM configurations */ 127#define BGE_SEND_RING_5_TO_6 0x00006000 128#define BGE_SEND_RING_5_TO_6_END 0x00006FFF 129#define BGE_SEND_RING_7_TO_8 0x00007000 130#define BGE_SEND_RING_7_TO_8_END 0x00007FFF 131#define BGE_SEND_RING_9_TO_16 0x00008000 132#define BGE_SEND_RING_9_TO_16_END 0x0000BFFF 133#define BGE_EXT_STD_RX_RINGS 0x0000C000 134#define BGE_EXT_STD_RX_RINGS_END 0x0000CFFF 135#define BGE_EXT_JUMBO_RX_RINGS 0x0000D000 136#define BGE_EXT_JUMBO_RX_RINGS_END 0x0000DFFF 137#define BGE_MINI_RX_RINGS 0x0000E000 138#define BGE_MINI_RX_RINGS_END 0x0000FFFF 139#define BGE_AVAIL_REGION1 0x00010000 /* or expansion ROM */ 140#define BGE_AVAIL_REGION1_END 0x00017FFF 141#define BGE_AVAIL_REGION2 0x00018000 /* or expansion ROM */ 142#define BGE_AVAIL_REGION2_END 0x0001FFFF 143#define BGE_EXT_SSRAM 0x00020000 144#define BGE_EXT_SSRAM_END 0x000FFFFF 145 146 147/* 148 * BCM570x register offsets. These are memory mapped registers 149 * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. 150 * Each register must be accessed using 32 bit operations. 151 * 152 * All registers are accessed through a 32K shared memory block. 153 * The first group of registers are actually copies of the PCI 154 * configuration space registers. 155 */ 156 157/* 158 * PCI registers defined in the PCI 2.2 spec. 159 */ 160#define BGE_PCI_VID 0x00 161#define BGE_PCI_DID 0x02 162#define BGE_PCI_CMD 0x04 163#define BGE_PCI_STS 0x06 164#define BGE_PCI_REV 0x08 165#define BGE_PCI_CLASS 0x09 166#define BGE_PCI_CACHESZ 0x0C 167#define BGE_PCI_LATTIMER 0x0D 168#define BGE_PCI_HDRTYPE 0x0E 169#define BGE_PCI_BIST 0x0F 170#define BGE_PCI_BAR0 0x10 171#define BGE_PCI_BAR1 0x14 172#define BGE_PCI_SUBSYS 0x2C 173#define BGE_PCI_SUBVID 0x2E 174#define BGE_PCI_ROMBASE 0x30 175#define BGE_PCI_CAPPTR 0x34 176#define BGE_PCI_INTLINE 0x3C 177#define BGE_PCI_INTPIN 0x3D 178#define BGE_PCI_MINGNT 0x3E 179#define BGE_PCI_MAXLAT 0x3F 180#define BGE_PCI_PCIXCAP 0x40 181#define BGE_PCI_NEXTPTR_PM 0x41 182#define BGE_PCI_PCIX_CMD 0x42 183#define BGE_PCI_PCIX_STS 0x44 184#define BGE_PCI_PWRMGMT_CAPID 0x48 185#define BGE_PCI_NEXTPTR_VPD 0x49 186#define BGE_PCI_PWRMGMT_CAPS 0x4A 187#define BGE_PCI_PWRMGMT_CMD 0x4C 188#define BGE_PCI_PWRMGMT_STS 0x4D 189#define BGE_PCI_PWRMGMT_DATA 0x4F 190#define BGE_PCI_VPD_CAPID 0x50 191#define BGE_PCI_NEXTPTR_MSI 0x51 192#define BGE_PCI_VPD_ADDR 0x52 193#define BGE_PCI_VPD_DATA 0x54 194#define BGE_PCI_MSI_CAPID 0x58 195#define BGE_PCI_NEXTPTR_NONE 0x59 196#define BGE_PCI_MSI_CTL 0x5A 197#define BGE_PCI_MSI_ADDR_HI 0x5C 198#define BGE_PCI_MSI_ADDR_LO 0x60 199#define BGE_PCI_MSI_DATA 0x64 200 201/* 202 * PCI Express definitions 203 * According to 204 * PCI Express base specification, REV. 1.0a 205 */ 206 207/* PCI Express device control, 16bits */ 208#define BGE_PCIE_DEVCTL 0x08 209#define BGE_PCIE_DEVCTL_MAX_READRQ_MASK 0x7000 210#define BGE_PCIE_DEVCTL_MAX_READRQ_128 0x0000 211#define BGE_PCIE_DEVCTL_MAX_READRQ_256 0x1000 212#define BGE_PCIE_DEVCTL_MAX_READRQ_512 0x2000 213#define BGE_PCIE_DEVCTL_MAX_READRQ_1024 0x3000 214#define BGE_PCIE_DEVCTL_MAX_READRQ_2048 0x4000 215#define BGE_PCIE_DEVCTL_MAX_READRQ_4096 0x5000 216 217/* PCI MSI. ??? */ 218#define BGE_PCIE_CAPID_REG 0xD0 219#define BGE_PCIE_CAPID 0x10 220 221/* 222 * PCI registers specific to the BCM570x family. 223 */ 224#define BGE_PCI_MISC_CTL 0x68 225#define BGE_PCI_DMA_RW_CTL 0x6C 226#define BGE_PCI_PCISTATE 0x70 227#define BGE_PCI_CLKCTL 0x74 228#define BGE_PCI_REG_BASEADDR 0x78 229#define BGE_PCI_MEMWIN_BASEADDR 0x7C 230#define BGE_PCI_REG_DATA 0x80 231#define BGE_PCI_MEMWIN_DATA 0x84 232#define BGE_PCI_MODECTL 0x88 233#define BGE_PCI_MISC_CFG 0x8C 234#define BGE_PCI_MISC_LOCALCTL 0x90 235#define BGE_PCI_UNDI_RX_STD_PRODIDX_HI 0x98 236#define BGE_PCI_UNDI_RX_STD_PRODIDX_LO 0x9C 237#define BGE_PCI_UNDI_RX_RTN_CONSIDX_HI 0xA0 238#define BGE_PCI_UNDI_RX_RTN_CONSIDX_LO 0xA4 239#define BGE_PCI_UNDI_TX_BD_PRODIDX_HI 0xA8 240#define BGE_PCI_UNDI_TX_BD_PRODIDX_LO 0xAC 241#define BGE_PCI_ISR_MBX_HI 0xB0 242#define BGE_PCI_ISR_MBX_LO 0xB4 243#define BGE_PCI_PRODID_ASICREV 0xBC 244#define BGE_PCI_GEN2_PRODID_ASICREV 0xF4 245#define BGE_PCI_GEN15_PRODID_ASICREV 0xFC 246 247/* PCI Misc. Host control register */ 248#define BGE_PCIMISCCTL_CLEAR_INTA 0x00000001 249#define BGE_PCIMISCCTL_MASK_PCI_INTR 0x00000002 250#define BGE_PCIMISCCTL_ENDIAN_BYTESWAP 0x00000004 251#define BGE_PCIMISCCTL_ENDIAN_WORDSWAP 0x00000008 252#define BGE_PCIMISCCTL_PCISTATE_RW 0x00000010 253#define BGE_PCIMISCCTL_CLOCKCTL_RW 0x00000020 254#define BGE_PCIMISCCTL_REG_WORDSWAP 0x00000040 255#define BGE_PCIMISCCTL_INDIRECT_ACCESS 0x00000080 256#define BGE_PCIMISCCTL_TAGGED_STATUS 0x00000200 257#define BGE_PCIMISCCTL_ASICREV 0xFFFF0000 258#define BGE_PCIMISCCTL_ASICREV_SHIFT 16 259 260#define BGE_HIF_SWAP_OPTIONS (BGE_PCIMISCCTL_ENDIAN_WORDSWAP) 261 262#define BGE_INIT \ 263 (BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_CLEAR_INTA| \ 264 BGE_PCIMISCCTL_MASK_PCI_INTR|BGE_PCIMISCCTL_INDIRECT_ACCESS) 265 266#define BGE_CHIPID_TIGON_I 0x4000 267#define BGE_CHIPID_TIGON_II 0x6000 268#define BGE_CHIPID_BCM5700_A0 0x7000 269#define BGE_CHIPID_BCM5700_A1 0x7001 270#define BGE_CHIPID_BCM5700_B0 0x7100 271#define BGE_CHIPID_BCM5700_B1 0x7101 272#define BGE_CHIPID_BCM5700_B2 0x7102 273#define BGE_CHIPID_BCM5700_B3 0x7103 274#define BGE_CHIPID_BCM5700_ALTIMA 0x7104 275#define BGE_CHIPID_BCM5700_C0 0x7200 276#define BGE_CHIPID_BCM5701_A0 0x0000 /* grrrr */ 277#define BGE_CHIPID_BCM5701_B0 0x0100 278#define BGE_CHIPID_BCM5701_B2 0x0102 279#define BGE_CHIPID_BCM5701_B5 0x0105 280#define BGE_CHIPID_BCM5703_A0 0x1000 281#define BGE_CHIPID_BCM5703_A1 0x1001 282#define BGE_CHIPID_BCM5703_A2 0x1002 283#define BGE_CHIPID_BCM5703_A3 0x1003 284#define BGE_CHIPID_BCM5703_B0 0x1100 285#define BGE_CHIPID_BCM5704_A0 0x2000 286#define BGE_CHIPID_BCM5704_A1 0x2001 287#define BGE_CHIPID_BCM5704_A2 0x2002 288#define BGE_CHIPID_BCM5704_A3 0x2003 289#define BGE_CHIPID_BCM5704_B0 0x2100 290#define BGE_CHIPID_BCM5705_A0 0x3000 291#define BGE_CHIPID_BCM5705_A1 0x3001 292#define BGE_CHIPID_BCM5705_A2 0x3002 293#define BGE_CHIPID_BCM5705_A3 0x3003 294#define BGE_CHIPID_BCM5750_A0 0x4000 295#define BGE_CHIPID_BCM5750_A1 0x4001 296#define BGE_CHIPID_BCM5750_A3 0x4000 297#define BGE_CHIPID_BCM5750_B0 0x4100 298#define BGE_CHIPID_BCM5750_B1 0x4101 299#define BGE_CHIPID_BCM5750_C0 0x4200 300#define BGE_CHIPID_BCM5750_C1 0x4201 301#define BGE_CHIPID_BCM5750_C2 0x4202 302#define BGE_CHIPID_BCM5714_A0 0x5000 303#define BGE_CHIPID_BCM5752_A0 0x6000 304#define BGE_CHIPID_BCM5752_A1 0x6001 305#define BGE_CHIPID_BCM5752_A2 0x6002 306#define BGE_CHIPID_BCM5714_B0 0x8000 307#define BGE_CHIPID_BCM5714_B3 0x8003 308#define BGE_CHIPID_BCM5715_A0 0x9000 309#define BGE_CHIPID_BCM5715_A1 0x9001 310#define BGE_CHIPID_BCM5715_A3 0x9003 311#define BGE_CHIPID_BCM5755_A0 0xa000 312#define BGE_CHIPID_BCM5755_A1 0xa001 313#define BGE_CHIPID_BCM5755_A2 0xa002 314#define BGE_CHIPID_BCM5722_A0 0xa200 315#define BGE_CHIPID_BCM5754_A0 0xb000 316#define BGE_CHIPID_BCM5754_A1 0xb001 317#define BGE_CHIPID_BCM5754_A2 0xb002 318#define BGE_CHIPID_BCM5761_A0 0x5761000 319#define BGE_CHIPID_BCM5761_A1 0x5761100 320#define BGE_CHIPID_BCM5784_A0 0x5784000 321#define BGE_CHIPID_BCM5784_A1 0x5784100 322#define BGE_CHIPID_BCM5787_A0 0xb000 323#define BGE_CHIPID_BCM5787_A1 0xb001 324#define BGE_CHIPID_BCM5787_A2 0xb002 325#define BGE_CHIPID_BCM5906_A0 0xc000 326#define BGE_CHIPID_BCM5906_A1 0xc001 327#define BGE_CHIPID_BCM5906_A2 0xc002 328#define BGE_CHIPID_BCM57780_A0 0x57780000 329#define BGE_CHIPID_BCM57780_A1 0x57780001 330#define BGE_CHIPID_BCM5717_A0 0x05717000 331#define BGE_CHIPID_BCM5717_B0 0x05717100 332#define BGE_CHIPID_BCM5719_A0 0x05719000 333#define BGE_CHIPID_BCM5720_A0 0x05720000 334#define BGE_CHIPID_BCM57765_A0 0x57785000 335#define BGE_CHIPID_BCM57765_B0 0x57785100 336 337/* shorthand one */ 338#define BGE_ASICREV(x) ((x) >> 12) 339#define BGE_ASICREV_BCM5701 0x00 340#define BGE_ASICREV_BCM5703 0x01 341#define BGE_ASICREV_BCM5704 0x02 342#define BGE_ASICREV_BCM5705 0x03 343#define BGE_ASICREV_BCM5750 0x04 344#define BGE_ASICREV_BCM5714_A0 0x05 345#define BGE_ASICREV_BCM5752 0x06 346#define BGE_ASICREV_BCM5700 0x07 347#define BGE_ASICREV_BCM5780 0x08 348#define BGE_ASICREV_BCM5714 0x09 349#define BGE_ASICREV_BCM5755 0x0a 350#define BGE_ASICREV_BCM5754 0x0b 351#define BGE_ASICREV_BCM5787 0x0b 352#define BGE_ASICREV_BCM5906 0x0c 353/* Should consult BGE_PCI_PRODID_ASICREV for ChipID */ 354#define BGE_ASICREV_USE_PRODID_REG 0x0f 355/* BGE_PCI_PRODID_ASICREV ASIC rev. identifiers. */ 356#define BGE_ASICREV_BCM5717 0x5717 357#define BGE_ASICREV_BCM5719 0x5719 358#define BGE_ASICREV_BCM5720 0x5720 359#define BGE_ASICREV_BCM5761 0x5761 360#define BGE_ASICREV_BCM5784 0x5784 361#define BGE_ASICREV_BCM5785 0x5785 362#define BGE_ASICREV_BCM57765 0x57785 363#define BGE_ASICREV_BCM57780 0x57780 364 365/* chip revisions */ 366#define BGE_CHIPREV(x) ((x) >> 8) 367#define BGE_CHIPREV_5700_AX 0x70 368#define BGE_CHIPREV_5700_BX 0x71 369#define BGE_CHIPREV_5700_CX 0x72 370#define BGE_CHIPREV_5701_AX 0x00 371#define BGE_CHIPREV_5703_AX 0x10 372#define BGE_CHIPREV_5704_AX 0x20 373#define BGE_CHIPREV_5704_BX 0x21 374#define BGE_CHIPREV_5750_AX 0x40 375#define BGE_CHIPREV_5750_BX 0x41 376/* BGE_PCI_PRODID_ASICREV chip rev. identifiers. */ 377#define BGE_CHIPREV_5717_AX 0x57170 378#define BGE_CHIPREV_5717_BX 0x57171 379#define BGE_CHIPREV_5761_AX 0x57611 380#define BGE_CHIPREV_5784_AX 0x57841 381 382/* PCI DMA Read/Write Control register */ 383#define BGE_PCIDMARWCTL_MINDMA 0x000000FF 384#define BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT 0x00000001 385#define BGE_PCIDMARWCTL_RDADRR_BNDRY 0x00000700 386#define BGE_PCIDMARWCTL_WRADDR_BNDRY 0x00003800 387#define BGE_PCIDMARWCTL_ONEDMA_ATONCE 0x0000C000 388#define BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL 0x00004000 389#define BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL 0x00008000 390#define BGE_PCIDMARWCTL_RD_WAT 0x00070000 391#define BGE_PCIDMARWCTL_WR_WAT 0x00380000 392#define BGE_PCIDMARWCTL_USE_MRM 0x00400000 393#define BGE_PCIDMARWCTL_ASRT_ALL_BE 0x00800000 394#define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD 0x0F000000 395#define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD 0xF0000000 396 397#define BGE_PCIDMARWCTL_RD_WAT_SHIFT(x) ((x) << 16) 398#define BGE_PCIDMARWCTL_WR_WAT_SHIFT(x) ((x) << 19) 399#define BGE_PCIDMARWCTL_RD_CMD_SHIFT(x) ((x) << 24) 400#define BGE_PCIDMARWCTL_WR_CMD_SHIFT(x) ((x) << 28) 401 402#define BGE_PCIDMARWCTL_TAGGED_STATUS_WA 0x00000080 403#define BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK 0x00000380 404 405#define BGE_PCI_READ_BNDRY_DISABLE 0x00000000 406#define BGE_PCI_READ_BNDRY_16BYTES 0x00000100 407#define BGE_PCI_READ_BNDRY_32BYTES 0x00000200 408#define BGE_PCI_READ_BNDRY_64BYTES 0x00000300 409#define BGE_PCI_READ_BNDRY_128BYTES 0x00000400 410#define BGE_PCI_READ_BNDRY_256BYTES 0x00000500 411#define BGE_PCI_READ_BNDRY_512BYTES 0x00000600 412#define BGE_PCI_READ_BNDRY_1024BYTES 0x00000700 413 414#define BGE_PCI_WRITE_BNDRY_DISABLE 0x00000000 415#define BGE_PCI_WRITE_BNDRY_16BYTES 0x00000800 416#define BGE_PCI_WRITE_BNDRY_32BYTES 0x00001000 417#define BGE_PCI_WRITE_BNDRY_64BYTES 0x00001800 418#define BGE_PCI_WRITE_BNDRY_128BYTES 0x00002000 419#define BGE_PCI_WRITE_BNDRY_256BYTES 0x00002800 420#define BGE_PCI_WRITE_BNDRY_512BYTES 0x00003000 421#define BGE_PCI_WRITE_BNDRY_1024BYTES 0x00003800 422 423/* 424 * PCI state register -- note, this register is read only 425 * unless the PCISTATE_WR bit of the PCI Misc. Host Control 426 * register is set. 427 */ 428#define BGE_PCISTATE_FORCE_RESET 0x00000001 429#define BGE_PCISTATE_INTR_STATE 0x00000002 430#define BGE_PCISTATE_PCI_BUSMODE 0x00000004 /* 1 = PCI, 0 = PCI-X */ 431#define BGE_PCISTATE_PCI_BUSSPEED 0x00000008 /* 1 = 66/133, 0 = 33/66 */ 432#define BGE_PCISTATE_32BIT_BUS 0x00000010 /* 1 = 32bit, 0 = 64bit */ 433#define BGE_PCISTATE_ROM_ENABLE 0x00000020 434#define BGE_PCISTATE_ROM_RETRY_ENABLE 0x00000040 435#define BGE_PCISTATE_FLATVIEW_MODE 0x00000100 436#define BGE_PCISTATE_PCI_TGT_RETRY_MAX 0x00000E00 437#define BGE_PCISTATE_RETRY_SAME_DMA 0x00002000 438#define BGE_PCISTATE_ALLOW_APE_CTLSPC_WR 0x00010000 439#define BGE_PCISTATE_ALLOW_APE_SHMEM_WR 0x00020000 440#define BGE_PCISTATE_ALLOW_APE_PSPACE_WR 0x00040000 441 442/* 443 * PCI Clock Control register -- note, this register is read only 444 * unless the CLOCKCTL_RW bit of the PCI Misc. Host Control 445 * register is set. 446 */ 447#define BGE_PCICLOCKCTL_DETECTED_SPEED 0x0000000F 448#define BGE_PCICLOCKCTL_M66EN 0x00000080 449#define BGE_PCICLOCKCTL_LOWPWR_CLKMODE 0x00000200 450#define BGE_PCICLOCKCTL_RXCPU_CLK_DIS 0x00000400 451#define BGE_PCICLOCKCTL_TXCPU_CLK_DIS 0x00000800 452#define BGE_PCICLOCKCTL_ALTCLK 0x00001000 453#define BGE_PCICLOCKCTL_ALTCLK_SRC 0x00002000 454#define BGE_PCICLOCKCTL_PCIPLL_DISABLE 0x00004000 455#define BGE_PCICLOCKCTL_SYSPLL_DISABLE 0x00008000 456#define BGE_PCICLOCKCTL_BIST_ENABLE 0x00010000 457 458 459#ifndef PCIM_CMD_MWIEN 460#define PCIM_CMD_MWIEN 0x0010 461#endif 462#ifndef PCIM_CMD_INTxDIS 463#define PCIM_CMD_INTxDIS 0x0400 464#endif 465 466/* BAR0 (MAC) Register Definitions */ 467 468/* 469 * High priority mailbox registers 470 * Each mailbox is 64-bits wide, though we only use the 471 * lower 32 bits. To write a 64-bit value, write the upper 32 bits 472 * first. The NIC will load the mailbox after the lower 32 bit word 473 * has been updated. 474 */ 475#define BGE_MBX_IRQ0_HI 0x0200 476#define BGE_MBX_IRQ0_LO 0x0204 477#define BGE_MBX_IRQ1_HI 0x0208 478#define BGE_MBX_IRQ1_LO 0x020C 479#define BGE_MBX_IRQ2_HI 0x0210 480#define BGE_MBX_IRQ2_LO 0x0214 481#define BGE_MBX_IRQ3_HI 0x0218 482#define BGE_MBX_IRQ3_LO 0x021C 483#define BGE_MBX_GEN0_HI 0x0220 484#define BGE_MBX_GEN0_LO 0x0224 485#define BGE_MBX_GEN1_HI 0x0228 486#define BGE_MBX_GEN1_LO 0x022C 487#define BGE_MBX_GEN2_HI 0x0230 488#define BGE_MBX_GEN2_LO 0x0234 489#define BGE_MBX_GEN3_HI 0x0228 490#define BGE_MBX_GEN3_LO 0x022C 491#define BGE_MBX_GEN4_HI 0x0240 492#define BGE_MBX_GEN4_LO 0x0244 493#define BGE_MBX_GEN5_HI 0x0248 494#define BGE_MBX_GEN5_LO 0x024C 495#define BGE_MBX_GEN6_HI 0x0250 496#define BGE_MBX_GEN6_LO 0x0254 497#define BGE_MBX_GEN7_HI 0x0258 498#define BGE_MBX_GEN7_LO 0x025C 499#define BGE_MBX_RELOAD_STATS_HI 0x0260 500#define BGE_MBX_RELOAD_STATS_LO 0x0264 501#define BGE_MBX_RX_STD_PROD_HI 0x0268 502#define BGE_MBX_RX_STD_PROD_LO 0x026C 503#define BGE_MBX_RX_JUMBO_PROD_HI 0x0270 504#define BGE_MBX_RX_JUMBO_PROD_LO 0x0274 505#define BGE_MBX_RX_MINI_PROD_HI 0x0278 506#define BGE_MBX_RX_MINI_PROD_LO 0x027C 507#define BGE_MBX_RX_CONS0_HI 0x0280 508#define BGE_MBX_RX_CONS0_LO 0x0284 509#define BGE_MBX_RX_CONS1_HI 0x0288 510#define BGE_MBX_RX_CONS1_LO 0x028C 511#define BGE_MBX_RX_CONS2_HI 0x0290 512#define BGE_MBX_RX_CONS2_LO 0x0294 513#define BGE_MBX_RX_CONS3_HI 0x0298 514#define BGE_MBX_RX_CONS3_LO 0x029C 515#define BGE_MBX_RX_CONS4_HI 0x02A0 516#define BGE_MBX_RX_CONS4_LO 0x02A4 517#define BGE_MBX_RX_CONS5_HI 0x02A8 518#define BGE_MBX_RX_CONS5_LO 0x02AC 519#define BGE_MBX_RX_CONS6_HI 0x02B0 520#define BGE_MBX_RX_CONS6_LO 0x02B4 521#define BGE_MBX_RX_CONS7_HI 0x02B8 522#define BGE_MBX_RX_CONS7_LO 0x02BC 523#define BGE_MBX_RX_CONS8_HI 0x02C0 524#define BGE_MBX_RX_CONS8_LO 0x02C4 525#define BGE_MBX_RX_CONS9_HI 0x02C8 526#define BGE_MBX_RX_CONS9_LO 0x02CC 527#define BGE_MBX_RX_CONS10_HI 0x02D0 528#define BGE_MBX_RX_CONS10_LO 0x02D4 529#define BGE_MBX_RX_CONS11_HI 0x02D8 530#define BGE_MBX_RX_CONS11_LO 0x02DC 531#define BGE_MBX_RX_CONS12_HI 0x02E0 532#define BGE_MBX_RX_CONS12_LO 0x02E4 533#define BGE_MBX_RX_CONS13_HI 0x02E8 534#define BGE_MBX_RX_CONS13_LO 0x02EC 535#define BGE_MBX_RX_CONS14_HI 0x02F0 536#define BGE_MBX_RX_CONS14_LO 0x02F4 537#define BGE_MBX_RX_CONS15_HI 0x02F8 538#define BGE_MBX_RX_CONS15_LO 0x02FC 539#define BGE_MBX_TX_HOST_PROD0_HI 0x0300 540#define BGE_MBX_TX_HOST_PROD0_LO 0x0304 541#define BGE_MBX_TX_HOST_PROD1_HI 0x0308 542#define BGE_MBX_TX_HOST_PROD1_LO 0x030C 543#define BGE_MBX_TX_HOST_PROD2_HI 0x0310 544#define BGE_MBX_TX_HOST_PROD2_LO 0x0314 545#define BGE_MBX_TX_HOST_PROD3_HI 0x0318 546#define BGE_MBX_TX_HOST_PROD3_LO 0x031C 547#define BGE_MBX_TX_HOST_PROD4_HI 0x0320 548#define BGE_MBX_TX_HOST_PROD4_LO 0x0324 549#define BGE_MBX_TX_HOST_PROD5_HI 0x0328 550#define BGE_MBX_TX_HOST_PROD5_LO 0x032C 551#define BGE_MBX_TX_HOST_PROD6_HI 0x0330 552#define BGE_MBX_TX_HOST_PROD6_LO 0x0334 553#define BGE_MBX_TX_HOST_PROD7_HI 0x0338 554#define BGE_MBX_TX_HOST_PROD7_LO 0x033C 555#define BGE_MBX_TX_HOST_PROD8_HI 0x0340 556#define BGE_MBX_TX_HOST_PROD8_LO 0x0344 557#define BGE_MBX_TX_HOST_PROD9_HI 0x0348 558#define BGE_MBX_TX_HOST_PROD9_LO 0x034C 559#define BGE_MBX_TX_HOST_PROD10_HI 0x0350 560#define BGE_MBX_TX_HOST_PROD10_LO 0x0354 561#define BGE_MBX_TX_HOST_PROD11_HI 0x0358 562#define BGE_MBX_TX_HOST_PROD11_LO 0x035C 563#define BGE_MBX_TX_HOST_PROD12_HI 0x0360 564#define BGE_MBX_TX_HOST_PROD12_LO 0x0364 565#define BGE_MBX_TX_HOST_PROD13_HI 0x0368 566#define BGE_MBX_TX_HOST_PROD13_LO 0x036C 567#define BGE_MBX_TX_HOST_PROD14_HI 0x0370 568#define BGE_MBX_TX_HOST_PROD14_LO 0x0374 569#define BGE_MBX_TX_HOST_PROD15_HI 0x0378 570#define BGE_MBX_TX_HOST_PROD15_LO 0x037C 571#define BGE_MBX_TX_NIC_PROD0_HI 0x0380 572#define BGE_MBX_TX_NIC_PROD0_LO 0x0384 573#define BGE_MBX_TX_NIC_PROD1_HI 0x0388 574#define BGE_MBX_TX_NIC_PROD1_LO 0x038C 575#define BGE_MBX_TX_NIC_PROD2_HI 0x0390 576#define BGE_MBX_TX_NIC_PROD2_LO 0x0394 577#define BGE_MBX_TX_NIC_PROD3_HI 0x0398 578#define BGE_MBX_TX_NIC_PROD3_LO 0x039C 579#define BGE_MBX_TX_NIC_PROD4_HI 0x03A0 580#define BGE_MBX_TX_NIC_PROD4_LO 0x03A4 581#define BGE_MBX_TX_NIC_PROD5_HI 0x03A8 582#define BGE_MBX_TX_NIC_PROD5_LO 0x03AC 583#define BGE_MBX_TX_NIC_PROD6_HI 0x03B0 584#define BGE_MBX_TX_NIC_PROD6_LO 0x03B4 585#define BGE_MBX_TX_NIC_PROD7_HI 0x03B8 586#define BGE_MBX_TX_NIC_PROD7_LO 0x03BC 587#define BGE_MBX_TX_NIC_PROD8_HI 0x03C0 588#define BGE_MBX_TX_NIC_PROD8_LO 0x03C4 589#define BGE_MBX_TX_NIC_PROD9_HI 0x03C8 590#define BGE_MBX_TX_NIC_PROD9_LO 0x03CC 591#define BGE_MBX_TX_NIC_PROD10_HI 0x03D0 592#define BGE_MBX_TX_NIC_PROD10_LO 0x03D4 593#define BGE_MBX_TX_NIC_PROD11_HI 0x03D8 594#define BGE_MBX_TX_NIC_PROD11_LO 0x03DC 595#define BGE_MBX_TX_NIC_PROD12_HI 0x03E0 596#define BGE_MBX_TX_NIC_PROD12_LO 0x03E4 597#define BGE_MBX_TX_NIC_PROD13_HI 0x03E8 598#define BGE_MBX_TX_NIC_PROD13_LO 0x03EC 599#define BGE_MBX_TX_NIC_PROD14_HI 0x03F0 600#define BGE_MBX_TX_NIC_PROD14_LO 0x03F4 601#define BGE_MBX_TX_NIC_PROD15_HI 0x03F8 602#define BGE_MBX_TX_NIC_PROD15_LO 0x03FC 603 604#define BGE_TX_RINGS_MAX 4 605#define BGE_TX_RINGS_EXTSSRAM_MAX 16 606#define BGE_RX_RINGS_MAX 16 607#define BGE_RX_RINGS_MAX_5717 17 608 609/* Ethernet MAC control registers */ 610#define BGE_MAC_MODE 0x0400 611#define BGE_MAC_STS 0x0404 612#define BGE_MAC_EVT_ENB 0x0408 613#define BGE_MAC_LED_CTL 0x040C 614#define BGE_MAC_ADDR1_LO 0x0410 615#define BGE_MAC_ADDR1_HI 0x0414 616#define BGE_MAC_ADDR2_LO 0x0418 617#define BGE_MAC_ADDR2_HI 0x041C 618#define BGE_MAC_ADDR3_LO 0x0420 619#define BGE_MAC_ADDR3_HI 0x0424 620#define BGE_MAC_ADDR4_LO 0x0428 621#define BGE_MAC_ADDR4_HI 0x042C 622#define BGE_WOL_PATPTR 0x0430 623#define BGE_WOL_PATCFG 0x0434 624#define BGE_TX_RANDOM_BACKOFF 0x0438 625#define BGE_RX_MTU 0x043C 626#define BGE_GBIT_PCS_TEST 0x0440 627#define BGE_TX_TBI_AUTONEG 0x0444 628#define BGE_RX_TBI_AUTONEG 0x0448 629#define BGE_MI_COMM 0x044C 630#define BGE_MI_STS 0x0450 631#define BGE_MI_MODE 0x0454 632#define BGE_AUTOPOLL_STS 0x0458 633#define BGE_TX_MODE 0x045C 634#define BGE_TX_STS 0x0460 635#define BGE_TX_LENGTHS 0x0464 636#define BGE_RX_MODE 0x0468 637#define BGE_RX_STS 0x046C 638#define BGE_MAR0 0x0470 639#define BGE_MAR1 0x0474 640#define BGE_MAR2 0x0478 641#define BGE_MAR3 0x047C 642#define BGE_RX_BD_RULES_CTL0 0x0480 643#define BGE_RX_BD_RULES_MASKVAL0 0x0484 644#define BGE_RX_BD_RULES_CTL1 0x0488 645#define BGE_RX_BD_RULES_MASKVAL1 0x048C 646#define BGE_RX_BD_RULES_CTL2 0x0490 647#define BGE_RX_BD_RULES_MASKVAL2 0x0494 648#define BGE_RX_BD_RULES_CTL3 0x0498 649#define BGE_RX_BD_RULES_MASKVAL3 0x049C 650#define BGE_RX_BD_RULES_CTL4 0x04A0 651#define BGE_RX_BD_RULES_MASKVAL4 0x04A4 652#define BGE_RX_BD_RULES_CTL5 0x04A8 653#define BGE_RX_BD_RULES_MASKVAL5 0x04AC 654#define BGE_RX_BD_RULES_CTL6 0x04B0 655#define BGE_RX_BD_RULES_MASKVAL6 0x04B4 656#define BGE_RX_BD_RULES_CTL7 0x04B8 657#define BGE_RX_BD_RULES_MASKVAL7 0x04BC 658#define BGE_RX_BD_RULES_CTL8 0x04C0 659#define BGE_RX_BD_RULES_MASKVAL8 0x04C4 660#define BGE_RX_BD_RULES_CTL9 0x04C8 661#define BGE_RX_BD_RULES_MASKVAL9 0x04CC 662#define BGE_RX_BD_RULES_CTL10 0x04D0 663#define BGE_RX_BD_RULES_MASKVAL10 0x04D4 664#define BGE_RX_BD_RULES_CTL11 0x04D8 665#define BGE_RX_BD_RULES_MASKVAL11 0x04DC 666#define BGE_RX_BD_RULES_CTL12 0x04E0 667#define BGE_RX_BD_RULES_MASKVAL12 0x04E4 668#define BGE_RX_BD_RULES_CTL13 0x04E8 669#define BGE_RX_BD_RULES_MASKVAL13 0x04EC 670#define BGE_RX_BD_RULES_CTL14 0x04F0 671#define BGE_RX_BD_RULES_MASKVAL14 0x04F4 672#define BGE_RX_BD_RULES_CTL15 0x04F8 673#define BGE_RX_BD_RULES_MASKVAL15 0x04FC 674#define BGE_RX_RULES_CFG 0x0500 675#define BGE_MAX_RX_FRAME_LOWAT 0x0504 676#define BGE_SERDES_CFG 0x0590 677#define BGE_SERDES_STS 0x0594 678#define BGE_SGDIG_CFG 0x05B0 679#define BGE_SGDIG_STS 0x05B4 680#define BGE_TX_MAC_STATS_OCTETS 0x0800 681#define BGE_TX_MAC_STATS_RESERVE_0 0x0804 682#define BGE_TX_MAC_STATS_COLLS 0x0808 683#define BGE_TX_MAC_STATS_XON_SENT 0x080C 684#define BGE_TX_MAC_STATS_XOFF_SENT 0x0810 685#define BGE_TX_MAC_STATS_RESERVE_1 0x0814 686#define BGE_TX_MAC_STATS_ERRORS 0x0818 687#define BGE_TX_MAC_STATS_SINGLE_COLL 0x081C 688#define BGE_TX_MAC_STATS_MULTI_COLL 0x0820 689#define BGE_TX_MAC_STATS_DEFERRED 0x0824 690#define BGE_TX_MAC_STATS_RESERVE_2 0x0828 691#define BGE_TX_MAC_STATS_EXCESS_COLL 0x082C 692#define BGE_TX_MAC_STATS_LATE_COLL 0x0830 693#define BGE_TX_MAC_STATS_RESERVE_3 0x0834 694#define BGE_TX_MAC_STATS_RESERVE_4 0x0838 695#define BGE_TX_MAC_STATS_RESERVE_5 0x083C 696#define BGE_TX_MAC_STATS_RESERVE_6 0x0840 697#define BGE_TX_MAC_STATS_RESERVE_7 0x0844 698#define BGE_TX_MAC_STATS_RESERVE_8 0x0848 699#define BGE_TX_MAC_STATS_RESERVE_9 0x084C 700#define BGE_TX_MAC_STATS_RESERVE_10 0x0850 701#define BGE_TX_MAC_STATS_RESERVE_11 0x0854 702#define BGE_TX_MAC_STATS_RESERVE_12 0x0858 703#define BGE_TX_MAC_STATS_RESERVE_13 0x085C 704#define BGE_TX_MAC_STATS_RESERVE_14 0x0860 705#define BGE_TX_MAC_STATS_RESERVE_15 0x0864 706#define BGE_TX_MAC_STATS_RESERVE_16 0x0868 707#define BGE_TX_MAC_STATS_UCAST 0x086C 708#define BGE_TX_MAC_STATS_MCAST 0x0870 709#define BGE_TX_MAC_STATS_BCAST 0x0874 710#define BGE_TX_MAC_STATS_RESERVE_17 0x0878 711#define BGE_TX_MAC_STATS_RESERVE_18 0x087C 712#define BGE_RX_MAC_STATS_OCTESTS 0x0880 713#define BGE_RX_MAC_STATS_RESERVE_0 0x0884 714#define BGE_RX_MAC_STATS_FRAGMENTS 0x0888 715#define BGE_RX_MAC_STATS_UCAST 0x088C 716#define BGE_RX_MAC_STATS_MCAST 0x0890 717#define BGE_RX_MAC_STATS_BCAST 0x0894 718#define BGE_RX_MAC_STATS_FCS_ERRORS 0x0898 719#define BGE_RX_MAC_STATS_ALGIN_ERRORS 0x089C 720#define BGE_RX_MAC_STATS_XON_RCVD 0x08A0 721#define BGE_RX_MAC_STATS_XOFF_RCVD 0x08A4 722#define BGE_RX_MAC_STATS_CTRL_RCVD 0x08A8 723#define BGE_RX_MAC_STATS_XOFF_ENTERED 0x08AC 724#define BGE_RX_MAC_STATS_FRAME_TOO_LONG 0x08B0 725#define BGE_RX_MAC_STATS_JABBERS 0x08B4 726#define BGE_RX_MAC_STATS_UNDERSIZE 0x08B8 727 728/* Ethernet MAC Mode register */ 729#define BGE_MACMODE_RESET 0x00000001 730#define BGE_MACMODE_HALF_DUPLEX 0x00000002 731#define BGE_MACMODE_PORTMODE 0x0000000C 732#define BGE_MACMODE_LOOPBACK 0x00000010 733#define BGE_MACMODE_RX_TAGGEDPKT 0x00000080 734#define BGE_MACMODE_TX_BURST_ENB 0x00000100 735#define BGE_MACMODE_MAX_DEFER 0x00000200 736#define BGE_MACMODE_LINK_POLARITY 0x00000400 737#define BGE_MACMODE_RX_STATS_ENB 0x00000800 738#define BGE_MACMODE_RX_STATS_CLEAR 0x00001000 739#define BGE_MACMODE_RX_STATS_FLUSH 0x00002000 740#define BGE_MACMODE_TX_STATS_ENB 0x00004000 741#define BGE_MACMODE_TX_STATS_CLEAR 0x00008000 742#define BGE_MACMODE_TX_STATS_FLUSH 0x00010000 743#define BGE_MACMODE_TBI_SEND_CFGS 0x00020000 744#define BGE_MACMODE_MAGIC_PKT_ENB 0x00040000 745#define BGE_MACMODE_ACPI_PWRON_ENB 0x00080000 746#define BGE_MACMODE_MIP_ENB 0x00100000 747#define BGE_MACMODE_TXDMA_ENB 0x00200000 748#define BGE_MACMODE_RXDMA_ENB 0x00400000 749#define BGE_MACMODE_FRMHDR_DMA_ENB 0x00800000 750#define BGE_MACMODE_APE_RX_EN 0x08000000 751#define BGE_MACMODE_APE_TX_EN 0x10000000 752 753#define BGE_PORTMODE_NONE 0x00000000 754#define BGE_PORTMODE_MII 0x00000004 755#define BGE_PORTMODE_GMII 0x00000008 756#define BGE_PORTMODE_TBI 0x0000000C 757 758/* MAC Status register */ 759#define BGE_MACSTAT_TBI_PCS_SYNCHED 0x00000001 760#define BGE_MACSTAT_TBI_SIGNAL_DETECT 0x00000002 761#define BGE_MACSTAT_RX_CFG 0x00000004 762#define BGE_MACSTAT_CFG_CHANGED 0x00000008 763#define BGE_MACSTAT_SYNC_CHANGED 0x00000010 764#define BGE_MACSTAT_PORT_DECODE_ERROR 0x00000400 765#define BGE_MACSTAT_LINK_CHANGED 0x00001000 766#define BGE_MACSTAT_MI_COMPLETE 0x00400000 767#define BGE_MACSTAT_MI_INTERRUPT 0x00800000 768#define BGE_MACSTAT_AUTOPOLL_ERROR 0x01000000 769#define BGE_MACSTAT_ODI_ERROR 0x02000000 770#define BGE_MACSTAT_RXSTAT_OFLOW 0x04000000 771#define BGE_MACSTAT_TXSTAT_OFLOW 0x08000000 772 773/* MAC Event Enable Register */ 774#define BGE_EVTENB_PORT_DECODE_ERROR 0x00000400 775#define BGE_EVTENB_LINK_CHANGED 0x00001000 776#define BGE_EVTENB_MI_COMPLETE 0x00400000 777#define BGE_EVTENB_MI_INTERRUPT 0x00800000 778#define BGE_EVTENB_AUTOPOLL_ERROR 0x01000000 779#define BGE_EVTENB_ODI_ERROR 0x02000000 780#define BGE_EVTENB_RXSTAT_OFLOW 0x04000000 781#define BGE_EVTENB_TXSTAT_OFLOW 0x08000000 782 783/* LED Control Register */ 784#define BGE_LEDCTL_LINKLED_OVERRIDE 0x00000001 785#define BGE_LEDCTL_1000MBPS_LED 0x00000002 786#define BGE_LEDCTL_100MBPS_LED 0x00000004 787#define BGE_LEDCTL_10MBPS_LED 0x00000008 788#define BGE_LEDCTL_TRAFLED_OVERRIDE 0x00000010 789#define BGE_LEDCTL_TRAFLED_BLINK 0x00000020 790#define BGE_LEDCTL_TRAFLED_BLINK_2 0x00000040 791#define BGE_LEDCTL_1000MBPS_STS 0x00000080 792#define BGE_LEDCTL_100MBPS_STS 0x00000100 793#define BGE_LEDCTL_10MBPS_STS 0x00000200 794#define BGE_LEDCTL_TRAFLED_STS 0x00000400 795#define BGE_LEDCTL_BLINKPERIOD 0x7FF80000 796#define BGE_LEDCTL_BLINKPERIOD_OVERRIDE 0x80000000 797 798/* TX backoff seed register */ 799#define BGE_TX_BACKOFF_SEED_MASK 0x3F 800 801/* Autopoll status register */ 802#define BGE_AUTOPOLLSTS_ERROR 0x00000001 803 804/* Transmit MAC mode register */ 805#define BGE_TXMODE_RESET 0x00000001 806#define BGE_TXMODE_ENABLE 0x00000002 807#define BGE_TXMODE_FLOWCTL_ENABLE 0x00000010 808#define BGE_TXMODE_BIGBACKOFF_ENABLE 0x00000020 809#define BGE_TXMODE_LONGPAUSE_ENABLE 0x00000040 810#define BGE_TXMODE_MBUF_LOCKUP_FIX 0x00000100 811#define BGE_TXMODE_JMB_FRM_LEN 0x00400000 812#define BGE_TXMODE_CNT_DN_MODE 0x00800000 813 814/* Transmit MAC status register */ 815#define BGE_TXSTAT_RX_XOFFED 0x00000001 816#define BGE_TXSTAT_SENT_XOFF 0x00000002 817#define BGE_TXSTAT_SENT_XON 0x00000004 818#define BGE_TXSTAT_LINK_UP 0x00000008 819#define BGE_TXSTAT_ODI_UFLOW 0x00000010 820#define BGE_TXSTAT_ODI_OFLOW 0x00000020 821 822/* Transmit MAC lengths register */ 823#define BGE_TXLEN_SLOTTIME 0x000000FF 824#define BGE_TXLEN_IPG 0x00000F00 825#define BGE_TXLEN_CRS 0x00003000 826#define BGE_TXLEN_JMB_FRM_LEN_MSK 0x00FF0000 827#define BGE_TXLEN_CNT_DN_VAL_MSK 0xFF000000 828 829/* Receive MAC mode register */ 830#define BGE_RXMODE_RESET 0x00000001 831#define BGE_RXMODE_ENABLE 0x00000002 832#define BGE_RXMODE_FLOWCTL_ENABLE 0x00000004 833#define BGE_RXMODE_RX_GIANTS 0x00000020 834#define BGE_RXMODE_RX_RUNTS 0x00000040 835#define BGE_RXMODE_8022_LENCHECK 0x00000080 836#define BGE_RXMODE_RX_PROMISC 0x00000100 837#define BGE_RXMODE_RX_NO_CRC_CHECK 0x00000200 838#define BGE_RXMODE_RX_KEEP_VLAN_DIAG 0x00000400 839#define BGE_RXMODE_IPV6_ENABLE 0x01000000 840 841/* Receive MAC status register */ 842#define BGE_RXSTAT_REMOTE_XOFFED 0x00000001 843#define BGE_RXSTAT_RCVD_XOFF 0x00000002 844#define BGE_RXSTAT_RCVD_XON 0x00000004 845 846/* Receive Rules Control register */ 847#define BGE_RXRULECTL_OFFSET 0x000000FF 848#define BGE_RXRULECTL_CLASS 0x00001F00 849#define BGE_RXRULECTL_HDRTYPE 0x0000E000 850#define BGE_RXRULECTL_COMPARE_OP 0x00030000 851#define BGE_RXRULECTL_MAP 0x01000000 852#define BGE_RXRULECTL_DISCARD 0x02000000 853#define BGE_RXRULECTL_MASK 0x04000000 854#define BGE_RXRULECTL_ACTIVATE_PROC3 0x08000000 855#define BGE_RXRULECTL_ACTIVATE_PROC2 0x10000000 856#define BGE_RXRULECTL_ACTIVATE_PROC1 0x20000000 857#define BGE_RXRULECTL_ANDWITHNEXT 0x40000000 858 859/* Receive Rules Mask register */ 860#define BGE_RXRULEMASK_VALUE 0x0000FFFF 861#define BGE_RXRULEMASK_MASKVAL 0xFFFF0000 862 863/* SERDES configuration register */ 864#define BGE_SERDESCFG_RXR 0x00000007 /* phase interpolator */ 865#define BGE_SERDESCFG_RXG 0x00000018 /* rx gain setting */ 866#define BGE_SERDESCFG_RXEDGESEL 0x00000040 /* rising/falling egde */ 867#define BGE_SERDESCFG_TX_BIAS 0x00000380 /* TXDAC bias setting */ 868#define BGE_SERDESCFG_IBMAX 0x00000400 /* bias current +25% */ 869#define BGE_SERDESCFG_IBMIN 0x00000800 /* bias current -25% */ 870#define BGE_SERDESCFG_TXMODE 0x00001000 871#define BGE_SERDESCFG_TXEDGESEL 0x00002000 /* rising/falling edge */ 872#define BGE_SERDESCFG_MODE 0x00004000 /* TXCP/TXCN disabled */ 873#define BGE_SERDESCFG_PLLTEST 0x00008000 /* PLL test mode */ 874#define BGE_SERDESCFG_CDET 0x00010000 /* comma detect enable */ 875#define BGE_SERDESCFG_TBILOOP 0x00020000 /* local loopback */ 876#define BGE_SERDESCFG_REMLOOP 0x00040000 /* remote loopback */ 877#define BGE_SERDESCFG_INVPHASE 0x00080000 /* Reverse 125Mhz clock */ 878#define BGE_SERDESCFG_12REGCTL 0x00300000 /* 1.2v regulator ctl */ 879#define BGE_SERDESCFG_REGCTL 0x00C00000 /* regulator ctl (2.5v) */ 880 881/* SERDES status register */ 882#define BGE_SERDESSTS_RXSTAT 0x0000000F /* receive status bits */ 883#define BGE_SERDESSTS_CDET 0x00000010 /* comma code detected */ 884 885/* SGDIG config (not documented) */ 886#define BGE_SGDIGCFG_PAUSE_CAP 0x00000800 887#define BGE_SGDIGCFG_ASYM_PAUSE 0x00001000 888#define BGE_SGDIGCFG_SEND 0x40000000 889#define BGE_SGDIGCFG_AUTO 0x80000000 890 891/* SGDIG status (not documented) */ 892#define BGE_SGDIGSTS_DONE 0x00000002 893#define BGE_SGDIGSTS_IS_SERDES 0x00000100 894#define BGE_SGDIGSTS_PAUSE_CAP 0x00080000 895#define BGE_SGDIGSTS_ASYM_PAUSE 0x00100000 896 897 898/* MI communication register */ 899#define BGE_MICOMM_DATA 0x0000FFFF 900#define BGE_MICOMM_REG 0x001F0000 901#define BGE_MICOMM_PHY 0x03E00000 902#define BGE_MICOMM_CMD 0x0C000000 903#define BGE_MICOMM_READFAIL 0x10000000 904#define BGE_MICOMM_BUSY 0x20000000 905 906#define BGE_MIREG(x) ((x & 0x1F) << 16) 907#define BGE_MIPHY(x) ((x & 0x1F) << 21) 908#define BGE_MICMD_WRITE 0x04000000 909#define BGE_MICMD_READ 0x08000000 910 911/* MI status register */ 912#define BGE_MISTS_LINK 0x00000001 913#define BGE_MISTS_10MBPS 0x00000002 914 915#define BGE_MIMODE_CLK_10MHZ 0x00000001 916#define BGE_MIMODE_SHORTPREAMBLE 0x00000002 917#define BGE_MIMODE_AUTOPOLL 0x00000010 918#define BGE_MIMODE_CLKCNT 0x001F0000 919#define BGE_MIMODE_500KHZ_CONST 0x00008000 920#define BGE_MIMODE_BASE 0x000C0000 921 922 923/* 924 * Send data initiator control registers. 925 */ 926#define BGE_SDI_MODE 0x0C00 927#define BGE_SDI_STATUS 0x0C04 928#define BGE_SDI_STATS_CTL 0x0C08 929#define BGE_SDI_STATS_ENABLE_MASK 0x0C0C 930#define BGE_SDI_STATS_INCREMENT_MASK 0x0C10 931#define BGE_ISO_PKT_TX 0x0C20 932#define BGE_LOCSTATS_COS0 0x0C80 933#define BGE_LOCSTATS_COS1 0x0C84 934#define BGE_LOCSTATS_COS2 0x0C88 935#define BGE_LOCSTATS_COS3 0x0C8C 936#define BGE_LOCSTATS_COS4 0x0C90 937#define BGE_LOCSTATS_COS5 0x0C84 938#define BGE_LOCSTATS_COS6 0x0C98 939#define BGE_LOCSTATS_COS7 0x0C9C 940#define BGE_LOCSTATS_COS8 0x0CA0 941#define BGE_LOCSTATS_COS9 0x0CA4 942#define BGE_LOCSTATS_COS10 0x0CA8 943#define BGE_LOCSTATS_COS11 0x0CAC 944#define BGE_LOCSTATS_COS12 0x0CB0 945#define BGE_LOCSTATS_COS13 0x0CB4 946#define BGE_LOCSTATS_COS14 0x0CB8 947#define BGE_LOCSTATS_COS15 0x0CBC 948#define BGE_LOCSTATS_DMA_RQ_FULL 0x0CC0 949#define BGE_LOCSTATS_DMA_HIPRIO_RQ_FULL 0x0CC4 950#define BGE_LOCSTATS_SDC_QUEUE_FULL 0x0CC8 951#define BGE_LOCSTATS_NIC_SENDPROD_SET 0x0CCC 952#define BGE_LOCSTATS_STATS_UPDATED 0x0CD0 953#define BGE_LOCSTATS_IRQS 0x0CD4 954#define BGE_LOCSTATS_AVOIDED_IRQS 0x0CD8 955#define BGE_LOCSTATS_TX_THRESH_HIT 0x0CDC 956 957/* Send Data Initiator mode register */ 958#define BGE_SDIMODE_RESET 0x00000001 959#define BGE_SDIMODE_ENABLE 0x00000002 960#define BGE_SDIMODE_STATS_OFLOW_ATTN 0x00000004 961#define BGE_SDIMODE_HW_LSO_PRE_DMA 0x00000008 962 963/* Send Data Initiator stats register */ 964#define BGE_SDISTAT_STATS_OFLOW_ATTN 0x00000004 965 966/* Send Data Initiator stats control register */ 967#define BGE_SDISTATSCTL_ENABLE 0x00000001 968#define BGE_SDISTATSCTL_FASTER 0x00000002 969#define BGE_SDISTATSCTL_CLEAR 0x00000004 970#define BGE_SDISTATSCTL_FORCEFLUSH 0x00000008 971#define BGE_SDISTATSCTL_FORCEZERO 0x00000010 972 973/* 974 * Send Data Completion Control registers 975 */ 976#define BGE_SDC_MODE 0x1000 977#define BGE_SDC_STATUS 0x1004 978 979/* Send Data completion mode register */ 980#define BGE_SDCMODE_RESET 0x00000001 981#define BGE_SDCMODE_ENABLE 0x00000002 982#define BGE_SDCMODE_ATTN 0x00000004 983#define BGE_SDCMODE_CDELAY 0x00000010 984 985/* Send Data completion status register */ 986#define BGE_SDCSTAT_ATTN 0x00000004 987 988/* 989 * Send BD Ring Selector Control registers 990 */ 991#define BGE_SRS_MODE 0x1400 992#define BGE_SRS_STATUS 0x1404 993#define BGE_SRS_HWDIAG 0x1408 994#define BGE_SRS_LOC_NIC_CONS0 0x1440 995#define BGE_SRS_LOC_NIC_CONS1 0x1444 996#define BGE_SRS_LOC_NIC_CONS2 0x1448 997#define BGE_SRS_LOC_NIC_CONS3 0x144C 998#define BGE_SRS_LOC_NIC_CONS4 0x1450 999#define BGE_SRS_LOC_NIC_CONS5 0x1454 1000#define BGE_SRS_LOC_NIC_CONS6 0x1458 1001#define BGE_SRS_LOC_NIC_CONS7 0x145C 1002#define BGE_SRS_LOC_NIC_CONS8 0x1460 1003#define BGE_SRS_LOC_NIC_CONS9 0x1464 1004#define BGE_SRS_LOC_NIC_CONS10 0x1468 1005#define BGE_SRS_LOC_NIC_CONS11 0x146C 1006#define BGE_SRS_LOC_NIC_CONS12 0x1470 1007#define BGE_SRS_LOC_NIC_CONS13 0x1474 1008#define BGE_SRS_LOC_NIC_CONS14 0x1478 1009#define BGE_SRS_LOC_NIC_CONS15 0x147C 1010 1011/* Send BD Ring Selector Mode register */ 1012#define BGE_SRSMODE_RESET 0x00000001 1013#define BGE_SRSMODE_ENABLE 0x00000002 1014#define BGE_SRSMODE_ATTN 0x00000004 1015 1016/* Send BD Ring Selector Status register */ 1017#define BGE_SRSSTAT_ERROR 0x00000004 1018 1019/* Send BD Ring Selector HW Diagnostics register */ 1020#define BGE_SRSHWDIAG_STATE 0x0000000F 1021#define BGE_SRSHWDIAG_CURRINGNUM 0x000000F0 1022#define BGE_SRSHWDIAG_STAGEDRINGNUM 0x00000F00 1023#define BGE_SRSHWDIAG_RINGNUM_IN_MBX 0x0000F000 1024 1025/* 1026 * Send BD Initiator Selector Control registers 1027 */ 1028#define BGE_SBDI_MODE 0x1800 1029#define BGE_SBDI_STATUS 0x1804 1030#define BGE_SBDI_LOC_NIC_PROD0 0x1808 1031#define BGE_SBDI_LOC_NIC_PROD1 0x180C 1032#define BGE_SBDI_LOC_NIC_PROD2 0x1810 1033#define BGE_SBDI_LOC_NIC_PROD3 0x1814 1034#define BGE_SBDI_LOC_NIC_PROD4 0x1818 1035#define BGE_SBDI_LOC_NIC_PROD5 0x181C 1036#define BGE_SBDI_LOC_NIC_PROD6 0x1820 1037#define BGE_SBDI_LOC_NIC_PROD7 0x1824 1038#define BGE_SBDI_LOC_NIC_PROD8 0x1828 1039#define BGE_SBDI_LOC_NIC_PROD9 0x182C 1040#define BGE_SBDI_LOC_NIC_PROD10 0x1830 1041#define BGE_SBDI_LOC_NIC_PROD11 0x1834 1042#define BGE_SBDI_LOC_NIC_PROD12 0x1838 1043#define BGE_SBDI_LOC_NIC_PROD13 0x183C 1044#define BGE_SBDI_LOC_NIC_PROD14 0x1840 1045#define BGE_SBDI_LOC_NIC_PROD15 0x1844 1046 1047/* Send BD Initiator Mode register */ 1048#define BGE_SBDIMODE_RESET 0x00000001 1049#define BGE_SBDIMODE_ENABLE 0x00000002 1050#define BGE_SBDIMODE_ATTN 0x00000004 1051 1052/* Send BD Initiator Status register */ 1053#define BGE_SBDISTAT_ERROR 0x00000004 1054 1055/* 1056 * Send BD Completion Control registers 1057 */ 1058#define BGE_SBDC_MODE 0x1C00 1059#define BGE_SBDC_STATUS 0x1C04 1060 1061/* Send BD Completion Control Mode register */ 1062#define BGE_SBDCMODE_RESET 0x00000001 1063#define BGE_SBDCMODE_ENABLE 0x00000002 1064#define BGE_SBDCMODE_ATTN 0x00000004 1065 1066/* Send BD Completion Control Status register */ 1067#define BGE_SBDCSTAT_ATTN 0x00000004 1068 1069/* 1070 * Receive List Placement Control registers 1071 */ 1072#define BGE_RXLP_MODE 0x2000 1073#define BGE_RXLP_STATUS 0x2004 1074#define BGE_RXLP_SEL_LIST_LOCK 0x2008 1075#define BGE_RXLP_SEL_NON_EMPTY_BITS 0x200C 1076#define BGE_RXLP_CFG 0x2010 1077#define BGE_RXLP_STATS_CTL 0x2014 1078#define BGE_RXLP_STATS_ENABLE_MASK 0x2018 1079#define BGE_RXLP_STATS_INCREMENT_MASK 0x201C 1080#define BGE_RXLP_HEAD0 0x2100 1081#define BGE_RXLP_TAIL0 0x2104 1082#define BGE_RXLP_COUNT0 0x2108 1083#define BGE_RXLP_HEAD1 0x2110 1084#define BGE_RXLP_TAIL1 0x2114 1085#define BGE_RXLP_COUNT1 0x2118 1086#define BGE_RXLP_HEAD2 0x2120 1087#define BGE_RXLP_TAIL2 0x2124 1088#define BGE_RXLP_COUNT2 0x2128 1089#define BGE_RXLP_HEAD3 0x2130 1090#define BGE_RXLP_TAIL3 0x2134 1091#define BGE_RXLP_COUNT3 0x2138 1092#define BGE_RXLP_HEAD4 0x2140 1093#define BGE_RXLP_TAIL4 0x2144 1094#define BGE_RXLP_COUNT4 0x2148 1095#define BGE_RXLP_HEAD5 0x2150 1096#define BGE_RXLP_TAIL5 0x2154 1097#define BGE_RXLP_COUNT5 0x2158 1098#define BGE_RXLP_HEAD6 0x2160 1099#define BGE_RXLP_TAIL6 0x2164 1100#define BGE_RXLP_COUNT6 0x2168 1101#define BGE_RXLP_HEAD7 0x2170 1102#define BGE_RXLP_TAIL7 0x2174 1103#define BGE_RXLP_COUNT7 0x2178 1104#define BGE_RXLP_HEAD8 0x2180 1105#define BGE_RXLP_TAIL8 0x2184 1106#define BGE_RXLP_COUNT8 0x2188 1107#define BGE_RXLP_HEAD9 0x2190 1108#define BGE_RXLP_TAIL9 0x2194 1109#define BGE_RXLP_COUNT9 0x2198 1110#define BGE_RXLP_HEAD10 0x21A0 1111#define BGE_RXLP_TAIL10 0x21A4 1112#define BGE_RXLP_COUNT10 0x21A8 1113#define BGE_RXLP_HEAD11 0x21B0 1114#define BGE_RXLP_TAIL11 0x21B4 1115#define BGE_RXLP_COUNT11 0x21B8 1116#define BGE_RXLP_HEAD12 0x21C0 1117#define BGE_RXLP_TAIL12 0x21C4 1118#define BGE_RXLP_COUNT12 0x21C8 1119#define BGE_RXLP_HEAD13 0x21D0 1120#define BGE_RXLP_TAIL13 0x21D4 1121#define BGE_RXLP_COUNT13 0x21D8 1122#define BGE_RXLP_HEAD14 0x21E0 1123#define BGE_RXLP_TAIL14 0x21E4 1124#define BGE_RXLP_COUNT14 0x21E8 1125#define BGE_RXLP_HEAD15 0x21F0 1126#define BGE_RXLP_TAIL15 0x21F4 1127#define BGE_RXLP_COUNT15 0x21F8 1128#define BGE_RXLP_LOCSTAT_COS0 0x2200 1129#define BGE_RXLP_LOCSTAT_COS1 0x2204 1130#define BGE_RXLP_LOCSTAT_COS2 0x2208 1131#define BGE_RXLP_LOCSTAT_COS3 0x220C 1132#define BGE_RXLP_LOCSTAT_COS4 0x2210 1133#define BGE_RXLP_LOCSTAT_COS5 0x2214 1134#define BGE_RXLP_LOCSTAT_COS6 0x2218 1135#define BGE_RXLP_LOCSTAT_COS7 0x221C 1136#define BGE_RXLP_LOCSTAT_COS8 0x2220 1137#define BGE_RXLP_LOCSTAT_COS9 0x2224 1138#define BGE_RXLP_LOCSTAT_COS10 0x2228 1139#define BGE_RXLP_LOCSTAT_COS11 0x222C 1140#define BGE_RXLP_LOCSTAT_COS12 0x2230 1141#define BGE_RXLP_LOCSTAT_COS13 0x2234 1142#define BGE_RXLP_LOCSTAT_COS14 0x2238 1143#define BGE_RXLP_LOCSTAT_COS15 0x223C 1144#define BGE_RXLP_LOCSTAT_FILTDROP 0x2240 1145#define BGE_RXLP_LOCSTAT_DMA_WRQ_FULL 0x2244 1146#define BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL 0x2248 1147#define BGE_RXLP_LOCSTAT_OUT_OF_BDS 0x224C 1148#define BGE_RXLP_LOCSTAT_IFIN_DROPS 0x2250 1149#define BGE_RXLP_LOCSTAT_IFIN_ERRORS 0x2254 1150#define BGE_RXLP_LOCSTAT_RXTHRESH_HIT 0x2258 1151 1152 1153/* Receive List Placement mode register */ 1154#define BGE_RXLPMODE_RESET 0x00000001 1155#define BGE_RXLPMODE_ENABLE 0x00000002 1156#define BGE_RXLPMODE_CLASS0_ATTN 0x00000004 1157#define BGE_RXLPMODE_MAPOUTRANGE_ATTN 0x00000008 1158#define BGE_RXLPMODE_STATSOFLOW_ATTN 0x00000010 1159 1160/* Receive List Placement Status register */ 1161#define BGE_RXLPSTAT_CLASS0_ATTN 0x00000004 1162#define BGE_RXLPSTAT_MAPOUTRANGE_ATTN 0x00000008 1163#define BGE_RXLPSTAT_STATSOFLOW_ATTN 0x00000010 1164 1165/* 1166 * Receive Data and Receive BD Initiator Control Registers 1167 */ 1168#define BGE_RDBDI_MODE 0x2400 1169#define BGE_RDBDI_STATUS 0x2404 1170#define BGE_RX_JUMBO_RCB_HADDR_HI 0x2440 1171#define BGE_RX_JUMBO_RCB_HADDR_LO 0x2444 1172#define BGE_RX_JUMBO_RCB_MAXLEN_FLAGS 0x2448 1173#define BGE_RX_JUMBO_RCB_NICADDR 0x244C 1174#define BGE_RX_STD_RCB_HADDR_HI 0x2450 1175#define BGE_RX_STD_RCB_HADDR_LO 0x2454 1176#define BGE_RX_STD_RCB_MAXLEN_FLAGS 0x2458 1177#define BGE_RX_STD_RCB_NICADDR 0x245C 1178#define BGE_RX_MINI_RCB_HADDR_HI 0x2460 1179#define BGE_RX_MINI_RCB_HADDR_LO 0x2464 1180#define BGE_RX_MINI_RCB_MAXLEN_FLAGS 0x2468 1181#define BGE_RX_MINI_RCB_NICADDR 0x246C 1182#define BGE_RDBDI_JUMBO_RX_CONS 0x2470 1183#define BGE_RDBDI_STD_RX_CONS 0x2474 1184#define BGE_RDBDI_MINI_RX_CONS 0x2478 1185#define BGE_RDBDI_RETURN_PROD0 0x2480 1186#define BGE_RDBDI_RETURN_PROD1 0x2484 1187#define BGE_RDBDI_RETURN_PROD2 0x2488 1188#define BGE_RDBDI_RETURN_PROD3 0x248C 1189#define BGE_RDBDI_RETURN_PROD4 0x2490 1190#define BGE_RDBDI_RETURN_PROD5 0x2494 1191#define BGE_RDBDI_RETURN_PROD6 0x2498 1192#define BGE_RDBDI_RETURN_PROD7 0x249C 1193#define BGE_RDBDI_RETURN_PROD8 0x24A0 1194#define BGE_RDBDI_RETURN_PROD9 0x24A4 1195#define BGE_RDBDI_RETURN_PROD10 0x24A8 1196#define BGE_RDBDI_RETURN_PROD11 0x24AC 1197#define BGE_RDBDI_RETURN_PROD12 0x24B0 1198#define BGE_RDBDI_RETURN_PROD13 0x24B4 1199#define BGE_RDBDI_RETURN_PROD14 0x24B8 1200#define BGE_RDBDI_RETURN_PROD15 0x24BC 1201#define BGE_RDBDI_HWDIAG 0x24C0 1202 1203 1204/* Receive Data and Receive BD Initiator Mode register */ 1205#define BGE_RDBDIMODE_RESET 0x00000001 1206#define BGE_RDBDIMODE_ENABLE 0x00000002 1207#define BGE_RDBDIMODE_JUMBO_ATTN 0x00000004 1208#define BGE_RDBDIMODE_GIANT_ATTN 0x00000008 1209#define BGE_RDBDIMODE_BADRINGSZ_ATTN 0x00000010 1210 1211/* Receive Data and Receive BD Initiator Status register */ 1212#define BGE_RDBDISTAT_JUMBO_ATTN 0x00000004 1213#define BGE_RDBDISTAT_GIANT_ATTN 0x00000008 1214#define BGE_RDBDISTAT_BADRINGSZ_ATTN 0x00000010 1215 1216 1217/* 1218 * Receive Data Completion Control registers 1219 */ 1220#define BGE_RDC_MODE 0x2800 1221 1222/* Receive Data Completion Mode register */ 1223#define BGE_RDCMODE_RESET 0x00000001 1224#define BGE_RDCMODE_ENABLE 0x00000002 1225#define BGE_RDCMODE_ATTN 0x00000004 1226 1227/* 1228 * Receive BD Initiator Control registers 1229 */ 1230#define BGE_RBDI_MODE 0x2C00 1231#define BGE_RBDI_STATUS 0x2C04 1232#define BGE_RBDI_NIC_JUMBO_BD_PROD 0x2C08 1233#define BGE_RBDI_NIC_STD_BD_PROD 0x2C0C 1234#define BGE_RBDI_NIC_MINI_BD_PROD 0x2C10 1235#define BGE_RBDI_MINI_REPL_THRESH 0x2C14 1236#define BGE_RBDI_STD_REPL_THRESH 0x2C18 1237#define BGE_RBDI_JUMBO_REPL_THRESH 0x2C1C 1238 1239#define BGE_STD_REPLENISH_LWM 0x2D00 1240#define BGE_JMB_REPLENISH_LWM 0x2D04 1241 1242/* Receive BD Initiator Mode register */ 1243#define BGE_RBDIMODE_RESET 0x00000001 1244#define BGE_RBDIMODE_ENABLE 0x00000002 1245#define BGE_RBDIMODE_ATTN 0x00000004 1246 1247/* Receive BD Initiator Status register */ 1248#define BGE_RBDISTAT_ATTN 0x00000004 1249 1250/* 1251 * Receive BD Completion Control registers 1252 */ 1253#define BGE_RBDC_MODE 0x3000 1254#define BGE_RBDC_STATUS 0x3004 1255#define BGE_RBDC_JUMBO_BD_PROD 0x3008 1256#define BGE_RBDC_STD_BD_PROD 0x300C 1257#define BGE_RBDC_MINI_BD_PROD 0x3010 1258 1259/* Receive BD completion mode register */ 1260#define BGE_RBDCMODE_RESET 0x00000001 1261#define BGE_RBDCMODE_ENABLE 0x00000002 1262#define BGE_RBDCMODE_ATTN 0x00000004 1263 1264/* Receive BD completion status register */ 1265#define BGE_RBDCSTAT_ERROR 0x00000004 1266 1267/* 1268 * Receive List Selector Control registers 1269 */ 1270#define BGE_RXLS_MODE 0x3400 1271#define BGE_RXLS_STATUS 0x3404 1272 1273/* Receive List Selector Mode register */ 1274#define BGE_RXLSMODE_RESET 0x00000001 1275#define BGE_RXLSMODE_ENABLE 0x00000002 1276#define BGE_RXLSMODE_ATTN 0x00000004 1277 1278/* Receive List Selector Status register */ 1279#define BGE_RXLSSTAT_ERROR 0x00000004 1280 1281#define BGE_CPMU_CTRL 0x3600 1282#define BGE_CPMU_LSPD_10MB_CLK 0x3604 1283#define BGE_CPMU_LSPD_1000MB_CLK 0x360C 1284#define BGE_CPMU_LNK_AWARE_PWRMD 0x3610 1285#define BGE_CPMU_HST_ACC 0x361C 1286#define BGE_CPMU_CLCK_ORIDE 0x3624 1287#define BGE_CPMU_CLCK_STAT 0x3630 1288#define BGE_CPMU_MUTEX_REQ 0x365C 1289#define BGE_CPMU_MUTEX_GNT 0x3660 1290#define BGE_CPMU_PHY_STRAP 0x3664 1291 1292/* Central Power Management Unit (CPMU) register */ 1293#define BGE_CPMU_CTRL_LINK_IDLE_MODE 0x00000200 1294#define BGE_CPMU_CTRL_LINK_AWARE_MODE 0x00000400 1295#define BGE_CPMU_CTRL_LINK_SPEED_MODE 0x00004000 1296#define BGE_CPMU_CTRL_GPHY_10MB_RXONLY 0x00010000 1297 1298/* Link Speed 10MB/No Link Power Mode Clock Policy register */ 1299#define BGE_CPMU_LSPD_10MB_MACCLK_MASK 0x001F0000 1300#define BGE_CPMU_LSPD_10MB_MACCLK_6_25 0x00130000 1301 1302/* Link Speed 1000MB Power Mode Clock Policy register */ 1303#define BGE_CPMU_LSPD_1000MB_MACCLK_62_5 0x00000000 1304#define BGE_CPMU_LSPD_1000MB_MACCLK_12_5 0x00110000 1305#define BGE_CPMU_LSPD_1000MB_MACCLK_MASK 0x001F0000 1306 1307/* Link Aware Power Mode Clock Policy register */ 1308#define BGE_CPMU_LNK_AWARE_MACCLK_MASK 0x001F0000 1309#define BGE_CPMU_LNK_AWARE_MACCLK_6_25 0x00130000 1310 1311#define BGE_CPMU_HST_ACC_MACCLK_MASK 0x001F0000 1312#define BGE_CPMU_HST_ACC_MACCLK_6_25 0x00130000 1313 1314/* Clock Speed Override Policy register */ 1315#define CPMU_CLCK_ORIDE_MAC_ORIDE_EN 0x80000000 1316 1317/* CPMU Clock Status register */ 1318#define BGE_CPMU_CLCK_STAT_MAC_CLCK_MASK 0x001F0000 1319#define BGE_CPMU_CLCK_STAT_MAC_CLCK_62_5 0x00000000 1320#define BGE_CPMU_CLCK_STAT_MAC_CLCK_12_5 0x00110000 1321#define BGE_CPMU_CLCK_STAT_MAC_CLCK_6_25 0x00130000 1322 1323/* CPMU Mutex Request register */ 1324#define BGE_CPMU_MUTEX_REQ_DRIVER 0x00001000 1325#define BGE_CPMU_MUTEX_GNT_DRIVER 0x00001000 1326 1327/* CPMU GPHY Strap register */ 1328#define BGE_CPMU_PHY_STRAP_IS_SERDES 0x00000020 1329 1330/* 1331 * Mbuf Cluster Free registers (has nothing to do with BSD mbufs) 1332 */ 1333#define BGE_MBCF_MODE 0x3800 1334#define BGE_MBCF_STATUS 0x3804 1335 1336/* Mbuf Cluster Free mode register */ 1337#define BGE_MBCFMODE_RESET 0x00000001 1338#define BGE_MBCFMODE_ENABLE 0x00000002 1339#define BGE_MBCFMODE_ATTN 0x00000004 1340 1341/* Mbuf Cluster Free status register */ 1342#define BGE_MBCFSTAT_ERROR 0x00000004 1343 1344/* 1345 * Host Coalescing Control registers 1346 */ 1347#define BGE_HCC_MODE 0x3C00 1348#define BGE_HCC_STATUS 0x3C04 1349#define BGE_HCC_RX_COAL_TICKS 0x3C08 1350#define BGE_HCC_TX_COAL_TICKS 0x3C0C 1351#define BGE_HCC_RX_MAX_COAL_BDS 0x3C10 1352#define BGE_HCC_TX_MAX_COAL_BDS 0x3C14 1353#define BGE_HCC_RX_COAL_TICKS_INT 0x3C18 /* ticks during interrupt */ 1354#define BGE_HCC_TX_COAL_TICKS_INT 0x3C1C /* ticks during interrupt */ 1355#define BGE_HCC_RX_MAX_COAL_BDS_INT 0x3C20 /* BDs during interrupt */ 1356#define BGE_HCC_TX_MAX_COAL_BDS_INT 0x3C24 /* BDs during interrupt */ 1357#define BGE_HCC_STATS_TICKS 0x3C28 1358#define BGE_HCC_STATS_ADDR_HI 0x3C30 1359#define BGE_HCC_STATS_ADDR_LO 0x3C34 1360#define BGE_HCC_STATUSBLK_ADDR_HI 0x3C38 1361#define BGE_HCC_STATUSBLK_ADDR_LO 0x3C3C 1362#define BGE_HCC_STATS_BASEADDR 0x3C40 /* address in NIC memory */ 1363#define BGE_HCC_STATUSBLK_BASEADDR 0x3C44 /* address in NIC memory */ 1364#define BGE_FLOW_ATTN 0x3C48 1365#define BGE_HCC_JUMBO_BD_CONS 0x3C50 1366#define BGE_HCC_STD_BD_CONS 0x3C54 1367#define BGE_HCC_MINI_BD_CONS 0x3C58 1368#define BGE_HCC_RX_RETURN_PROD0 0x3C80 1369#define BGE_HCC_RX_RETURN_PROD1 0x3C84 1370#define BGE_HCC_RX_RETURN_PROD2 0x3C88 1371#define BGE_HCC_RX_RETURN_PROD3 0x3C8C 1372#define BGE_HCC_RX_RETURN_PROD4 0x3C90 1373#define BGE_HCC_RX_RETURN_PROD5 0x3C94 1374#define BGE_HCC_RX_RETURN_PROD6 0x3C98 1375#define BGE_HCC_RX_RETURN_PROD7 0x3C9C 1376#define BGE_HCC_RX_RETURN_PROD8 0x3CA0 1377#define BGE_HCC_RX_RETURN_PROD9 0x3CA4 1378#define BGE_HCC_RX_RETURN_PROD10 0x3CA8 1379#define BGE_HCC_RX_RETURN_PROD11 0x3CAC 1380#define BGE_HCC_RX_RETURN_PROD12 0x3CB0 1381#define BGE_HCC_RX_RETURN_PROD13 0x3CB4 1382#define BGE_HCC_RX_RETURN_PROD14 0x3CB8 1383#define BGE_HCC_RX_RETURN_PROD15 0x3CBC 1384#define BGE_HCC_TX_BD_CONS0 0x3CC0 1385#define BGE_HCC_TX_BD_CONS1 0x3CC4 1386#define BGE_HCC_TX_BD_CONS2 0x3CC8 1387#define BGE_HCC_TX_BD_CONS3 0x3CCC 1388#define BGE_HCC_TX_BD_CONS4 0x3CD0 1389#define BGE_HCC_TX_BD_CONS5 0x3CD4 1390#define BGE_HCC_TX_BD_CONS6 0x3CD8 1391#define BGE_HCC_TX_BD_CONS7 0x3CDC 1392#define BGE_HCC_TX_BD_CONS8 0x3CE0 1393#define BGE_HCC_TX_BD_CONS9 0x3CE4 1394#define BGE_HCC_TX_BD_CONS10 0x3CE8 1395#define BGE_HCC_TX_BD_CONS11 0x3CEC 1396#define BGE_HCC_TX_BD_CONS12 0x3CF0 1397#define BGE_HCC_TX_BD_CONS13 0x3CF4 1398#define BGE_HCC_TX_BD_CONS14 0x3CF8 1399#define BGE_HCC_TX_BD_CONS15 0x3CFC 1400 1401 1402/* Host coalescing mode register */ 1403#define BGE_HCCMODE_RESET 0x00000001 1404#define BGE_HCCMODE_ENABLE 0x00000002 1405#define BGE_HCCMODE_ATTN 0x00000004 1406#define BGE_HCCMODE_COAL_NOW 0x00000008 1407#define BGE_HCCMODE_MSI_BITS 0x00000070 1408#define BGE_HCCMODE_STATBLK_SIZE 0x00000180 1409 1410#define BGE_STATBLKSZ_FULL 0x00000000 1411#define BGE_STATBLKSZ_64BYTE 0x00000080 1412#define BGE_STATBLKSZ_32BYTE 0x00000100 1413 1414/* Host coalescing status register */ 1415#define BGE_HCCSTAT_ERROR 0x00000004 1416 1417/* Flow attention register */ 1418#define BGE_FLOWATTN_MB_LOWAT 0x00000040 1419#define BGE_FLOWATTN_MEMARB 0x00000080 1420#define BGE_FLOWATTN_HOSTCOAL 0x00008000 1421#define BGE_FLOWATTN_DMADONE_DISCARD 0x00010000 1422#define BGE_FLOWATTN_RCB_INVAL 0x00020000 1423#define BGE_FLOWATTN_RXDATA_CORRUPT 0x00040000 1424#define BGE_FLOWATTN_RDBDI 0x00080000 1425#define BGE_FLOWATTN_RXLS 0x00100000 1426#define BGE_FLOWATTN_RXLP 0x00200000 1427#define BGE_FLOWATTN_RBDC 0x00400000 1428#define BGE_FLOWATTN_RBDI 0x00800000 1429#define BGE_FLOWATTN_SDC 0x08000000 1430#define BGE_FLOWATTN_SDI 0x10000000 1431#define BGE_FLOWATTN_SRS 0x20000000 1432#define BGE_FLOWATTN_SBDC 0x40000000 1433#define BGE_FLOWATTN_SBDI 0x80000000 1434 1435/* 1436 * Memory arbiter registers 1437 */ 1438#define BGE_MARB_MODE 0x4000 1439#define BGE_MARB_STATUS 0x4004 1440#define BGE_MARB_TRAPADDR_HI 0x4008 1441#define BGE_MARB_TRAPADDR_LO 0x400C 1442 1443/* Memory arbiter mode register */ 1444#define BGE_MARBMODE_RESET 0x00000001 1445#define BGE_MARBMODE_ENABLE 0x00000002 1446#define BGE_MARBMODE_TX_ADDR_TRAP 0x00000004 1447#define BGE_MARBMODE_RX_ADDR_TRAP 0x00000008 1448#define BGE_MARBMODE_DMAW1_TRAP 0x00000010 1449#define BGE_MARBMODE_DMAR1_TRAP 0x00000020 1450#define BGE_MARBMODE_RXRISC_TRAP 0x00000040 1451#define BGE_MARBMODE_TXRISC_TRAP 0x00000080 1452#define BGE_MARBMODE_PCI_TRAP 0x00000100 1453#define BGE_MARBMODE_DMAR2_TRAP 0x00000200 1454#define BGE_MARBMODE_RXQ_TRAP 0x00000400 1455#define BGE_MARBMODE_RXDI1_TRAP 0x00000800 1456#define BGE_MARBMODE_RXDI2_TRAP 0x00001000 1457#define BGE_MARBMODE_DC_GRPMEM_TRAP 0x00002000 1458#define BGE_MARBMODE_HCOAL_TRAP 0x00004000 1459#define BGE_MARBMODE_MBUF_TRAP 0x00008000 1460#define BGE_MARBMODE_TXDI_TRAP 0x00010000 1461#define BGE_MARBMODE_SDC_DMAC_TRAP 0x00020000 1462#define BGE_MARBMODE_TXBD_TRAP 0x00040000 1463#define BGE_MARBMODE_BUFFMAN_TRAP 0x00080000 1464#define BGE_MARBMODE_DMAW2_TRAP 0x00100000 1465#define BGE_MARBMODE_XTSSRAM_ROFLO_TRAP 0x00200000 1466#define BGE_MARBMODE_XTSSRAM_RUFLO_TRAP 0x00400000 1467#define BGE_MARBMODE_XTSSRAM_WOFLO_TRAP 0x00800000 1468#define BGE_MARBMODE_XTSSRAM_WUFLO_TRAP 0x01000000 1469#define BGE_MARBMODE_XTSSRAM_PERR_TRAP 0x02000000 1470 1471/* Memory arbiter status register */ 1472#define BGE_MARBSTAT_TX_ADDR_TRAP 0x00000004 1473#define BGE_MARBSTAT_RX_ADDR_TRAP 0x00000008 1474#define BGE_MARBSTAT_DMAW1_TRAP 0x00000010 1475#define BGE_MARBSTAT_DMAR1_TRAP 0x00000020 1476#define BGE_MARBSTAT_RXRISC_TRAP 0x00000040 1477#define BGE_MARBSTAT_TXRISC_TRAP 0x00000080 1478#define BGE_MARBSTAT_PCI_TRAP 0x00000100 1479#define BGE_MARBSTAT_DMAR2_TRAP 0x00000200 1480#define BGE_MARBSTAT_RXQ_TRAP 0x00000400 1481#define BGE_MARBSTAT_RXDI1_TRAP 0x00000800 1482#define BGE_MARBSTAT_RXDI2_TRAP 0x00001000 1483#define BGE_MARBSTAT_DC_GRPMEM_TRAP 0x00002000 1484#define BGE_MARBSTAT_HCOAL_TRAP 0x00004000 1485#define BGE_MARBSTAT_MBUF_TRAP 0x00008000 1486#define BGE_MARBSTAT_TXDI_TRAP 0x00010000 1487#define BGE_MARBSTAT_SDC_DMAC_TRAP 0x00020000 1488#define BGE_MARBSTAT_TXBD_TRAP 0x00040000 1489#define BGE_MARBSTAT_BUFFMAN_TRAP 0x00080000 1490#define BGE_MARBSTAT_DMAW2_TRAP 0x00100000 1491#define BGE_MARBSTAT_XTSSRAM_ROFLO_TRAP 0x00200000 1492#define BGE_MARBSTAT_XTSSRAM_RUFLO_TRAP 0x00400000 1493#define BGE_MARBSTAT_XTSSRAM_WOFLO_TRAP 0x00800000 1494#define BGE_MARBSTAT_XTSSRAM_WUFLO_TRAP 0x01000000 1495#define BGE_MARBSTAT_XTSSRAM_PERR_TRAP 0x02000000 1496 1497/* 1498 * Buffer manager control registers 1499 */ 1500#define BGE_BMAN_MODE 0x4400 1501#define BGE_BMAN_STATUS 0x4404 1502#define BGE_BMAN_MBUFPOOL_BASEADDR 0x4408 1503#define BGE_BMAN_MBUFPOOL_LEN 0x440C 1504#define BGE_BMAN_MBUFPOOL_READDMA_LOWAT 0x4410 1505#define BGE_BMAN_MBUFPOOL_MACRX_LOWAT 0x4414 1506#define BGE_BMAN_MBUFPOOL_HIWAT 0x4418 1507#define BGE_BMAN_RXCPU_MBALLOC_REQ 0x441C 1508#define BGE_BMAN_RXCPU_MBALLOC_RESP 0x4420 1509#define BGE_BMAN_TXCPU_MBALLOC_REQ 0x4424 1510#define BGE_BMAN_TXCPU_MBALLOC_RESP 0x4428 1511#define BGE_BMAN_DMA_DESCPOOL_BASEADDR 0x442C 1512#define BGE_BMAN_DMA_DESCPOOL_LEN 0x4430 1513#define BGE_BMAN_DMA_DESCPOOL_LOWAT 0x4434 1514#define BGE_BMAN_DMA_DESCPOOL_HIWAT 0x4438 1515#define BGE_BMAN_RXCPU_DMAALLOC_REQ 0x443C 1516#define BGE_BMAN_RXCPU_DMAALLOC_RESP 0x4440 1517#define BGE_BMAN_TXCPU_DMAALLOC_REQ 0x4444 1518#define BGE_BMAN_TXCPU_DMALLLOC_RESP 0x4448 1519#define BGE_BMAN_HWDIAG_1 0x444C 1520#define BGE_BMAN_HWDIAG_2 0x4450 1521#define BGE_BMAN_HWDIAG_3 0x4454 1522 1523/* Buffer manager mode register */ 1524#define BGE_BMANMODE_RESET 0x00000001 1525#define BGE_BMANMODE_ENABLE 0x00000002 1526#define BGE_BMANMODE_ATTN 0x00000004 1527#define BGE_BMANMODE_TESTMODE 0x00000008 1528#define BGE_BMANMODE_LOMBUF_ATTN 0x00000010 1529#define BGE_BMANMODE_NO_TX_UNDERRUN 0x80000000 1530 1531/* Buffer manager status register */ 1532#define BGE_BMANSTAT_ERRO 0x00000004 1533#define BGE_BMANSTAT_LOWMBUF_ERROR 0x00000010 1534 1535 1536/* 1537 * Read DMA Control registers 1538 */ 1539#define BGE_RDMA_MODE 0x4800 1540#define BGE_RDMA_STATUS 0x4804 1541#define BGE_RDMA_RSRVCTRL 0x4900 1542#define BGE_RDMA_LSO_CRPTEN_CTRL 0x4910 1543 1544/* Read DMA mode register */ 1545#define BGE_RDMAMODE_RESET 0x00000001 1546#define BGE_RDMAMODE_ENABLE 0x00000002 1547#define BGE_RDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1548#define BGE_RDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1549#define BGE_RDMAMODE_PCI_PERR_ATTN 0x00000010 1550#define BGE_RDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1551#define BGE_RDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1552#define BGE_RDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1553#define BGE_RDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1554#define BGE_RDMAMODE_LOCWRITE_TOOBIG 0x00000200 1555#define BGE_RDMAMODE_ALL_ATTNS 0x000003FC 1556#define BGE_RDMAMODE_BD_SBD_CRPT_ATTN 0x00000800 1557#define BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN 0x00001000 1558#define BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN 0x00002000 1559#define BGE_RDMAMODE_FIFO_SIZE_128 0x00020000 1560#define BGE_RDMAMODE_FIFO_LONG_BURST 0x00030000 1561#define BGE_RDMAMODE_MULT_DMA_RD_DIS 0x01000000 1562#define BGE_RDMAMODE_TSO4_ENABLE 0x08000000 1563#define BGE_RDMAMODE_TSO6_ENABLE 0x10000000 1564#define BGE_RDMAMODE_H2BNC_VLAN_DET 0x20000000 1565 1566/* Read DMA status register */ 1567#define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1568#define BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1569#define BGE_RDMASTAT_PCI_PERR_ATTN 0x00000010 1570#define BGE_RDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1571#define BGE_RDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1572#define BGE_RDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1573#define BGE_RDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1574#define BGE_RDMASTAT_LOCWRITE_TOOBIG 0x00000200 1575 1576/* Read DMA Reserved Control register */ 1577#define BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX 0x00000004 1578#define BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K 0x00000C00 1579#define BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K 0x000C0000 1580#define BGE_RDMA_RSRVCTRL_TXMRGN_320B 0x28000000 1581#define BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK 0x00000FF0 1582#define BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK 0x000FF000 1583#define BGE_RDMA_RSRVCTRL_TXMRGN_MASK 0xFFE00000 1584 1585#define BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 0x00020000 1586#define BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K 0x00030000 1587#define BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K 0x000C0000 1588 1589/* BD Read DMA Mode register */ 1590#define BGE_RDMA_BD_MODE 0x4A00 1591/* BD Read DMA Mode status register */ 1592#define BGE_RDMA_BD_STATUS 0x4A04 1593 1594#define BGE_RDMA_BD_MODE_RESET 0x00000001 1595#define BGE_RDMA_BD_MODE_ENABLE 0x00000002 1596 1597/* Non-LSO Read DMA Mode register */ 1598#define BGE_RDMA_NON_LSO_MODE 0x4B00 1599/* Non-LSO Read DMA Mode status register */ 1600#define BGE_RDMA_NON_LSO_STATUS 0x4B04 1601 1602#define BGE_RDMA_NON_LSO_MODE_RESET 0x00000001 1603#define BGE_RDMA_NON_LSO_MODE_ENABLE 0x00000002 1604 1605/* 1606 * Write DMA control registers 1607 */ 1608#define BGE_WDMA_MODE 0x4C00 1609#define BGE_WDMA_STATUS 0x4C04 1610 1611/* Write DMA mode register */ 1612#define BGE_WDMAMODE_RESET 0x00000001 1613#define BGE_WDMAMODE_ENABLE 0x00000002 1614#define BGE_WDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1615#define BGE_WDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1616#define BGE_WDMAMODE_PCI_PERR_ATTN 0x00000010 1617#define BGE_WDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1618#define BGE_WDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1619#define BGE_WDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1620#define BGE_WDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1621#define BGE_WDMAMODE_LOCREAD_TOOBIG 0x00000200 1622#define BGE_WDMAMODE_ALL_ATTNS 0x000003FC 1623#define BGE_WDMAMODE_STATUS_TAG_FIX 0x20000000 1624#define BGE_WDMAMODE_BURST_ALL_DATA 0xC0000000 1625 1626/* Write DMA status register */ 1627#define BGE_WDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1628#define BGE_WDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1629#define BGE_WDMASTAT_PCI_PERR_ATTN 0x00000010 1630#define BGE_WDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1631#define BGE_WDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1632#define BGE_WDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1633#define BGE_WDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1634#define BGE_WDMASTAT_LOCREAD_TOOBIG 0x00000200 1635 1636 1637/* 1638 * RX CPU registers 1639 */ 1640#define BGE_RXCPU_MODE 0x5000 1641#define BGE_RXCPU_STATUS 0x5004 1642#define BGE_RXCPU_PC 0x501C 1643 1644/* RX CPU mode register */ 1645#define BGE_RXCPUMODE_RESET 0x00000001 1646#define BGE_RXCPUMODE_SINGLESTEP 0x00000002 1647#define BGE_RXCPUMODE_P0_DATAHLT_ENB 0x00000004 1648#define BGE_RXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1649#define BGE_RXCPUMODE_WR_POSTBUF_ENB 0x00000010 1650#define BGE_RXCPUMODE_DATACACHE_ENB 0x00000020 1651#define BGE_RXCPUMODE_ROMFAIL 0x00000040 1652#define BGE_RXCPUMODE_WATCHDOG_ENB 0x00000080 1653#define BGE_RXCPUMODE_INSTRCACHE_PRF 0x00000100 1654#define BGE_RXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1655#define BGE_RXCPUMODE_HALTCPU 0x00000400 1656#define BGE_RXCPUMODE_INVDATAHLT_ENB 0x00000800 1657#define BGE_RXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1658#define BGE_RXCPUMODE_RADDRTRAPHLT_ENB 0x00002000 1659 1660/* RX CPU status register */ 1661#define BGE_RXCPUSTAT_HW_BREAKPOINT 0x00000001 1662#define BGE_RXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1663#define BGE_RXCPUSTAT_INVALID_INSTR 0x00000004 1664#define BGE_RXCPUSTAT_P0_DATAREF 0x00000008 1665#define BGE_RXCPUSTAT_P0_INSTRREF 0x00000010 1666#define BGE_RXCPUSTAT_INVALID_DATAACC 0x00000020 1667#define BGE_RXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1668#define BGE_RXCPUSTAT_BAD_MEMALIGN 0x00000080 1669#define BGE_RXCPUSTAT_MADDR_TRAP 0x00000100 1670#define BGE_RXCPUSTAT_REGADDR_TRAP 0x00000200 1671#define BGE_RXCPUSTAT_DATAACC_STALL 0x00001000 1672#define BGE_RXCPUSTAT_INSTRFETCH_STALL 0x00002000 1673#define BGE_RXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1674#define BGE_RXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1675#define BGE_RXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1676#define BGE_RXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1677#define BGE_RXCPUSTAT_BLOCKING_READ 0x80000000 1678 1679/* 1680 * V? CPU registers 1681 */ 1682#define BGE_VCPU_STATUS 0x5100 1683#define BGE_VCPU_EXT_CTRL 0x6890 1684 1685#define BGE_VCPU_STATUS_INIT_DONE 0x04000000 1686#define BGE_VCPU_STATUS_DRV_RESET 0x08000000 1687 1688#define BGE_VCPU_EXT_CTRL_HALT_CPU 0x00400000 1689#define BGE_VCPU_EXT_CTRL_DISABLE_WOL 0x20000000 1690 1691/* 1692 * TX CPU registers 1693 */ 1694#define BGE_TXCPU_MODE 0x5400 1695#define BGE_TXCPU_STATUS 0x5404 1696#define BGE_TXCPU_PC 0x541C 1697 1698/* TX CPU mode register */ 1699#define BGE_TXCPUMODE_RESET 0x00000001 1700#define BGE_TXCPUMODE_SINGLESTEP 0x00000002 1701#define BGE_TXCPUMODE_P0_DATAHLT_ENB 0x00000004 1702#define BGE_TXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1703#define BGE_TXCPUMODE_WR_POSTBUF_ENB 0x00000010 1704#define BGE_TXCPUMODE_DATACACHE_ENB 0x00000020 1705#define BGE_TXCPUMODE_ROMFAIL 0x00000040 1706#define BGE_TXCPUMODE_WATCHDOG_ENB 0x00000080 1707#define BGE_TXCPUMODE_INSTRCACHE_PRF 0x00000100 1708#define BGE_TXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1709#define BGE_TXCPUMODE_HALTCPU 0x00000400 1710#define BGE_TXCPUMODE_INVDATAHLT_ENB 0x00000800 1711#define BGE_TXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1712 1713/* TX CPU status register */ 1714#define BGE_TXCPUSTAT_HW_BREAKPOINT 0x00000001 1715#define BGE_TXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1716#define BGE_TXCPUSTAT_INVALID_INSTR 0x00000004 1717#define BGE_TXCPUSTAT_P0_DATAREF 0x00000008 1718#define BGE_TXCPUSTAT_P0_INSTRREF 0x00000010 1719#define BGE_TXCPUSTAT_INVALID_DATAACC 0x00000020 1720#define BGE_TXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1721#define BGE_TXCPUSTAT_BAD_MEMALIGN 0x00000080 1722#define BGE_TXCPUSTAT_MADDR_TRAP 0x00000100 1723#define BGE_TXCPUSTAT_REGADDR_TRAP 0x00000200 1724#define BGE_TXCPUSTAT_DATAACC_STALL 0x00001000 1725#define BGE_TXCPUSTAT_INSTRFETCH_STALL 0x00002000 1726#define BGE_TXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1727#define BGE_TXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1728#define BGE_TXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1729#define BGE_TXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1730#define BGE_TXCPUSTAT_BLOCKING_READ 0x80000000 1731 1732 1733/* 1734 * Low priority mailbox registers 1735 */ 1736#define BGE_LPMBX_IRQ0_HI 0x5800 1737#define BGE_LPMBX_IRQ0_LO 0x5804 1738#define BGE_LPMBX_IRQ1_HI 0x5808 1739#define BGE_LPMBX_IRQ1_LO 0x580C 1740#define BGE_LPMBX_IRQ2_HI 0x5810 1741#define BGE_LPMBX_IRQ2_LO 0x5814 1742#define BGE_LPMBX_IRQ3_HI 0x5818 1743#define BGE_LPMBX_IRQ3_LO 0x581C 1744#define BGE_LPMBX_GEN0_HI 0x5820 1745#define BGE_LPMBX_GEN0_LO 0x5824 1746#define BGE_LPMBX_GEN1_HI 0x5828 1747#define BGE_LPMBX_GEN1_LO 0x582C 1748#define BGE_LPMBX_GEN2_HI 0x5830 1749#define BGE_LPMBX_GEN2_LO 0x5834 1750#define BGE_LPMBX_GEN3_HI 0x5828 1751#define BGE_LPMBX_GEN3_LO 0x582C 1752#define BGE_LPMBX_GEN4_HI 0x5840 1753#define BGE_LPMBX_GEN4_LO 0x5844 1754#define BGE_LPMBX_GEN5_HI 0x5848 1755#define BGE_LPMBX_GEN5_LO 0x584C 1756#define BGE_LPMBX_GEN6_HI 0x5850 1757#define BGE_LPMBX_GEN6_LO 0x5854 1758#define BGE_LPMBX_GEN7_HI 0x5858 1759#define BGE_LPMBX_GEN7_LO 0x585C 1760#define BGE_LPMBX_RELOAD_STATS_HI 0x5860 1761#define BGE_LPMBX_RELOAD_STATS_LO 0x5864 1762#define BGE_LPMBX_RX_STD_PROD_HI 0x5868 1763#define BGE_LPMBX_RX_STD_PROD_LO 0x586C 1764#define BGE_LPMBX_RX_JUMBO_PROD_HI 0x5870 1765#define BGE_LPMBX_RX_JUMBO_PROD_LO 0x5874 1766#define BGE_LPMBX_RX_MINI_PROD_HI 0x5878 1767#define BGE_LPMBX_RX_MINI_PROD_LO 0x587C 1768#define BGE_LPMBX_RX_CONS0_HI 0x5880 1769#define BGE_LPMBX_RX_CONS0_LO 0x5884 1770#define BGE_LPMBX_RX_CONS1_HI 0x5888 1771#define BGE_LPMBX_RX_CONS1_LO 0x588C 1772#define BGE_LPMBX_RX_CONS2_HI 0x5890 1773#define BGE_LPMBX_RX_CONS2_LO 0x5894 1774#define BGE_LPMBX_RX_CONS3_HI 0x5898 1775#define BGE_LPMBX_RX_CONS3_LO 0x589C 1776#define BGE_LPMBX_RX_CONS4_HI 0x58A0 1777#define BGE_LPMBX_RX_CONS4_LO 0x58A4 1778#define BGE_LPMBX_RX_CONS5_HI 0x58A8 1779#define BGE_LPMBX_RX_CONS5_LO 0x58AC 1780#define BGE_LPMBX_RX_CONS6_HI 0x58B0 1781#define BGE_LPMBX_RX_CONS6_LO 0x58B4 1782#define BGE_LPMBX_RX_CONS7_HI 0x58B8 1783#define BGE_LPMBX_RX_CONS7_LO 0x58BC 1784#define BGE_LPMBX_RX_CONS8_HI 0x58C0 1785#define BGE_LPMBX_RX_CONS8_LO 0x58C4 1786#define BGE_LPMBX_RX_CONS9_HI 0x58C8 1787#define BGE_LPMBX_RX_CONS9_LO 0x58CC 1788#define BGE_LPMBX_RX_CONS10_HI 0x58D0 1789#define BGE_LPMBX_RX_CONS10_LO 0x58D4 1790#define BGE_LPMBX_RX_CONS11_HI 0x58D8 1791#define BGE_LPMBX_RX_CONS11_LO 0x58DC 1792#define BGE_LPMBX_RX_CONS12_HI 0x58E0 1793#define BGE_LPMBX_RX_CONS12_LO 0x58E4 1794#define BGE_LPMBX_RX_CONS13_HI 0x58E8 1795#define BGE_LPMBX_RX_CONS13_LO 0x58EC 1796#define BGE_LPMBX_RX_CONS14_HI 0x58F0 1797#define BGE_LPMBX_RX_CONS14_LO 0x58F4 1798#define BGE_LPMBX_RX_CONS15_HI 0x58F8 1799#define BGE_LPMBX_RX_CONS15_LO 0x58FC 1800#define BGE_LPMBX_TX_HOST_PROD0_HI 0x5900 1801#define BGE_LPMBX_TX_HOST_PROD0_LO 0x5904 1802#define BGE_LPMBX_TX_HOST_PROD1_HI 0x5908 1803#define BGE_LPMBX_TX_HOST_PROD1_LO 0x590C 1804#define BGE_LPMBX_TX_HOST_PROD2_HI 0x5910 1805#define BGE_LPMBX_TX_HOST_PROD2_LO 0x5914 1806#define BGE_LPMBX_TX_HOST_PROD3_HI 0x5918 1807#define BGE_LPMBX_TX_HOST_PROD3_LO 0x591C 1808#define BGE_LPMBX_TX_HOST_PROD4_HI 0x5920 1809#define BGE_LPMBX_TX_HOST_PROD4_LO 0x5924 1810#define BGE_LPMBX_TX_HOST_PROD5_HI 0x5928 1811#define BGE_LPMBX_TX_HOST_PROD5_LO 0x592C 1812#define BGE_LPMBX_TX_HOST_PROD6_HI 0x5930 1813#define BGE_LPMBX_TX_HOST_PROD6_LO 0x5934 1814#define BGE_LPMBX_TX_HOST_PROD7_HI 0x5938 1815#define BGE_LPMBX_TX_HOST_PROD7_LO 0x593C 1816#define BGE_LPMBX_TX_HOST_PROD8_HI 0x5940 1817#define BGE_LPMBX_TX_HOST_PROD8_LO 0x5944 1818#define BGE_LPMBX_TX_HOST_PROD9_HI 0x5948 1819#define BGE_LPMBX_TX_HOST_PROD9_LO 0x594C 1820#define BGE_LPMBX_TX_HOST_PROD10_HI 0x5950 1821#define BGE_LPMBX_TX_HOST_PROD10_LO 0x5954 1822#define BGE_LPMBX_TX_HOST_PROD11_HI 0x5958 1823#define BGE_LPMBX_TX_HOST_PROD11_LO 0x595C 1824#define BGE_LPMBX_TX_HOST_PROD12_HI 0x5960 1825#define BGE_LPMBX_TX_HOST_PROD12_LO 0x5964 1826#define BGE_LPMBX_TX_HOST_PROD13_HI 0x5968 1827#define BGE_LPMBX_TX_HOST_PROD13_LO 0x596C 1828#define BGE_LPMBX_TX_HOST_PROD14_HI 0x5970 1829#define BGE_LPMBX_TX_HOST_PROD14_LO 0x5974 1830#define BGE_LPMBX_TX_HOST_PROD15_HI 0x5978 1831#define BGE_LPMBX_TX_HOST_PROD15_LO 0x597C 1832#define BGE_LPMBX_TX_NIC_PROD0_HI 0x5980 1833#define BGE_LPMBX_TX_NIC_PROD0_LO 0x5984 1834#define BGE_LPMBX_TX_NIC_PROD1_HI 0x5988 1835#define BGE_LPMBX_TX_NIC_PROD1_LO 0x598C 1836#define BGE_LPMBX_TX_NIC_PROD2_HI 0x5990 1837#define BGE_LPMBX_TX_NIC_PROD2_LO 0x5994 1838#define BGE_LPMBX_TX_NIC_PROD3_HI 0x5998 1839#define BGE_LPMBX_TX_NIC_PROD3_LO 0x599C 1840#define BGE_LPMBX_TX_NIC_PROD4_HI 0x59A0 1841#define BGE_LPMBX_TX_NIC_PROD4_LO 0x59A4 1842#define BGE_LPMBX_TX_NIC_PROD5_HI 0x59A8 1843#define BGE_LPMBX_TX_NIC_PROD5_LO 0x59AC 1844#define BGE_LPMBX_TX_NIC_PROD6_HI 0x59B0 1845#define BGE_LPMBX_TX_NIC_PROD6_LO 0x59B4 1846#define BGE_LPMBX_TX_NIC_PROD7_HI 0x59B8 1847#define BGE_LPMBX_TX_NIC_PROD7_LO 0x59BC 1848#define BGE_LPMBX_TX_NIC_PROD8_HI 0x59C0 1849#define BGE_LPMBX_TX_NIC_PROD8_LO 0x59C4 1850#define BGE_LPMBX_TX_NIC_PROD9_HI 0x59C8 1851#define BGE_LPMBX_TX_NIC_PROD9_LO 0x59CC 1852#define BGE_LPMBX_TX_NIC_PROD10_HI 0x59D0 1853#define BGE_LPMBX_TX_NIC_PROD10_LO 0x59D4 1854#define BGE_LPMBX_TX_NIC_PROD11_HI 0x59D8 1855#define BGE_LPMBX_TX_NIC_PROD11_LO 0x59DC 1856#define BGE_LPMBX_TX_NIC_PROD12_HI 0x59E0 1857#define BGE_LPMBX_TX_NIC_PROD12_LO 0x59E4 1858#define BGE_LPMBX_TX_NIC_PROD13_HI 0x59E8 1859#define BGE_LPMBX_TX_NIC_PROD13_LO 0x59EC 1860#define BGE_LPMBX_TX_NIC_PROD14_HI 0x59F0 1861#define BGE_LPMBX_TX_NIC_PROD14_LO 0x59F4 1862#define BGE_LPMBX_TX_NIC_PROD15_HI 0x59F8 1863#define BGE_LPMBX_TX_NIC_PROD15_LO 0x59FC 1864 1865/* 1866 * Flow throw Queue reset register 1867 */ 1868#define BGE_FTQ_RESET 0x5C00 1869 1870#define BGE_FTQRESET_DMAREAD 0x00000002 1871#define BGE_FTQRESET_DMAHIPRIO_RD 0x00000004 1872#define BGE_FTQRESET_DMADONE 0x00000010 1873#define BGE_FTQRESET_SBDC 0x00000020 1874#define BGE_FTQRESET_SDI 0x00000040 1875#define BGE_FTQRESET_WDMA 0x00000080 1876#define BGE_FTQRESET_DMAHIPRIO_WR 0x00000100 1877#define BGE_FTQRESET_TYPE1_SOFTWARE 0x00000200 1878#define BGE_FTQRESET_SDC 0x00000400 1879#define BGE_FTQRESET_HCC 0x00000800 1880#define BGE_FTQRESET_TXFIFO 0x00001000 1881#define BGE_FTQRESET_MBC 0x00002000 1882#define BGE_FTQRESET_RBDC 0x00004000 1883#define BGE_FTQRESET_RXLP 0x00008000 1884#define BGE_FTQRESET_RDBDI 0x00010000 1885#define BGE_FTQRESET_RDC 0x00020000 1886#define BGE_FTQRESET_TYPE2_SOFTWARE 0x00040000 1887 1888/* 1889 * Message Signaled Interrupt registers 1890 */ 1891#define BGE_MSI_MODE 0x6000 1892#define BGE_MSI_STATUS 0x6004 1893#define BGE_MSI_FIFOACCESS 0x6008 1894 1895/* MSI mode register */ 1896#define BGE_MSIMODE_RESET 0x00000001 1897#define BGE_MSIMODE_ENABLE 0x00000002 1898#define BGE_MSIMODE_ONE_SHOT_DISABLE 0x00000020 1899#define BGE_MSIMODE_MULTIVEC_ENABLE 0x00000080 1900 1901/* MSI status register */ 1902#define BGE_MSISTAT_PCI_TGT_ABRT_ATTN 0x00000004 1903#define BGE_MSISTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1904#define BGE_MSISTAT_PCI_PERR_ATTN 0x00000010 1905#define BGE_MSISTAT_MSI_FIFOUFLOW_ATTN 0x00000020 1906#define BGE_MSISTAT_MSI_FIFOOFLOW_ATTN 0x00000040 1907 1908 1909/* 1910 * DMA Completion registers 1911 */ 1912#define BGE_DMAC_MODE 0x6400 1913 1914/* DMA Completion mode register */ 1915#define BGE_DMACMODE_RESET 0x00000001 1916#define BGE_DMACMODE_ENABLE 0x00000002 1917 1918 1919/* 1920 * General control registers. 1921 */ 1922#define BGE_MODE_CTL 0x6800 1923#define BGE_MISC_CFG 0x6804 1924#define BGE_MISC_LOCAL_CTL 0x6808 1925#define BGE_RX_CPU_EVENT 0x6810 1926#define BGE_TX_CPU_EVENT 0x6820 1927#define BGE_EE_ADDR 0x6838 1928#define BGE_EE_DATA 0x683C 1929#define BGE_EE_CTL 0x6840 1930#define BGE_MDI_CTL 0x6844 1931#define BGE_EE_DELAY 0x6848 1932#define BGE_FASTBOOT_PC 0x6894 1933 1934#define BGE_RX_CPU_DRV_EVENT 0x00004000 1935 1936/* 1937 * NVRAM Control registers 1938 */ 1939#define BGE_NVRAM_CMD 0x7000 1940#define BGE_NVRAM_STAT 0x7004 1941#define BGE_NVRAM_WRDATA 0x7008 1942#define BGE_NVRAM_ADDR 0x700c 1943#define BGE_NVRAM_RDDATA 0x7010 1944#define BGE_NVRAM_CFG1 0x7014 1945#define BGE_NVRAM_CFG2 0x7018 1946#define BGE_NVRAM_CFG3 0x701c 1947#define BGE_NVRAM_SWARB 0x7020 1948#define BGE_NVRAM_ACCESS 0x7024 1949#define BGE_NVRAM_WRITE1 0x7028 1950 1951#define BGE_NVRAMCMD_RESET 0x00000001 1952#define BGE_NVRAMCMD_DONE 0x00000008 1953#define BGE_NVRAMCMD_START 0x00000010 1954#define BGE_NVRAMCMD_WR 0x00000020 /* 1 = wr, 0 = rd */ 1955#define BGE_NVRAMCMD_ERASE 0x00000040 1956#define BGE_NVRAMCMD_FIRST 0x00000080 1957#define BGE_NVRAMCMD_LAST 0x00000100 1958 1959#define BGE_NVRAM_READCMD \ 1960 (BGE_NVRAMCMD_FIRST|BGE_NVRAMCMD_LAST| \ 1961 BGE_NVRAMCMD_START|BGE_NVRAMCMD_DONE) 1962#define BGE_NVRAM_WRITECMD \ 1963 (BGE_NVRAMCMD_FIRST|BGE_NVRAMCMD_LAST| \ 1964 BGE_NVRAMCMD_START|BGE_NVRAMCMD_DONE|BGE_NVRAMCMD_WR) 1965 1966#define BGE_NVRAMSWARB_SET0 0x00000001 1967#define BGE_NVRAMSWARB_SET1 0x00000002 1968#define BGE_NVRAMSWARB_SET2 0x00000003 1969#define BGE_NVRAMSWARB_SET3 0x00000004 1970#define BGE_NVRAMSWARB_CLR0 0x00000010 1971#define BGE_NVRAMSWARB_CLR1 0x00000020 1972#define BGE_NVRAMSWARB_CLR2 0x00000040 1973#define BGE_NVRAMSWARB_CLR3 0x00000080 1974#define BGE_NVRAMSWARB_GNT0 0x00000100 1975#define BGE_NVRAMSWARB_GNT1 0x00000200 1976#define BGE_NVRAMSWARB_GNT2 0x00000400 1977#define BGE_NVRAMSWARB_GNT3 0x00000800 1978#define BGE_NVRAMSWARB_REQ0 0x00001000 1979#define BGE_NVRAMSWARB_REQ1 0x00002000 1980#define BGE_NVRAMSWARB_REQ2 0x00004000 1981#define BGE_NVRAMSWARB_REQ3 0x00008000 1982 1983#define BGE_NVRAMACC_ENABLE 0x00000001 1984#define BGE_NVRAMACC_WRENABLE 0x00000002 1985 1986/* Mode control register */ 1987#define BGE_MODECTL_INT_SNDCOAL_ONLY 0x00000001 1988#define BGE_MODECTL_BYTESWAP_NONFRAME 0x00000002 1989#define BGE_MODECTL_WORDSWAP_NONFRAME 0x00000004 1990#define BGE_MODECTL_BYTESWAP_DATA 0x00000010 1991#define BGE_MODECTL_WORDSWAP_DATA 0x00000020 1992#define BGE_MODECTL_BYTESWAP_B2HRX_DATA 0x00000040 1993#define BGE_MODECTL_WORDSWAP_B2HRX_DATA 0x00000080 1994#define BGE_MODECTL_NO_FRAME_CRACKING 0x00000200 1995#define BGE_MODECTL_NO_RX_CRC 0x00000400 1996#define BGE_MODECTL_RX_BADFRAMES 0x00000800 1997#define BGE_MODECTL_NO_TX_INTR 0x00002000 1998#define BGE_MODECTL_NO_RX_INTR 0x00004000 1999#define BGE_MODECTL_FORCE_PCI32 0x00008000 2000#define BGE_MODECTL_B2HRX_ENABLE 0x00008000 2001#define BGE_MODECTL_STACKUP 0x00010000 2002#define BGE_MODECTL_HOST_SEND_BDS 0x00020000 2003#define BGE_MODECTL_HTX2B_ENABLE 0x00040000 2004#define BGE_MODECTL_TX_NO_PHDR_CSUM 0x00100000 2005#define BGE_MODECTL_RX_NO_PHDR_CSUM 0x00800000 2006#define BGE_MODECTL_TX_ATTN_INTR 0x01000000 2007#define BGE_MODECTL_RX_ATTN_INTR 0x02000000 2008#define BGE_MODECTL_MAC_ATTN_INTR 0x04000000 2009#define BGE_MODECTL_DMA_ATTN_INTR 0x08000000 2010#define BGE_MODECTL_FLOWCTL_ATTN_INTR 0x10000000 2011#define BGE_MODECTL_4X_SENDRING_SZ 0x20000000 2012#define BGE_MODECTL_FW_PROCESS_MCASTS 0x40000000 2013 2014/* Misc. config register */ 2015#define BGE_MISCCFG_RESET_CORE_CLOCKS 0x00000001 2016#define BGE_MISCCFG_TIMER_PRESCALER 0x000000FE 2017#define BGE_MISCCFG_BOARD_ID_MASK 0x0001E000 2018#define BGE_MISCCFG_BOARD_ID_5704 0x00000000 2019#define BGE_MISCCFG_BOARD_ID_5704CIOBE 0x00004000 2020#define BGE_MISCCFG_BOARD_ID_5788 0x00010000 2021#define BGE_MISCCFG_BOARD_ID_5788M 0x00018000 2022#define BGE_MISCCFG_EPHY_IDDQ 0x00200000 2023#define BGE_MISCCFG_GPHY_PD_OVERRIDE 0x04000000 2024 2025#define BGE_32BITTIME_66MHZ (0x41 << 1) 2026 2027/* Misc. Local Control */ 2028#define BGE_MLC_INTR_STATE 0x00000001 2029#define BGE_MLC_INTR_CLR 0x00000002 2030#define BGE_MLC_INTR_SET 0x00000004 2031#define BGE_MLC_INTR_ONATTN 0x00000008 2032#define BGE_MLC_MISCIO_IN0 0x00000100 2033#define BGE_MLC_MISCIO_IN1 0x00000200 2034#define BGE_MLC_MISCIO_IN2 0x00000400 2035#define BGE_MLC_MISCIO_OUTEN0 0x00000800 2036#define BGE_MLC_MISCIO_OUTEN1 0x00001000 2037#define BGE_MLC_MISCIO_OUTEN2 0x00002000 2038#define BGE_MLC_MISCIO_OUT0 0x00004000 2039#define BGE_MLC_MISCIO_OUT1 0x00008000 2040#define BGE_MLC_MISCIO_OUT2 0x00010000 2041#define BGE_MLC_EXTRAM_ENB 0x00020000 2042#define BGE_MLC_SRAM_SIZE 0x001C0000 2043#define BGE_MLC_BANK_SEL 0x00200000 /* 0 = 2 banks, 1 == 1 */ 2044#define BGE_MLC_SSRAM_TYPE 0x00400000 /* 1 = ZBT, 0 = standard */ 2045#define BGE_MLC_SSRAM_CYC_DESEL 0x00800000 2046#define BGE_MLC_AUTO_EEPROM 0x01000000 2047 2048#define BGE_SSRAMSIZE_256KB 0x00000000 2049#define BGE_SSRAMSIZE_512KB 0x00040000 2050#define BGE_SSRAMSIZE_1MB 0x00080000 2051#define BGE_SSRAMSIZE_2MB 0x000C0000 2052#define BGE_SSRAMSIZE_4MB 0x00100000 2053#define BGE_SSRAMSIZE_8MB 0x00140000 2054#define BGE_SSRAMSIZE_16M 0x00180000 2055 2056/* EEPROM address register */ 2057#define BGE_EEADDR_ADDRESS 0x0000FFFC 2058#define BGE_EEADDR_HALFCLK 0x01FF0000 2059#define BGE_EEADDR_START 0x02000000 2060#define BGE_EEADDR_DEVID 0x1C000000 2061#define BGE_EEADDR_RESET 0x20000000 2062#define BGE_EEADDR_DONE 0x40000000 2063#define BGE_EEADDR_RW 0x80000000 /* 1 = rd, 0 = wr */ 2064 2065#define BGE_EEDEVID(x) ((x & 7) << 26) 2066#define BGE_EEHALFCLK(x) ((x & 0x1FF) << 16) 2067#define BGE_HALFCLK_384SCL 0x60 2068#define BGE_EE_READCMD \ 2069 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 2070 BGE_EEADDR_START|BGE_EEADDR_RW|BGE_EEADDR_DONE) 2071#define BGE_EE_WRCMD \ 2072 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 2073 BGE_EEADDR_START|BGE_EEADDR_DONE) 2074 2075/* EEPROM Control register */ 2076#define BGE_EECTL_CLKOUT_TRISTATE 0x00000001 2077#define BGE_EECTL_CLKOUT 0x00000002 2078#define BGE_EECTL_CLKIN 0x00000004 2079#define BGE_EECTL_DATAOUT_TRISTATE 0x00000008 2080#define BGE_EECTL_DATAOUT 0x00000010 2081#define BGE_EECTL_DATAIN 0x00000020 2082 2083/* MDI (MII/GMII) access register */ 2084#define BGE_MDI_DATA 0x00000001 2085#define BGE_MDI_DIR 0x00000002 2086#define BGE_MDI_SEL 0x00000004 2087#define BGE_MDI_CLK 0x00000008 2088 2089#define BGE_MEMWIN_START 0x00008000 2090#define BGE_MEMWIN_END 0x0000FFFF 2091 2092/* BAR1 (APE) Register Definitions */ 2093 2094#define BGE_APE_GPIO_MSG 0x0008 2095#define BGE_APE_EVENT 0x000C 2096#define BGE_APE_LOCK_REQ 0x002C 2097#define BGE_APE_LOCK_GRANT 0x004C 2098 2099#define BGE_APE_GPIO_MSG_SHIFT 4 2100 2101#define BGE_APE_EVENT_1 0x00000001 2102 2103#define BGE_APE_LOCK_REQ_DRIVER0 0x00001000 2104 2105#define BGE_APE_LOCK_GRANT_DRIVER0 0x00001000 2106 2107/* APE Shared Memory block (writable by APE only) */ 2108#define BGE_APE_SEG_SIG 0x4000 2109#define BGE_APE_FW_STATUS 0x400C 2110#define BGE_APE_FW_FEATURES 0x4010 2111#define BGE_APE_FW_BEHAVIOR 0x4014 2112#define BGE_APE_FW_VERSION 0x4018 2113#define BGE_APE_FW_HEARTBEAT_INTERVAL 0x4024 2114#define BGE_APE_FW_HEARTBEAT 0x4028 2115#define BGE_APE_FW_ERROR_FLAGS 0x4074 2116 2117#define BGE_APE_SEG_SIG_MAGIC 0x41504521 2118 2119#define BGE_APE_FW_STATUS_READY 0x00000100 2120 2121#define BGE_APE_FW_FEATURE_DASH 0x00000001 2122#define BGE_APE_FW_FEATURE_NCSI 0x00000002 2123 2124#define BGE_APE_FW_VERSION_MAJMSK 0xFF000000 2125#define BGE_APE_FW_VERSION_MAJSFT 24 2126#define BGE_APE_FW_VERSION_MINMSK 0x00FF0000 2127#define BGE_APE_FW_VERSION_MINSFT 16 2128#define BGE_APE_FW_VERSION_REVMSK 0x0000FF00 2129#define BGE_APE_FW_VERSION_REVSFT 8 2130#define BGE_APE_FW_VERSION_BLDMSK 0x000000FF 2131 2132/* Host Shared Memory block (writable by host only) */ 2133#define BGE_APE_HOST_SEG_SIG 0x4200 2134#define BGE_APE_HOST_SEG_LEN 0x4204 2135#define BGE_APE_HOST_INIT_COUNT 0x4208 2136#define BGE_APE_HOST_DRIVER_ID 0x420C 2137#define BGE_APE_HOST_BEHAVIOR 0x4210 2138#define BGE_APE_HOST_HEARTBEAT_INT_MS 0x4214 2139#define BGE_APE_HOST_HEARTBEAT_COUNT 0x4218 2140#define BGE_APE_HOST_DRVR_STATE 0x421C 2141#define BGE_APE_HOST_WOL_SPEED 0x4224 2142 2143#define BGE_APE_HOST_SEG_SIG_MAGIC 0x484F5354 2144 2145#define BGE_APE_HOST_SEG_LEN_MAGIC 0x00000020 2146 2147#define BGE_APE_HOST_DRIVER_ID_FBSD 0xF6000000 2148#define BGE_APE_HOST_DRIVER_ID_MAGIC(maj, min) \ 2149 (BGE_APE_HOST_DRIVER_ID_FBSD | \ 2150 ((maj) & 0xffd) << 16 | ((min) & 0xff) << 8) 2151 2152#define BGE_APE_HOST_BEHAV_NO_PHYLOCK 0x00000001 2153 2154#define BGE_APE_HOST_HEARTBEAT_INT_DISABLE 0 2155#define BGE_APE_HOST_HEARTBEAT_INT_5SEC 5000 2156 2157#define BGE_APE_HOST_DRVR_STATE_START 0x00000001 2158#define BGE_APE_HOST_DRVR_STATE_UNLOAD 0x00000002 2159#define BGE_APE_HOST_DRVR_STATE_WOL 0x00000003 2160#define BGE_APE_HOST_DRVR_STATE_SUSPEND 0x00000004 2161 2162#define BGE_APE_HOST_WOL_SPEED_AUTO 0x00008000 2163 2164#define BGE_APE_EVENT_STATUS 0x4300 2165 2166#define BGE_APE_EVENT_STATUS_DRIVER_EVNT 0x00000010 2167#define BGE_APE_EVENT_STATUS_STATE_CHNGE 0x00000500 2168#define BGE_APE_EVENT_STATUS_STATE_START 0x00010000 2169#define BGE_APE_EVENT_STATUS_STATE_UNLOAD 0x00020000 2170#define BGE_APE_EVENT_STATUS_STATE_WOL 0x00030000 2171#define BGE_APE_EVENT_STATUS_STATE_SUSPEND 0x00040000 2172#define BGE_APE_EVENT_STATUS_EVENT_PENDING 0x80000000 2173 2174#define BGE_APE_DEBUG_LOG 0x4E00 2175#define BGE_APE_DEBUG_LOG_LEN 0x0100 2176 2177#define BGE_APE_PER_LOCK_REQ 0x8400 2178#define BGE_APE_PER_LOCK_GRANT 0x8420 2179 2180#define BGE_APE_LOCK_PER_REQ_DRIVER0 0x00001000 2181#define BGE_APE_LOCK_PER_REQ_DRIVER1 0x00000002 2182#define BGE_APE_LOCK_PER_REQ_DRIVER2 0x00000004 2183#define BGE_APE_LOCK_PER_REQ_DRIVER3 0x00000008 2184 2185#define BGE_APE_PER_LOCK_GRANT_DRIVER0 0x00001000 2186#define BGE_APE_PER_LOCK_GRANT_DRIVER1 0x00000002 2187#define BGE_APE_PER_LOCK_GRANT_DRIVER2 0x00000004 2188#define BGE_APE_PER_LOCK_GRANT_DRIVER3 0x00000008 2189 2190/* APE Mutex Resources */ 2191#define BGE_APE_LOCK_PHY0 0 2192#define BGE_APE_LOCK_GRC 1 2193#define BGE_APE_LOCK_PHY1 2 2194#define BGE_APE_LOCK_PHY2 3 2195#define BGE_APE_LOCK_MEM 4 2196#define BGE_APE_LOCK_PHY3 5 2197#define BGE_APE_LOCK_GPIO 7 2198 2199#define BGE_MEMWIN_READ(sc, x, val) \ 2200 do { \ 2201 pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \ 2202 (0xFFFF0000 & x), 4); \ 2203 val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \ 2204 } while(0) 2205 2206#define BGE_MEMWIN_WRITE(sc, x, val) \ 2207 do { \ 2208 pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \ 2209 (0xFFFF0000 & x), 4); \ 2210 CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val); \ 2211 } while(0) 2212 2213/* 2214 * This magic number is written to the firmware mailbox at 0xb50 2215 * before a software reset is issued. After the internal firmware 2216 * has completed its initialization it will write the opposite of 2217 * this value, ~BGE_SRAM_FW_MB_MAGIC, to the same location, 2218 * allowing the driver to synchronize with the firmware. 2219 */ 2220#define BGE_SRAM_FW_MB_MAGIC 0x4B657654 2221 2222typedef struct { 2223 uint32_t bge_addr_hi; 2224 uint32_t bge_addr_lo; 2225} bge_hostaddr; 2226 2227#define BGE_HOSTADDR(x, y) \ 2228 do { \ 2229 (x).bge_addr_lo = ((uint64_t) (y) & 0xffffffff); \ 2230 (x).bge_addr_hi = ((uint64_t) (y) >> 32); \ 2231 } while(0) 2232 2233#define BGE_ADDR_LO(y) \ 2234 ((uint64_t) (y) & 0xFFFFFFFF) 2235#define BGE_ADDR_HI(y) \ 2236 ((uint64_t) (y) >> 32) 2237 2238/* Ring control block structure */ 2239struct bge_rcb { 2240 bge_hostaddr bge_hostaddr; 2241 uint32_t bge_maxlen_flags; 2242 uint32_t bge_nicaddr; 2243}; 2244 2245#define RCB_WRITE_4(sc, rcb, offset, val) \ 2246 bus_write_4(sc->bge_res, rcb + offsetof(struct bge_rcb, offset), val) 2247#define BGE_RCB_MAXLEN_FLAGS(maxlen, flags) ((maxlen) << 16 | (flags)) 2248 2249#define BGE_RCB_FLAG_USE_EXT_RX_BD 0x0001 2250#define BGE_RCB_FLAG_RING_DISABLED 0x0002 2251 2252struct bge_tx_bd { 2253 bge_hostaddr bge_addr; 2254#if BYTE_ORDER == LITTLE_ENDIAN 2255 uint16_t bge_flags; 2256 uint16_t bge_len; 2257 uint16_t bge_vlan_tag; 2258 uint16_t bge_mss; 2259#else 2260 uint16_t bge_len; 2261 uint16_t bge_flags; 2262 uint16_t bge_mss; 2263 uint16_t bge_vlan_tag; 2264#endif 2265}; 2266 2267#define BGE_TXBDFLAG_TCP_UDP_CSUM 0x0001 2268#define BGE_TXBDFLAG_IP_CSUM 0x0002 2269#define BGE_TXBDFLAG_END 0x0004 2270#define BGE_TXBDFLAG_IP_FRAG 0x0008 2271#define BGE_TXBDFLAG_JUMBO_FRAME 0x0008 /* 5717 */ 2272#define BGE_TXBDFLAG_IP_FRAG_END 0x0010 2273#define BGE_TXBDFLAG_HDRLEN_BIT2 0x0010 /* 5717 */ 2274#define BGE_TXBDFLAG_SNAP 0x0020 /* 5717 */ 2275#define BGE_TXBDFLAG_VLAN_TAG 0x0040 2276#define BGE_TXBDFLAG_COAL_NOW 0x0080 2277#define BGE_TXBDFLAG_CPU_PRE_DMA 0x0100 2278#define BGE_TXBDFLAG_CPU_POST_DMA 0x0200 2279#define BGE_TXBDFLAG_HDRLEN_BIT3 0x0400 /* 5717 */ 2280#define BGE_TXBDFLAG_HDRLEN_BIT4 0x0800 /* 5717 */ 2281#define BGE_TXBDFLAG_INSERT_SRC_ADDR 0x1000 2282#define BGE_TXBDFLAG_HDRLEN_BIT5 0x1000 /* 5717 */ 2283#define BGE_TXBDFLAG_HDRLEN_BIT6 0x2000 /* 5717 */ 2284#define BGE_TXBDFLAG_HDRLEN_BIT7 0x4000 /* 5717 */ 2285#define BGE_TXBDFLAG_CHOOSE_SRC_ADDR 0x6000 2286#define BGE_TXBDFLAG_NO_CRC 0x8000 2287 2288#define BGE_TXBDFLAG_MSS_SIZE_MASK 0x3FFF /* 5717 */ 2289/* Bits [1:0] of the MSS header length. */ 2290#define BGE_TXBDFLAG_MSS_HDRLEN_MASK 0xC000 /* 5717 */ 2291 2292#define BGE_NIC_TXRING_ADDR(ringno, size) \ 2293 BGE_SEND_RING_1_TO_4 + \ 2294 ((ringno * sizeof(struct bge_tx_bd) * size) / 4) 2295 2296struct bge_rx_bd { 2297 bge_hostaddr bge_addr; 2298#if BYTE_ORDER == LITTLE_ENDIAN 2299 uint16_t bge_len; 2300 uint16_t bge_idx; 2301 uint16_t bge_flags; 2302 uint16_t bge_type; 2303 uint16_t bge_tcp_udp_csum; 2304 uint16_t bge_ip_csum; 2305 uint16_t bge_vlan_tag; 2306 uint16_t bge_error_flag; 2307#else 2308 uint16_t bge_idx; 2309 uint16_t bge_len; 2310 uint16_t bge_type; 2311 uint16_t bge_flags; 2312 uint16_t bge_ip_csum; 2313 uint16_t bge_tcp_udp_csum; 2314 uint16_t bge_error_flag; 2315 uint16_t bge_vlan_tag; 2316#endif 2317 uint32_t bge_rsvd; 2318 uint32_t bge_opaque; 2319}; 2320 2321struct bge_extrx_bd { 2322 bge_hostaddr bge_addr1; 2323 bge_hostaddr bge_addr2; 2324 bge_hostaddr bge_addr3; 2325#if BYTE_ORDER == LITTLE_ENDIAN 2326 uint16_t bge_len2; 2327 uint16_t bge_len1; 2328 uint16_t bge_rsvd1; 2329 uint16_t bge_len3; 2330#else 2331 uint16_t bge_len1; 2332 uint16_t bge_len2; 2333 uint16_t bge_len3; 2334 uint16_t bge_rsvd1; 2335#endif 2336 bge_hostaddr bge_addr0; 2337#if BYTE_ORDER == LITTLE_ENDIAN 2338 uint16_t bge_len0; 2339 uint16_t bge_idx; 2340 uint16_t bge_flags; 2341 uint16_t bge_type; 2342 uint16_t bge_tcp_udp_csum; 2343 uint16_t bge_ip_csum; 2344 uint16_t bge_vlan_tag; 2345 uint16_t bge_error_flag; 2346#else 2347 uint16_t bge_idx; 2348 uint16_t bge_len0; 2349 uint16_t bge_type; 2350 uint16_t bge_flags; 2351 uint16_t bge_ip_csum; 2352 uint16_t bge_tcp_udp_csum; 2353 uint16_t bge_error_flag; 2354 uint16_t bge_vlan_tag; 2355#endif 2356 uint32_t bge_rsvd0; 2357 uint32_t bge_opaque; 2358}; 2359 2360#define BGE_RXBDFLAG_END 0x0004 2361#define BGE_RXBDFLAG_JUMBO_RING 0x0020 2362#define BGE_RXBDFLAG_VLAN_TAG 0x0040 2363#define BGE_RXBDFLAG_ERROR 0x0400 2364#define BGE_RXBDFLAG_MINI_RING 0x0800 2365#define BGE_RXBDFLAG_IP_CSUM 0x1000 2366#define BGE_RXBDFLAG_TCP_UDP_CSUM 0x2000 2367#define BGE_RXBDFLAG_TCP_UDP_IS_TCP 0x4000 2368#define BGE_RXBDFLAG_IPV6 0x8000 2369 2370#define BGE_RXERRFLAG_BAD_CRC 0x0001 2371#define BGE_RXERRFLAG_COLL_DETECT 0x0002 2372#define BGE_RXERRFLAG_LINK_LOST 0x0004 2373#define BGE_RXERRFLAG_PHY_DECODE_ERR 0x0008 2374#define BGE_RXERRFLAG_MAC_ABORT 0x0010 2375#define BGE_RXERRFLAG_RUNT 0x0020 2376#define BGE_RXERRFLAG_TRUNC_NO_RSRCS 0x0040 2377#define BGE_RXERRFLAG_GIANT 0x0080 2378#define BGE_RXERRFLAG_IP_CSUM_NOK 0x1000 /* 5717 */ 2379 2380struct bge_sts_idx { 2381#if BYTE_ORDER == LITTLE_ENDIAN 2382 uint16_t bge_rx_prod_idx; 2383 uint16_t bge_tx_cons_idx; 2384#else 2385 uint16_t bge_tx_cons_idx; 2386 uint16_t bge_rx_prod_idx; 2387#endif 2388}; 2389 2390struct bge_status_block { 2391 uint32_t bge_status; 2392 uint32_t bge_status_tag; 2393#if BYTE_ORDER == LITTLE_ENDIAN 2394 uint16_t bge_rx_jumbo_cons_idx; 2395 uint16_t bge_rx_std_cons_idx; 2396 uint16_t bge_rx_mini_cons_idx; 2397 uint16_t bge_rsvd1; 2398#else 2399 uint16_t bge_rx_std_cons_idx; 2400 uint16_t bge_rx_jumbo_cons_idx; 2401 uint16_t bge_rsvd1; 2402 uint16_t bge_rx_mini_cons_idx; 2403#endif 2404 struct bge_sts_idx bge_idx[16]; 2405}; 2406 2407#define BGE_STATFLAG_UPDATED 0x00000001 2408#define BGE_STATFLAG_LINKSTATE_CHANGED 0x00000002 2409#define BGE_STATFLAG_ERROR 0x00000004 2410 2411 2412/* 2413 * Broadcom Vendor ID 2414 * (Note: the BCM570x still defaults to the Alteon PCI vendor ID 2415 * even though they're now manufactured by Broadcom) 2416 */ 2417#define BCOM_VENDORID 0x14E4 2418#define BCOM_DEVICEID_BCM5700 0x1644 2419#define BCOM_DEVICEID_BCM5701 0x1645 2420#define BCOM_DEVICEID_BCM5702 0x1646 2421#define BCOM_DEVICEID_BCM5702X 0x16A6 2422#define BCOM_DEVICEID_BCM5702_ALT 0x16C6 2423#define BCOM_DEVICEID_BCM5703 0x1647 2424#define BCOM_DEVICEID_BCM5703X 0x16A7 2425#define BCOM_DEVICEID_BCM5703_ALT 0x16C7 2426#define BCOM_DEVICEID_BCM5704C 0x1648 2427#define BCOM_DEVICEID_BCM5704S 0x16A8 2428#define BCOM_DEVICEID_BCM5704S_ALT 0x1649 2429#define BCOM_DEVICEID_BCM5705 0x1653 2430#define BCOM_DEVICEID_BCM5705K 0x1654 2431#define BCOM_DEVICEID_BCM5705F 0x166E 2432#define BCOM_DEVICEID_BCM5705M 0x165D 2433#define BCOM_DEVICEID_BCM5705M_ALT 0x165E 2434#define BCOM_DEVICEID_BCM5714C 0x1668 2435#define BCOM_DEVICEID_BCM5714S 0x1669 2436#define BCOM_DEVICEID_BCM5715 0x1678 2437#define BCOM_DEVICEID_BCM5715S 0x1679 2438#define BCOM_DEVICEID_BCM5717 0x1655 2439#define BCOM_DEVICEID_BCM5718 0x1656 2440#define BCOM_DEVICEID_BCM5719 0x1657 2441#define BCOM_DEVICEID_BCM5720_PP 0x1658 /* Not released to public. */ 2442#define BCOM_DEVICEID_BCM5720 0x165F 2443#define BCOM_DEVICEID_BCM5721 0x1659 2444#define BCOM_DEVICEID_BCM5722 0x165A 2445#define BCOM_DEVICEID_BCM5723 0x165B 2446#define BCOM_DEVICEID_BCM5750 0x1676 2447#define BCOM_DEVICEID_BCM5750M 0x167C 2448#define BCOM_DEVICEID_BCM5751 0x1677 2449#define BCOM_DEVICEID_BCM5751F 0x167E 2450#define BCOM_DEVICEID_BCM5751M 0x167D 2451#define BCOM_DEVICEID_BCM5752 0x1600 2452#define BCOM_DEVICEID_BCM5752M 0x1601 2453#define BCOM_DEVICEID_BCM5753 0x16F7 2454#define BCOM_DEVICEID_BCM5753F 0x16FE 2455#define BCOM_DEVICEID_BCM5753M 0x16FD 2456#define BCOM_DEVICEID_BCM5754 0x167A 2457#define BCOM_DEVICEID_BCM5754M 0x1672 2458#define BCOM_DEVICEID_BCM5755 0x167B 2459#define BCOM_DEVICEID_BCM5755M 0x1673 2460#define BCOM_DEVICEID_BCM5756 0x1674 2461#define BCOM_DEVICEID_BCM5761 0x1681 2462#define BCOM_DEVICEID_BCM5761E 0x1680 2463#define BCOM_DEVICEID_BCM5761S 0x1688 2464#define BCOM_DEVICEID_BCM5761SE 0x1689 2465#define BCOM_DEVICEID_BCM5764 0x1684 2466#define BCOM_DEVICEID_BCM5780 0x166A 2467#define BCOM_DEVICEID_BCM5780S 0x166B 2468#define BCOM_DEVICEID_BCM5781 0x16DD 2469#define BCOM_DEVICEID_BCM5782 0x1696 2470#define BCOM_DEVICEID_BCM5784 0x1698 2471#define BCOM_DEVICEID_BCM5785F 0x16a0 2472#define BCOM_DEVICEID_BCM5785G 0x1699 2473#define BCOM_DEVICEID_BCM5786 0x169A 2474#define BCOM_DEVICEID_BCM5787 0x169B 2475#define BCOM_DEVICEID_BCM5787M 0x1693 2476#define BCOM_DEVICEID_BCM5787F 0x167f 2477#define BCOM_DEVICEID_BCM5788 0x169C 2478#define BCOM_DEVICEID_BCM5789 0x169D 2479#define BCOM_DEVICEID_BCM5901 0x170D 2480#define BCOM_DEVICEID_BCM5901A2 0x170E 2481#define BCOM_DEVICEID_BCM5903M 0x16FF 2482#define BCOM_DEVICEID_BCM5906 0x1712 2483#define BCOM_DEVICEID_BCM5906M 0x1713 2484#define BCOM_DEVICEID_BCM57760 0x1690 2485#define BCOM_DEVICEID_BCM57761 0x16B0 2486#define BCOM_DEVICEID_BCM57765 0x16B4 2487#define BCOM_DEVICEID_BCM57780 0x1692 2488#define BCOM_DEVICEID_BCM57781 0x16B1 2489#define BCOM_DEVICEID_BCM57785 0x16B5 2490#define BCOM_DEVICEID_BCM57788 0x1691 2491#define BCOM_DEVICEID_BCM57790 0x1694 2492#define BCOM_DEVICEID_BCM57791 0x16B2 2493#define BCOM_DEVICEID_BCM57795 0x16B6 2494 2495/* 2496 * Alteon AceNIC PCI vendor/device ID. 2497 */ 2498#define ALTEON_VENDORID 0x12AE 2499#define ALTEON_DEVICEID_ACENIC 0x0001 2500#define ALTEON_DEVICEID_ACENIC_COPPER 0x0002 2501#define ALTEON_DEVICEID_BCM5700 0x0003 2502#define ALTEON_DEVICEID_BCM5701 0x0004 2503 2504/* 2505 * 3Com 3c996 PCI vendor/device ID. 2506 */ 2507#define TC_VENDORID 0x10B7 2508#define TC_DEVICEID_3C996 0x0003 2509 2510/* 2511 * SysKonnect PCI vendor ID 2512 */ 2513#define SK_VENDORID 0x1148 2514#define SK_DEVICEID_ALTIMA 0x4400 2515#define SK_SUBSYSID_9D21 0x4421 2516#define SK_SUBSYSID_9D41 0x4441 2517 2518/* 2519 * Altima PCI vendor/device ID. 2520 */ 2521#define ALTIMA_VENDORID 0x173b 2522#define ALTIMA_DEVICE_AC1000 0x03e8 2523#define ALTIMA_DEVICE_AC1002 0x03e9 2524#define ALTIMA_DEVICE_AC9100 0x03ea 2525 2526/* 2527 * Dell PCI vendor ID 2528 */ 2529 2530#define DELL_VENDORID 0x1028 2531 2532/* 2533 * Apple PCI vendor ID. 2534 */ 2535#define APPLE_VENDORID 0x106b 2536#define APPLE_DEVICE_BCM5701 0x1645 2537 2538/* 2539 * Sun PCI vendor ID 2540 */ 2541#define SUN_VENDORID 0x108e 2542 2543/* 2544 * Fujitsu vendor/device IDs 2545 */ 2546#define FJTSU_VENDORID 0x10cf 2547#define FJTSU_DEVICEID_PW008GE5 0x11a1 2548#define FJTSU_DEVICEID_PW008GE4 0x11a2 2549#define FJTSU_DEVICEID_PP250450 0x11cc /* PRIMEPOWER250/450 LAN */ 2550 2551/* 2552 * Offset of MAC address inside EEPROM. 2553 */ 2554#define BGE_EE_MAC_OFFSET 0x7C 2555#define BGE_EE_MAC_OFFSET_5906 0x10 2556#define BGE_EE_HWCFG_OFFSET 0xC8 2557 2558#define BGE_HWCFG_VOLTAGE 0x00000003 2559#define BGE_HWCFG_PHYLED_MODE 0x0000000C 2560#define BGE_HWCFG_MEDIA 0x00000030 2561#define BGE_HWCFG_ASF 0x00000080 2562 2563#define BGE_VOLTAGE_1POINT3 0x00000000 2564#define BGE_VOLTAGE_1POINT8 0x00000001 2565 2566#define BGE_PHYLEDMODE_UNSPEC 0x00000000 2567#define BGE_PHYLEDMODE_TRIPLELED 0x00000004 2568#define BGE_PHYLEDMODE_SINGLELED 0x00000008 2569 2570#define BGE_MEDIA_UNSPEC 0x00000000 2571#define BGE_MEDIA_COPPER 0x00000010 2572#define BGE_MEDIA_FIBER 0x00000020 2573 2574#define BGE_TICKS_PER_SEC 1000000 2575 2576/* 2577 * Ring size constants. 2578 */ 2579#define BGE_EVENT_RING_CNT 256 2580#define BGE_CMD_RING_CNT 64 2581#define BGE_STD_RX_RING_CNT 512 2582#define BGE_JUMBO_RX_RING_CNT 256 2583#define BGE_MINI_RX_RING_CNT 1024 2584#define BGE_RETURN_RING_CNT 1024 2585 2586/* 5705 has smaller return ring size */ 2587 2588#define BGE_RETURN_RING_CNT_5705 512 2589 2590/* 2591 * Possible TX ring sizes. 2592 */ 2593#define BGE_TX_RING_CNT_128 128 2594#define BGE_TX_RING_BASE_128 0x3800 2595 2596#define BGE_TX_RING_CNT_256 256 2597#define BGE_TX_RING_BASE_256 0x3000 2598 2599#define BGE_TX_RING_CNT_512 512 2600#define BGE_TX_RING_BASE_512 0x2000 2601 2602#define BGE_TX_RING_CNT BGE_TX_RING_CNT_512 2603#define BGE_TX_RING_BASE BGE_TX_RING_BASE_512 2604 2605/* 2606 * Tigon III statistics counters. 2607 */ 2608/* Statistics maintained MAC Receive block. */ 2609struct bge_rx_mac_stats { 2610 bge_hostaddr ifHCInOctets; 2611 bge_hostaddr Reserved1; 2612 bge_hostaddr etherStatsFragments; 2613 bge_hostaddr ifHCInUcastPkts; 2614 bge_hostaddr ifHCInMulticastPkts; 2615 bge_hostaddr ifHCInBroadcastPkts; 2616 bge_hostaddr dot3StatsFCSErrors; 2617 bge_hostaddr dot3StatsAlignmentErrors; 2618 bge_hostaddr xonPauseFramesReceived; 2619 bge_hostaddr xoffPauseFramesReceived; 2620 bge_hostaddr macControlFramesReceived; 2621 bge_hostaddr xoffStateEntered; 2622 bge_hostaddr dot3StatsFramesTooLong; 2623 bge_hostaddr etherStatsJabbers; 2624 bge_hostaddr etherStatsUndersizePkts; 2625 bge_hostaddr inRangeLengthError; 2626 bge_hostaddr outRangeLengthError; 2627 bge_hostaddr etherStatsPkts64Octets; 2628 bge_hostaddr etherStatsPkts65Octetsto127Octets; 2629 bge_hostaddr etherStatsPkts128Octetsto255Octets; 2630 bge_hostaddr etherStatsPkts256Octetsto511Octets; 2631 bge_hostaddr etherStatsPkts512Octetsto1023Octets; 2632 bge_hostaddr etherStatsPkts1024Octetsto1522Octets; 2633 bge_hostaddr etherStatsPkts1523Octetsto2047Octets; 2634 bge_hostaddr etherStatsPkts2048Octetsto4095Octets; 2635 bge_hostaddr etherStatsPkts4096Octetsto8191Octets; 2636 bge_hostaddr etherStatsPkts8192Octetsto9022Octets; 2637}; 2638 2639 2640/* Statistics maintained MAC Transmit block. */ 2641struct bge_tx_mac_stats { 2642 bge_hostaddr ifHCOutOctets; 2643 bge_hostaddr Reserved2; 2644 bge_hostaddr etherStatsCollisions; 2645 bge_hostaddr outXonSent; 2646 bge_hostaddr outXoffSent; 2647 bge_hostaddr flowControlDone; 2648 bge_hostaddr dot3StatsInternalMacTransmitErrors; 2649 bge_hostaddr dot3StatsSingleCollisionFrames; 2650 bge_hostaddr dot3StatsMultipleCollisionFrames; 2651 bge_hostaddr dot3StatsDeferredTransmissions; 2652 bge_hostaddr Reserved3; 2653 bge_hostaddr dot3StatsExcessiveCollisions; 2654 bge_hostaddr dot3StatsLateCollisions; 2655 bge_hostaddr dot3Collided2Times; 2656 bge_hostaddr dot3Collided3Times; 2657 bge_hostaddr dot3Collided4Times; 2658 bge_hostaddr dot3Collided5Times; 2659 bge_hostaddr dot3Collided6Times; 2660 bge_hostaddr dot3Collided7Times; 2661 bge_hostaddr dot3Collided8Times; 2662 bge_hostaddr dot3Collided9Times; 2663 bge_hostaddr dot3Collided10Times; 2664 bge_hostaddr dot3Collided11Times; 2665 bge_hostaddr dot3Collided12Times; 2666 bge_hostaddr dot3Collided13Times; 2667 bge_hostaddr dot3Collided14Times; 2668 bge_hostaddr dot3Collided15Times; 2669 bge_hostaddr ifHCOutUcastPkts; 2670 bge_hostaddr ifHCOutMulticastPkts; 2671 bge_hostaddr ifHCOutBroadcastPkts; 2672 bge_hostaddr dot3StatsCarrierSenseErrors; 2673 bge_hostaddr ifOutDiscards; 2674 bge_hostaddr ifOutErrors; 2675}; 2676 2677/* Stats counters access through registers */ 2678struct bge_mac_stats { 2679 /* TX MAC statistics */ 2680 uint64_t ifHCOutOctets; 2681 uint64_t Reserved0; 2682 uint64_t etherStatsCollisions; 2683 uint64_t outXonSent; 2684 uint64_t outXoffSent; 2685 uint64_t Reserved1; 2686 uint64_t dot3StatsInternalMacTransmitErrors; 2687 uint64_t dot3StatsSingleCollisionFrames; 2688 uint64_t dot3StatsMultipleCollisionFrames; 2689 uint64_t dot3StatsDeferredTransmissions; 2690 uint64_t Reserved2; 2691 uint64_t dot3StatsExcessiveCollisions; 2692 uint64_t dot3StatsLateCollisions; 2693 uint64_t Reserved3[14]; 2694 uint64_t ifHCOutUcastPkts; 2695 uint64_t ifHCOutMulticastPkts; 2696 uint64_t ifHCOutBroadcastPkts; 2697 uint64_t Reserved4[2]; 2698 /* RX MAC statistics */ 2699 uint64_t ifHCInOctets; 2700 uint64_t Reserved5; 2701 uint64_t etherStatsFragments; 2702 uint64_t ifHCInUcastPkts; 2703 uint64_t ifHCInMulticastPkts; 2704 uint64_t ifHCInBroadcastPkts; 2705 uint64_t dot3StatsFCSErrors; 2706 uint64_t dot3StatsAlignmentErrors; 2707 uint64_t xonPauseFramesReceived; 2708 uint64_t xoffPauseFramesReceived; 2709 uint64_t macControlFramesReceived; 2710 uint64_t xoffStateEntered; 2711 uint64_t dot3StatsFramesTooLong; 2712 uint64_t etherStatsJabbers; 2713 uint64_t etherStatsUndersizePkts; 2714 /* Receive List Placement control */ 2715 uint64_t FramesDroppedDueToFilters; 2716 uint64_t DmaWriteQueueFull; 2717 uint64_t DmaWriteHighPriQueueFull; 2718 uint64_t NoMoreRxBDs; 2719 uint64_t InputDiscards; 2720 uint64_t InputErrors; 2721 uint64_t RecvThresholdHit; 2722}; 2723 2724struct bge_stats { 2725 uint8_t Reserved0[256]; 2726 2727 /* Statistics maintained by Receive MAC. */ 2728 struct bge_rx_mac_stats rxstats; 2729 2730 bge_hostaddr Unused1[37]; 2731 2732 /* Statistics maintained by Transmit MAC. */ 2733 struct bge_tx_mac_stats txstats; 2734 2735 bge_hostaddr Unused2[31]; 2736 2737 /* Statistics maintained by Receive List Placement. */ 2738 bge_hostaddr COSIfHCInPkts[16]; 2739 bge_hostaddr COSFramesDroppedDueToFilters; 2740 bge_hostaddr nicDmaWriteQueueFull; 2741 bge_hostaddr nicDmaWriteHighPriQueueFull; 2742 bge_hostaddr nicNoMoreRxBDs; 2743 bge_hostaddr ifInDiscards; 2744 bge_hostaddr ifInErrors; 2745 bge_hostaddr nicRecvThresholdHit; 2746 2747 bge_hostaddr Unused3[9]; 2748 2749 /* Statistics maintained by Send Data Initiator. */ 2750 bge_hostaddr COSIfHCOutPkts[16]; 2751 bge_hostaddr nicDmaReadQueueFull; 2752 bge_hostaddr nicDmaReadHighPriQueueFull; 2753 bge_hostaddr nicSendDataCompQueueFull; 2754 2755 /* Statistics maintained by Host Coalescing. */ 2756 bge_hostaddr nicRingSetSendProdIndex; 2757 bge_hostaddr nicRingStatusUpdate; 2758 bge_hostaddr nicInterrupts; 2759 bge_hostaddr nicAvoidedInterrupts; 2760 bge_hostaddr nicSendThresholdHit; 2761 2762 uint8_t Reserved4[320]; 2763}; 2764 2765/* 2766 * Tigon general information block. This resides in host memory 2767 * and contains the status counters, ring control blocks and 2768 * producer pointers. 2769 */ 2770 2771struct bge_gib { 2772 struct bge_stats bge_stats; 2773 struct bge_rcb bge_tx_rcb[16]; 2774 struct bge_rcb bge_std_rx_rcb; 2775 struct bge_rcb bge_jumbo_rx_rcb; 2776 struct bge_rcb bge_mini_rx_rcb; 2777 struct bge_rcb bge_return_rcb; 2778}; 2779 2780#define BGE_FRAMELEN 1518 2781#define BGE_MAX_FRAMELEN 1536 2782#define BGE_JUMBO_FRAMELEN 9018 2783#define BGE_JUMBO_MTU (BGE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 2784#define BGE_MIN_FRAMELEN 60 2785 2786/* 2787 * Other utility macros. 2788 */ 2789#define BGE_INC(x, y) (x) = (x + 1) % y 2790 2791/* 2792 * BAR0 MAC register access macros. The Tigon always uses memory mapped register 2793 * accesses and all registers must be accessed with 32 bit operations. 2794 */ 2795 2796#define CSR_WRITE_4(sc, reg, val) \ 2797 bus_write_4(sc->bge_res, reg, val) 2798 2799#define CSR_READ_4(sc, reg) \ 2800 bus_read_4(sc->bge_res, reg) 2801 2802#define BGE_SETBIT(sc, reg, x) \ 2803 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | (x))) 2804#define BGE_CLRBIT(sc, reg, x) \ 2805 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~(x))) 2806 2807/* BAR2 APE register access macros. */ 2808#define APE_WRITE_4(sc, reg, val) \ 2809 bus_write_4(sc->bge_res2, reg, val) 2810 2811#define APE_READ_4(sc, reg) \ 2812 bus_read_4(sc->bge_res2, reg) 2813 2814#define APE_SETBIT(sc, reg, x) \ 2815 APE_WRITE_4(sc, reg, (APE_READ_4(sc, reg) | (x))) 2816#define APE_CLRBIT(sc, reg, x) \ 2817 APE_WRITE_4(sc, reg, (APE_READ_4(sc, reg) & ~(x))) 2818 2819#define PCI_SETBIT(dev, reg, x, s) \ 2820 pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | (x)), s) 2821#define PCI_CLRBIT(dev, reg, x, s) \ 2822 pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~(x)), s) 2823 2824/* 2825 * Memory management stuff. 2826 */ 2827 2828#define BGE_NSEG_JUMBO 4 2829#define BGE_NSEG_NEW 32 2830#define BGE_TSOSEG_SZ 4096 2831 2832/* Maximum DMA address for controllers that have 40bit DMA address bug. */ 2833#if (BUS_SPACE_MAXADDR < 0xFFFFFFFFFF) 2834#define BGE_DMA_MAXADDR BUS_SPACE_MAXADDR 2835#else 2836#define BGE_DMA_MAXADDR 0xFFFFFFFFFF 2837#endif 2838 2839/* 2840 * Ring structures. Most of these reside in host memory and we tell 2841 * the NIC where they are via the ring control blocks. The exceptions 2842 * are the tx and command rings, which live in NIC memory and which 2843 * we access via the shared memory window. 2844 */ 2845 2846struct bge_ring_data { 2847 struct bge_rx_bd *bge_rx_std_ring; 2848 bus_addr_t bge_rx_std_ring_paddr; 2849 struct bge_extrx_bd *bge_rx_jumbo_ring; 2850 bus_addr_t bge_rx_jumbo_ring_paddr; 2851 struct bge_rx_bd *bge_rx_return_ring; 2852 bus_addr_t bge_rx_return_ring_paddr; 2853 struct bge_tx_bd *bge_tx_ring; 2854 bus_addr_t bge_tx_ring_paddr; 2855 struct bge_status_block *bge_status_block; 2856 bus_addr_t bge_status_block_paddr; 2857 struct bge_stats *bge_stats; 2858 bus_addr_t bge_stats_paddr; 2859 struct bge_gib bge_info; 2860}; 2861 2862#define BGE_STD_RX_RING_SZ \ 2863 (sizeof(struct bge_rx_bd) * BGE_STD_RX_RING_CNT) 2864#define BGE_JUMBO_RX_RING_SZ \ 2865 (sizeof(struct bge_extrx_bd) * BGE_JUMBO_RX_RING_CNT) 2866#define BGE_TX_RING_SZ \ 2867 (sizeof(struct bge_tx_bd) * BGE_TX_RING_CNT) 2868#define BGE_RX_RTN_RING_SZ(x) \ 2869 (sizeof(struct bge_rx_bd) * x->bge_return_ring_cnt) 2870 2871#define BGE_STATUS_BLK_SZ sizeof (struct bge_status_block) 2872 2873#define BGE_STATS_SZ sizeof (struct bge_stats) 2874 2875/* 2876 * Mbuf pointers. We need these to keep track of the virtual addresses 2877 * of our mbuf chains since we can only convert from physical to virtual, 2878 * not the other way around. 2879 */ 2880struct bge_chain_data { 2881 bus_dma_tag_t bge_parent_tag; 2882 bus_dma_tag_t bge_buffer_tag; 2883 bus_dma_tag_t bge_rx_std_ring_tag; 2884 bus_dma_tag_t bge_rx_jumbo_ring_tag; 2885 bus_dma_tag_t bge_rx_return_ring_tag; 2886 bus_dma_tag_t bge_tx_ring_tag; 2887 bus_dma_tag_t bge_status_tag; 2888 bus_dma_tag_t bge_stats_tag; 2889 bus_dma_tag_t bge_rx_mtag; /* Rx mbuf mapping tag */ 2890 bus_dma_tag_t bge_tx_mtag; /* Tx mbuf mapping tag */ 2891 bus_dma_tag_t bge_mtag_jumbo; /* Jumbo mbuf mapping tag */ 2892 bus_dmamap_t bge_tx_dmamap[BGE_TX_RING_CNT]; 2893 bus_dmamap_t bge_rx_std_sparemap; 2894 bus_dmamap_t bge_rx_std_dmamap[BGE_STD_RX_RING_CNT]; 2895 bus_dmamap_t bge_rx_jumbo_sparemap; 2896 bus_dmamap_t bge_rx_jumbo_dmamap[BGE_JUMBO_RX_RING_CNT]; 2897 bus_dmamap_t bge_rx_std_ring_map; 2898 bus_dmamap_t bge_rx_jumbo_ring_map; 2899 bus_dmamap_t bge_tx_ring_map; 2900 bus_dmamap_t bge_rx_return_ring_map; 2901 bus_dmamap_t bge_status_map; 2902 bus_dmamap_t bge_stats_map; 2903 struct mbuf *bge_tx_chain[BGE_TX_RING_CNT]; 2904 struct mbuf *bge_rx_std_chain[BGE_STD_RX_RING_CNT]; 2905 struct mbuf *bge_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT]; 2906 int bge_rx_std_seglen[BGE_STD_RX_RING_CNT]; 2907 int bge_rx_jumbo_seglen[BGE_JUMBO_RX_RING_CNT][4]; 2908}; 2909 2910struct bge_dmamap_arg { 2911 bus_addr_t bge_busaddr; 2912}; 2913 2914#define BGE_HWREV_TIGON 0x01 2915#define BGE_HWREV_TIGON_II 0x02 2916#define BGE_TIMEOUT 100000 2917#define BGE_TXCONS_UNSET 0xFFFF /* impossible value */ 2918 2919struct bge_bcom_hack { 2920 int reg; 2921 int val; 2922}; 2923 2924#define ASF_ENABLE 1 2925#define ASF_NEW_HANDSHAKE 2 2926#define ASF_STACKUP 4 2927 2928struct bge_softc { 2929 struct ifnet *bge_ifp; /* interface info */ 2930 device_t bge_dev; 2931 struct mtx bge_mtx; 2932 device_t bge_miibus; 2933 void *bge_intrhand; 2934 struct resource *bge_irq; 2935 struct resource *bge_res; /* MAC mapped I/O */ 2936 struct resource *bge_res2; /* APE mapped I/O */ 2937 struct ifmedia bge_ifmedia; /* TBI media info */ 2938 int bge_expcap; 2939 int bge_expmrq; 2940 int bge_msicap; 2941 int bge_pcixcap; 2942 uint32_t bge_flags; 2943#define BGE_FLAG_TBI 0x00000001 2944#define BGE_FLAG_JUMBO 0x00000002 2945#define BGE_FLAG_JUMBO_STD 0x00000004 2946#define BGE_FLAG_EADDR 0x00000008 2947#define BGE_FLAG_MII_SERDES 0x00000010 2948#define BGE_FLAG_CPMU_PRESENT 0x00000020 2949#define BGE_FLAG_TAGGED_STATUS 0x00000040 2950#define BGE_FLAG_APE 0x00000080 2951#define BGE_FLAG_MSI 0x00000100 2952#define BGE_FLAG_PCIX 0x00000200 2953#define BGE_FLAG_PCIE 0x00000400 2954#define BGE_FLAG_TSO 0x00000800 2955#define BGE_FLAG_TSO3 0x00001000 2956#define BGE_FLAG_JUMBO_FRAME 0x00002000 2957#define BGE_FLAG_5700_FAMILY 0x00010000 2958#define BGE_FLAG_5705_PLUS 0x00020000 2959#define BGE_FLAG_5714_FAMILY 0x00040000 2960#define BGE_FLAG_575X_PLUS 0x00080000 2961#define BGE_FLAG_5755_PLUS 0x00100000 2962#define BGE_FLAG_5788 0x00200000 2963#define BGE_FLAG_5717_PLUS 0x00400000 2964#define BGE_FLAG_40BIT_BUG 0x01000000 2965#define BGE_FLAG_4G_BNDRY_BUG 0x02000000 2966#define BGE_FLAG_RX_ALIGNBUG 0x04000000 2967#define BGE_FLAG_SHORT_DMA_BUG 0x08000000 2968#define BGE_FLAG_4K_RDMA_BUG 0x10000000 2969#define BGE_FLAG_MBOX_REORDER 0x20000000 2970 uint32_t bge_mfw_flags; /* Management F/W flags */ 2971#define BGE_MFW_ON_RXCPU 0x00000001 2972#define BGE_MFW_ON_APE 0x00000002 2973#define BGE_MFW_TYPE_NCSI 0x00000004 2974#define BGE_MFW_TYPE_DASH 0x00000008 2975 int bge_phy_ape_lock; 2976 int bge_func_addr; 2977 int bge_phy_addr; 2978 uint32_t bge_phy_flags; 2979#define BGE_PHY_NO_WIRESPEED 0x00000001 2980#define BGE_PHY_ADC_BUG 0x00000002 2981#define BGE_PHY_5704_A0_BUG 0x00000004 2982#define BGE_PHY_JITTER_BUG 0x00000008 2983#define BGE_PHY_BER_BUG 0x00000010 2984#define BGE_PHY_ADJUST_TRIM 0x00000020 2985#define BGE_PHY_CRC_BUG 0x00000040 2986#define BGE_PHY_NO_3LED 0x00000080 2987 uint32_t bge_chipid; 2988 uint32_t bge_asicrev; 2989 uint32_t bge_chiprev; 2990 uint8_t bge_asf_mode; 2991 uint8_t bge_asf_count; 2992 uint16_t bge_mps; 2993 struct bge_ring_data bge_ldata; /* rings */ 2994 struct bge_chain_data bge_cdata; /* mbufs */ 2995 uint16_t bge_tx_saved_considx; 2996 uint16_t bge_rx_saved_considx; 2997 uint16_t bge_ev_saved_considx; 2998 uint16_t bge_return_ring_cnt; 2999 uint16_t bge_std; /* current std ring head */ 3000 uint16_t bge_jumbo; /* current jumo ring head */ 3001 uint32_t bge_stat_ticks; 3002 uint32_t bge_rx_coal_ticks; 3003 uint32_t bge_tx_coal_ticks; 3004 uint32_t bge_tx_prodidx; 3005 uint32_t bge_rx_max_coal_bds; 3006 uint32_t bge_tx_max_coal_bds; 3007 uint32_t bge_mi_mode; 3008 int bge_if_flags; 3009 int bge_txcnt; 3010 int bge_link; /* link state */ 3011 int bge_link_evt; /* pending link event */ 3012 int bge_timer; 3013 int bge_forced_collapse; 3014 int bge_forced_udpcsum; 3015 int bge_msi; 3016 int bge_csum_features; 3017 struct callout bge_stat_ch; 3018 uint32_t bge_rx_discards; 3019 uint32_t bge_rx_inerrs; 3020 uint32_t bge_rx_nobds; 3021 uint32_t bge_tx_discards; 3022 uint32_t bge_tx_collisions; 3023#ifdef DEVICE_POLLING 3024 int rxcycles; 3025#endif /* DEVICE_POLLING */ 3026 struct bge_mac_stats bge_mac_stats; 3027 struct task bge_intr_task; 3028 struct taskqueue *bge_tq; 3029}; 3030 3031#define BGE_LOCK_INIT(_sc, _name) \ 3032 mtx_init(&(_sc)->bge_mtx, _name, MTX_NETWORK_LOCK, MTX_DEF) 3033#define BGE_LOCK(_sc) mtx_lock(&(_sc)->bge_mtx) 3034#define BGE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->bge_mtx, MA_OWNED) 3035#define BGE_UNLOCK(_sc) mtx_unlock(&(_sc)->bge_mtx) 3036#define BGE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->bge_mtx) 3037