if_bgereg.h revision 161546
1/*- 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2001 4 * Bill Paul <wpaul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD: head/sys/dev/bge/if_bgereg.h 161546 2006-08-23 11:32:54Z glebius $ 34 */ 35 36/* 37 * BCM570x memory map. The internal memory layout varies somewhat 38 * depending on whether or not we have external SSRAM attached. 39 * The BCM5700 can have up to 16MB of external memory. The BCM5701 40 * is apparently not designed to use external SSRAM. The mappings 41 * up to the first 4 send rings are the same for both internal and 42 * external memory configurations. Note that mini RX ring space is 43 * only available with external SSRAM configurations, which means 44 * the mini RX ring is not supported on the BCM5701. 45 * 46 * The NIC's memory can be accessed by the host in one of 3 ways: 47 * 48 * 1) Indirect register access. The MEMWIN_BASEADDR and MEMWIN_DATA 49 * registers in PCI config space can be used to read any 32-bit 50 * address within the NIC's memory. 51 * 52 * 2) Memory window access. The MEMWIN_BASEADDR register in PCI config 53 * space can be used in conjunction with the memory window in the 54 * device register space at offset 0x8000 to read any 32K chunk 55 * of NIC memory. 56 * 57 * 3) Flat mode. If the 'flat mode' bit in the PCI state register is 58 * set, the device I/O mapping consumes 32MB of host address space, 59 * allowing all of the registers and internal NIC memory to be 60 * accessed directly. NIC memory addresses are offset by 0x01000000. 61 * Flat mode consumes so much host address space that it is not 62 * recommended. 63 */ 64#define BGE_PAGE_ZERO 0x00000000 65#define BGE_PAGE_ZERO_END 0x000000FF 66#define BGE_SEND_RING_RCB 0x00000100 67#define BGE_SEND_RING_RCB_END 0x000001FF 68#define BGE_RX_RETURN_RING_RCB 0x00000200 69#define BGE_RX_RETURN_RING_RCB_END 0x000002FF 70#define BGE_STATS_BLOCK 0x00000300 71#define BGE_STATS_BLOCK_END 0x00000AFF 72#define BGE_STATUS_BLOCK 0x00000B00 73#define BGE_STATUS_BLOCK_END 0x00000B4F 74#define BGE_SOFTWARE_GENCOMM 0x00000B50 75#define BGE_SOFTWARE_GENCOMM_SIG 0x00000B54 76#define BGE_SOFTWARE_GENCOMM_NICCFG 0x00000B58 77#define BGE_SOFTWARE_GENCOMM_END 0x00000FFF 78#define BGE_UNMAPPED 0x00001000 79#define BGE_UNMAPPED_END 0x00001FFF 80#define BGE_DMA_DESCRIPTORS 0x00002000 81#define BGE_DMA_DESCRIPTORS_END 0x00003FFF 82#define BGE_SEND_RING_1_TO_4 0x00004000 83#define BGE_SEND_RING_1_TO_4_END 0x00005FFF 84 85/* Mappings for internal memory configuration */ 86#define BGE_STD_RX_RINGS 0x00006000 87#define BGE_STD_RX_RINGS_END 0x00006FFF 88#define BGE_JUMBO_RX_RINGS 0x00007000 89#define BGE_JUMBO_RX_RINGS_END 0x00007FFF 90#define BGE_BUFFPOOL_1 0x00008000 91#define BGE_BUFFPOOL_1_END 0x0000FFFF 92#define BGE_BUFFPOOL_2 0x00010000 /* or expansion ROM */ 93#define BGE_BUFFPOOL_2_END 0x00017FFF 94#define BGE_BUFFPOOL_3 0x00018000 /* or expansion ROM */ 95#define BGE_BUFFPOOL_3_END 0x0001FFFF 96 97/* Mappings for external SSRAM configurations */ 98#define BGE_SEND_RING_5_TO_6 0x00006000 99#define BGE_SEND_RING_5_TO_6_END 0x00006FFF 100#define BGE_SEND_RING_7_TO_8 0x00007000 101#define BGE_SEND_RING_7_TO_8_END 0x00007FFF 102#define BGE_SEND_RING_9_TO_16 0x00008000 103#define BGE_SEND_RING_9_TO_16_END 0x0000BFFF 104#define BGE_EXT_STD_RX_RINGS 0x0000C000 105#define BGE_EXT_STD_RX_RINGS_END 0x0000CFFF 106#define BGE_EXT_JUMBO_RX_RINGS 0x0000D000 107#define BGE_EXT_JUMBO_RX_RINGS_END 0x0000DFFF 108#define BGE_MINI_RX_RINGS 0x0000E000 109#define BGE_MINI_RX_RINGS_END 0x0000FFFF 110#define BGE_AVAIL_REGION1 0x00010000 /* or expansion ROM */ 111#define BGE_AVAIL_REGION1_END 0x00017FFF 112#define BGE_AVAIL_REGION2 0x00018000 /* or expansion ROM */ 113#define BGE_AVAIL_REGION2_END 0x0001FFFF 114#define BGE_EXT_SSRAM 0x00020000 115#define BGE_EXT_SSRAM_END 0x000FFFFF 116 117 118/* 119 * BCM570x register offsets. These are memory mapped registers 120 * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. 121 * Each register must be accessed using 32 bit operations. 122 * 123 * All registers are accessed through a 32K shared memory block. 124 * The first group of registers are actually copies of the PCI 125 * configuration space registers. 126 */ 127 128/* 129 * PCI registers defined in the PCI 2.2 spec. 130 */ 131#define BGE_PCI_VID 0x00 132#define BGE_PCI_DID 0x02 133#define BGE_PCI_CMD 0x04 134#define BGE_PCI_STS 0x06 135#define BGE_PCI_REV 0x08 136#define BGE_PCI_CLASS 0x09 137#define BGE_PCI_CACHESZ 0x0C 138#define BGE_PCI_LATTIMER 0x0D 139#define BGE_PCI_HDRTYPE 0x0E 140#define BGE_PCI_BIST 0x0F 141#define BGE_PCI_BAR0 0x10 142#define BGE_PCI_BAR1 0x14 143#define BGE_PCI_SUBSYS 0x2C 144#define BGE_PCI_SUBVID 0x2E 145#define BGE_PCI_ROMBASE 0x30 146#define BGE_PCI_CAPPTR 0x34 147#define BGE_PCI_INTLINE 0x3C 148#define BGE_PCI_INTPIN 0x3D 149#define BGE_PCI_MINGNT 0x3E 150#define BGE_PCI_MAXLAT 0x3F 151#define BGE_PCI_PCIXCAP 0x40 152#define BGE_PCI_NEXTPTR_PM 0x41 153#define BGE_PCI_PCIX_CMD 0x42 154#define BGE_PCI_PCIX_STS 0x44 155#define BGE_PCI_PWRMGMT_CAPID 0x48 156#define BGE_PCI_NEXTPTR_VPD 0x49 157#define BGE_PCI_PWRMGMT_CAPS 0x4A 158#define BGE_PCI_PWRMGMT_CMD 0x4C 159#define BGE_PCI_PWRMGMT_STS 0x4D 160#define BGE_PCI_PWRMGMT_DATA 0x4F 161#define BGE_PCI_VPD_CAPID 0x50 162#define BGE_PCI_NEXTPTR_MSI 0x51 163#define BGE_PCI_VPD_ADDR 0x52 164#define BGE_PCI_VPD_DATA 0x54 165#define BGE_PCI_MSI_CAPID 0x58 166#define BGE_PCI_NEXTPTR_NONE 0x59 167#define BGE_PCI_MSI_CTL 0x5A 168#define BGE_PCI_MSI_ADDR_HI 0x5C 169#define BGE_PCI_MSI_ADDR_LO 0x60 170#define BGE_PCI_MSI_DATA 0x64 171 172/* PCI MSI. ??? */ 173#define BGE_PCIE_CAPID_REG 0xD0 174#define BGE_PCIE_CAPID 0x10 175 176/* 177 * PCI registers specific to the BCM570x family. 178 */ 179#define BGE_PCI_MISC_CTL 0x68 180#define BGE_PCI_DMA_RW_CTL 0x6C 181#define BGE_PCI_PCISTATE 0x70 182#define BGE_PCI_CLKCTL 0x74 183#define BGE_PCI_REG_BASEADDR 0x78 184#define BGE_PCI_MEMWIN_BASEADDR 0x7C 185#define BGE_PCI_REG_DATA 0x80 186#define BGE_PCI_MEMWIN_DATA 0x84 187#define BGE_PCI_MODECTL 0x88 188#define BGE_PCI_MISC_CFG 0x8C 189#define BGE_PCI_MISC_LOCALCTL 0x90 190#define BGE_PCI_UNDI_RX_STD_PRODIDX_HI 0x98 191#define BGE_PCI_UNDI_RX_STD_PRODIDX_LO 0x9C 192#define BGE_PCI_UNDI_RX_RTN_CONSIDX_HI 0xA0 193#define BGE_PCI_UNDI_RX_RTN_CONSIDX_LO 0xA4 194#define BGE_PCI_UNDI_TX_BD_PRODIDX_HI 0xA8 195#define BGE_PCI_UNDI_TX_BD_PRODIDX_LO 0xAC 196#define BGE_PCI_ISR_MBX_HI 0xB0 197#define BGE_PCI_ISR_MBX_LO 0xB4 198 199/* PCI Misc. Host control register */ 200#define BGE_PCIMISCCTL_CLEAR_INTA 0x00000001 201#define BGE_PCIMISCCTL_MASK_PCI_INTR 0x00000002 202#define BGE_PCIMISCCTL_ENDIAN_BYTESWAP 0x00000004 203#define BGE_PCIMISCCTL_ENDIAN_WORDSWAP 0x00000008 204#define BGE_PCIMISCCTL_PCISTATE_RW 0x00000010 205#define BGE_PCIMISCCTL_CLOCKCTL_RW 0x00000020 206#define BGE_PCIMISCCTL_REG_WORDSWAP 0x00000040 207#define BGE_PCIMISCCTL_INDIRECT_ACCESS 0x00000080 208#define BGE_PCIMISCCTL_ASICREV 0xFFFF0000 209 210#define BGE_HIF_SWAP_OPTIONS (BGE_PCIMISCCTL_ENDIAN_WORDSWAP) 211#if BYTE_ORDER == LITTLE_ENDIAN 212#define BGE_DMA_SWAP_OPTIONS \ 213 BGE_MODECTL_WORDSWAP_NONFRAME| \ 214 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA 215#else 216#define BGE_DMA_SWAP_OPTIONS \ 217 BGE_MODECTL_WORDSWAP_NONFRAME|BGE_MODECTL_BYTESWAP_NONFRAME| \ 218 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA 219#endif 220 221#define BGE_INIT \ 222 (BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_CLEAR_INTA| \ 223 BGE_PCIMISCCTL_MASK_PCI_INTR|BGE_PCIMISCCTL_INDIRECT_ACCESS) 224 225#define BGE_CHIPID_TIGON_I 0x40000000 226#define BGE_CHIPID_TIGON_II 0x60000000 227#define BGE_CHIPID_BCM5700_A0 0x70000000 228#define BGE_CHIPID_BCM5700_A1 0x70010000 229#define BGE_CHIPID_BCM5700_B0 0x71000000 230#define BGE_CHIPID_BCM5700_B1 0x71010000 231#define BGE_CHIPID_BCM5700_B2 0x71020000 232#define BGE_CHIPID_BCM5700_B3 0x71030000 233#define BGE_CHIPID_BCM5700_ALTIMA 0x71040000 234#define BGE_CHIPID_BCM5700_C0 0x72000000 235#define BGE_CHIPID_BCM5701_A0 0x00000000 /* grrrr */ 236#define BGE_CHIPID_BCM5701_B0 0x01000000 237#define BGE_CHIPID_BCM5701_B2 0x01020000 238#define BGE_CHIPID_BCM5701_B5 0x01050000 239#define BGE_CHIPID_BCM5703_A0 0x10000000 240#define BGE_CHIPID_BCM5703_A1 0x10010000 241#define BGE_CHIPID_BCM5703_A2 0x10020000 242#define BGE_CHIPID_BCM5703_A3 0x10030000 243#define BGE_CHIPID_BCM5703_B0 0x11000000 244#define BGE_CHIPID_BCM5704_A0 0x20000000 245#define BGE_CHIPID_BCM5704_A1 0x20010000 246#define BGE_CHIPID_BCM5704_A2 0x20020000 247#define BGE_CHIPID_BCM5704_A3 0x20030000 248#define BGE_CHIPID_BCM5704_B0 0x21000000 249#define BGE_CHIPID_BCM5705_A0 0x30000000 250#define BGE_CHIPID_BCM5705_A1 0x30010000 251#define BGE_CHIPID_BCM5705_A2 0x30020000 252#define BGE_CHIPID_BCM5705_A3 0x30030000 253#define BGE_CHIPID_BCM5750_A0 0x40000000 254#define BGE_CHIPID_BCM5750_A1 0x40010000 255#define BGE_CHIPID_BCM5750_A3 0x40030000 256#define BGE_CHIPID_BCM5750_B0 0x40100000 257#define BGE_CHIPID_BCM5750_B1 0x41010000 258#define BGE_CHIPID_BCM5750_C0 0x42000000 259#define BGE_CHIPID_BCM5750_C1 0x42010000 260#define BGE_CHIPID_BCM5750_C2 0x42020000 261#define BGE_CHIPID_BCM5714_A0 0x50000000 262#define BGE_CHIPID_BCM5752_A0 0x60000000 263#define BGE_CHIPID_BCM5752_A1 0x60010000 264#define BGE_CHIPID_BCM5752_A2 0x60020000 265#define BGE_CHIPID_BCM5714_B0 0x80000000 266#define BGE_CHIPID_BCM5714_B3 0x80030000 267#define BGE_CHIPID_BCM5715_A0 0x90000000 268#define BGE_CHIPID_BCM5715_A1 0x90010000 269 270/* shorthand one */ 271#define BGE_ASICREV(x) ((x) >> 28) 272#define BGE_ASICREV_BCM5701 0x00 273#define BGE_ASICREV_BCM5703 0x01 274#define BGE_ASICREV_BCM5704 0x02 275#define BGE_ASICREV_BCM5705 0x03 276#define BGE_ASICREV_BCM5750 0x04 277#define BGE_ASICREV_BCM5714_A0 0x05 278#define BGE_ASICREV_BCM5752 0x06 279#define BGE_ASICREV_BCM5700 0x07 280#define BGE_ASICREV_BCM5780 0x08 281#define BGE_ASICREV_BCM5714 0x09 282#define BGE_ASICREV_BCM5755 0x0a 283#define BGE_ASICREV_BCM5787 0x0b 284 285/* chip revisions */ 286#define BGE_CHIPREV(x) ((x) >> 24) 287#define BGE_CHIPREV_5700_AX 0x70 288#define BGE_CHIPREV_5700_BX 0x71 289#define BGE_CHIPREV_5700_CX 0x72 290#define BGE_CHIPREV_5701_AX 0x00 291 292/* PCI DMA Read/Write Control register */ 293#define BGE_PCIDMARWCTL_MINDMA 0x000000FF 294#define BGE_PCIDMARWCTL_RDADRR_BNDRY 0x00000700 295#define BGE_PCIDMARWCTL_WRADDR_BNDRY 0x00003800 296#define BGE_PCIDMARWCTL_ONEDMA_ATONCE 0x00004000 297#define BGE_PCIDMARWCTL_RD_WAT 0x00070000 298# define BGE_PCIDMARWCTL_RD_WAT_SHIFT 16 299#define BGE_PCIDMARWCTL_WR_WAT 0x00380000 300# define BGE_PCIDMARWCTL_WR_WAT_SHIFT 19 301#define BGE_PCIDMARWCTL_USE_MRM 0x00400000 302#define BGE_PCIDMARWCTL_ASRT_ALL_BE 0x00800000 303#define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD 0x0F000000 304# define BGE_PCIDMA_RWCTL_PCI_RD_CMD_SHIFT 24 305#define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD 0xF0000000 306# define BGE_PCIDMA_RWCTL_PCI_WR_CMD_SHIFT 28 307 308#define BGE_PCI_READ_BNDRY_DISABLE 0x00000000 309#define BGE_PCI_READ_BNDRY_16BYTES 0x00000100 310#define BGE_PCI_READ_BNDRY_32BYTES 0x00000200 311#define BGE_PCI_READ_BNDRY_64BYTES 0x00000300 312#define BGE_PCI_READ_BNDRY_128BYTES 0x00000400 313#define BGE_PCI_READ_BNDRY_256BYTES 0x00000500 314#define BGE_PCI_READ_BNDRY_512BYTES 0x00000600 315#define BGE_PCI_READ_BNDRY_1024BYTES 0x00000700 316 317#define BGE_PCI_WRITE_BNDRY_DISABLE 0x00000000 318#define BGE_PCI_WRITE_BNDRY_16BYTES 0x00000800 319#define BGE_PCI_WRITE_BNDRY_32BYTES 0x00001000 320#define BGE_PCI_WRITE_BNDRY_64BYTES 0x00001800 321#define BGE_PCI_WRITE_BNDRY_128BYTES 0x00002000 322#define BGE_PCI_WRITE_BNDRY_256BYTES 0x00002800 323#define BGE_PCI_WRITE_BNDRY_512BYTES 0x00003000 324#define BGE_PCI_WRITE_BNDRY_1024BYTES 0x00003800 325 326/* 327 * PCI state register -- note, this register is read only 328 * unless the PCISTATE_WR bit of the PCI Misc. Host Control 329 * register is set. 330 */ 331#define BGE_PCISTATE_FORCE_RESET 0x00000001 332#define BGE_PCISTATE_INTR_STATE 0x00000002 333#define BGE_PCISTATE_PCI_BUSMODE 0x00000004 /* 1 = PCI, 0 = PCI-X */ 334#define BGE_PCISTATE_PCI_BUSSPEED 0x00000008 /* 1 = 33/66, 0 = 66/133 */ 335#define BGE_PCISTATE_32BIT_BUS 0x00000010 /* 1 = 32bit, 0 = 64bit */ 336#define BGE_PCISTATE_WANT_EXPROM 0x00000020 337#define BGE_PCISTATE_EXPROM_RETRY 0x00000040 338#define BGE_PCISTATE_FLATVIEW_MODE 0x00000100 339#define BGE_PCISTATE_PCI_TGT_RETRY_MAX 0x00000E00 340 341/* 342 * PCI Clock Control register -- note, this register is read only 343 * unless the CLOCKCTL_RW bit of the PCI Misc. Host Control 344 * register is set. 345 */ 346#define BGE_PCICLOCKCTL_DETECTED_SPEED 0x0000000F 347#define BGE_PCICLOCKCTL_M66EN 0x00000080 348#define BGE_PCICLOCKCTL_LOWPWR_CLKMODE 0x00000200 349#define BGE_PCICLOCKCTL_RXCPU_CLK_DIS 0x00000400 350#define BGE_PCICLOCKCTL_TXCPU_CLK_DIS 0x00000800 351#define BGE_PCICLOCKCTL_ALTCLK 0x00001000 352#define BGE_PCICLOCKCTL_ALTCLK_SRC 0x00002000 353#define BGE_PCICLOCKCTL_PCIPLL_DISABLE 0x00004000 354#define BGE_PCICLOCKCTL_SYSPLL_DISABLE 0x00008000 355#define BGE_PCICLOCKCTL_BIST_ENABLE 0x00010000 356 357 358#ifndef PCIM_CMD_MWIEN 359#define PCIM_CMD_MWIEN 0x0010 360#endif 361 362/* 363 * High priority mailbox registers 364 * Each mailbox is 64-bits wide, though we only use the 365 * lower 32 bits. To write a 64-bit value, write the upper 32 bits 366 * first. The NIC will load the mailbox after the lower 32 bit word 367 * has been updated. 368 */ 369#define BGE_MBX_IRQ0_HI 0x0200 370#define BGE_MBX_IRQ0_LO 0x0204 371#define BGE_MBX_IRQ1_HI 0x0208 372#define BGE_MBX_IRQ1_LO 0x020C 373#define BGE_MBX_IRQ2_HI 0x0210 374#define BGE_MBX_IRQ2_LO 0x0214 375#define BGE_MBX_IRQ3_HI 0x0218 376#define BGE_MBX_IRQ3_LO 0x021C 377#define BGE_MBX_GEN0_HI 0x0220 378#define BGE_MBX_GEN0_LO 0x0224 379#define BGE_MBX_GEN1_HI 0x0228 380#define BGE_MBX_GEN1_LO 0x022C 381#define BGE_MBX_GEN2_HI 0x0230 382#define BGE_MBX_GEN2_LO 0x0234 383#define BGE_MBX_GEN3_HI 0x0228 384#define BGE_MBX_GEN3_LO 0x022C 385#define BGE_MBX_GEN4_HI 0x0240 386#define BGE_MBX_GEN4_LO 0x0244 387#define BGE_MBX_GEN5_HI 0x0248 388#define BGE_MBX_GEN5_LO 0x024C 389#define BGE_MBX_GEN6_HI 0x0250 390#define BGE_MBX_GEN6_LO 0x0254 391#define BGE_MBX_GEN7_HI 0x0258 392#define BGE_MBX_GEN7_LO 0x025C 393#define BGE_MBX_RELOAD_STATS_HI 0x0260 394#define BGE_MBX_RELOAD_STATS_LO 0x0264 395#define BGE_MBX_RX_STD_PROD_HI 0x0268 396#define BGE_MBX_RX_STD_PROD_LO 0x026C 397#define BGE_MBX_RX_JUMBO_PROD_HI 0x0270 398#define BGE_MBX_RX_JUMBO_PROD_LO 0x0274 399#define BGE_MBX_RX_MINI_PROD_HI 0x0278 400#define BGE_MBX_RX_MINI_PROD_LO 0x027C 401#define BGE_MBX_RX_CONS0_HI 0x0280 402#define BGE_MBX_RX_CONS0_LO 0x0284 403#define BGE_MBX_RX_CONS1_HI 0x0288 404#define BGE_MBX_RX_CONS1_LO 0x028C 405#define BGE_MBX_RX_CONS2_HI 0x0290 406#define BGE_MBX_RX_CONS2_LO 0x0294 407#define BGE_MBX_RX_CONS3_HI 0x0298 408#define BGE_MBX_RX_CONS3_LO 0x029C 409#define BGE_MBX_RX_CONS4_HI 0x02A0 410#define BGE_MBX_RX_CONS4_LO 0x02A4 411#define BGE_MBX_RX_CONS5_HI 0x02A8 412#define BGE_MBX_RX_CONS5_LO 0x02AC 413#define BGE_MBX_RX_CONS6_HI 0x02B0 414#define BGE_MBX_RX_CONS6_LO 0x02B4 415#define BGE_MBX_RX_CONS7_HI 0x02B8 416#define BGE_MBX_RX_CONS7_LO 0x02BC 417#define BGE_MBX_RX_CONS8_HI 0x02C0 418#define BGE_MBX_RX_CONS8_LO 0x02C4 419#define BGE_MBX_RX_CONS9_HI 0x02C8 420#define BGE_MBX_RX_CONS9_LO 0x02CC 421#define BGE_MBX_RX_CONS10_HI 0x02D0 422#define BGE_MBX_RX_CONS10_LO 0x02D4 423#define BGE_MBX_RX_CONS11_HI 0x02D8 424#define BGE_MBX_RX_CONS11_LO 0x02DC 425#define BGE_MBX_RX_CONS12_HI 0x02E0 426#define BGE_MBX_RX_CONS12_LO 0x02E4 427#define BGE_MBX_RX_CONS13_HI 0x02E8 428#define BGE_MBX_RX_CONS13_LO 0x02EC 429#define BGE_MBX_RX_CONS14_HI 0x02F0 430#define BGE_MBX_RX_CONS14_LO 0x02F4 431#define BGE_MBX_RX_CONS15_HI 0x02F8 432#define BGE_MBX_RX_CONS15_LO 0x02FC 433#define BGE_MBX_TX_HOST_PROD0_HI 0x0300 434#define BGE_MBX_TX_HOST_PROD0_LO 0x0304 435#define BGE_MBX_TX_HOST_PROD1_HI 0x0308 436#define BGE_MBX_TX_HOST_PROD1_LO 0x030C 437#define BGE_MBX_TX_HOST_PROD2_HI 0x0310 438#define BGE_MBX_TX_HOST_PROD2_LO 0x0314 439#define BGE_MBX_TX_HOST_PROD3_HI 0x0318 440#define BGE_MBX_TX_HOST_PROD3_LO 0x031C 441#define BGE_MBX_TX_HOST_PROD4_HI 0x0320 442#define BGE_MBX_TX_HOST_PROD4_LO 0x0324 443#define BGE_MBX_TX_HOST_PROD5_HI 0x0328 444#define BGE_MBX_TX_HOST_PROD5_LO 0x032C 445#define BGE_MBX_TX_HOST_PROD6_HI 0x0330 446#define BGE_MBX_TX_HOST_PROD6_LO 0x0334 447#define BGE_MBX_TX_HOST_PROD7_HI 0x0338 448#define BGE_MBX_TX_HOST_PROD7_LO 0x033C 449#define BGE_MBX_TX_HOST_PROD8_HI 0x0340 450#define BGE_MBX_TX_HOST_PROD8_LO 0x0344 451#define BGE_MBX_TX_HOST_PROD9_HI 0x0348 452#define BGE_MBX_TX_HOST_PROD9_LO 0x034C 453#define BGE_MBX_TX_HOST_PROD10_HI 0x0350 454#define BGE_MBX_TX_HOST_PROD10_LO 0x0354 455#define BGE_MBX_TX_HOST_PROD11_HI 0x0358 456#define BGE_MBX_TX_HOST_PROD11_LO 0x035C 457#define BGE_MBX_TX_HOST_PROD12_HI 0x0360 458#define BGE_MBX_TX_HOST_PROD12_LO 0x0364 459#define BGE_MBX_TX_HOST_PROD13_HI 0x0368 460#define BGE_MBX_TX_HOST_PROD13_LO 0x036C 461#define BGE_MBX_TX_HOST_PROD14_HI 0x0370 462#define BGE_MBX_TX_HOST_PROD14_LO 0x0374 463#define BGE_MBX_TX_HOST_PROD15_HI 0x0378 464#define BGE_MBX_TX_HOST_PROD15_LO 0x037C 465#define BGE_MBX_TX_NIC_PROD0_HI 0x0380 466#define BGE_MBX_TX_NIC_PROD0_LO 0x0384 467#define BGE_MBX_TX_NIC_PROD1_HI 0x0388 468#define BGE_MBX_TX_NIC_PROD1_LO 0x038C 469#define BGE_MBX_TX_NIC_PROD2_HI 0x0390 470#define BGE_MBX_TX_NIC_PROD2_LO 0x0394 471#define BGE_MBX_TX_NIC_PROD3_HI 0x0398 472#define BGE_MBX_TX_NIC_PROD3_LO 0x039C 473#define BGE_MBX_TX_NIC_PROD4_HI 0x03A0 474#define BGE_MBX_TX_NIC_PROD4_LO 0x03A4 475#define BGE_MBX_TX_NIC_PROD5_HI 0x03A8 476#define BGE_MBX_TX_NIC_PROD5_LO 0x03AC 477#define BGE_MBX_TX_NIC_PROD6_HI 0x03B0 478#define BGE_MBX_TX_NIC_PROD6_LO 0x03B4 479#define BGE_MBX_TX_NIC_PROD7_HI 0x03B8 480#define BGE_MBX_TX_NIC_PROD7_LO 0x03BC 481#define BGE_MBX_TX_NIC_PROD8_HI 0x03C0 482#define BGE_MBX_TX_NIC_PROD8_LO 0x03C4 483#define BGE_MBX_TX_NIC_PROD9_HI 0x03C8 484#define BGE_MBX_TX_NIC_PROD9_LO 0x03CC 485#define BGE_MBX_TX_NIC_PROD10_HI 0x03D0 486#define BGE_MBX_TX_NIC_PROD10_LO 0x03D4 487#define BGE_MBX_TX_NIC_PROD11_HI 0x03D8 488#define BGE_MBX_TX_NIC_PROD11_LO 0x03DC 489#define BGE_MBX_TX_NIC_PROD12_HI 0x03E0 490#define BGE_MBX_TX_NIC_PROD12_LO 0x03E4 491#define BGE_MBX_TX_NIC_PROD13_HI 0x03E8 492#define BGE_MBX_TX_NIC_PROD13_LO 0x03EC 493#define BGE_MBX_TX_NIC_PROD14_HI 0x03F0 494#define BGE_MBX_TX_NIC_PROD14_LO 0x03F4 495#define BGE_MBX_TX_NIC_PROD15_HI 0x03F8 496#define BGE_MBX_TX_NIC_PROD15_LO 0x03FC 497 498#define BGE_TX_RINGS_MAX 4 499#define BGE_TX_RINGS_EXTSSRAM_MAX 16 500#define BGE_RX_RINGS_MAX 16 501 502/* Ethernet MAC control registers */ 503#define BGE_MAC_MODE 0x0400 504#define BGE_MAC_STS 0x0404 505#define BGE_MAC_EVT_ENB 0x0408 506#define BGE_MAC_LED_CTL 0x040C 507#define BGE_MAC_ADDR1_LO 0x0410 508#define BGE_MAC_ADDR1_HI 0x0414 509#define BGE_MAC_ADDR2_LO 0x0418 510#define BGE_MAC_ADDR2_HI 0x041C 511#define BGE_MAC_ADDR3_LO 0x0420 512#define BGE_MAC_ADDR3_HI 0x0424 513#define BGE_MAC_ADDR4_LO 0x0428 514#define BGE_MAC_ADDR4_HI 0x042C 515#define BGE_WOL_PATPTR 0x0430 516#define BGE_WOL_PATCFG 0x0434 517#define BGE_TX_RANDOM_BACKOFF 0x0438 518#define BGE_RX_MTU 0x043C 519#define BGE_GBIT_PCS_TEST 0x0440 520#define BGE_TX_TBI_AUTONEG 0x0444 521#define BGE_RX_TBI_AUTONEG 0x0448 522#define BGE_MI_COMM 0x044C 523#define BGE_MI_STS 0x0450 524#define BGE_MI_MODE 0x0454 525#define BGE_AUTOPOLL_STS 0x0458 526#define BGE_TX_MODE 0x045C 527#define BGE_TX_STS 0x0460 528#define BGE_TX_LENGTHS 0x0464 529#define BGE_RX_MODE 0x0468 530#define BGE_RX_STS 0x046C 531#define BGE_MAR0 0x0470 532#define BGE_MAR1 0x0474 533#define BGE_MAR2 0x0478 534#define BGE_MAR3 0x047C 535#define BGE_RX_BD_RULES_CTL0 0x0480 536#define BGE_RX_BD_RULES_MASKVAL0 0x0484 537#define BGE_RX_BD_RULES_CTL1 0x0488 538#define BGE_RX_BD_RULES_MASKVAL1 0x048C 539#define BGE_RX_BD_RULES_CTL2 0x0490 540#define BGE_RX_BD_RULES_MASKVAL2 0x0494 541#define BGE_RX_BD_RULES_CTL3 0x0498 542#define BGE_RX_BD_RULES_MASKVAL3 0x049C 543#define BGE_RX_BD_RULES_CTL4 0x04A0 544#define BGE_RX_BD_RULES_MASKVAL4 0x04A4 545#define BGE_RX_BD_RULES_CTL5 0x04A8 546#define BGE_RX_BD_RULES_MASKVAL5 0x04AC 547#define BGE_RX_BD_RULES_CTL6 0x04B0 548#define BGE_RX_BD_RULES_MASKVAL6 0x04B4 549#define BGE_RX_BD_RULES_CTL7 0x04B8 550#define BGE_RX_BD_RULES_MASKVAL7 0x04BC 551#define BGE_RX_BD_RULES_CTL8 0x04C0 552#define BGE_RX_BD_RULES_MASKVAL8 0x04C4 553#define BGE_RX_BD_RULES_CTL9 0x04C8 554#define BGE_RX_BD_RULES_MASKVAL9 0x04CC 555#define BGE_RX_BD_RULES_CTL10 0x04D0 556#define BGE_RX_BD_RULES_MASKVAL10 0x04D4 557#define BGE_RX_BD_RULES_CTL11 0x04D8 558#define BGE_RX_BD_RULES_MASKVAL11 0x04DC 559#define BGE_RX_BD_RULES_CTL12 0x04E0 560#define BGE_RX_BD_RULES_MASKVAL12 0x04E4 561#define BGE_RX_BD_RULES_CTL13 0x04E8 562#define BGE_RX_BD_RULES_MASKVAL13 0x04EC 563#define BGE_RX_BD_RULES_CTL14 0x04F0 564#define BGE_RX_BD_RULES_MASKVAL14 0x04F4 565#define BGE_RX_BD_RULES_CTL15 0x04F8 566#define BGE_RX_BD_RULES_MASKVAL15 0x04FC 567#define BGE_RX_RULES_CFG 0x0500 568#define BGE_SERDES_CFG 0x0590 569#define BGE_SERDES_STS 0x0594 570#define BGE_SGDIG_CFG 0x05B0 571#define BGE_SGDIG_STS 0x05B4 572#define BGE_RX_STATS 0x0800 573#define BGE_TX_STATS 0x0880 574 575/* Ethernet MAC Mode register */ 576#define BGE_MACMODE_RESET 0x00000001 577#define BGE_MACMODE_HALF_DUPLEX 0x00000002 578#define BGE_MACMODE_PORTMODE 0x0000000C 579#define BGE_MACMODE_LOOPBACK 0x00000010 580#define BGE_MACMODE_RX_TAGGEDPKT 0x00000080 581#define BGE_MACMODE_TX_BURST_ENB 0x00000100 582#define BGE_MACMODE_MAX_DEFER 0x00000200 583#define BGE_MACMODE_LINK_POLARITY 0x00000400 584#define BGE_MACMODE_RX_STATS_ENB 0x00000800 585#define BGE_MACMODE_RX_STATS_CLEAR 0x00001000 586#define BGE_MACMODE_RX_STATS_FLUSH 0x00002000 587#define BGE_MACMODE_TX_STATS_ENB 0x00004000 588#define BGE_MACMODE_TX_STATS_CLEAR 0x00008000 589#define BGE_MACMODE_TX_STATS_FLUSH 0x00010000 590#define BGE_MACMODE_TBI_SEND_CFGS 0x00020000 591#define BGE_MACMODE_MAGIC_PKT_ENB 0x00040000 592#define BGE_MACMODE_ACPI_PWRON_ENB 0x00080000 593#define BGE_MACMODE_MIP_ENB 0x00100000 594#define BGE_MACMODE_TXDMA_ENB 0x00200000 595#define BGE_MACMODE_RXDMA_ENB 0x00400000 596#define BGE_MACMODE_FRMHDR_DMA_ENB 0x00800000 597 598#define BGE_PORTMODE_NONE 0x00000000 599#define BGE_PORTMODE_MII 0x00000004 600#define BGE_PORTMODE_GMII 0x00000008 601#define BGE_PORTMODE_TBI 0x0000000C 602 603/* MAC Status register */ 604#define BGE_MACSTAT_TBI_PCS_SYNCHED 0x00000001 605#define BGE_MACSTAT_TBI_SIGNAL_DETECT 0x00000002 606#define BGE_MACSTAT_RX_CFG 0x00000004 607#define BGE_MACSTAT_CFG_CHANGED 0x00000008 608#define BGE_MACSTAT_SYNC_CHANGED 0x00000010 609#define BGE_MACSTAT_PORT_DECODE_ERROR 0x00000400 610#define BGE_MACSTAT_LINK_CHANGED 0x00001000 611#define BGE_MACSTAT_MI_COMPLETE 0x00400000 612#define BGE_MACSTAT_MI_INTERRUPT 0x00800000 613#define BGE_MACSTAT_AUTOPOLL_ERROR 0x01000000 614#define BGE_MACSTAT_ODI_ERROR 0x02000000 615#define BGE_MACSTAT_RXSTAT_OFLOW 0x04000000 616#define BGE_MACSTAT_TXSTAT_OFLOW 0x08000000 617 618/* MAC Event Enable Register */ 619#define BGE_EVTENB_PORT_DECODE_ERROR 0x00000400 620#define BGE_EVTENB_LINK_CHANGED 0x00001000 621#define BGE_EVTENB_MI_COMPLETE 0x00400000 622#define BGE_EVTENB_MI_INTERRUPT 0x00800000 623#define BGE_EVTENB_AUTOPOLL_ERROR 0x01000000 624#define BGE_EVTENB_ODI_ERROR 0x02000000 625#define BGE_EVTENB_RXSTAT_OFLOW 0x04000000 626#define BGE_EVTENB_TXSTAT_OFLOW 0x08000000 627 628/* LED Control Register */ 629#define BGE_LEDCTL_LINKLED_OVERRIDE 0x00000001 630#define BGE_LEDCTL_1000MBPS_LED 0x00000002 631#define BGE_LEDCTL_100MBPS_LED 0x00000004 632#define BGE_LEDCTL_10MBPS_LED 0x00000008 633#define BGE_LEDCTL_TRAFLED_OVERRIDE 0x00000010 634#define BGE_LEDCTL_TRAFLED_BLINK 0x00000020 635#define BGE_LEDCTL_TREFLED_BLINK_2 0x00000040 636#define BGE_LEDCTL_1000MBPS_STS 0x00000080 637#define BGE_LEDCTL_100MBPS_STS 0x00000100 638#define BGE_LEDCTL_10MBPS_STS 0x00000200 639#define BGE_LEDCTL_TRADLED_STS 0x00000400 640#define BGE_LEDCTL_BLINKPERIOD 0x7FF80000 641#define BGE_LEDCTL_BLINKPERIOD_OVERRIDE 0x80000000 642 643/* TX backoff seed register */ 644#define BGE_TX_BACKOFF_SEED_MASK 0x3F 645 646/* Autopoll status register */ 647#define BGE_AUTOPOLLSTS_ERROR 0x00000001 648 649/* Transmit MAC mode register */ 650#define BGE_TXMODE_RESET 0x00000001 651#define BGE_TXMODE_ENABLE 0x00000002 652#define BGE_TXMODE_FLOWCTL_ENABLE 0x00000010 653#define BGE_TXMODE_BIGBACKOFF_ENABLE 0x00000020 654#define BGE_TXMODE_LONGPAUSE_ENABLE 0x00000040 655 656/* Transmit MAC status register */ 657#define BGE_TXSTAT_RX_XOFFED 0x00000001 658#define BGE_TXSTAT_SENT_XOFF 0x00000002 659#define BGE_TXSTAT_SENT_XON 0x00000004 660#define BGE_TXSTAT_LINK_UP 0x00000008 661#define BGE_TXSTAT_ODI_UFLOW 0x00000010 662#define BGE_TXSTAT_ODI_OFLOW 0x00000020 663 664/* Transmit MAC lengths register */ 665#define BGE_TXLEN_SLOTTIME 0x000000FF 666#define BGE_TXLEN_IPG 0x00000F00 667#define BGE_TXLEN_CRS 0x00003000 668 669/* Receive MAC mode register */ 670#define BGE_RXMODE_RESET 0x00000001 671#define BGE_RXMODE_ENABLE 0x00000002 672#define BGE_RXMODE_FLOWCTL_ENABLE 0x00000004 673#define BGE_RXMODE_RX_GIANTS 0x00000020 674#define BGE_RXMODE_RX_RUNTS 0x00000040 675#define BGE_RXMODE_8022_LENCHECK 0x00000080 676#define BGE_RXMODE_RX_PROMISC 0x00000100 677#define BGE_RXMODE_RX_NO_CRC_CHECK 0x00000200 678#define BGE_RXMODE_RX_KEEP_VLAN_DIAG 0x00000400 679 680/* Receive MAC status register */ 681#define BGE_RXSTAT_REMOTE_XOFFED 0x00000001 682#define BGE_RXSTAT_RCVD_XOFF 0x00000002 683#define BGE_RXSTAT_RCVD_XON 0x00000004 684 685/* Receive Rules Control register */ 686#define BGE_RXRULECTL_OFFSET 0x000000FF 687#define BGE_RXRULECTL_CLASS 0x00001F00 688#define BGE_RXRULECTL_HDRTYPE 0x0000E000 689#define BGE_RXRULECTL_COMPARE_OP 0x00030000 690#define BGE_RXRULECTL_MAP 0x01000000 691#define BGE_RXRULECTL_DISCARD 0x02000000 692#define BGE_RXRULECTL_MASK 0x04000000 693#define BGE_RXRULECTL_ACTIVATE_PROC3 0x08000000 694#define BGE_RXRULECTL_ACTIVATE_PROC2 0x10000000 695#define BGE_RXRULECTL_ACTIVATE_PROC1 0x20000000 696#define BGE_RXRULECTL_ANDWITHNEXT 0x40000000 697 698/* Receive Rules Mask register */ 699#define BGE_RXRULEMASK_VALUE 0x0000FFFF 700#define BGE_RXRULEMASK_MASKVAL 0xFFFF0000 701 702/* SERDES configuration register */ 703#define BGE_SERDESCFG_RXR 0x00000007 /* phase interpolator */ 704#define BGE_SERDESCFG_RXG 0x00000018 /* rx gain setting */ 705#define BGE_SERDESCFG_RXEDGESEL 0x00000040 /* rising/falling egde */ 706#define BGE_SERDESCFG_TX_BIAS 0x00000380 /* TXDAC bias setting */ 707#define BGE_SERDESCFG_IBMAX 0x00000400 /* bias current +25% */ 708#define BGE_SERDESCFG_IBMIN 0x00000800 /* bias current -25% */ 709#define BGE_SERDESCFG_TXMODE 0x00001000 710#define BGE_SERDESCFG_TXEDGESEL 0x00002000 /* rising/falling edge */ 711#define BGE_SERDESCFG_MODE 0x00004000 /* TXCP/TXCN disabled */ 712#define BGE_SERDESCFG_PLLTEST 0x00008000 /* PLL test mode */ 713#define BGE_SERDESCFG_CDET 0x00010000 /* comma detect enable */ 714#define BGE_SERDESCFG_TBILOOP 0x00020000 /* local loopback */ 715#define BGE_SERDESCFG_REMLOOP 0x00040000 /* remote loopback */ 716#define BGE_SERDESCFG_INVPHASE 0x00080000 /* Reverse 125Mhz clock */ 717#define BGE_SERDESCFG_12REGCTL 0x00300000 /* 1.2v regulator ctl */ 718#define BGE_SERDESCFG_REGCTL 0x00C00000 /* regulator ctl (2.5v) */ 719 720/* SERDES status register */ 721#define BGE_SERDESSTS_RXSTAT 0x0000000F /* receive status bits */ 722#define BGE_SERDESSTS_CDET 0x00000010 /* comma code detected */ 723 724/* SGDIG config (not documented) */ 725#define BGE_SGDIGCFG_PAUSE_CAP 0x00000800 726#define BGE_SGDIGCFG_ASYM_PAUSE 0x00001000 727#define BGE_SGDIGCFG_SEND 0x40000000 728#define BGE_SGDIGCFG_AUTO 0x80000000 729 730/* SGDIG status (not documented) */ 731#define BGE_SGDIGSTS_PAUSE_CAP 0x00080000 732#define BGE_SGDIGSTS_ASYM_PAUSE 0x00100000 733#define BGE_SGDIGSTS_DONE 0x00000002 734 735 736/* MI communication register */ 737#define BGE_MICOMM_DATA 0x0000FFFF 738#define BGE_MICOMM_REG 0x001F0000 739#define BGE_MICOMM_PHY 0x03E00000 740#define BGE_MICOMM_CMD 0x0C000000 741#define BGE_MICOMM_READFAIL 0x10000000 742#define BGE_MICOMM_BUSY 0x20000000 743 744#define BGE_MIREG(x) ((x & 0x1F) << 16) 745#define BGE_MIPHY(x) ((x & 0x1F) << 21) 746#define BGE_MICMD_WRITE 0x04000000 747#define BGE_MICMD_READ 0x08000000 748 749/* MI status register */ 750#define BGE_MISTS_LINK 0x00000001 751#define BGE_MISTS_10MBPS 0x00000002 752 753#define BGE_MIMODE_SHORTPREAMBLE 0x00000002 754#define BGE_MIMODE_AUTOPOLL 0x00000010 755#define BGE_MIMODE_CLKCNT 0x001F0000 756 757 758/* 759 * Send data initiator control registers. 760 */ 761#define BGE_SDI_MODE 0x0C00 762#define BGE_SDI_STATUS 0x0C04 763#define BGE_SDI_STATS_CTL 0x0C08 764#define BGE_SDI_STATS_ENABLE_MASK 0x0C0C 765#define BGE_SDI_STATS_INCREMENT_MASK 0x0C10 766#define BGE_LOCSTATS_COS0 0x0C80 767#define BGE_LOCSTATS_COS1 0x0C84 768#define BGE_LOCSTATS_COS2 0x0C88 769#define BGE_LOCSTATS_COS3 0x0C8C 770#define BGE_LOCSTATS_COS4 0x0C90 771#define BGE_LOCSTATS_COS5 0x0C84 772#define BGE_LOCSTATS_COS6 0x0C98 773#define BGE_LOCSTATS_COS7 0x0C9C 774#define BGE_LOCSTATS_COS8 0x0CA0 775#define BGE_LOCSTATS_COS9 0x0CA4 776#define BGE_LOCSTATS_COS10 0x0CA8 777#define BGE_LOCSTATS_COS11 0x0CAC 778#define BGE_LOCSTATS_COS12 0x0CB0 779#define BGE_LOCSTATS_COS13 0x0CB4 780#define BGE_LOCSTATS_COS14 0x0CB8 781#define BGE_LOCSTATS_COS15 0x0CBC 782#define BGE_LOCSTATS_DMA_RQ_FULL 0x0CC0 783#define BGE_LOCSTATS_DMA_HIPRIO_RQ_FULL 0x0CC4 784#define BGE_LOCSTATS_SDC_QUEUE_FULL 0x0CC8 785#define BGE_LOCSTATS_NIC_SENDPROD_SET 0x0CCC 786#define BGE_LOCSTATS_STATS_UPDATED 0x0CD0 787#define BGE_LOCSTATS_IRQS 0x0CD4 788#define BGE_LOCSTATS_AVOIDED_IRQS 0x0CD8 789#define BGE_LOCSTATS_TX_THRESH_HIT 0x0CDC 790 791/* Send Data Initiator mode register */ 792#define BGE_SDIMODE_RESET 0x00000001 793#define BGE_SDIMODE_ENABLE 0x00000002 794#define BGE_SDIMODE_STATS_OFLOW_ATTN 0x00000004 795 796/* Send Data Initiator stats register */ 797#define BGE_SDISTAT_STATS_OFLOW_ATTN 0x00000004 798 799/* Send Data Initiator stats control register */ 800#define BGE_SDISTATSCTL_ENABLE 0x00000001 801#define BGE_SDISTATSCTL_FASTER 0x00000002 802#define BGE_SDISTATSCTL_CLEAR 0x00000004 803#define BGE_SDISTATSCTL_FORCEFLUSH 0x00000008 804#define BGE_SDISTATSCTL_FORCEZERO 0x00000010 805 806/* 807 * Send Data Completion Control registers 808 */ 809#define BGE_SDC_MODE 0x1000 810#define BGE_SDC_STATUS 0x1004 811 812/* Send Data completion mode register */ 813#define BGE_SDCMODE_RESET 0x00000001 814#define BGE_SDCMODE_ENABLE 0x00000002 815#define BGE_SDCMODE_ATTN 0x00000004 816 817/* Send Data completion status register */ 818#define BGE_SDCSTAT_ATTN 0x00000004 819 820/* 821 * Send BD Ring Selector Control registers 822 */ 823#define BGE_SRS_MODE 0x1400 824#define BGE_SRS_STATUS 0x1404 825#define BGE_SRS_HWDIAG 0x1408 826#define BGE_SRS_LOC_NIC_CONS0 0x1440 827#define BGE_SRS_LOC_NIC_CONS1 0x1444 828#define BGE_SRS_LOC_NIC_CONS2 0x1448 829#define BGE_SRS_LOC_NIC_CONS3 0x144C 830#define BGE_SRS_LOC_NIC_CONS4 0x1450 831#define BGE_SRS_LOC_NIC_CONS5 0x1454 832#define BGE_SRS_LOC_NIC_CONS6 0x1458 833#define BGE_SRS_LOC_NIC_CONS7 0x145C 834#define BGE_SRS_LOC_NIC_CONS8 0x1460 835#define BGE_SRS_LOC_NIC_CONS9 0x1464 836#define BGE_SRS_LOC_NIC_CONS10 0x1468 837#define BGE_SRS_LOC_NIC_CONS11 0x146C 838#define BGE_SRS_LOC_NIC_CONS12 0x1470 839#define BGE_SRS_LOC_NIC_CONS13 0x1474 840#define BGE_SRS_LOC_NIC_CONS14 0x1478 841#define BGE_SRS_LOC_NIC_CONS15 0x147C 842 843/* Send BD Ring Selector Mode register */ 844#define BGE_SRSMODE_RESET 0x00000001 845#define BGE_SRSMODE_ENABLE 0x00000002 846#define BGE_SRSMODE_ATTN 0x00000004 847 848/* Send BD Ring Selector Status register */ 849#define BGE_SRSSTAT_ERROR 0x00000004 850 851/* Send BD Ring Selector HW Diagnostics register */ 852#define BGE_SRSHWDIAG_STATE 0x0000000F 853#define BGE_SRSHWDIAG_CURRINGNUM 0x000000F0 854#define BGE_SRSHWDIAG_STAGEDRINGNUM 0x00000F00 855#define BGE_SRSHWDIAG_RINGNUM_IN_MBX 0x0000F000 856 857/* 858 * Send BD Initiator Selector Control registers 859 */ 860#define BGE_SBDI_MODE 0x1800 861#define BGE_SBDI_STATUS 0x1804 862#define BGE_SBDI_LOC_NIC_PROD0 0x1808 863#define BGE_SBDI_LOC_NIC_PROD1 0x180C 864#define BGE_SBDI_LOC_NIC_PROD2 0x1810 865#define BGE_SBDI_LOC_NIC_PROD3 0x1814 866#define BGE_SBDI_LOC_NIC_PROD4 0x1818 867#define BGE_SBDI_LOC_NIC_PROD5 0x181C 868#define BGE_SBDI_LOC_NIC_PROD6 0x1820 869#define BGE_SBDI_LOC_NIC_PROD7 0x1824 870#define BGE_SBDI_LOC_NIC_PROD8 0x1828 871#define BGE_SBDI_LOC_NIC_PROD9 0x182C 872#define BGE_SBDI_LOC_NIC_PROD10 0x1830 873#define BGE_SBDI_LOC_NIC_PROD11 0x1834 874#define BGE_SBDI_LOC_NIC_PROD12 0x1838 875#define BGE_SBDI_LOC_NIC_PROD13 0x183C 876#define BGE_SBDI_LOC_NIC_PROD14 0x1840 877#define BGE_SBDI_LOC_NIC_PROD15 0x1844 878 879/* Send BD Initiator Mode register */ 880#define BGE_SBDIMODE_RESET 0x00000001 881#define BGE_SBDIMODE_ENABLE 0x00000002 882#define BGE_SBDIMODE_ATTN 0x00000004 883 884/* Send BD Initiator Status register */ 885#define BGE_SBDISTAT_ERROR 0x00000004 886 887/* 888 * Send BD Completion Control registers 889 */ 890#define BGE_SBDC_MODE 0x1C00 891#define BGE_SBDC_STATUS 0x1C04 892 893/* Send BD Completion Control Mode register */ 894#define BGE_SBDCMODE_RESET 0x00000001 895#define BGE_SBDCMODE_ENABLE 0x00000002 896#define BGE_SBDCMODE_ATTN 0x00000004 897 898/* Send BD Completion Control Status register */ 899#define BGE_SBDCSTAT_ATTN 0x00000004 900 901/* 902 * Receive List Placement Control registers 903 */ 904#define BGE_RXLP_MODE 0x2000 905#define BGE_RXLP_STATUS 0x2004 906#define BGE_RXLP_SEL_LIST_LOCK 0x2008 907#define BGE_RXLP_SEL_NON_EMPTY_BITS 0x200C 908#define BGE_RXLP_CFG 0x2010 909#define BGE_RXLP_STATS_CTL 0x2014 910#define BGE_RXLP_STATS_ENABLE_MASK 0x2018 911#define BGE_RXLP_STATS_INCREMENT_MASK 0x201C 912#define BGE_RXLP_HEAD0 0x2100 913#define BGE_RXLP_TAIL0 0x2104 914#define BGE_RXLP_COUNT0 0x2108 915#define BGE_RXLP_HEAD1 0x2110 916#define BGE_RXLP_TAIL1 0x2114 917#define BGE_RXLP_COUNT1 0x2118 918#define BGE_RXLP_HEAD2 0x2120 919#define BGE_RXLP_TAIL2 0x2124 920#define BGE_RXLP_COUNT2 0x2128 921#define BGE_RXLP_HEAD3 0x2130 922#define BGE_RXLP_TAIL3 0x2134 923#define BGE_RXLP_COUNT3 0x2138 924#define BGE_RXLP_HEAD4 0x2140 925#define BGE_RXLP_TAIL4 0x2144 926#define BGE_RXLP_COUNT4 0x2148 927#define BGE_RXLP_HEAD5 0x2150 928#define BGE_RXLP_TAIL5 0x2154 929#define BGE_RXLP_COUNT5 0x2158 930#define BGE_RXLP_HEAD6 0x2160 931#define BGE_RXLP_TAIL6 0x2164 932#define BGE_RXLP_COUNT6 0x2168 933#define BGE_RXLP_HEAD7 0x2170 934#define BGE_RXLP_TAIL7 0x2174 935#define BGE_RXLP_COUNT7 0x2178 936#define BGE_RXLP_HEAD8 0x2180 937#define BGE_RXLP_TAIL8 0x2184 938#define BGE_RXLP_COUNT8 0x2188 939#define BGE_RXLP_HEAD9 0x2190 940#define BGE_RXLP_TAIL9 0x2194 941#define BGE_RXLP_COUNT9 0x2198 942#define BGE_RXLP_HEAD10 0x21A0 943#define BGE_RXLP_TAIL10 0x21A4 944#define BGE_RXLP_COUNT10 0x21A8 945#define BGE_RXLP_HEAD11 0x21B0 946#define BGE_RXLP_TAIL11 0x21B4 947#define BGE_RXLP_COUNT11 0x21B8 948#define BGE_RXLP_HEAD12 0x21C0 949#define BGE_RXLP_TAIL12 0x21C4 950#define BGE_RXLP_COUNT12 0x21C8 951#define BGE_RXLP_HEAD13 0x21D0 952#define BGE_RXLP_TAIL13 0x21D4 953#define BGE_RXLP_COUNT13 0x21D8 954#define BGE_RXLP_HEAD14 0x21E0 955#define BGE_RXLP_TAIL14 0x21E4 956#define BGE_RXLP_COUNT14 0x21E8 957#define BGE_RXLP_HEAD15 0x21F0 958#define BGE_RXLP_TAIL15 0x21F4 959#define BGE_RXLP_COUNT15 0x21F8 960#define BGE_RXLP_LOCSTAT_COS0 0x2200 961#define BGE_RXLP_LOCSTAT_COS1 0x2204 962#define BGE_RXLP_LOCSTAT_COS2 0x2208 963#define BGE_RXLP_LOCSTAT_COS3 0x220C 964#define BGE_RXLP_LOCSTAT_COS4 0x2210 965#define BGE_RXLP_LOCSTAT_COS5 0x2214 966#define BGE_RXLP_LOCSTAT_COS6 0x2218 967#define BGE_RXLP_LOCSTAT_COS7 0x221C 968#define BGE_RXLP_LOCSTAT_COS8 0x2220 969#define BGE_RXLP_LOCSTAT_COS9 0x2224 970#define BGE_RXLP_LOCSTAT_COS10 0x2228 971#define BGE_RXLP_LOCSTAT_COS11 0x222C 972#define BGE_RXLP_LOCSTAT_COS12 0x2230 973#define BGE_RXLP_LOCSTAT_COS13 0x2234 974#define BGE_RXLP_LOCSTAT_COS14 0x2238 975#define BGE_RXLP_LOCSTAT_COS15 0x223C 976#define BGE_RXLP_LOCSTAT_FILTDROP 0x2240 977#define BGE_RXLP_LOCSTAT_DMA_WRQ_FULL 0x2244 978#define BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL 0x2248 979#define BGE_RXLP_LOCSTAT_OUT_OF_BDS 0x224C 980#define BGE_RXLP_LOCSTAT_IFIN_DROPS 0x2250 981#define BGE_RXLP_LOCSTAT_IFIN_ERRORS 0x2254 982#define BGE_RXLP_LOCSTAT_RXTHRESH_HIT 0x2258 983 984 985/* Receive List Placement mode register */ 986#define BGE_RXLPMODE_RESET 0x00000001 987#define BGE_RXLPMODE_ENABLE 0x00000002 988#define BGE_RXLPMODE_CLASS0_ATTN 0x00000004 989#define BGE_RXLPMODE_MAPOUTRANGE_ATTN 0x00000008 990#define BGE_RXLPMODE_STATSOFLOW_ATTN 0x00000010 991 992/* Receive List Placement Status register */ 993#define BGE_RXLPSTAT_CLASS0_ATTN 0x00000004 994#define BGE_RXLPSTAT_MAPOUTRANGE_ATTN 0x00000008 995#define BGE_RXLPSTAT_STATSOFLOW_ATTN 0x00000010 996 997/* 998 * Receive Data and Receive BD Initiator Control Registers 999 */ 1000#define BGE_RDBDI_MODE 0x2400 1001#define BGE_RDBDI_STATUS 0x2404 1002#define BGE_RX_JUMBO_RCB_HADDR_HI 0x2440 1003#define BGE_RX_JUMBO_RCB_HADDR_LO 0x2444 1004#define BGE_RX_JUMBO_RCB_MAXLEN_FLAGS 0x2448 1005#define BGE_RX_JUMBO_RCB_NICADDR 0x244C 1006#define BGE_RX_STD_RCB_HADDR_HI 0x2450 1007#define BGE_RX_STD_RCB_HADDR_LO 0x2454 1008#define BGE_RX_STD_RCB_MAXLEN_FLAGS 0x2458 1009#define BGE_RX_STD_RCB_NICADDR 0x245C 1010#define BGE_RX_MINI_RCB_HADDR_HI 0x2460 1011#define BGE_RX_MINI_RCB_HADDR_LO 0x2464 1012#define BGE_RX_MINI_RCB_MAXLEN_FLAGS 0x2468 1013#define BGE_RX_MINI_RCB_NICADDR 0x246C 1014#define BGE_RDBDI_JUMBO_RX_CONS 0x2470 1015#define BGE_RDBDI_STD_RX_CONS 0x2474 1016#define BGE_RDBDI_MINI_RX_CONS 0x2478 1017#define BGE_RDBDI_RETURN_PROD0 0x2480 1018#define BGE_RDBDI_RETURN_PROD1 0x2484 1019#define BGE_RDBDI_RETURN_PROD2 0x2488 1020#define BGE_RDBDI_RETURN_PROD3 0x248C 1021#define BGE_RDBDI_RETURN_PROD4 0x2490 1022#define BGE_RDBDI_RETURN_PROD5 0x2494 1023#define BGE_RDBDI_RETURN_PROD6 0x2498 1024#define BGE_RDBDI_RETURN_PROD7 0x249C 1025#define BGE_RDBDI_RETURN_PROD8 0x24A0 1026#define BGE_RDBDI_RETURN_PROD9 0x24A4 1027#define BGE_RDBDI_RETURN_PROD10 0x24A8 1028#define BGE_RDBDI_RETURN_PROD11 0x24AC 1029#define BGE_RDBDI_RETURN_PROD12 0x24B0 1030#define BGE_RDBDI_RETURN_PROD13 0x24B4 1031#define BGE_RDBDI_RETURN_PROD14 0x24B8 1032#define BGE_RDBDI_RETURN_PROD15 0x24BC 1033#define BGE_RDBDI_HWDIAG 0x24C0 1034 1035 1036/* Receive Data and Receive BD Initiator Mode register */ 1037#define BGE_RDBDIMODE_RESET 0x00000001 1038#define BGE_RDBDIMODE_ENABLE 0x00000002 1039#define BGE_RDBDIMODE_JUMBO_ATTN 0x00000004 1040#define BGE_RDBDIMODE_GIANT_ATTN 0x00000008 1041#define BGE_RDBDIMODE_BADRINGSZ_ATTN 0x00000010 1042 1043/* Receive Data and Receive BD Initiator Status register */ 1044#define BGE_RDBDISTAT_JUMBO_ATTN 0x00000004 1045#define BGE_RDBDISTAT_GIANT_ATTN 0x00000008 1046#define BGE_RDBDISTAT_BADRINGSZ_ATTN 0x00000010 1047 1048 1049/* 1050 * Receive Data Completion Control registers 1051 */ 1052#define BGE_RDC_MODE 0x2800 1053 1054/* Receive Data Completion Mode register */ 1055#define BGE_RDCMODE_RESET 0x00000001 1056#define BGE_RDCMODE_ENABLE 0x00000002 1057#define BGE_RDCMODE_ATTN 0x00000004 1058 1059/* 1060 * Receive BD Initiator Control registers 1061 */ 1062#define BGE_RBDI_MODE 0x2C00 1063#define BGE_RBDI_STATUS 0x2C04 1064#define BGE_RBDI_NIC_JUMBO_BD_PROD 0x2C08 1065#define BGE_RBDI_NIC_STD_BD_PROD 0x2C0C 1066#define BGE_RBDI_NIC_MINI_BD_PROD 0x2C10 1067#define BGE_RBDI_MINI_REPL_THRESH 0x2C14 1068#define BGE_RBDI_STD_REPL_THRESH 0x2C18 1069#define BGE_RBDI_JUMBO_REPL_THRESH 0x2C1C 1070 1071/* Receive BD Initiator Mode register */ 1072#define BGE_RBDIMODE_RESET 0x00000001 1073#define BGE_RBDIMODE_ENABLE 0x00000002 1074#define BGE_RBDIMODE_ATTN 0x00000004 1075 1076/* Receive BD Initiator Status register */ 1077#define BGE_RBDISTAT_ATTN 0x00000004 1078 1079/* 1080 * Receive BD Completion Control registers 1081 */ 1082#define BGE_RBDC_MODE 0x3000 1083#define BGE_RBDC_STATUS 0x3004 1084#define BGE_RBDC_JUMBO_BD_PROD 0x3008 1085#define BGE_RBDC_STD_BD_PROD 0x300C 1086#define BGE_RBDC_MINI_BD_PROD 0x3010 1087 1088/* Receive BD completion mode register */ 1089#define BGE_RBDCMODE_RESET 0x00000001 1090#define BGE_RBDCMODE_ENABLE 0x00000002 1091#define BGE_RBDCMODE_ATTN 0x00000004 1092 1093/* Receive BD completion status register */ 1094#define BGE_RBDCSTAT_ERROR 0x00000004 1095 1096/* 1097 * Receive List Selector Control registers 1098 */ 1099#define BGE_RXLS_MODE 0x3400 1100#define BGE_RXLS_STATUS 0x3404 1101 1102/* Receive List Selector Mode register */ 1103#define BGE_RXLSMODE_RESET 0x00000001 1104#define BGE_RXLSMODE_ENABLE 0x00000002 1105#define BGE_RXLSMODE_ATTN 0x00000004 1106 1107/* Receive List Selector Status register */ 1108#define BGE_RXLSSTAT_ERROR 0x00000004 1109 1110/* 1111 * Mbuf Cluster Free registers (has nothing to do with BSD mbufs) 1112 */ 1113#define BGE_MBCF_MODE 0x3800 1114#define BGE_MBCF_STATUS 0x3804 1115 1116/* Mbuf Cluster Free mode register */ 1117#define BGE_MBCFMODE_RESET 0x00000001 1118#define BGE_MBCFMODE_ENABLE 0x00000002 1119#define BGE_MBCFMODE_ATTN 0x00000004 1120 1121/* Mbuf Cluster Free status register */ 1122#define BGE_MBCFSTAT_ERROR 0x00000004 1123 1124/* 1125 * Host Coalescing Control registers 1126 */ 1127#define BGE_HCC_MODE 0x3C00 1128#define BGE_HCC_STATUS 0x3C04 1129#define BGE_HCC_RX_COAL_TICKS 0x3C08 1130#define BGE_HCC_TX_COAL_TICKS 0x3C0C 1131#define BGE_HCC_RX_MAX_COAL_BDS 0x3C10 1132#define BGE_HCC_TX_MAX_COAL_BDS 0x3C14 1133#define BGE_HCC_RX_COAL_TICKS_INT 0x3C18 /* ticks during interrupt */ 1134#define BGE_HCC_TX_COAL_TICKS_INT 0x3C1C /* ticks during interrupt */ 1135#define BGE_HCC_RX_MAX_COAL_BDS_INT 0x3C20 /* BDs during interrupt */ 1136#define BGE_HCC_TX_MAX_COAL_BDS_INT 0x3C24 /* BDs during interrupt */ 1137#define BGE_HCC_STATS_TICKS 0x3C28 1138#define BGE_HCC_STATS_ADDR_HI 0x3C30 1139#define BGE_HCC_STATS_ADDR_LO 0x3C34 1140#define BGE_HCC_STATUSBLK_ADDR_HI 0x3C38 1141#define BGE_HCC_STATUSBLK_ADDR_LO 0x3C3C 1142#define BGE_HCC_STATS_BASEADDR 0x3C40 /* address in NIC memory */ 1143#define BGE_HCC_STATUSBLK_BASEADDR 0x3C44 /* address in NIC memory */ 1144#define BGE_FLOW_ATTN 0x3C48 1145#define BGE_HCC_JUMBO_BD_CONS 0x3C50 1146#define BGE_HCC_STD_BD_CONS 0x3C54 1147#define BGE_HCC_MINI_BD_CONS 0x3C58 1148#define BGE_HCC_RX_RETURN_PROD0 0x3C80 1149#define BGE_HCC_RX_RETURN_PROD1 0x3C84 1150#define BGE_HCC_RX_RETURN_PROD2 0x3C88 1151#define BGE_HCC_RX_RETURN_PROD3 0x3C8C 1152#define BGE_HCC_RX_RETURN_PROD4 0x3C90 1153#define BGE_HCC_RX_RETURN_PROD5 0x3C94 1154#define BGE_HCC_RX_RETURN_PROD6 0x3C98 1155#define BGE_HCC_RX_RETURN_PROD7 0x3C9C 1156#define BGE_HCC_RX_RETURN_PROD8 0x3CA0 1157#define BGE_HCC_RX_RETURN_PROD9 0x3CA4 1158#define BGE_HCC_RX_RETURN_PROD10 0x3CA8 1159#define BGE_HCC_RX_RETURN_PROD11 0x3CAC 1160#define BGE_HCC_RX_RETURN_PROD12 0x3CB0 1161#define BGE_HCC_RX_RETURN_PROD13 0x3CB4 1162#define BGE_HCC_RX_RETURN_PROD14 0x3CB8 1163#define BGE_HCC_RX_RETURN_PROD15 0x3CBC 1164#define BGE_HCC_TX_BD_CONS0 0x3CC0 1165#define BGE_HCC_TX_BD_CONS1 0x3CC4 1166#define BGE_HCC_TX_BD_CONS2 0x3CC8 1167#define BGE_HCC_TX_BD_CONS3 0x3CCC 1168#define BGE_HCC_TX_BD_CONS4 0x3CD0 1169#define BGE_HCC_TX_BD_CONS5 0x3CD4 1170#define BGE_HCC_TX_BD_CONS6 0x3CD8 1171#define BGE_HCC_TX_BD_CONS7 0x3CDC 1172#define BGE_HCC_TX_BD_CONS8 0x3CE0 1173#define BGE_HCC_TX_BD_CONS9 0x3CE4 1174#define BGE_HCC_TX_BD_CONS10 0x3CE8 1175#define BGE_HCC_TX_BD_CONS11 0x3CEC 1176#define BGE_HCC_TX_BD_CONS12 0x3CF0 1177#define BGE_HCC_TX_BD_CONS13 0x3CF4 1178#define BGE_HCC_TX_BD_CONS14 0x3CF8 1179#define BGE_HCC_TX_BD_CONS15 0x3CFC 1180 1181 1182/* Host coalescing mode register */ 1183#define BGE_HCCMODE_RESET 0x00000001 1184#define BGE_HCCMODE_ENABLE 0x00000002 1185#define BGE_HCCMODE_ATTN 0x00000004 1186#define BGE_HCCMODE_COAL_NOW 0x00000008 1187#define BGE_HCCMODE_MSI_BITS 0x00000070 1188#define BGE_HCCMODE_STATBLK_SIZE 0x00000180 1189 1190#define BGE_STATBLKSZ_FULL 0x00000000 1191#define BGE_STATBLKSZ_64BYTE 0x00000080 1192#define BGE_STATBLKSZ_32BYTE 0x00000100 1193 1194/* Host coalescing status register */ 1195#define BGE_HCCSTAT_ERROR 0x00000004 1196 1197/* Flow attention register */ 1198#define BGE_FLOWATTN_MB_LOWAT 0x00000040 1199#define BGE_FLOWATTN_MEMARB 0x00000080 1200#define BGE_FLOWATTN_HOSTCOAL 0x00008000 1201#define BGE_FLOWATTN_DMADONE_DISCARD 0x00010000 1202#define BGE_FLOWATTN_RCB_INVAL 0x00020000 1203#define BGE_FLOWATTN_RXDATA_CORRUPT 0x00040000 1204#define BGE_FLOWATTN_RDBDI 0x00080000 1205#define BGE_FLOWATTN_RXLS 0x00100000 1206#define BGE_FLOWATTN_RXLP 0x00200000 1207#define BGE_FLOWATTN_RBDC 0x00400000 1208#define BGE_FLOWATTN_RBDI 0x00800000 1209#define BGE_FLOWATTN_SDC 0x08000000 1210#define BGE_FLOWATTN_SDI 0x10000000 1211#define BGE_FLOWATTN_SRS 0x20000000 1212#define BGE_FLOWATTN_SBDC 0x40000000 1213#define BGE_FLOWATTN_SBDI 0x80000000 1214 1215/* 1216 * Memory arbiter registers 1217 */ 1218#define BGE_MARB_MODE 0x4000 1219#define BGE_MARB_STATUS 0x4004 1220#define BGE_MARB_TRAPADDR_HI 0x4008 1221#define BGE_MARB_TRAPADDR_LO 0x400C 1222 1223/* Memory arbiter mode register */ 1224#define BGE_MARBMODE_RESET 0x00000001 1225#define BGE_MARBMODE_ENABLE 0x00000002 1226#define BGE_MARBMODE_TX_ADDR_TRAP 0x00000004 1227#define BGE_MARBMODE_RX_ADDR_TRAP 0x00000008 1228#define BGE_MARBMODE_DMAW1_TRAP 0x00000010 1229#define BGE_MARBMODE_DMAR1_TRAP 0x00000020 1230#define BGE_MARBMODE_RXRISC_TRAP 0x00000040 1231#define BGE_MARBMODE_TXRISC_TRAP 0x00000080 1232#define BGE_MARBMODE_PCI_TRAP 0x00000100 1233#define BGE_MARBMODE_DMAR2_TRAP 0x00000200 1234#define BGE_MARBMODE_RXQ_TRAP 0x00000400 1235#define BGE_MARBMODE_RXDI1_TRAP 0x00000800 1236#define BGE_MARBMODE_RXDI2_TRAP 0x00001000 1237#define BGE_MARBMODE_DC_GRPMEM_TRAP 0x00002000 1238#define BGE_MARBMODE_HCOAL_TRAP 0x00004000 1239#define BGE_MARBMODE_MBUF_TRAP 0x00008000 1240#define BGE_MARBMODE_TXDI_TRAP 0x00010000 1241#define BGE_MARBMODE_SDC_DMAC_TRAP 0x00020000 1242#define BGE_MARBMODE_TXBD_TRAP 0x00040000 1243#define BGE_MARBMODE_BUFFMAN_TRAP 0x00080000 1244#define BGE_MARBMODE_DMAW2_TRAP 0x00100000 1245#define BGE_MARBMODE_XTSSRAM_ROFLO_TRAP 0x00200000 1246#define BGE_MARBMODE_XTSSRAM_RUFLO_TRAP 0x00400000 1247#define BGE_MARBMODE_XTSSRAM_WOFLO_TRAP 0x00800000 1248#define BGE_MARBMODE_XTSSRAM_WUFLO_TRAP 0x01000000 1249#define BGE_MARBMODE_XTSSRAM_PERR_TRAP 0x02000000 1250 1251/* Memory arbiter status register */ 1252#define BGE_MARBSTAT_TX_ADDR_TRAP 0x00000004 1253#define BGE_MARBSTAT_RX_ADDR_TRAP 0x00000008 1254#define BGE_MARBSTAT_DMAW1_TRAP 0x00000010 1255#define BGE_MARBSTAT_DMAR1_TRAP 0x00000020 1256#define BGE_MARBSTAT_RXRISC_TRAP 0x00000040 1257#define BGE_MARBSTAT_TXRISC_TRAP 0x00000080 1258#define BGE_MARBSTAT_PCI_TRAP 0x00000100 1259#define BGE_MARBSTAT_DMAR2_TRAP 0x00000200 1260#define BGE_MARBSTAT_RXQ_TRAP 0x00000400 1261#define BGE_MARBSTAT_RXDI1_TRAP 0x00000800 1262#define BGE_MARBSTAT_RXDI2_TRAP 0x00001000 1263#define BGE_MARBSTAT_DC_GRPMEM_TRAP 0x00002000 1264#define BGE_MARBSTAT_HCOAL_TRAP 0x00004000 1265#define BGE_MARBSTAT_MBUF_TRAP 0x00008000 1266#define BGE_MARBSTAT_TXDI_TRAP 0x00010000 1267#define BGE_MARBSTAT_SDC_DMAC_TRAP 0x00020000 1268#define BGE_MARBSTAT_TXBD_TRAP 0x00040000 1269#define BGE_MARBSTAT_BUFFMAN_TRAP 0x00080000 1270#define BGE_MARBSTAT_DMAW2_TRAP 0x00100000 1271#define BGE_MARBSTAT_XTSSRAM_ROFLO_TRAP 0x00200000 1272#define BGE_MARBSTAT_XTSSRAM_RUFLO_TRAP 0x00400000 1273#define BGE_MARBSTAT_XTSSRAM_WOFLO_TRAP 0x00800000 1274#define BGE_MARBSTAT_XTSSRAM_WUFLO_TRAP 0x01000000 1275#define BGE_MARBSTAT_XTSSRAM_PERR_TRAP 0x02000000 1276 1277/* 1278 * Buffer manager control registers 1279 */ 1280#define BGE_BMAN_MODE 0x4400 1281#define BGE_BMAN_STATUS 0x4404 1282#define BGE_BMAN_MBUFPOOL_BASEADDR 0x4408 1283#define BGE_BMAN_MBUFPOOL_LEN 0x440C 1284#define BGE_BMAN_MBUFPOOL_READDMA_LOWAT 0x4410 1285#define BGE_BMAN_MBUFPOOL_MACRX_LOWAT 0x4414 1286#define BGE_BMAN_MBUFPOOL_HIWAT 0x4418 1287#define BGE_BMAN_RXCPU_MBALLOC_REQ 0x441C 1288#define BGE_BMAN_RXCPU_MBALLOC_RESP 0x4420 1289#define BGE_BMAN_TXCPU_MBALLOC_REQ 0x4424 1290#define BGE_BMAN_TXCPU_MBALLOC_RESP 0x4428 1291#define BGE_BMAN_DMA_DESCPOOL_BASEADDR 0x442C 1292#define BGE_BMAN_DMA_DESCPOOL_LEN 0x4430 1293#define BGE_BMAN_DMA_DESCPOOL_LOWAT 0x4434 1294#define BGE_BMAN_DMA_DESCPOOL_HIWAT 0x4438 1295#define BGE_BMAN_RXCPU_DMAALLOC_REQ 0x443C 1296#define BGE_BMAN_RXCPU_DMAALLOC_RESP 0x4440 1297#define BGE_BMAN_TXCPU_DMAALLOC_REQ 0x4444 1298#define BGE_BMAN_TXCPU_DMALLLOC_RESP 0x4448 1299#define BGE_BMAN_HWDIAG_1 0x444C 1300#define BGE_BMAN_HWDIAG_2 0x4450 1301#define BGE_BMAN_HWDIAG_3 0x4454 1302 1303/* Buffer manager mode register */ 1304#define BGE_BMANMODE_RESET 0x00000001 1305#define BGE_BMANMODE_ENABLE 0x00000002 1306#define BGE_BMANMODE_ATTN 0x00000004 1307#define BGE_BMANMODE_TESTMODE 0x00000008 1308#define BGE_BMANMODE_LOMBUF_ATTN 0x00000010 1309 1310/* Buffer manager status register */ 1311#define BGE_BMANSTAT_ERRO 0x00000004 1312#define BGE_BMANSTAT_LOWMBUF_ERROR 0x00000010 1313 1314 1315/* 1316 * Read DMA Control registers 1317 */ 1318#define BGE_RDMA_MODE 0x4800 1319#define BGE_RDMA_STATUS 0x4804 1320 1321/* Read DMA mode register */ 1322#define BGE_RDMAMODE_RESET 0x00000001 1323#define BGE_RDMAMODE_ENABLE 0x00000002 1324#define BGE_RDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1325#define BGE_RDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1326#define BGE_RDMAMODE_PCI_PERR_ATTN 0x00000010 1327#define BGE_RDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1328#define BGE_RDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1329#define BGE_RDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1330#define BGE_RDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1331#define BGE_RDMAMODE_LOCWRITE_TOOBIG 0x00000200 1332#define BGE_RDMAMODE_ALL_ATTNS 0x000003FC 1333 1334/* Read DMA status register */ 1335#define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1336#define BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1337#define BGE_RDMASTAT_PCI_PERR_ATTN 0x00000010 1338#define BGE_RDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1339#define BGE_RDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1340#define BGE_RDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1341#define BGE_RDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1342#define BGE_RDMASTAT_LOCWRITE_TOOBIG 0x00000200 1343 1344/* 1345 * Write DMA control registers 1346 */ 1347#define BGE_WDMA_MODE 0x4C00 1348#define BGE_WDMA_STATUS 0x4C04 1349 1350/* Write DMA mode register */ 1351#define BGE_WDMAMODE_RESET 0x00000001 1352#define BGE_WDMAMODE_ENABLE 0x00000002 1353#define BGE_WDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1354#define BGE_WDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1355#define BGE_WDMAMODE_PCI_PERR_ATTN 0x00000010 1356#define BGE_WDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1357#define BGE_WDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1358#define BGE_WDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1359#define BGE_WDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1360#define BGE_WDMAMODE_LOCREAD_TOOBIG 0x00000200 1361#define BGE_WDMAMODE_ALL_ATTNS 0x000003FC 1362 1363/* Write DMA status register */ 1364#define BGE_WDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1365#define BGE_WDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1366#define BGE_WDMASTAT_PCI_PERR_ATTN 0x00000010 1367#define BGE_WDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1368#define BGE_WDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1369#define BGE_WDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1370#define BGE_WDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1371#define BGE_WDMASTAT_LOCREAD_TOOBIG 0x00000200 1372 1373 1374/* 1375 * RX CPU registers 1376 */ 1377#define BGE_RXCPU_MODE 0x5000 1378#define BGE_RXCPU_STATUS 0x5004 1379#define BGE_RXCPU_PC 0x501C 1380 1381/* RX CPU mode register */ 1382#define BGE_RXCPUMODE_RESET 0x00000001 1383#define BGE_RXCPUMODE_SINGLESTEP 0x00000002 1384#define BGE_RXCPUMODE_P0_DATAHLT_ENB 0x00000004 1385#define BGE_RXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1386#define BGE_RXCPUMODE_WR_POSTBUF_ENB 0x00000010 1387#define BGE_RXCPUMODE_DATACACHE_ENB 0x00000020 1388#define BGE_RXCPUMODE_ROMFAIL 0x00000040 1389#define BGE_RXCPUMODE_WATCHDOG_ENB 0x00000080 1390#define BGE_RXCPUMODE_INSTRCACHE_PRF 0x00000100 1391#define BGE_RXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1392#define BGE_RXCPUMODE_HALTCPU 0x00000400 1393#define BGE_RXCPUMODE_INVDATAHLT_ENB 0x00000800 1394#define BGE_RXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1395#define BGE_RXCPUMODE_RADDRTRAPHLT_ENB 0x00002000 1396 1397/* RX CPU status register */ 1398#define BGE_RXCPUSTAT_HW_BREAKPOINT 0x00000001 1399#define BGE_RXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1400#define BGE_RXCPUSTAT_INVALID_INSTR 0x00000004 1401#define BGE_RXCPUSTAT_P0_DATAREF 0x00000008 1402#define BGE_RXCPUSTAT_P0_INSTRREF 0x00000010 1403#define BGE_RXCPUSTAT_INVALID_DATAACC 0x00000020 1404#define BGE_RXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1405#define BGE_RXCPUSTAT_BAD_MEMALIGN 0x00000080 1406#define BGE_RXCPUSTAT_MADDR_TRAP 0x00000100 1407#define BGE_RXCPUSTAT_REGADDR_TRAP 0x00000200 1408#define BGE_RXCPUSTAT_DATAACC_STALL 0x00001000 1409#define BGE_RXCPUSTAT_INSTRFETCH_STALL 0x00002000 1410#define BGE_RXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1411#define BGE_RXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1412#define BGE_RXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1413#define BGE_RXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1414#define BGE_RXCPUSTAT_BLOCKING_READ 0x80000000 1415 1416 1417/* 1418 * TX CPU registers 1419 */ 1420#define BGE_TXCPU_MODE 0x5400 1421#define BGE_TXCPU_STATUS 0x5404 1422#define BGE_TXCPU_PC 0x541C 1423 1424/* TX CPU mode register */ 1425#define BGE_TXCPUMODE_RESET 0x00000001 1426#define BGE_TXCPUMODE_SINGLESTEP 0x00000002 1427#define BGE_TXCPUMODE_P0_DATAHLT_ENB 0x00000004 1428#define BGE_TXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1429#define BGE_TXCPUMODE_WR_POSTBUF_ENB 0x00000010 1430#define BGE_TXCPUMODE_DATACACHE_ENB 0x00000020 1431#define BGE_TXCPUMODE_ROMFAIL 0x00000040 1432#define BGE_TXCPUMODE_WATCHDOG_ENB 0x00000080 1433#define BGE_TXCPUMODE_INSTRCACHE_PRF 0x00000100 1434#define BGE_TXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1435#define BGE_TXCPUMODE_HALTCPU 0x00000400 1436#define BGE_TXCPUMODE_INVDATAHLT_ENB 0x00000800 1437#define BGE_TXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1438 1439/* TX CPU status register */ 1440#define BGE_TXCPUSTAT_HW_BREAKPOINT 0x00000001 1441#define BGE_TXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1442#define BGE_TXCPUSTAT_INVALID_INSTR 0x00000004 1443#define BGE_TXCPUSTAT_P0_DATAREF 0x00000008 1444#define BGE_TXCPUSTAT_P0_INSTRREF 0x00000010 1445#define BGE_TXCPUSTAT_INVALID_DATAACC 0x00000020 1446#define BGE_TXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1447#define BGE_TXCPUSTAT_BAD_MEMALIGN 0x00000080 1448#define BGE_TXCPUSTAT_MADDR_TRAP 0x00000100 1449#define BGE_TXCPUSTAT_REGADDR_TRAP 0x00000200 1450#define BGE_TXCPUSTAT_DATAACC_STALL 0x00001000 1451#define BGE_TXCPUSTAT_INSTRFETCH_STALL 0x00002000 1452#define BGE_TXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1453#define BGE_TXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1454#define BGE_TXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1455#define BGE_TXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1456#define BGE_TXCPUSTAT_BLOCKING_READ 0x80000000 1457 1458 1459/* 1460 * Low priority mailbox registers 1461 */ 1462#define BGE_LPMBX_IRQ0_HI 0x5800 1463#define BGE_LPMBX_IRQ0_LO 0x5804 1464#define BGE_LPMBX_IRQ1_HI 0x5808 1465#define BGE_LPMBX_IRQ1_LO 0x580C 1466#define BGE_LPMBX_IRQ2_HI 0x5810 1467#define BGE_LPMBX_IRQ2_LO 0x5814 1468#define BGE_LPMBX_IRQ3_HI 0x5818 1469#define BGE_LPMBX_IRQ3_LO 0x581C 1470#define BGE_LPMBX_GEN0_HI 0x5820 1471#define BGE_LPMBX_GEN0_LO 0x5824 1472#define BGE_LPMBX_GEN1_HI 0x5828 1473#define BGE_LPMBX_GEN1_LO 0x582C 1474#define BGE_LPMBX_GEN2_HI 0x5830 1475#define BGE_LPMBX_GEN2_LO 0x5834 1476#define BGE_LPMBX_GEN3_HI 0x5828 1477#define BGE_LPMBX_GEN3_LO 0x582C 1478#define BGE_LPMBX_GEN4_HI 0x5840 1479#define BGE_LPMBX_GEN4_LO 0x5844 1480#define BGE_LPMBX_GEN5_HI 0x5848 1481#define BGE_LPMBX_GEN5_LO 0x584C 1482#define BGE_LPMBX_GEN6_HI 0x5850 1483#define BGE_LPMBX_GEN6_LO 0x5854 1484#define BGE_LPMBX_GEN7_HI 0x5858 1485#define BGE_LPMBX_GEN7_LO 0x585C 1486#define BGE_LPMBX_RELOAD_STATS_HI 0x5860 1487#define BGE_LPMBX_RELOAD_STATS_LO 0x5864 1488#define BGE_LPMBX_RX_STD_PROD_HI 0x5868 1489#define BGE_LPMBX_RX_STD_PROD_LO 0x586C 1490#define BGE_LPMBX_RX_JUMBO_PROD_HI 0x5870 1491#define BGE_LPMBX_RX_JUMBO_PROD_LO 0x5874 1492#define BGE_LPMBX_RX_MINI_PROD_HI 0x5878 1493#define BGE_LPMBX_RX_MINI_PROD_LO 0x587C 1494#define BGE_LPMBX_RX_CONS0_HI 0x5880 1495#define BGE_LPMBX_RX_CONS0_LO 0x5884 1496#define BGE_LPMBX_RX_CONS1_HI 0x5888 1497#define BGE_LPMBX_RX_CONS1_LO 0x588C 1498#define BGE_LPMBX_RX_CONS2_HI 0x5890 1499#define BGE_LPMBX_RX_CONS2_LO 0x5894 1500#define BGE_LPMBX_RX_CONS3_HI 0x5898 1501#define BGE_LPMBX_RX_CONS3_LO 0x589C 1502#define BGE_LPMBX_RX_CONS4_HI 0x58A0 1503#define BGE_LPMBX_RX_CONS4_LO 0x58A4 1504#define BGE_LPMBX_RX_CONS5_HI 0x58A8 1505#define BGE_LPMBX_RX_CONS5_LO 0x58AC 1506#define BGE_LPMBX_RX_CONS6_HI 0x58B0 1507#define BGE_LPMBX_RX_CONS6_LO 0x58B4 1508#define BGE_LPMBX_RX_CONS7_HI 0x58B8 1509#define BGE_LPMBX_RX_CONS7_LO 0x58BC 1510#define BGE_LPMBX_RX_CONS8_HI 0x58C0 1511#define BGE_LPMBX_RX_CONS8_LO 0x58C4 1512#define BGE_LPMBX_RX_CONS9_HI 0x58C8 1513#define BGE_LPMBX_RX_CONS9_LO 0x58CC 1514#define BGE_LPMBX_RX_CONS10_HI 0x58D0 1515#define BGE_LPMBX_RX_CONS10_LO 0x58D4 1516#define BGE_LPMBX_RX_CONS11_HI 0x58D8 1517#define BGE_LPMBX_RX_CONS11_LO 0x58DC 1518#define BGE_LPMBX_RX_CONS12_HI 0x58E0 1519#define BGE_LPMBX_RX_CONS12_LO 0x58E4 1520#define BGE_LPMBX_RX_CONS13_HI 0x58E8 1521#define BGE_LPMBX_RX_CONS13_LO 0x58EC 1522#define BGE_LPMBX_RX_CONS14_HI 0x58F0 1523#define BGE_LPMBX_RX_CONS14_LO 0x58F4 1524#define BGE_LPMBX_RX_CONS15_HI 0x58F8 1525#define BGE_LPMBX_RX_CONS15_LO 0x58FC 1526#define BGE_LPMBX_TX_HOST_PROD0_HI 0x5900 1527#define BGE_LPMBX_TX_HOST_PROD0_LO 0x5904 1528#define BGE_LPMBX_TX_HOST_PROD1_HI 0x5908 1529#define BGE_LPMBX_TX_HOST_PROD1_LO 0x590C 1530#define BGE_LPMBX_TX_HOST_PROD2_HI 0x5910 1531#define BGE_LPMBX_TX_HOST_PROD2_LO 0x5914 1532#define BGE_LPMBX_TX_HOST_PROD3_HI 0x5918 1533#define BGE_LPMBX_TX_HOST_PROD3_LO 0x591C 1534#define BGE_LPMBX_TX_HOST_PROD4_HI 0x5920 1535#define BGE_LPMBX_TX_HOST_PROD4_LO 0x5924 1536#define BGE_LPMBX_TX_HOST_PROD5_HI 0x5928 1537#define BGE_LPMBX_TX_HOST_PROD5_LO 0x592C 1538#define BGE_LPMBX_TX_HOST_PROD6_HI 0x5930 1539#define BGE_LPMBX_TX_HOST_PROD6_LO 0x5934 1540#define BGE_LPMBX_TX_HOST_PROD7_HI 0x5938 1541#define BGE_LPMBX_TX_HOST_PROD7_LO 0x593C 1542#define BGE_LPMBX_TX_HOST_PROD8_HI 0x5940 1543#define BGE_LPMBX_TX_HOST_PROD8_LO 0x5944 1544#define BGE_LPMBX_TX_HOST_PROD9_HI 0x5948 1545#define BGE_LPMBX_TX_HOST_PROD9_LO 0x594C 1546#define BGE_LPMBX_TX_HOST_PROD10_HI 0x5950 1547#define BGE_LPMBX_TX_HOST_PROD10_LO 0x5954 1548#define BGE_LPMBX_TX_HOST_PROD11_HI 0x5958 1549#define BGE_LPMBX_TX_HOST_PROD11_LO 0x595C 1550#define BGE_LPMBX_TX_HOST_PROD12_HI 0x5960 1551#define BGE_LPMBX_TX_HOST_PROD12_LO 0x5964 1552#define BGE_LPMBX_TX_HOST_PROD13_HI 0x5968 1553#define BGE_LPMBX_TX_HOST_PROD13_LO 0x596C 1554#define BGE_LPMBX_TX_HOST_PROD14_HI 0x5970 1555#define BGE_LPMBX_TX_HOST_PROD14_LO 0x5974 1556#define BGE_LPMBX_TX_HOST_PROD15_HI 0x5978 1557#define BGE_LPMBX_TX_HOST_PROD15_LO 0x597C 1558#define BGE_LPMBX_TX_NIC_PROD0_HI 0x5980 1559#define BGE_LPMBX_TX_NIC_PROD0_LO 0x5984 1560#define BGE_LPMBX_TX_NIC_PROD1_HI 0x5988 1561#define BGE_LPMBX_TX_NIC_PROD1_LO 0x598C 1562#define BGE_LPMBX_TX_NIC_PROD2_HI 0x5990 1563#define BGE_LPMBX_TX_NIC_PROD2_LO 0x5994 1564#define BGE_LPMBX_TX_NIC_PROD3_HI 0x5998 1565#define BGE_LPMBX_TX_NIC_PROD3_LO 0x599C 1566#define BGE_LPMBX_TX_NIC_PROD4_HI 0x59A0 1567#define BGE_LPMBX_TX_NIC_PROD4_LO 0x59A4 1568#define BGE_LPMBX_TX_NIC_PROD5_HI 0x59A8 1569#define BGE_LPMBX_TX_NIC_PROD5_LO 0x59AC 1570#define BGE_LPMBX_TX_NIC_PROD6_HI 0x59B0 1571#define BGE_LPMBX_TX_NIC_PROD6_LO 0x59B4 1572#define BGE_LPMBX_TX_NIC_PROD7_HI 0x59B8 1573#define BGE_LPMBX_TX_NIC_PROD7_LO 0x59BC 1574#define BGE_LPMBX_TX_NIC_PROD8_HI 0x59C0 1575#define BGE_LPMBX_TX_NIC_PROD8_LO 0x59C4 1576#define BGE_LPMBX_TX_NIC_PROD9_HI 0x59C8 1577#define BGE_LPMBX_TX_NIC_PROD9_LO 0x59CC 1578#define BGE_LPMBX_TX_NIC_PROD10_HI 0x59D0 1579#define BGE_LPMBX_TX_NIC_PROD10_LO 0x59D4 1580#define BGE_LPMBX_TX_NIC_PROD11_HI 0x59D8 1581#define BGE_LPMBX_TX_NIC_PROD11_LO 0x59DC 1582#define BGE_LPMBX_TX_NIC_PROD12_HI 0x59E0 1583#define BGE_LPMBX_TX_NIC_PROD12_LO 0x59E4 1584#define BGE_LPMBX_TX_NIC_PROD13_HI 0x59E8 1585#define BGE_LPMBX_TX_NIC_PROD13_LO 0x59EC 1586#define BGE_LPMBX_TX_NIC_PROD14_HI 0x59F0 1587#define BGE_LPMBX_TX_NIC_PROD14_LO 0x59F4 1588#define BGE_LPMBX_TX_NIC_PROD15_HI 0x59F8 1589#define BGE_LPMBX_TX_NIC_PROD15_LO 0x59FC 1590 1591/* 1592 * Flow throw Queue reset register 1593 */ 1594#define BGE_FTQ_RESET 0x5C00 1595 1596#define BGE_FTQRESET_DMAREAD 0x00000002 1597#define BGE_FTQRESET_DMAHIPRIO_RD 0x00000004 1598#define BGE_FTQRESET_DMADONE 0x00000010 1599#define BGE_FTQRESET_SBDC 0x00000020 1600#define BGE_FTQRESET_SDI 0x00000040 1601#define BGE_FTQRESET_WDMA 0x00000080 1602#define BGE_FTQRESET_DMAHIPRIO_WR 0x00000100 1603#define BGE_FTQRESET_TYPE1_SOFTWARE 0x00000200 1604#define BGE_FTQRESET_SDC 0x00000400 1605#define BGE_FTQRESET_HCC 0x00000800 1606#define BGE_FTQRESET_TXFIFO 0x00001000 1607#define BGE_FTQRESET_MBC 0x00002000 1608#define BGE_FTQRESET_RBDC 0x00004000 1609#define BGE_FTQRESET_RXLP 0x00008000 1610#define BGE_FTQRESET_RDBDI 0x00010000 1611#define BGE_FTQRESET_RDC 0x00020000 1612#define BGE_FTQRESET_TYPE2_SOFTWARE 0x00040000 1613 1614/* 1615 * Message Signaled Interrupt registers 1616 */ 1617#define BGE_MSI_MODE 0x6000 1618#define BGE_MSI_STATUS 0x6004 1619#define BGE_MSI_FIFOACCESS 0x6008 1620 1621/* MSI mode register */ 1622#define BGE_MSIMODE_RESET 0x00000001 1623#define BGE_MSIMODE_ENABLE 0x00000002 1624#define BGE_MSIMODE_PCI_TGT_ABRT_ATTN 0x00000004 1625#define BGE_MSIMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1626#define BGE_MSIMODE_PCI_PERR_ATTN 0x00000010 1627#define BGE_MSIMODE_MSI_FIFOUFLOW_ATTN 0x00000020 1628#define BGE_MSIMODE_MSI_FIFOOFLOW_ATTN 0x00000040 1629 1630/* MSI status register */ 1631#define BGE_MSISTAT_PCI_TGT_ABRT_ATTN 0x00000004 1632#define BGE_MSISTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1633#define BGE_MSISTAT_PCI_PERR_ATTN 0x00000010 1634#define BGE_MSISTAT_MSI_FIFOUFLOW_ATTN 0x00000020 1635#define BGE_MSISTAT_MSI_FIFOOFLOW_ATTN 0x00000040 1636 1637 1638/* 1639 * DMA Completion registers 1640 */ 1641#define BGE_DMAC_MODE 0x6400 1642 1643/* DMA Completion mode register */ 1644#define BGE_DMACMODE_RESET 0x00000001 1645#define BGE_DMACMODE_ENABLE 0x00000002 1646 1647 1648/* 1649 * General control registers. 1650 */ 1651#define BGE_MODE_CTL 0x6800 1652#define BGE_MISC_CFG 0x6804 1653#define BGE_MISC_LOCAL_CTL 0x6808 1654#define BGE_EE_ADDR 0x6838 1655#define BGE_EE_DATA 0x683C 1656#define BGE_EE_CTL 0x6840 1657#define BGE_MDI_CTL 0x6844 1658#define BGE_EE_DELAY 0x6848 1659 1660/* Mode control register */ 1661#define BGE_MODECTL_INT_SNDCOAL_ONLY 0x00000001 1662#define BGE_MODECTL_BYTESWAP_NONFRAME 0x00000002 1663#define BGE_MODECTL_WORDSWAP_NONFRAME 0x00000004 1664#define BGE_MODECTL_BYTESWAP_DATA 0x00000010 1665#define BGE_MODECTL_WORDSWAP_DATA 0x00000020 1666#define BGE_MODECTL_NO_FRAME_CRACKING 0x00000200 1667#define BGE_MODECTL_NO_RX_CRC 0x00000400 1668#define BGE_MODECTL_RX_BADFRAMES 0x00000800 1669#define BGE_MODECTL_NO_TX_INTR 0x00002000 1670#define BGE_MODECTL_NO_RX_INTR 0x00004000 1671#define BGE_MODECTL_FORCE_PCI32 0x00008000 1672#define BGE_MODECTL_STACKUP 0x00010000 1673#define BGE_MODECTL_HOST_SEND_BDS 0x00020000 1674#define BGE_MODECTL_TX_NO_PHDR_CSUM 0x00100000 1675#define BGE_MODECTL_RX_NO_PHDR_CSUM 0x00800000 1676#define BGE_MODECTL_TX_ATTN_INTR 0x01000000 1677#define BGE_MODECTL_RX_ATTN_INTR 0x02000000 1678#define BGE_MODECTL_MAC_ATTN_INTR 0x04000000 1679#define BGE_MODECTL_DMA_ATTN_INTR 0x08000000 1680#define BGE_MODECTL_FLOWCTL_ATTN_INTR 0x10000000 1681#define BGE_MODECTL_4X_SENDRING_SZ 0x20000000 1682#define BGE_MODECTL_FW_PROCESS_MCASTS 0x40000000 1683 1684/* Misc. config register */ 1685#define BGE_MISCCFG_RESET_CORE_CLOCKS 0x00000001 1686#define BGE_MISCCFG_TIMER_PRESCALER 0x000000FE 1687 1688#define BGE_32BITTIME_66MHZ (0x41 << 1) 1689 1690/* Misc. Local Control */ 1691#define BGE_MLC_INTR_STATE 0x00000001 1692#define BGE_MLC_INTR_CLR 0x00000002 1693#define BGE_MLC_INTR_SET 0x00000004 1694#define BGE_MLC_INTR_ONATTN 0x00000008 1695#define BGE_MLC_MISCIO_IN0 0x00000100 1696#define BGE_MLC_MISCIO_IN1 0x00000200 1697#define BGE_MLC_MISCIO_IN2 0x00000400 1698#define BGE_MLC_MISCIO_OUTEN0 0x00000800 1699#define BGE_MLC_MISCIO_OUTEN1 0x00001000 1700#define BGE_MLC_MISCIO_OUTEN2 0x00002000 1701#define BGE_MLC_MISCIO_OUT0 0x00004000 1702#define BGE_MLC_MISCIO_OUT1 0x00008000 1703#define BGE_MLC_MISCIO_OUT2 0x00010000 1704#define BGE_MLC_EXTRAM_ENB 0x00020000 1705#define BGE_MLC_SRAM_SIZE 0x001C0000 1706#define BGE_MLC_BANK_SEL 0x00200000 /* 0 = 2 banks, 1 == 1 */ 1707#define BGE_MLC_SSRAM_TYPE 0x00400000 /* 1 = ZBT, 0 = standard */ 1708#define BGE_MLC_SSRAM_CYC_DESEL 0x00800000 1709#define BGE_MLC_AUTO_EEPROM 0x01000000 1710 1711#define BGE_SSRAMSIZE_256KB 0x00000000 1712#define BGE_SSRAMSIZE_512KB 0x00040000 1713#define BGE_SSRAMSIZE_1MB 0x00080000 1714#define BGE_SSRAMSIZE_2MB 0x000C0000 1715#define BGE_SSRAMSIZE_4MB 0x00100000 1716#define BGE_SSRAMSIZE_8MB 0x00140000 1717#define BGE_SSRAMSIZE_16M 0x00180000 1718 1719/* EEPROM address register */ 1720#define BGE_EEADDR_ADDRESS 0x0000FFFC 1721#define BGE_EEADDR_HALFCLK 0x01FF0000 1722#define BGE_EEADDR_START 0x02000000 1723#define BGE_EEADDR_DEVID 0x1C000000 1724#define BGE_EEADDR_RESET 0x20000000 1725#define BGE_EEADDR_DONE 0x40000000 1726#define BGE_EEADDR_RW 0x80000000 /* 1 = rd, 0 = wr */ 1727 1728#define BGE_EEDEVID(x) ((x & 7) << 26) 1729#define BGE_EEHALFCLK(x) ((x & 0x1FF) << 16) 1730#define BGE_HALFCLK_384SCL 0x60 1731#define BGE_EE_READCMD \ 1732 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 1733 BGE_EEADDR_START|BGE_EEADDR_RW|BGE_EEADDR_DONE) 1734#define BGE_EE_WRCMD \ 1735 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 1736 BGE_EEADDR_START|BGE_EEADDR_DONE) 1737 1738/* EEPROM Control register */ 1739#define BGE_EECTL_CLKOUT_TRISTATE 0x00000001 1740#define BGE_EECTL_CLKOUT 0x00000002 1741#define BGE_EECTL_CLKIN 0x00000004 1742#define BGE_EECTL_DATAOUT_TRISTATE 0x00000008 1743#define BGE_EECTL_DATAOUT 0x00000010 1744#define BGE_EECTL_DATAIN 0x00000020 1745 1746/* MDI (MII/GMII) access register */ 1747#define BGE_MDI_DATA 0x00000001 1748#define BGE_MDI_DIR 0x00000002 1749#define BGE_MDI_SEL 0x00000004 1750#define BGE_MDI_CLK 0x00000008 1751 1752#define BGE_MEMWIN_START 0x00008000 1753#define BGE_MEMWIN_END 0x0000FFFF 1754 1755 1756#define BGE_MEMWIN_READ(sc, x, val) \ 1757 do { \ 1758 pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \ 1759 (0xFFFF0000 & x), 4); \ 1760 val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \ 1761 } while(0) 1762 1763#define BGE_MEMWIN_WRITE(sc, x, val) \ 1764 do { \ 1765 pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \ 1766 (0xFFFF0000 & x), 4); \ 1767 CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val); \ 1768 } while(0) 1769 1770/* 1771 * This magic number is used to prevent PXE restart when we 1772 * issue a software reset. We write this magic number to the 1773 * firmware mailbox at 0xB50 in order to prevent the PXE boot 1774 * code from running. 1775 */ 1776#define BGE_MAGIC_NUMBER 0x4B657654 1777 1778typedef struct { 1779 uint32_t bge_addr_hi; 1780 uint32_t bge_addr_lo; 1781} bge_hostaddr; 1782 1783#define BGE_HOSTADDR(x, y) \ 1784 do { \ 1785 (x).bge_addr_lo = ((uint64_t) (y) & 0xffffffff); \ 1786 (x).bge_addr_hi = ((uint64_t) (y) >> 32); \ 1787 } while(0) 1788 1789#define BGE_ADDR_LO(y) \ 1790 ((uint64_t) (y) & 0xFFFFFFFF) 1791#define BGE_ADDR_HI(y) \ 1792 ((uint64_t) (y) >> 32) 1793 1794/* Ring control block structure */ 1795struct bge_rcb { 1796 bge_hostaddr bge_hostaddr; 1797 uint32_t bge_maxlen_flags; 1798 uint32_t bge_nicaddr; 1799}; 1800 1801#define RCB_WRITE_4(sc, rcb, offset, val) \ 1802 bus_space_write_4(sc->bge_btag, sc->bge_bhandle, \ 1803 rcb + offsetof(struct bge_rcb, offset), val) 1804#define BGE_RCB_MAXLEN_FLAGS(maxlen, flags) ((maxlen) << 16 | (flags)) 1805 1806#define BGE_RCB_FLAG_USE_EXT_RX_BD 0x0001 1807#define BGE_RCB_FLAG_RING_DISABLED 0x0002 1808 1809struct bge_tx_bd { 1810 bge_hostaddr bge_addr; 1811#if BYTE_ORDER == LITTLE_ENDIAN 1812 uint16_t bge_flags; 1813 uint16_t bge_len; 1814 uint16_t bge_vlan_tag; 1815 uint16_t bge_rsvd; 1816#else 1817 uint16_t bge_len; 1818 uint16_t bge_flags; 1819 uint16_t bge_rsvd; 1820 uint16_t bge_vlan_tag; 1821#endif 1822}; 1823 1824#define BGE_TXBDFLAG_TCP_UDP_CSUM 0x0001 1825#define BGE_TXBDFLAG_IP_CSUM 0x0002 1826#define BGE_TXBDFLAG_END 0x0004 1827#define BGE_TXBDFLAG_IP_FRAG 0x0008 1828#define BGE_TXBDFLAG_IP_FRAG_END 0x0010 1829#define BGE_TXBDFLAG_VLAN_TAG 0x0040 1830#define BGE_TXBDFLAG_COAL_NOW 0x0080 1831#define BGE_TXBDFLAG_CPU_PRE_DMA 0x0100 1832#define BGE_TXBDFLAG_CPU_POST_DMA 0x0200 1833#define BGE_TXBDFLAG_INSERT_SRC_ADDR 0x1000 1834#define BGE_TXBDFLAG_CHOOSE_SRC_ADDR 0x6000 1835#define BGE_TXBDFLAG_NO_CRC 0x8000 1836 1837#define BGE_NIC_TXRING_ADDR(ringno, size) \ 1838 BGE_SEND_RING_1_TO_4 + \ 1839 ((ringno * sizeof(struct bge_tx_bd) * size) / 4) 1840 1841struct bge_rx_bd { 1842 bge_hostaddr bge_addr; 1843#if BYTE_ORDER == LITTLE_ENDIAN 1844 uint16_t bge_len; 1845 uint16_t bge_idx; 1846 uint16_t bge_flags; 1847 uint16_t bge_type; 1848 uint16_t bge_tcp_udp_csum; 1849 uint16_t bge_ip_csum; 1850 uint16_t bge_vlan_tag; 1851 uint16_t bge_error_flag; 1852#else 1853 uint16_t bge_idx; 1854 uint16_t bge_len; 1855 uint16_t bge_type; 1856 uint16_t bge_flags; 1857 uint16_t bge_ip_csum; 1858 uint16_t bge_tcp_udp_csum; 1859 uint16_t bge_error_flag; 1860 uint16_t bge_vlan_tag; 1861#endif 1862 uint32_t bge_rsvd; 1863 uint32_t bge_opaque; 1864}; 1865 1866struct bge_extrx_bd { 1867 bge_hostaddr bge_addr1; 1868 bge_hostaddr bge_addr2; 1869 bge_hostaddr bge_addr3; 1870#if BYTE_ORDER == LITTLE_ENDIAN 1871 uint16_t bge_len2; 1872 uint16_t bge_len1; 1873 uint16_t bge_rsvd1; 1874 uint16_t bge_len3; 1875#else 1876 uint16_t bge_len1; 1877 uint16_t bge_len2; 1878 uint16_t bge_len3; 1879 uint16_t bge_rsvd1; 1880#endif 1881 bge_hostaddr bge_addr0; 1882#if BYTE_ORDER == LITTLE_ENDIAN 1883 uint16_t bge_len0; 1884 uint16_t bge_idx; 1885 uint16_t bge_flags; 1886 uint16_t bge_type; 1887 uint16_t bge_tcp_udp_csum; 1888 uint16_t bge_ip_csum; 1889 uint16_t bge_vlan_tag; 1890 uint16_t bge_error_flag; 1891#else 1892 uint16_t bge_idx; 1893 uint16_t bge_len0; 1894 uint16_t bge_type; 1895 uint16_t bge_flags; 1896 uint16_t bge_ip_csum; 1897 uint16_t bge_tcp_udp_csum; 1898 uint16_t bge_error_flag; 1899 uint16_t bge_vlan_tag; 1900#endif 1901 uint32_t bge_rsvd0; 1902 uint32_t bge_opaque; 1903}; 1904 1905#define BGE_RXBDFLAG_END 0x0004 1906#define BGE_RXBDFLAG_JUMBO_RING 0x0020 1907#define BGE_RXBDFLAG_VLAN_TAG 0x0040 1908#define BGE_RXBDFLAG_ERROR 0x0400 1909#define BGE_RXBDFLAG_MINI_RING 0x0800 1910#define BGE_RXBDFLAG_IP_CSUM 0x1000 1911#define BGE_RXBDFLAG_TCP_UDP_CSUM 0x2000 1912#define BGE_RXBDFLAG_TCP_UDP_IS_TCP 0x4000 1913 1914#define BGE_RXERRFLAG_BAD_CRC 0x0001 1915#define BGE_RXERRFLAG_COLL_DETECT 0x0002 1916#define BGE_RXERRFLAG_LINK_LOST 0x0004 1917#define BGE_RXERRFLAG_PHY_DECODE_ERR 0x0008 1918#define BGE_RXERRFLAG_MAC_ABORT 0x0010 1919#define BGE_RXERRFLAG_RUNT 0x0020 1920#define BGE_RXERRFLAG_TRUNC_NO_RSRCS 0x0040 1921#define BGE_RXERRFLAG_GIANT 0x0080 1922 1923struct bge_sts_idx { 1924#if BYTE_ORDER == LITTLE_ENDIAN 1925 uint16_t bge_rx_prod_idx; 1926 uint16_t bge_tx_cons_idx; 1927#else 1928 uint16_t bge_tx_cons_idx; 1929 uint16_t bge_rx_prod_idx; 1930#endif 1931}; 1932 1933struct bge_status_block { 1934 uint32_t bge_status; 1935 uint32_t bge_rsvd0; 1936#if BYTE_ORDER == LITTLE_ENDIAN 1937 uint16_t bge_rx_jumbo_cons_idx; 1938 uint16_t bge_rx_std_cons_idx; 1939 uint16_t bge_rx_mini_cons_idx; 1940 uint16_t bge_rsvd1; 1941#else 1942 uint16_t bge_rx_std_cons_idx; 1943 uint16_t bge_rx_jumbo_cons_idx; 1944 uint16_t bge_rsvd1; 1945 uint16_t bge_rx_mini_cons_idx; 1946#endif 1947 struct bge_sts_idx bge_idx[16]; 1948}; 1949 1950#define BGE_TX_CONSIDX(x, i) x->bge_idx[i].bge_tx_considx 1951#define BGE_RX_PRODIDX(x, i) x->bge_idx[i].bge_rx_prodidx 1952 1953#define BGE_STATFLAG_UPDATED 0x00000001 1954#define BGE_STATFLAG_LINKSTATE_CHANGED 0x00000002 1955#define BGE_STATFLAG_ERROR 0x00000004 1956 1957 1958/* 1959 * Broadcom Vendor ID 1960 * (Note: the BCM570x still defaults to the Alteon PCI vendor ID 1961 * even though they're now manufactured by Broadcom) 1962 */ 1963#define BCOM_VENDORID 0x14E4 1964#define BCOM_DEVICEID_BCM5700 0x1644 1965#define BCOM_DEVICEID_BCM5701 0x1645 1966#define BCOM_DEVICEID_BCM5702 0x1646 1967#define BCOM_DEVICEID_BCM5702X 0x16A6 1968#define BCOM_DEVICEID_BCM5702_ALT 0x16C6 1969#define BCOM_DEVICEID_BCM5703 0x1647 1970#define BCOM_DEVICEID_BCM5703X 0x16A7 1971#define BCOM_DEVICEID_BCM5703_ALT 0x16C7 1972#define BCOM_DEVICEID_BCM5704C 0x1648 1973#define BCOM_DEVICEID_BCM5704S 0x16A8 1974#define BCOM_DEVICEID_BCM5704S_ALT 0x1649 1975#define BCOM_DEVICEID_BCM5705 0x1653 1976#define BCOM_DEVICEID_BCM5705K 0x1654 1977#define BCOM_DEVICEID_BCM5705F 0x166E 1978#define BCOM_DEVICEID_BCM5705M 0x165D 1979#define BCOM_DEVICEID_BCM5705M_ALT 0x165E 1980#define BCOM_DEVICEID_BCM5714C 0x1668 1981#define BCOM_DEVICEID_BCM5714S 0x1669 1982#define BCOM_DEVICEID_BCM5715 0x1678 1983#define BCOM_DEVICEID_BCM5715S 0x1679 1984#define BCOM_DEVICEID_BCM5720 0x1658 1985#define BCOM_DEVICEID_BCM5721 0x1659 1986#define BCOM_DEVICEID_BCM5750 0x1676 1987#define BCOM_DEVICEID_BCM5750M 0x167C 1988#define BCOM_DEVICEID_BCM5751 0x1677 1989#define BCOM_DEVICEID_BCM5751F 0x167E 1990#define BCOM_DEVICEID_BCM5751M 0x167D 1991#define BCOM_DEVICEID_BCM5752 0x1600 1992#define BCOM_DEVICEID_BCM5752M 0x1601 1993#define BCOM_DEVICEID_BCM5753 0x16F7 1994#define BCOM_DEVICEID_BCM5753F 0x16FE 1995#define BCOM_DEVICEID_BCM5753M 0x16FD 1996#define BCOM_DEVICEID_BCM5754 0x167A 1997#define BCOM_DEVICEID_BCM5754M 0x1672 1998#define BCOM_DEVICEID_BCM5755 0x167B 1999#define BCOM_DEVICEID_BCM5755M 0x1673 2000#define BCOM_DEVICEID_BCM5780 0x166A 2001#define BCOM_DEVICEID_BCM5780S 0x166B 2002#define BCOM_DEVICEID_BCM5781 0x16DD 2003#define BCOM_DEVICEID_BCM5782 0x1696 2004#define BCOM_DEVICEID_BCM5786 0x169A 2005#define BCOM_DEVICEID_BCM5787 0x169B 2006#define BCOM_DEVICEID_BCM5787M 0x1693 2007#define BCOM_DEVICEID_BCM5788 0x169C 2008#define BCOM_DEVICEID_BCM5789 0x169D 2009#define BCOM_DEVICEID_BCM5901 0x170D 2010#define BCOM_DEVICEID_BCM5901A2 0x170E 2011#define BCOM_DEVICEID_BCM5903M 0x16FF 2012 2013/* 2014 * Alteon AceNIC PCI vendor/device ID. 2015 */ 2016#define ALTEON_VENDORID 0x12AE 2017#define ALTEON_DEVICEID_ACENIC 0x0001 2018#define ALTEON_DEVICEID_ACENIC_COPPER 0x0002 2019#define ALTEON_DEVICEID_BCM5700 0x0003 2020#define ALTEON_DEVICEID_BCM5701 0x0004 2021 2022/* 2023 * 3Com 3c985 PCI vendor/device ID. 2024 */ 2025#define TC_VENDORID 0x10B7 2026#define TC_DEVICEID_3C985 0x0001 2027#define TC_DEVICEID_3C996 0x0003 2028 2029/* 2030 * SysKonnect PCI vendor ID 2031 */ 2032#define SK_VENDORID 0x1148 2033#define SK_DEVICEID_ALTIMA 0x4400 2034#define SK_SUBSYSID_9D21 0x4421 2035#define SK_SUBSYSID_9D41 0x4441 2036 2037/* 2038 * Altima PCI vendor/device ID. 2039 */ 2040#define ALTIMA_VENDORID 0x173b 2041#define ALTIMA_DEVICE_AC1000 0x03e8 2042#define ALTIMA_DEVICE_AC1002 0x03e9 2043#define ALTIMA_DEVICE_AC9100 0x03ea 2044 2045/* 2046 * Dell PCI vendor ID 2047 */ 2048 2049#define DELL_VENDORID 0x1028 2050 2051/* 2052 * Apple PCI vendor ID. 2053 */ 2054#define APPLE_VENDORID 0x106b 2055#define APPLE_DEVICE_BCM5701 0x1645 2056 2057/* 2058 * Offset of MAC address inside EEPROM. 2059 */ 2060#define BGE_EE_MAC_OFFSET 0x7C 2061#define BGE_EE_HWCFG_OFFSET 0xC8 2062 2063#define BGE_HWCFG_VOLTAGE 0x00000003 2064#define BGE_HWCFG_PHYLED_MODE 0x0000000C 2065#define BGE_HWCFG_MEDIA 0x00000030 2066 2067#define BGE_VOLTAGE_1POINT3 0x00000000 2068#define BGE_VOLTAGE_1POINT8 0x00000001 2069 2070#define BGE_PHYLEDMODE_UNSPEC 0x00000000 2071#define BGE_PHYLEDMODE_TRIPLELED 0x00000004 2072#define BGE_PHYLEDMODE_SINGLELED 0x00000008 2073 2074#define BGE_MEDIA_UNSPEC 0x00000000 2075#define BGE_MEDIA_COPPER 0x00000010 2076#define BGE_MEDIA_FIBER 0x00000020 2077 2078#define BGE_PCI_READ_CMD 0x06000000 2079#define BGE_PCI_WRITE_CMD 0x70000000 2080 2081#define BGE_TICKS_PER_SEC 1000000 2082 2083/* 2084 * Ring size constants. 2085 */ 2086#define BGE_EVENT_RING_CNT 256 2087#define BGE_CMD_RING_CNT 64 2088#define BGE_STD_RX_RING_CNT 512 2089#define BGE_JUMBO_RX_RING_CNT 256 2090#define BGE_MINI_RX_RING_CNT 1024 2091#define BGE_RETURN_RING_CNT 1024 2092 2093/* 5705 has smaller return ring size */ 2094 2095#define BGE_RETURN_RING_CNT_5705 512 2096 2097/* 2098 * Possible TX ring sizes. 2099 */ 2100#define BGE_TX_RING_CNT_128 128 2101#define BGE_TX_RING_BASE_128 0x3800 2102 2103#define BGE_TX_RING_CNT_256 256 2104#define BGE_TX_RING_BASE_256 0x3000 2105 2106#define BGE_TX_RING_CNT_512 512 2107#define BGE_TX_RING_BASE_512 0x2000 2108 2109#define BGE_TX_RING_CNT BGE_TX_RING_CNT_512 2110#define BGE_TX_RING_BASE BGE_TX_RING_BASE_512 2111 2112/* 2113 * Tigon III statistics counters. 2114 */ 2115/* Statistics maintained MAC Receive block. */ 2116struct bge_rx_mac_stats { 2117 bge_hostaddr ifHCInOctets; 2118 bge_hostaddr Reserved1; 2119 bge_hostaddr etherStatsFragments; 2120 bge_hostaddr ifHCInUcastPkts; 2121 bge_hostaddr ifHCInMulticastPkts; 2122 bge_hostaddr ifHCInBroadcastPkts; 2123 bge_hostaddr dot3StatsFCSErrors; 2124 bge_hostaddr dot3StatsAlignmentErrors; 2125 bge_hostaddr xonPauseFramesReceived; 2126 bge_hostaddr xoffPauseFramesReceived; 2127 bge_hostaddr macControlFramesReceived; 2128 bge_hostaddr xoffStateEntered; 2129 bge_hostaddr dot3StatsFramesTooLong; 2130 bge_hostaddr etherStatsJabbers; 2131 bge_hostaddr etherStatsUndersizePkts; 2132 bge_hostaddr inRangeLengthError; 2133 bge_hostaddr outRangeLengthError; 2134 bge_hostaddr etherStatsPkts64Octets; 2135 bge_hostaddr etherStatsPkts65Octetsto127Octets; 2136 bge_hostaddr etherStatsPkts128Octetsto255Octets; 2137 bge_hostaddr etherStatsPkts256Octetsto511Octets; 2138 bge_hostaddr etherStatsPkts512Octetsto1023Octets; 2139 bge_hostaddr etherStatsPkts1024Octetsto1522Octets; 2140 bge_hostaddr etherStatsPkts1523Octetsto2047Octets; 2141 bge_hostaddr etherStatsPkts2048Octetsto4095Octets; 2142 bge_hostaddr etherStatsPkts4096Octetsto8191Octets; 2143 bge_hostaddr etherStatsPkts8192Octetsto9022Octets; 2144}; 2145 2146 2147/* Statistics maintained MAC Transmit block. */ 2148struct bge_tx_mac_stats { 2149 bge_hostaddr ifHCOutOctets; 2150 bge_hostaddr Reserved2; 2151 bge_hostaddr etherStatsCollisions; 2152 bge_hostaddr outXonSent; 2153 bge_hostaddr outXoffSent; 2154 bge_hostaddr flowControlDone; 2155 bge_hostaddr dot3StatsInternalMacTransmitErrors; 2156 bge_hostaddr dot3StatsSingleCollisionFrames; 2157 bge_hostaddr dot3StatsMultipleCollisionFrames; 2158 bge_hostaddr dot3StatsDeferredTransmissions; 2159 bge_hostaddr Reserved3; 2160 bge_hostaddr dot3StatsExcessiveCollisions; 2161 bge_hostaddr dot3StatsLateCollisions; 2162 bge_hostaddr dot3Collided2Times; 2163 bge_hostaddr dot3Collided3Times; 2164 bge_hostaddr dot3Collided4Times; 2165 bge_hostaddr dot3Collided5Times; 2166 bge_hostaddr dot3Collided6Times; 2167 bge_hostaddr dot3Collided7Times; 2168 bge_hostaddr dot3Collided8Times; 2169 bge_hostaddr dot3Collided9Times; 2170 bge_hostaddr dot3Collided10Times; 2171 bge_hostaddr dot3Collided11Times; 2172 bge_hostaddr dot3Collided12Times; 2173 bge_hostaddr dot3Collided13Times; 2174 bge_hostaddr dot3Collided14Times; 2175 bge_hostaddr dot3Collided15Times; 2176 bge_hostaddr ifHCOutUcastPkts; 2177 bge_hostaddr ifHCOutMulticastPkts; 2178 bge_hostaddr ifHCOutBroadcastPkts; 2179 bge_hostaddr dot3StatsCarrierSenseErrors; 2180 bge_hostaddr ifOutDiscards; 2181 bge_hostaddr ifOutErrors; 2182}; 2183 2184/* Stats counters access through registers */ 2185struct bge_mac_stats_regs { 2186 uint32_t ifHCOutOctets; 2187 uint32_t Reserved0; 2188 uint32_t etherStatsCollisions; 2189 uint32_t outXonSent; 2190 uint32_t outXoffSent; 2191 uint32_t Reserved1; 2192 uint32_t dot3StatsInternalMacTransmitErrors; 2193 uint32_t dot3StatsSingleCollisionFrames; 2194 uint32_t dot3StatsMultipleCollisionFrames; 2195 uint32_t dot3StatsDeferredTransmissions; 2196 uint32_t Reserved2; 2197 uint32_t dot3StatsExcessiveCollisions; 2198 uint32_t dot3StatsLateCollisions; 2199 uint32_t Reserved3[14]; 2200 uint32_t ifHCOutUcastPkts; 2201 uint32_t ifHCOutMulticastPkts; 2202 uint32_t ifHCOutBroadcastPkts; 2203 uint32_t Reserved4[2]; 2204 uint32_t ifHCInOctets; 2205 uint32_t Reserved5; 2206 uint32_t etherStatsFragments; 2207 uint32_t ifHCInUcastPkts; 2208 uint32_t ifHCInMulticastPkts; 2209 uint32_t ifHCInBroadcastPkts; 2210 uint32_t dot3StatsFCSErrors; 2211 uint32_t dot3StatsAlignmentErrors; 2212 uint32_t xonPauseFramesReceived; 2213 uint32_t xoffPauseFramesReceived; 2214 uint32_t macControlFramesReceived; 2215 uint32_t xoffStateEntered; 2216 uint32_t dot3StatsFramesTooLong; 2217 uint32_t etherStatsJabbers; 2218 uint32_t etherStatsUndersizePkts; 2219}; 2220 2221struct bge_stats { 2222 uint8_t Reserved0[256]; 2223 2224 /* Statistics maintained by Receive MAC. */ 2225 struct bge_rx_mac_stats rxstats; 2226 2227 bge_hostaddr Unused1[37]; 2228 2229 /* Statistics maintained by Transmit MAC. */ 2230 struct bge_tx_mac_stats txstats; 2231 2232 bge_hostaddr Unused2[31]; 2233 2234 /* Statistics maintained by Receive List Placement. */ 2235 bge_hostaddr COSIfHCInPkts[16]; 2236 bge_hostaddr COSFramesDroppedDueToFilters; 2237 bge_hostaddr nicDmaWriteQueueFull; 2238 bge_hostaddr nicDmaWriteHighPriQueueFull; 2239 bge_hostaddr nicNoMoreRxBDs; 2240 bge_hostaddr ifInDiscards; 2241 bge_hostaddr ifInErrors; 2242 bge_hostaddr nicRecvThresholdHit; 2243 2244 bge_hostaddr Unused3[9]; 2245 2246 /* Statistics maintained by Send Data Initiator. */ 2247 bge_hostaddr COSIfHCOutPkts[16]; 2248 bge_hostaddr nicDmaReadQueueFull; 2249 bge_hostaddr nicDmaReadHighPriQueueFull; 2250 bge_hostaddr nicSendDataCompQueueFull; 2251 2252 /* Statistics maintained by Host Coalescing. */ 2253 bge_hostaddr nicRingSetSendProdIndex; 2254 bge_hostaddr nicRingStatusUpdate; 2255 bge_hostaddr nicInterrupts; 2256 bge_hostaddr nicAvoidedInterrupts; 2257 bge_hostaddr nicSendThresholdHit; 2258 2259 uint8_t Reserved4[320]; 2260}; 2261 2262/* 2263 * Tigon general information block. This resides in host memory 2264 * and contains the status counters, ring control blocks and 2265 * producer pointers. 2266 */ 2267 2268struct bge_gib { 2269 struct bge_stats bge_stats; 2270 struct bge_rcb bge_tx_rcb[16]; 2271 struct bge_rcb bge_std_rx_rcb; 2272 struct bge_rcb bge_jumbo_rx_rcb; 2273 struct bge_rcb bge_mini_rx_rcb; 2274 struct bge_rcb bge_return_rcb; 2275}; 2276 2277#define BGE_FRAMELEN 1518 2278#define BGE_MAX_FRAMELEN 1536 2279#define BGE_JUMBO_FRAMELEN 9018 2280#define BGE_JUMBO_MTU (BGE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 2281#define BGE_MIN_FRAMELEN 60 2282 2283/* 2284 * Other utility macros. 2285 */ 2286#define BGE_INC(x, y) (x) = (x + 1) % y 2287 2288/* 2289 * Vital product data and structures. 2290 */ 2291#define BGE_VPD_FLAG 0x8000 2292 2293/* VPD structures */ 2294struct vpd_res { 2295 uint8_t vr_id; 2296 uint8_t vr_len; 2297 uint8_t vr_pad; 2298}; 2299 2300struct vpd_key { 2301 char vk_key[2]; 2302 uint8_t vk_len; 2303}; 2304 2305#define VPD_RES_ID 0x82 /* ID string */ 2306#define VPD_RES_READ 0x90 /* start of read only area */ 2307#define VPD_RES_WRITE 0x81 /* start of read/write area */ 2308#define VPD_RES_END 0x78 /* end tag */ 2309 2310 2311/* 2312 * Register access macros. The Tigon always uses memory mapped register 2313 * accesses and all registers must be accessed with 32 bit operations. 2314 */ 2315 2316#define CSR_WRITE_4(sc, reg, val) \ 2317 bus_space_write_4(sc->bge_btag, sc->bge_bhandle, reg, val) 2318 2319#define CSR_READ_4(sc, reg) \ 2320 bus_space_read_4(sc->bge_btag, sc->bge_bhandle, reg) 2321 2322#define BGE_SETBIT(sc, reg, x) \ 2323 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | (x))) 2324#define BGE_CLRBIT(sc, reg, x) \ 2325 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~(x))) 2326 2327#define PCI_SETBIT(dev, reg, x, s) \ 2328 pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | (x)), s) 2329#define PCI_CLRBIT(dev, reg, x, s) \ 2330 pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~(x)), s) 2331 2332/* 2333 * Memory management stuff. Note: the SSLOTS, MSLOTS and JSLOTS 2334 * values are tuneable. They control the actual amount of buffers 2335 * allocated for the standard, mini and jumbo receive rings. 2336 */ 2337 2338#define BGE_SSLOTS 256 2339#define BGE_MSLOTS 256 2340#define BGE_JSLOTS 384 2341 2342#define BGE_JRAWLEN (BGE_JUMBO_FRAMELEN + ETHER_ALIGN) 2343#define BGE_JLEN (BGE_JRAWLEN + (sizeof(uint64_t) - \ 2344 (BGE_JRAWLEN % sizeof(uint64_t)))) 2345#define BGE_JPAGESZ PAGE_SIZE 2346#define BGE_RESID (BGE_JPAGESZ - (BGE_JLEN * BGE_JSLOTS) % BGE_JPAGESZ) 2347#define BGE_JMEM ((BGE_JLEN * BGE_JSLOTS) + BGE_RESID) 2348 2349#define BGE_NSEG_JUMBO 4 2350#define BGE_NSEG_NEW 32 2351 2352/* 2353 * Ring structures. Most of these reside in host memory and we tell 2354 * the NIC where they are via the ring control blocks. The exceptions 2355 * are the tx and command rings, which live in NIC memory and which 2356 * we access via the shared memory window. 2357 */ 2358 2359struct bge_ring_data { 2360 struct bge_rx_bd *bge_rx_std_ring; 2361 bus_addr_t bge_rx_std_ring_paddr; 2362 struct bge_extrx_bd *bge_rx_jumbo_ring; 2363 bus_addr_t bge_rx_jumbo_ring_paddr; 2364 struct bge_rx_bd *bge_rx_return_ring; 2365 bus_addr_t bge_rx_return_ring_paddr; 2366 struct bge_tx_bd *bge_tx_ring; 2367 bus_addr_t bge_tx_ring_paddr; 2368 struct bge_status_block *bge_status_block; 2369 bus_addr_t bge_status_block_paddr; 2370 struct bge_stats *bge_stats; 2371 bus_addr_t bge_stats_paddr; 2372 struct bge_gib bge_info; 2373}; 2374 2375#define BGE_STD_RX_RING_SZ \ 2376 (sizeof(struct bge_rx_bd) * BGE_STD_RX_RING_CNT) 2377#define BGE_JUMBO_RX_RING_SZ \ 2378 (sizeof(struct bge_extrx_bd) * BGE_JUMBO_RX_RING_CNT) 2379#define BGE_TX_RING_SZ \ 2380 (sizeof(struct bge_tx_bd) * BGE_TX_RING_CNT) 2381#define BGE_RX_RTN_RING_SZ(x) \ 2382 (sizeof(struct bge_rx_bd) * x->bge_return_ring_cnt) 2383 2384#define BGE_STATUS_BLK_SZ sizeof (struct bge_status_block) 2385 2386#define BGE_STATS_SZ sizeof (struct bge_stats) 2387 2388/* 2389 * Mbuf pointers. We need these to keep track of the virtual addresses 2390 * of our mbuf chains since we can only convert from physical to virtual, 2391 * not the other way around. 2392 */ 2393struct bge_chain_data { 2394 bus_dma_tag_t bge_parent_tag; 2395 bus_dma_tag_t bge_rx_std_ring_tag; 2396 bus_dma_tag_t bge_rx_jumbo_ring_tag; 2397 bus_dma_tag_t bge_rx_return_ring_tag; 2398 bus_dma_tag_t bge_tx_ring_tag; 2399 bus_dma_tag_t bge_status_tag; 2400 bus_dma_tag_t bge_stats_tag; 2401 bus_dma_tag_t bge_mtag; /* mbuf mapping tag */ 2402 bus_dma_tag_t bge_mtag_jumbo; /* mbuf mapping tag */ 2403 bus_dmamap_t bge_tx_dmamap[BGE_TX_RING_CNT]; 2404 bus_dmamap_t bge_rx_std_dmamap[BGE_STD_RX_RING_CNT]; 2405 bus_dmamap_t bge_rx_jumbo_dmamap[BGE_JUMBO_RX_RING_CNT]; 2406 bus_dmamap_t bge_rx_std_ring_map; 2407 bus_dmamap_t bge_rx_jumbo_ring_map; 2408 bus_dmamap_t bge_tx_ring_map; 2409 bus_dmamap_t bge_rx_return_ring_map; 2410 bus_dmamap_t bge_status_map; 2411 bus_dmamap_t bge_stats_map; 2412 struct mbuf *bge_tx_chain[BGE_TX_RING_CNT]; 2413 struct mbuf *bge_rx_std_chain[BGE_STD_RX_RING_CNT]; 2414 struct mbuf *bge_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT]; 2415}; 2416 2417struct bge_dmamap_arg { 2418 struct bge_softc *sc; 2419 bus_addr_t bge_busaddr; 2420 uint16_t bge_flags; 2421 int bge_idx; 2422 int bge_maxsegs; 2423 struct bge_tx_bd *bge_ring; 2424}; 2425 2426#define BGE_HWREV_TIGON 0x01 2427#define BGE_HWREV_TIGON_II 0x02 2428#define BGE_TIMEOUT 100000 2429#define BGE_TXCONS_UNSET 0xFFFF /* impossible value */ 2430 2431struct bge_bcom_hack { 2432 int reg; 2433 int val; 2434}; 2435 2436struct bge_softc { 2437 struct ifnet *bge_ifp; /* interface info */ 2438 device_t bge_dev; 2439 struct mtx bge_mtx; 2440 device_t bge_miibus; 2441 bus_space_handle_t bge_bhandle; 2442 bus_space_tag_t bge_btag; 2443 void *bge_intrhand; 2444 struct resource *bge_irq; 2445 struct resource *bge_res; 2446 struct ifmedia bge_ifmedia; /* TBI media info */ 2447 uint32_t bge_flags; 2448#define BGE_FLAG_EXTRAM 0x00000001 /* Has external SSRAM. */ 2449#define BGE_FLAG_TBI 0x00000002 2450#define BGE_FLAG_RX_ALIGNBUG 0x00000004 2451#define BGE_FLAG_NO3LED 0x00000008 2452#define BGE_FLAG_PCIX 0x00000010 2453#define BGE_FLAG_PCIE 0x00000020 2454 uint32_t bge_chipid; 2455 uint8_t bge_asicrev; 2456 uint8_t bge_chiprev; 2457 struct bge_ring_data bge_ldata; /* rings */ 2458 struct bge_chain_data bge_cdata; /* mbufs */ 2459 uint16_t bge_tx_saved_considx; 2460 uint16_t bge_rx_saved_considx; 2461 uint16_t bge_ev_saved_considx; 2462 uint16_t bge_return_ring_cnt; 2463 uint16_t bge_std; /* current std ring head */ 2464 uint16_t bge_jumbo; /* current jumo ring head */ 2465 uint32_t bge_stat_ticks; 2466 uint32_t bge_rx_coal_ticks; 2467 uint32_t bge_tx_coal_ticks; 2468 uint32_t bge_tx_prodidx; 2469 uint32_t bge_rx_max_coal_bds; 2470 uint32_t bge_tx_max_coal_bds; 2471 uint32_t bge_tx_buf_ratio; 2472 int bge_if_flags; 2473 int bge_txcnt; 2474 int bge_link; /* link state */ 2475 int bge_link_evt; /* pending link event */ 2476 struct callout bge_stat_ch; 2477 char *bge_vpd_prodname; 2478 char *bge_vpd_readonly; 2479 u_long bge_rx_discards; 2480 u_long bge_tx_discards; 2481 u_long bge_tx_collisions; 2482#ifdef DEVICE_POLLING 2483 int rxcycles; 2484#endif /* DEVICE_POLLING */ 2485}; 2486 2487#define BGE_LOCK_INIT(_sc, _name) \ 2488 mtx_init(&(_sc)->bge_mtx, _name, MTX_NETWORK_LOCK, MTX_DEF) 2489#define BGE_LOCK(_sc) mtx_lock(&(_sc)->bge_mtx) 2490#define BGE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->bge_mtx, MA_OWNED) 2491#define BGE_UNLOCK(_sc) mtx_unlock(&(_sc)->bge_mtx) 2492#define BGE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->bge_mtx) 2493