if_bfe.c revision 129616
1193880Syongari/* 2193880Syongari * Copyright (c) 2003 Stuart Walsh<stu@ipng.org.uk> 3193880Syongari * and Duncan Barclay<dmlb@dmlb.org> 4193880Syongari */ 5193880Syongari 6193880Syongari/* 7193880Syongari * Redistribution and use in source and binary forms, with or without 8193880Syongari * modification, are permitted provided that the following conditions 9193880Syongari * are met: 10193880Syongari * 1. Redistributions of source code must retain the above copyright 11193880Syongari * notice, this list of conditions and the following disclaimer. 12193880Syongari * 2. Redistributions in binary form must reproduce the above copyright 13193880Syongari * notice, this list of conditions and the following disclaimer in the 14193880Syongari * documentation and/or other materials provided with the distribution. 15193880Syongari * 16193880Syongari * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND 17193880Syongari * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18193880Syongari * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19193880Syongari * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20193880Syongari * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21193880Syongari * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22193880Syongari * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23193880Syongari * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24193880Syongari * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25193880Syongari * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26193880Syongari * SUCH DAMAGE. 27193880Syongari */ 28193880Syongari 29193880Syongari 30193880Syongari#include <sys/cdefs.h> 31193880Syongari__FBSDID("$FreeBSD: head/sys/dev/bfe/if_bfe.c 129616 2004-05-23 16:11:53Z mux $"); 32193880Syongari 33193880Syongari#include <sys/param.h> 34193880Syongari#include <sys/systm.h> 35193880Syongari#include <sys/sockio.h> 36193880Syongari#include <sys/mbuf.h> 37193880Syongari#include <sys/malloc.h> 38193880Syongari#include <sys/kernel.h> 39193880Syongari#include <sys/socket.h> 40193880Syongari#include <sys/queue.h> 41193880Syongari 42193880Syongari#include <net/if.h> 43193880Syongari#include <net/if_arp.h> 44193880Syongari#include <net/ethernet.h> 45264442Syongari#include <net/if_dl.h> 46193880Syongari#include <net/if_media.h> 47193880Syongari 48193880Syongari#include <net/bpf.h> 49193880Syongari 50193880Syongari#include <net/if_types.h> 51193880Syongari#include <net/if_vlan_var.h> 52193880Syongari 53193880Syongari#include <netinet/in_systm.h> 54193880Syongari#include <netinet/in.h> 55273366Syongari#include <netinet/ip.h> 56273366Syongari 57273366Syongari#include <machine/clock.h> /* for DELAY */ 58273366Syongari#include <machine/bus_memio.h> 59193880Syongari#include <machine/bus.h> 60193880Syongari#include <machine/resource.h> 61193880Syongari#include <sys/bus.h> 62193880Syongari#include <sys/rman.h> 63193880Syongari 64193880Syongari#include <dev/mii/mii.h> 65193880Syongari#include <dev/mii/miivar.h> 66193880Syongari#include "miidevs.h" 67193880Syongari 68193880Syongari#include <dev/pci/pcireg.h> 69193880Syongari#include <dev/pci/pcivar.h> 70193880Syongari 71193880Syongari#include <dev/bfe/if_bfereg.h> 72193880Syongari 73193880SyongariMODULE_DEPEND(bfe, pci, 1, 1, 1); 74193880SyongariMODULE_DEPEND(bfe, ether, 1, 1, 1); 75193880SyongariMODULE_DEPEND(bfe, miibus, 1, 1, 1); 76211105Syongari 77193880Syongari/* "controller miibus0" required. See GENERIC if you get errors here. */ 78193880Syongari#include "miibus_if.h" 79193880Syongari 80193880Syongari#define BFE_DEVDESC_MAX 64 /* Maximum device description length */ 81193880Syongari 82193880Syongaristatic struct bfe_type bfe_devs[] = { 83193880Syongari { BCOM_VENDORID, BCOM_DEVICEID_BCM4401, 84193880Syongari "Broadcom BCM4401 Fast Ethernet" }, 85193880Syongari { 0, 0, NULL } 86193880Syongari}; 87193880Syongari 88193880Syongaristatic int bfe_probe (device_t); 89193880Syongaristatic int bfe_attach (device_t); 90193880Syongaristatic int bfe_detach (device_t); 91193880Syongaristatic void bfe_release_resources (struct bfe_softc *); 92193880Syongaristatic void bfe_intr (void *); 93193880Syongaristatic void bfe_start (struct ifnet *); 94193880Syongaristatic int bfe_ioctl (struct ifnet *, u_long, caddr_t); 95193880Syongaristatic void bfe_init (void *); 96193880Syongaristatic void bfe_stop (struct bfe_softc *); 97193880Syongaristatic void bfe_watchdog (struct ifnet *); 98193880Syongaristatic void bfe_shutdown (device_t); 99193880Syongaristatic void bfe_tick (void *); 100193880Syongaristatic void bfe_txeof (struct bfe_softc *); 101193880Syongaristatic void bfe_rxeof (struct bfe_softc *); 102193880Syongaristatic void bfe_set_rx_mode (struct bfe_softc *); 103193880Syongaristatic int bfe_list_rx_init (struct bfe_softc *); 104193880Syongaristatic int bfe_list_newbuf (struct bfe_softc *, int, struct mbuf*); 105193880Syongaristatic void bfe_rx_ring_free (struct bfe_softc *); 106193880Syongari 107193880Syongaristatic void bfe_pci_setup (struct bfe_softc *, u_int32_t); 108193880Syongaristatic int bfe_ifmedia_upd (struct ifnet *); 109193880Syongaristatic void bfe_ifmedia_sts (struct ifnet *, struct ifmediareq *); 110193880Syongaristatic int bfe_miibus_readreg (device_t, int, int); 111193880Syongaristatic int bfe_miibus_writereg (device_t, int, int, int); 112193880Syongaristatic void bfe_miibus_statchg (device_t); 113193880Syongaristatic int bfe_wait_bit (struct bfe_softc *, u_int32_t, u_int32_t, 114193880Syongari u_long, const int); 115193880Syongaristatic void bfe_get_config (struct bfe_softc *sc); 116193880Syongaristatic void bfe_read_eeprom (struct bfe_softc *, u_int8_t *); 117193880Syongaristatic void bfe_stats_update (struct bfe_softc *); 118193880Syongaristatic void bfe_clear_stats (struct bfe_softc *); 119193880Syongaristatic int bfe_readphy (struct bfe_softc *, u_int32_t, u_int32_t*); 120193880Syongaristatic int bfe_writephy (struct bfe_softc *, u_int32_t, u_int32_t); 121193880Syongaristatic int bfe_resetphy (struct bfe_softc *); 122193880Syongaristatic int bfe_setupphy (struct bfe_softc *); 123193880Syongaristatic void bfe_chip_reset (struct bfe_softc *); 124193880Syongaristatic void bfe_chip_halt (struct bfe_softc *); 125193880Syongaristatic void bfe_core_reset (struct bfe_softc *); 126193880Syongaristatic void bfe_core_disable (struct bfe_softc *); 127193880Syongaristatic int bfe_dma_alloc (device_t); 128193880Syongaristatic void bfe_dma_map_desc (void *, bus_dma_segment_t *, int, int); 129193880Syongaristatic void bfe_dma_map (void *, bus_dma_segment_t *, int, int); 130193880Syongaristatic void bfe_cam_write (struct bfe_softc *, u_char *, int); 131193880Syongari 132193880Syongaristatic device_method_t bfe_methods[] = { 133193880Syongari /* Device interface */ 134193880Syongari DEVMETHOD(device_probe, bfe_probe), 135193880Syongari DEVMETHOD(device_attach, bfe_attach), 136193880Syongari DEVMETHOD(device_detach, bfe_detach), 137193880Syongari DEVMETHOD(device_shutdown, bfe_shutdown), 138193880Syongari 139193880Syongari /* bus interface */ 140193880Syongari DEVMETHOD(bus_print_child, bus_generic_print_child), 141193880Syongari DEVMETHOD(bus_driver_added, bus_generic_driver_added), 142193880Syongari 143193880Syongari /* MII interface */ 144193880Syongari DEVMETHOD(miibus_readreg, bfe_miibus_readreg), 145193880Syongari DEVMETHOD(miibus_writereg, bfe_miibus_writereg), 146193880Syongari DEVMETHOD(miibus_statchg, bfe_miibus_statchg), 147193880Syongari 148193880Syongari { 0, 0 } 149193880Syongari}; 150193880Syongari 151193880Syongaristatic driver_t bfe_driver = { 152193880Syongari "bfe", 153193880Syongari bfe_methods, 154193880Syongari sizeof(struct bfe_softc) 155193880Syongari}; 156193880Syongari 157193880Syongaristatic devclass_t bfe_devclass; 158193880Syongari 159193880SyongariDRIVER_MODULE(bfe, pci, bfe_driver, bfe_devclass, 0, 0); 160193880SyongariDRIVER_MODULE(miibus, bfe, miibus_driver, miibus_devclass, 0, 0); 161193880Syongari 162193880Syongari/* 163193880Syongari * Probe for a Broadcom 4401 chip. 164193880Syongari */ 165193880Syongaristatic int 166193880Syongaribfe_probe(device_t dev) 167193880Syongari{ 168193880Syongari struct bfe_type *t; 169193880Syongari struct bfe_softc *sc; 170193880Syongari 171193880Syongari t = bfe_devs; 172193880Syongari 173193880Syongari sc = device_get_softc(dev); 174193880Syongari bzero(sc, sizeof(struct bfe_softc)); 175193880Syongari sc->bfe_unit = device_get_unit(dev); 176193880Syongari sc->bfe_dev = dev; 177193880Syongari 178193880Syongari while(t->bfe_name != NULL) { 179193880Syongari if ((pci_get_vendor(dev) == t->bfe_vid) && 180193880Syongari (pci_get_device(dev) == t->bfe_did)) { 181193880Syongari device_set_desc_copy(dev, t->bfe_name); 182193880Syongari return(0); 183193880Syongari } 184193880Syongari t++; 185193880Syongari } 186193880Syongari 187193880Syongari return(ENXIO); 188193880Syongari} 189193880Syongari 190193880Syongaristatic int 191193880Syongaribfe_dma_alloc(device_t dev) 192193880Syongari{ 193193880Syongari struct bfe_softc *sc; 194211105Syongari int error, i; 195211105Syongari 196211105Syongari sc = device_get_softc(dev); 197211105Syongari 198211105Syongari /* parent tag */ 199211105Syongari error = bus_dma_tag_create(NULL, /* parent */ 200211105Syongari PAGE_SIZE, 0, /* alignment, boundary */ 201193880Syongari BUS_SPACE_MAXADDR, /* lowaddr */ 202193880Syongari BUS_SPACE_MAXADDR_32BIT, /* highaddr */ 203193880Syongari NULL, NULL, /* filter, filterarg */ 204193880Syongari MAXBSIZE, /* maxsize */ 205193880Syongari BUS_SPACE_UNRESTRICTED, /* num of segments */ 206193880Syongari BUS_SPACE_MAXSIZE_32BIT, /* max segment size */ 207193880Syongari BUS_DMA_ALLOCNOW, /* flags */ 208193880Syongari NULL, NULL, /* lockfunc, lockarg */ 209193880Syongari &sc->bfe_parent_tag); 210193880Syongari 211193880Syongari /* tag for TX ring */ 212193880Syongari error = bus_dma_tag_create(sc->bfe_parent_tag, 213211105Syongari BFE_TX_LIST_SIZE, BFE_TX_LIST_SIZE, 214193880Syongari BUS_SPACE_MAXADDR, 215193880Syongari BUS_SPACE_MAXADDR, 216193880Syongari NULL, NULL, 217193880Syongari BFE_TX_LIST_SIZE, 218193880Syongari 1, 219193880Syongari BUS_SPACE_MAXSIZE_32BIT, 220193880Syongari 0, 221211053Syongari NULL, NULL, 222211053Syongari &sc->bfe_tx_tag); 223193880Syongari 224193880Syongari if (error) { 225193880Syongari device_printf(dev, "could not allocate dma tag\n"); 226193880Syongari return(ENOMEM); 227193880Syongari } 228211053Syongari 229193880Syongari /* tag for RX ring */ 230193880Syongari error = bus_dma_tag_create(sc->bfe_parent_tag, 231193880Syongari BFE_RX_LIST_SIZE, BFE_RX_LIST_SIZE, 232193880Syongari BUS_SPACE_MAXADDR, 233211105Syongari BUS_SPACE_MAXADDR, 234211105Syongari NULL, NULL, 235211105Syongari BFE_RX_LIST_SIZE, 236273366Syongari 1, 237273366Syongari BUS_SPACE_MAXSIZE_32BIT, 238193880Syongari 0, 239193880Syongari NULL, NULL, 240193880Syongari &sc->bfe_rx_tag); 241193880Syongari 242193880Syongari if (error) { 243193880Syongari device_printf(dev, "could not allocate dma tag\n"); 244193880Syongari return(ENOMEM); 245193880Syongari } 246193880Syongari 247193880Syongari /* tag for mbufs */ 248193880Syongari error = bus_dma_tag_create(sc->bfe_parent_tag, 249193880Syongari ETHER_ALIGN, 0, 250193880Syongari BUS_SPACE_MAXADDR, 251193880Syongari BUS_SPACE_MAXADDR, 252193880Syongari NULL, NULL, 253193880Syongari MCLBYTES, 254193880Syongari 1, 255193880Syongari BUS_SPACE_MAXSIZE_32BIT, 256193880Syongari 0, 257193880Syongari NULL, NULL, 258193880Syongari &sc->bfe_tag); 259193880Syongari 260193880Syongari if (error) { 261193880Syongari device_printf(dev, "could not allocate dma tag\n"); 262193880Syongari return(ENOMEM); 263193880Syongari } 264193880Syongari 265193880Syongari /* pre allocate dmamaps for RX list */ 266193880Syongari for (i = 0; i < BFE_RX_LIST_CNT; i++) { 267193880Syongari error = bus_dmamap_create(sc->bfe_tag, 0, 268193880Syongari &sc->bfe_rx_ring[i].bfe_map); 269193880Syongari if (error) { 270193880Syongari device_printf(dev, "cannot create DMA map for RX\n"); 271193880Syongari return(ENOMEM); 272193880Syongari } 273193880Syongari } 274193880Syongari 275193880Syongari /* pre allocate dmamaps for TX list */ 276193880Syongari for (i = 0; i < BFE_TX_LIST_CNT; i++) { 277193880Syongari error = bus_dmamap_create(sc->bfe_tag, 0, 278193880Syongari &sc->bfe_tx_ring[i].bfe_map); 279193880Syongari if (error) { 280193880Syongari device_printf(dev, "cannot create DMA map for TX\n"); 281193880Syongari return(ENOMEM); 282193880Syongari } 283193880Syongari } 284193880Syongari 285193880Syongari /* Alloc dma for rx ring */ 286193880Syongari error = bus_dmamem_alloc(sc->bfe_rx_tag, (void *)&sc->bfe_rx_list, 287 BUS_DMA_NOWAIT, &sc->bfe_rx_map); 288 289 if(error) 290 return(ENOMEM); 291 292 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 293 error = bus_dmamap_load(sc->bfe_rx_tag, sc->bfe_rx_map, 294 sc->bfe_rx_list, sizeof(struct bfe_desc), 295 bfe_dma_map, &sc->bfe_rx_dma, 0); 296 297 if(error) 298 return(ENOMEM); 299 300 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 301 302 error = bus_dmamem_alloc(sc->bfe_tx_tag, (void *)&sc->bfe_tx_list, 303 BUS_DMA_NOWAIT, &sc->bfe_tx_map); 304 if (error) 305 return(ENOMEM); 306 307 308 error = bus_dmamap_load(sc->bfe_tx_tag, sc->bfe_tx_map, 309 sc->bfe_tx_list, sizeof(struct bfe_desc), 310 bfe_dma_map, &sc->bfe_tx_dma, 0); 311 if(error) 312 return(ENOMEM); 313 314 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 315 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD); 316 317 return(0); 318} 319 320static int 321bfe_attach(device_t dev) 322{ 323 struct ifnet *ifp; 324 struct bfe_softc *sc; 325 int unit, error = 0, rid; 326 327 sc = device_get_softc(dev); 328 mtx_init(&sc->bfe_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 329 MTX_DEF | MTX_RECURSE); 330 331 unit = device_get_unit(dev); 332 sc->bfe_dev = dev; 333 sc->bfe_unit = unit; 334 335 /* 336 * Handle power management nonsense. 337 */ 338 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 339 u_int32_t membase, irq; 340 341 /* Save important PCI config data. */ 342 membase = pci_read_config(dev, BFE_PCI_MEMLO, 4); 343 irq = pci_read_config(dev, BFE_PCI_INTLINE, 4); 344 345 /* Reset the power state. */ 346 printf("bfe%d: chip is is in D%d power mode -- setting to D0\n", 347 sc->bfe_unit, pci_get_powerstate(dev)); 348 349 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 350 351 /* Restore PCI config data. */ 352 pci_write_config(dev, BFE_PCI_MEMLO, membase, 4); 353 pci_write_config(dev, BFE_PCI_INTLINE, irq, 4); 354 } 355 356 /* 357 * Map control/status registers. 358 */ 359 pci_enable_busmaster(dev); 360 361 rid = BFE_PCI_MEMLO; 362 sc->bfe_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 363 RF_ACTIVE); 364 if (sc->bfe_res == NULL) { 365 printf ("bfe%d: couldn't map memory\n", unit); 366 error = ENXIO; 367 goto fail; 368 } 369 370 sc->bfe_btag = rman_get_bustag(sc->bfe_res); 371 sc->bfe_bhandle = rman_get_bushandle(sc->bfe_res); 372 sc->bfe_vhandle = (vm_offset_t)rman_get_virtual(sc->bfe_res); 373 374 /* Allocate interrupt */ 375 rid = 0; 376 377 sc->bfe_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 378 RF_SHAREABLE | RF_ACTIVE); 379 if (sc->bfe_irq == NULL) { 380 printf("bfe%d: couldn't map interrupt\n", unit); 381 error = ENXIO; 382 goto fail; 383 } 384 385 if (bfe_dma_alloc(dev)) { 386 printf("bfe%d: failed to allocate DMA resources\n", 387 sc->bfe_unit); 388 bfe_release_resources(sc); 389 error = ENXIO; 390 goto fail; 391 } 392 393 /* Set up ifnet structure */ 394 ifp = &sc->arpcom.ac_if; 395 ifp->if_softc = sc; 396 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 397 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 398 ifp->if_ioctl = bfe_ioctl; 399 ifp->if_start = bfe_start; 400 ifp->if_watchdog = bfe_watchdog; 401 ifp->if_init = bfe_init; 402 ifp->if_mtu = ETHERMTU; 403 ifp->if_baudrate = 10000000; 404 ifp->if_snd.ifq_maxlen = BFE_TX_QLEN; 405 406 bfe_get_config(sc); 407 408 /* Reset the chip and turn on the PHY */ 409 bfe_chip_reset(sc); 410 411 if (mii_phy_probe(dev, &sc->bfe_miibus, 412 bfe_ifmedia_upd, bfe_ifmedia_sts)) { 413 printf("bfe%d: MII without any PHY!\n", sc->bfe_unit); 414 error = ENXIO; 415 goto fail; 416 } 417 418 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 419 callout_handle_init(&sc->bfe_stat_ch); 420 421 /* 422 * Hook interrupt last to avoid having to lock softc 423 */ 424 error = bus_setup_intr(dev, sc->bfe_irq, INTR_TYPE_NET, 425 bfe_intr, sc, &sc->bfe_intrhand); 426 427 if (error) { 428 bfe_release_resources(sc); 429 printf("bfe%d: couldn't set up irq\n", unit); 430 goto fail; 431 } 432fail: 433 if(error) 434 bfe_release_resources(sc); 435 return(error); 436} 437 438static int 439bfe_detach(device_t dev) 440{ 441 struct bfe_softc *sc; 442 struct ifnet *ifp; 443 444 sc = device_get_softc(dev); 445 446 KASSERT(mtx_initialized(&sc->bfe_mtx), ("bfe mutex not initialized")); 447 BFE_LOCK(scp); 448 449 ifp = &sc->arpcom.ac_if; 450 451 if (device_is_attached(dev)) { 452 bfe_stop(sc); 453 ether_ifdetach(ifp); 454 } 455 456 bfe_chip_reset(sc); 457 458 bus_generic_detach(dev); 459 if(sc->bfe_miibus != NULL) 460 device_delete_child(dev, sc->bfe_miibus); 461 462 bfe_release_resources(sc); 463 BFE_UNLOCK(sc); 464 mtx_destroy(&sc->bfe_mtx); 465 466 return(0); 467} 468 469/* 470 * Stop all chip I/O so that the kernel's probe routines don't 471 * get confused by errant DMAs when rebooting. 472 */ 473static void 474bfe_shutdown(device_t dev) 475{ 476 struct bfe_softc *sc; 477 478 sc = device_get_softc(dev); 479 BFE_LOCK(sc); 480 bfe_stop(sc); 481 482 BFE_UNLOCK(sc); 483 return; 484} 485 486static int 487bfe_miibus_readreg(device_t dev, int phy, int reg) 488{ 489 struct bfe_softc *sc; 490 u_int32_t ret; 491 492 sc = device_get_softc(dev); 493 if(phy != sc->bfe_phyaddr) 494 return(0); 495 bfe_readphy(sc, reg, &ret); 496 497 return(ret); 498} 499 500static int 501bfe_miibus_writereg(device_t dev, int phy, int reg, int val) 502{ 503 struct bfe_softc *sc; 504 505 sc = device_get_softc(dev); 506 if(phy != sc->bfe_phyaddr) 507 return(0); 508 bfe_writephy(sc, reg, val); 509 510 return(0); 511} 512 513static void 514bfe_miibus_statchg(device_t dev) 515{ 516 return; 517} 518 519static void 520bfe_tx_ring_free(struct bfe_softc *sc) 521{ 522 int i; 523 524 for(i = 0; i < BFE_TX_LIST_CNT; i++) { 525 if(sc->bfe_tx_ring[i].bfe_mbuf != NULL) { 526 m_freem(sc->bfe_tx_ring[i].bfe_mbuf); 527 sc->bfe_tx_ring[i].bfe_mbuf = NULL; 528 bus_dmamap_unload(sc->bfe_tag, 529 sc->bfe_tx_ring[i].bfe_map); 530 bus_dmamap_destroy(sc->bfe_tag, 531 sc->bfe_tx_ring[i].bfe_map); 532 } 533 } 534 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 535 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD); 536} 537 538static void 539bfe_rx_ring_free(struct bfe_softc *sc) 540{ 541 int i; 542 543 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 544 if (sc->bfe_rx_ring[i].bfe_mbuf != NULL) { 545 m_freem(sc->bfe_rx_ring[i].bfe_mbuf); 546 sc->bfe_rx_ring[i].bfe_mbuf = NULL; 547 bus_dmamap_unload(sc->bfe_tag, 548 sc->bfe_rx_ring[i].bfe_map); 549 bus_dmamap_destroy(sc->bfe_tag, 550 sc->bfe_rx_ring[i].bfe_map); 551 } 552 } 553 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 554 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 555} 556 557 558static int 559bfe_list_rx_init(struct bfe_softc *sc) 560{ 561 int i; 562 563 for(i = 0; i < BFE_RX_LIST_CNT; i++) { 564 if(bfe_list_newbuf(sc, i, NULL) == ENOBUFS) 565 return ENOBUFS; 566 } 567 568 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 569 CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc))); 570 571 sc->bfe_rx_cons = 0; 572 573 return(0); 574} 575 576static int 577bfe_list_newbuf(struct bfe_softc *sc, int c, struct mbuf *m) 578{ 579 struct bfe_rxheader *rx_header; 580 struct bfe_desc *d; 581 struct bfe_data *r; 582 u_int32_t ctrl; 583 584 if ((c < 0) || (c >= BFE_RX_LIST_CNT)) 585 return(EINVAL); 586 587 if(m == NULL) { 588 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 589 if(m == NULL) 590 return(ENOBUFS); 591 m->m_len = m->m_pkthdr.len = MCLBYTES; 592 } 593 else 594 m->m_data = m->m_ext.ext_buf; 595 596 rx_header = mtod(m, struct bfe_rxheader *); 597 rx_header->len = 0; 598 rx_header->flags = 0; 599 600 /* Map the mbuf into DMA */ 601 sc->bfe_rx_cnt = c; 602 d = &sc->bfe_rx_list[c]; 603 r = &sc->bfe_rx_ring[c]; 604 bus_dmamap_load(sc->bfe_tag, r->bfe_map, mtod(m, void *), 605 MCLBYTES, bfe_dma_map_desc, d, 0); 606 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_PREWRITE); 607 608 ctrl = ETHER_MAX_LEN + 32; 609 610 if(c == BFE_RX_LIST_CNT - 1) 611 ctrl |= BFE_DESC_EOT; 612 613 d->bfe_ctrl = ctrl; 614 r->bfe_mbuf = m; 615 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 616 return(0); 617} 618 619static void 620bfe_get_config(struct bfe_softc *sc) 621{ 622 u_int8_t eeprom[128]; 623 624 bfe_read_eeprom(sc, eeprom); 625 626 sc->arpcom.ac_enaddr[0] = eeprom[79]; 627 sc->arpcom.ac_enaddr[1] = eeprom[78]; 628 sc->arpcom.ac_enaddr[2] = eeprom[81]; 629 sc->arpcom.ac_enaddr[3] = eeprom[80]; 630 sc->arpcom.ac_enaddr[4] = eeprom[83]; 631 sc->arpcom.ac_enaddr[5] = eeprom[82]; 632 633 sc->bfe_phyaddr = eeprom[90] & 0x1f; 634 sc->bfe_mdc_port = (eeprom[90] >> 14) & 0x1; 635 636 sc->bfe_core_unit = 0; 637 sc->bfe_dma_offset = BFE_PCI_DMA; 638} 639 640static void 641bfe_pci_setup(struct bfe_softc *sc, u_int32_t cores) 642{ 643 u_int32_t bar_orig, pci_rev, val; 644 645 bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4); 646 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4); 647 pci_rev = CSR_READ_4(sc, BFE_SBIDHIGH) & BFE_RC_MASK; 648 649 val = CSR_READ_4(sc, BFE_SBINTVEC); 650 val |= cores; 651 CSR_WRITE_4(sc, BFE_SBINTVEC, val); 652 653 val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2); 654 val |= BFE_SSB_PCI_PREF | BFE_SSB_PCI_BURST; 655 CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val); 656 657 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4); 658} 659 660static void 661bfe_clear_stats(struct bfe_softc *sc) 662{ 663 u_long reg; 664 665 BFE_LOCK(sc); 666 667 CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ); 668 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) 669 CSR_READ_4(sc, reg); 670 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) 671 CSR_READ_4(sc, reg); 672 673 BFE_UNLOCK(sc); 674} 675 676static int 677bfe_resetphy(struct bfe_softc *sc) 678{ 679 u_int32_t val; 680 681 BFE_LOCK(sc); 682 bfe_writephy(sc, 0, BMCR_RESET); 683 DELAY(100); 684 bfe_readphy(sc, 0, &val); 685 if (val & BMCR_RESET) { 686 printf("bfe%d: PHY Reset would not complete.\n", sc->bfe_unit); 687 BFE_UNLOCK(sc); 688 return ENXIO; 689 } 690 BFE_UNLOCK(sc); 691 return 0; 692} 693 694static void 695bfe_chip_halt(struct bfe_softc *sc) 696{ 697 BFE_LOCK(sc); 698 /* disable interrupts - not that it actually does..*/ 699 CSR_WRITE_4(sc, BFE_IMASK, 0); 700 CSR_READ_4(sc, BFE_IMASK); 701 702 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 703 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 200, 1); 704 705 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 706 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 707 DELAY(10); 708 709 BFE_UNLOCK(sc); 710} 711 712static void 713bfe_chip_reset(struct bfe_softc *sc) 714{ 715 u_int32_t val; 716 717 BFE_LOCK(sc); 718 719 /* Set the interrupt vector for the enet core */ 720 bfe_pci_setup(sc, BFE_INTVEC_ENET0); 721 722 /* is core up? */ 723 val = CSR_READ_4(sc, BFE_SBTMSLOW) & 724 (BFE_RESET | BFE_REJECT | BFE_CLOCK); 725 if (val == BFE_CLOCK) { 726 /* It is, so shut it down */ 727 CSR_WRITE_4(sc, BFE_RCV_LAZY, 0); 728 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 729 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 100, 1); 730 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 731 sc->bfe_tx_cnt = sc->bfe_tx_prod = sc->bfe_tx_cons = 0; 732 if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK) 733 bfe_wait_bit(sc, BFE_DMARX_STAT, BFE_STAT_SIDLE, 734 100, 0); 735 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 736 sc->bfe_rx_prod = sc->bfe_rx_cons = 0; 737 } 738 739 bfe_core_reset(sc); 740 bfe_clear_stats(sc); 741 742 /* 743 * We want the phy registers to be accessible even when 744 * the driver is "downed" so initialize MDC preamble, frequency, 745 * and whether internal or external phy here. 746 */ 747 748 /* 4402 has 62.5Mhz SB clock and internal phy */ 749 CSR_WRITE_4(sc, BFE_MDIO_CTRL, 0x8d); 750 751 /* Internal or external PHY? */ 752 val = CSR_READ_4(sc, BFE_DEVCTRL); 753 if(!(val & BFE_IPP)) 754 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_EPSEL); 755 else if(CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) { 756 BFE_AND(sc, BFE_DEVCTRL, ~BFE_EPR); 757 DELAY(100); 758 } 759 760 /* Enable CRC32 generation and set proper LED modes */ 761 BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB | BFE_CTRL_LED); 762 763 /* Reset or clear powerdown control bit */ 764 BFE_AND(sc, BFE_MAC_CTRL, ~BFE_CTRL_PDOWN); 765 766 CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) & 767 BFE_LAZY_FC_MASK)); 768 769 /* 770 * We don't want lazy interrupts, so just send them at 771 * the end of a frame, please 772 */ 773 BFE_OR(sc, BFE_RCV_LAZY, 0); 774 775 /* Set max lengths, accounting for VLAN tags */ 776 CSR_WRITE_4(sc, BFE_RXMAXLEN, ETHER_MAX_LEN+32); 777 CSR_WRITE_4(sc, BFE_TXMAXLEN, ETHER_MAX_LEN+32); 778 779 /* Set watermark XXX - magic */ 780 CSR_WRITE_4(sc, BFE_TX_WMARK, 56); 781 782 /* 783 * Initialise DMA channels 784 * - not forgetting dma addresses need to be added to BFE_PCI_DMA 785 */ 786 CSR_WRITE_4(sc, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE); 787 CSR_WRITE_4(sc, BFE_DMATX_ADDR, sc->bfe_tx_dma + BFE_PCI_DMA); 788 789 CSR_WRITE_4(sc, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT) | 790 BFE_RX_CTRL_ENABLE); 791 CSR_WRITE_4(sc, BFE_DMARX_ADDR, sc->bfe_rx_dma + BFE_PCI_DMA); 792 793 bfe_resetphy(sc); 794 bfe_setupphy(sc); 795 796 BFE_UNLOCK(sc); 797} 798 799static void 800bfe_core_disable(struct bfe_softc *sc) 801{ 802 if((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET) 803 return; 804 805 /* 806 * Set reject, wait for it set, then wait for the core to stop 807 * being busy, then set reset and reject and enable the clocks. 808 */ 809 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK)); 810 bfe_wait_bit(sc, BFE_SBTMSLOW, BFE_REJECT, 1000, 0); 811 bfe_wait_bit(sc, BFE_SBTMSHIGH, BFE_BUSY, 1000, 1); 812 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT | 813 BFE_RESET)); 814 CSR_READ_4(sc, BFE_SBTMSLOW); 815 DELAY(10); 816 /* Leave reset and reject set */ 817 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET)); 818 DELAY(10); 819} 820 821static void 822bfe_core_reset(struct bfe_softc *sc) 823{ 824 u_int32_t val; 825 826 /* Disable the core */ 827 bfe_core_disable(sc); 828 829 /* and bring it back up */ 830 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC)); 831 CSR_READ_4(sc, BFE_SBTMSLOW); 832 DELAY(10); 833 834 /* Chip bug, clear SERR, IB and TO if they are set. */ 835 if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR) 836 CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0); 837 val = CSR_READ_4(sc, BFE_SBIMSTATE); 838 if (val & (BFE_IBE | BFE_TO)) 839 CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO)); 840 841 /* Clear reset and allow it to move through the core */ 842 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC)); 843 CSR_READ_4(sc, BFE_SBTMSLOW); 844 DELAY(10); 845 846 /* Leave the clock set */ 847 CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK); 848 CSR_READ_4(sc, BFE_SBTMSLOW); 849 DELAY(10); 850} 851 852static void 853bfe_cam_write(struct bfe_softc *sc, u_char *data, int index) 854{ 855 u_int32_t val; 856 857 val = ((u_int32_t) data[2]) << 24; 858 val |= ((u_int32_t) data[3]) << 16; 859 val |= ((u_int32_t) data[4]) << 8; 860 val |= ((u_int32_t) data[5]); 861 CSR_WRITE_4(sc, BFE_CAM_DATA_LO, val); 862 val = (BFE_CAM_HI_VALID | 863 (((u_int32_t) data[0]) << 8) | 864 (((u_int32_t) data[1]))); 865 CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val); 866 CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE | 867 ((u_int32_t) index << BFE_CAM_INDEX_SHIFT))); 868 bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1); 869} 870 871static void 872bfe_set_rx_mode(struct bfe_softc *sc) 873{ 874 struct ifnet *ifp = &sc->arpcom.ac_if; 875 struct ifmultiaddr *ifma; 876 u_int32_t val; 877 int i = 0; 878 879 val = CSR_READ_4(sc, BFE_RXCONF); 880 881 if (ifp->if_flags & IFF_PROMISC) 882 val |= BFE_RXCONF_PROMISC; 883 else 884 val &= ~BFE_RXCONF_PROMISC; 885 886 if (ifp->if_flags & IFF_BROADCAST) 887 val &= ~BFE_RXCONF_DBCAST; 888 else 889 val |= BFE_RXCONF_DBCAST; 890 891 892 CSR_WRITE_4(sc, BFE_CAM_CTRL, 0); 893 bfe_cam_write(sc, sc->arpcom.ac_enaddr, i++); 894 895 if (ifp->if_flags & IFF_ALLMULTI) 896 val |= BFE_RXCONF_ALLMULTI; 897 else { 898 val &= ~BFE_RXCONF_ALLMULTI; 899 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 900 if (ifma->ifma_addr->sa_family != AF_LINK) 901 continue; 902 bfe_cam_write(sc, 903 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i++); 904 } 905 } 906 907 CSR_WRITE_4(sc, BFE_RXCONF, val); 908 BFE_OR(sc, BFE_CAM_CTRL, BFE_CAM_ENABLE); 909} 910 911static void 912bfe_dma_map(void *arg, bus_dma_segment_t *segs, int nseg, int error) 913{ 914 u_int32_t *ptr; 915 916 ptr = arg; 917 *ptr = segs->ds_addr; 918} 919 920static void 921bfe_dma_map_desc(void *arg, bus_dma_segment_t *segs, int nseg, int error) 922{ 923 struct bfe_desc *d; 924 925 d = arg; 926 /* The chip needs all addresses to be added to BFE_PCI_DMA */ 927 d->bfe_addr = segs->ds_addr + BFE_PCI_DMA; 928} 929 930static void 931bfe_release_resources(struct bfe_softc *sc) 932{ 933 device_t dev; 934 int i; 935 936 dev = sc->bfe_dev; 937 938 if (sc->bfe_vpd_prodname != NULL) 939 free(sc->bfe_vpd_prodname, M_DEVBUF); 940 941 if (sc->bfe_vpd_readonly != NULL) 942 free(sc->bfe_vpd_readonly, M_DEVBUF); 943 944 if (sc->bfe_intrhand != NULL) 945 bus_teardown_intr(dev, sc->bfe_irq, sc->bfe_intrhand); 946 947 if (sc->bfe_irq != NULL) 948 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bfe_irq); 949 950 if (sc->bfe_res != NULL) 951 bus_release_resource(dev, SYS_RES_MEMORY, 0x10, sc->bfe_res); 952 953 if(sc->bfe_tx_tag != NULL) { 954 bus_dmamap_unload(sc->bfe_tx_tag, sc->bfe_tx_map); 955 bus_dmamem_free(sc->bfe_tx_tag, sc->bfe_tx_list, 956 sc->bfe_tx_map); 957 bus_dma_tag_destroy(sc->bfe_tx_tag); 958 sc->bfe_tx_tag = NULL; 959 } 960 961 if(sc->bfe_rx_tag != NULL) { 962 bus_dmamap_unload(sc->bfe_rx_tag, sc->bfe_rx_map); 963 bus_dmamem_free(sc->bfe_rx_tag, sc->bfe_rx_list, 964 sc->bfe_rx_map); 965 bus_dma_tag_destroy(sc->bfe_rx_tag); 966 sc->bfe_rx_tag = NULL; 967 } 968 969 if(sc->bfe_tag != NULL) { 970 for(i = 0; i < BFE_TX_LIST_CNT; i++) { 971 bus_dmamap_destroy(sc->bfe_tag, 972 sc->bfe_tx_ring[i].bfe_map); 973 } 974 bus_dma_tag_destroy(sc->bfe_tag); 975 sc->bfe_tag = NULL; 976 } 977 978 if(sc->bfe_parent_tag != NULL) 979 bus_dma_tag_destroy(sc->bfe_parent_tag); 980 981 return; 982} 983 984static void 985bfe_read_eeprom(struct bfe_softc *sc, u_int8_t *data) 986{ 987 long i; 988 u_int16_t *ptr = (u_int16_t *)data; 989 990 for(i = 0; i < 128; i += 2) 991 ptr[i/2] = CSR_READ_4(sc, 4096 + i); 992} 993 994static int 995bfe_wait_bit(struct bfe_softc *sc, u_int32_t reg, u_int32_t bit, 996 u_long timeout, const int clear) 997{ 998 u_long i; 999 1000 for (i = 0; i < timeout; i++) { 1001 u_int32_t val = CSR_READ_4(sc, reg); 1002 1003 if (clear && !(val & bit)) 1004 break; 1005 if (!clear && (val & bit)) 1006 break; 1007 DELAY(10); 1008 } 1009 if (i == timeout) { 1010 printf("bfe%d: BUG! Timeout waiting for bit %08x of register " 1011 "%x to %s.\n", sc->bfe_unit, bit, reg, 1012 (clear ? "clear" : "set")); 1013 return -1; 1014 } 1015 return 0; 1016} 1017 1018static int 1019bfe_readphy(struct bfe_softc *sc, u_int32_t reg, u_int32_t *val) 1020{ 1021 int err; 1022 1023 BFE_LOCK(sc); 1024 /* Clear MII ISR */ 1025 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1026 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1027 (BFE_MDIO_OP_READ << BFE_MDIO_OP_SHIFT) | 1028 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1029 (reg << BFE_MDIO_RA_SHIFT) | 1030 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT))); 1031 err = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1032 *val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA; 1033 1034 BFE_UNLOCK(sc); 1035 return err; 1036} 1037 1038static int 1039bfe_writephy(struct bfe_softc *sc, u_int32_t reg, u_int32_t val) 1040{ 1041 int status; 1042 1043 BFE_LOCK(sc); 1044 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1045 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1046 (BFE_MDIO_OP_WRITE << BFE_MDIO_OP_SHIFT) | 1047 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1048 (reg << BFE_MDIO_RA_SHIFT) | 1049 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT) | 1050 (val & BFE_MDIO_DATA_DATA))); 1051 status = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1052 BFE_UNLOCK(sc); 1053 1054 return status; 1055} 1056 1057/* 1058 * XXX - I think this is handled by the PHY driver, but it can't hurt to do it 1059 * twice 1060 */ 1061static int 1062bfe_setupphy(struct bfe_softc *sc) 1063{ 1064 u_int32_t val; 1065 BFE_LOCK(sc); 1066 1067 /* Enable activity LED */ 1068 bfe_readphy(sc, 26, &val); 1069 bfe_writephy(sc, 26, val & 0x7fff); 1070 bfe_readphy(sc, 26, &val); 1071 1072 /* Enable traffic meter LED mode */ 1073 bfe_readphy(sc, 27, &val); 1074 bfe_writephy(sc, 27, val | (1 << 6)); 1075 1076 BFE_UNLOCK(sc); 1077 return 0; 1078} 1079 1080static void 1081bfe_stats_update(struct bfe_softc *sc) 1082{ 1083 u_long reg; 1084 u_int32_t *val; 1085 1086 val = &sc->bfe_hwstats.tx_good_octets; 1087 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) { 1088 *val++ += CSR_READ_4(sc, reg); 1089 } 1090 val = &sc->bfe_hwstats.rx_good_octets; 1091 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) { 1092 *val++ += CSR_READ_4(sc, reg); 1093 } 1094} 1095 1096static void 1097bfe_txeof(struct bfe_softc *sc) 1098{ 1099 struct ifnet *ifp; 1100 int i, chipidx; 1101 1102 BFE_LOCK(sc); 1103 1104 ifp = &sc->arpcom.ac_if; 1105 1106 chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK; 1107 chipidx /= sizeof(struct bfe_desc); 1108 1109 i = sc->bfe_tx_cons; 1110 /* Go through the mbufs and free those that have been transmitted */ 1111 while(i != chipidx) { 1112 struct bfe_data *r = &sc->bfe_tx_ring[i]; 1113 if(r->bfe_mbuf != NULL) { 1114 ifp->if_opackets++; 1115 m_freem(r->bfe_mbuf); 1116 r->bfe_mbuf = NULL; 1117 bus_dmamap_unload(sc->bfe_tag, r->bfe_map); 1118 } 1119 sc->bfe_tx_cnt--; 1120 BFE_INC(i, BFE_TX_LIST_CNT); 1121 } 1122 1123 if(i != sc->bfe_tx_cons) { 1124 /* we freed up some mbufs */ 1125 sc->bfe_tx_cons = i; 1126 ifp->if_flags &= ~IFF_OACTIVE; 1127 } 1128 if(sc->bfe_tx_cnt == 0) 1129 ifp->if_timer = 0; 1130 else 1131 ifp->if_timer = 5; 1132 1133 BFE_UNLOCK(sc); 1134} 1135 1136/* Pass a received packet up the stack */ 1137static void 1138bfe_rxeof(struct bfe_softc *sc) 1139{ 1140 struct mbuf *m; 1141 struct ifnet *ifp; 1142 struct bfe_rxheader *rxheader; 1143 struct bfe_data *r; 1144 int cons; 1145 u_int32_t status, current, len, flags; 1146 1147 BFE_LOCK(sc); 1148 cons = sc->bfe_rx_cons; 1149 status = CSR_READ_4(sc, BFE_DMARX_STAT); 1150 current = (status & BFE_STAT_CDMASK) / sizeof(struct bfe_desc); 1151 1152 ifp = &sc->arpcom.ac_if; 1153 1154 while(current != cons) { 1155 r = &sc->bfe_rx_ring[cons]; 1156 m = r->bfe_mbuf; 1157 rxheader = mtod(m, struct bfe_rxheader*); 1158 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_POSTWRITE); 1159 len = rxheader->len; 1160 r->bfe_mbuf = NULL; 1161 1162 bus_dmamap_unload(sc->bfe_tag, r->bfe_map); 1163 flags = rxheader->flags; 1164 1165 len -= ETHER_CRC_LEN; 1166 1167 /* flag an error and try again */ 1168 if ((len > ETHER_MAX_LEN+32) || (flags & BFE_RX_FLAG_ERRORS)) { 1169 ifp->if_ierrors++; 1170 if (flags & BFE_RX_FLAG_SERR) 1171 ifp->if_collisions++; 1172 bfe_list_newbuf(sc, cons, m); 1173 BFE_INC(cons, BFE_RX_LIST_CNT); 1174 continue; 1175 } 1176 1177 /* Go past the rx header */ 1178 if (bfe_list_newbuf(sc, cons, NULL) == 0) { 1179 m_adj(m, BFE_RX_OFFSET); 1180 m->m_len = m->m_pkthdr.len = len; 1181 } else { 1182 bfe_list_newbuf(sc, cons, m); 1183 ifp->if_ierrors++; 1184 BFE_INC(cons, BFE_RX_LIST_CNT); 1185 continue; 1186 } 1187 1188 ifp->if_ipackets++; 1189 m->m_pkthdr.rcvif = ifp; 1190 BFE_UNLOCK(sc); 1191 (*ifp->if_input)(ifp, m); 1192 BFE_LOCK(sc); 1193 1194 BFE_INC(cons, BFE_RX_LIST_CNT); 1195 } 1196 sc->bfe_rx_cons = cons; 1197 BFE_UNLOCK(sc); 1198} 1199 1200static void 1201bfe_intr(void *xsc) 1202{ 1203 struct bfe_softc *sc = xsc; 1204 struct ifnet *ifp; 1205 u_int32_t istat, imask, flag; 1206 1207 ifp = &sc->arpcom.ac_if; 1208 1209 BFE_LOCK(sc); 1210 1211 istat = CSR_READ_4(sc, BFE_ISTAT); 1212 imask = CSR_READ_4(sc, BFE_IMASK); 1213 1214 /* 1215 * Defer unsolicited interrupts - This is necessary because setting the 1216 * chips interrupt mask register to 0 doesn't actually stop the 1217 * interrupts 1218 */ 1219 istat &= imask; 1220 CSR_WRITE_4(sc, BFE_ISTAT, istat); 1221 CSR_READ_4(sc, BFE_ISTAT); 1222 1223 /* not expecting this interrupt, disregard it */ 1224 if(istat == 0) { 1225 BFE_UNLOCK(sc); 1226 return; 1227 } 1228 1229 if(istat & BFE_ISTAT_ERRORS) { 1230 flag = CSR_READ_4(sc, BFE_DMATX_STAT); 1231 if(flag & BFE_STAT_EMASK) 1232 ifp->if_oerrors++; 1233 1234 flag = CSR_READ_4(sc, BFE_DMARX_STAT); 1235 if(flag & BFE_RX_FLAG_ERRORS) 1236 ifp->if_ierrors++; 1237 1238 ifp->if_flags &= ~IFF_RUNNING; 1239 bfe_init(sc); 1240 } 1241 1242 /* A packet was received */ 1243 if(istat & BFE_ISTAT_RX) 1244 bfe_rxeof(sc); 1245 1246 /* A packet was sent */ 1247 if(istat & BFE_ISTAT_TX) 1248 bfe_txeof(sc); 1249 1250 /* We have packets pending, fire them out */ 1251 if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL) 1252 bfe_start(ifp); 1253 1254 BFE_UNLOCK(sc); 1255} 1256 1257static int 1258bfe_encap(struct bfe_softc *sc, struct mbuf *m_head, u_int32_t *txidx) 1259{ 1260 struct bfe_desc *d = NULL; 1261 struct bfe_data *r = NULL; 1262 struct mbuf *m; 1263 u_int32_t frag, cur, cnt = 0; 1264 int chainlen = 0; 1265 1266 if(BFE_TX_LIST_CNT - sc->bfe_tx_cnt < 2) 1267 return(ENOBUFS); 1268 1269 /* 1270 * Count the number of frags in this chain to see if 1271 * we need to m_defrag. Since the descriptor list is shared 1272 * by all packets, we'll m_defrag long chains so that they 1273 * do not use up the entire list, even if they would fit. 1274 */ 1275 for(m = m_head; m != NULL; m = m->m_next) 1276 chainlen++; 1277 1278 1279 if ((chainlen > BFE_TX_LIST_CNT / 4) || 1280 ((BFE_TX_LIST_CNT - (chainlen + sc->bfe_tx_cnt)) < 2)) { 1281 m = m_defrag(m_head, M_DONTWAIT); 1282 if (m == NULL) 1283 return(ENOBUFS); 1284 m_head = m; 1285 } 1286 1287 /* 1288 * Start packing the mbufs in this chain into 1289 * the fragment pointers. Stop when we run out 1290 * of fragments or hit the end of the mbuf chain. 1291 */ 1292 m = m_head; 1293 cur = frag = *txidx; 1294 cnt = 0; 1295 1296 for(m = m_head; m != NULL; m = m->m_next) { 1297 if(m->m_len != 0) { 1298 if((BFE_TX_LIST_CNT - (sc->bfe_tx_cnt + cnt)) < 2) 1299 return(ENOBUFS); 1300 1301 d = &sc->bfe_tx_list[cur]; 1302 r = &sc->bfe_tx_ring[cur]; 1303 d->bfe_ctrl = BFE_DESC_LEN & m->m_len; 1304 /* always intterupt on completion */ 1305 d->bfe_ctrl |= BFE_DESC_IOC; 1306 if(cnt == 0) 1307 /* Set start of frame */ 1308 d->bfe_ctrl |= BFE_DESC_SOF; 1309 if(cur == BFE_TX_LIST_CNT - 1) 1310 /* 1311 * Tell the chip to wrap to the start of 1312 * the descriptor list 1313 */ 1314 d->bfe_ctrl |= BFE_DESC_EOT; 1315 1316 bus_dmamap_load(sc->bfe_tag, 1317 r->bfe_map, mtod(m, void*), m->m_len, 1318 bfe_dma_map_desc, d, 0); 1319 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, 1320 BUS_DMASYNC_PREREAD); 1321 1322 frag = cur; 1323 BFE_INC(cur, BFE_TX_LIST_CNT); 1324 cnt++; 1325 } 1326 } 1327 1328 if (m != NULL) 1329 return(ENOBUFS); 1330 1331 sc->bfe_tx_list[frag].bfe_ctrl |= BFE_DESC_EOF; 1332 sc->bfe_tx_ring[frag].bfe_mbuf = m_head; 1333 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD); 1334 1335 *txidx = cur; 1336 sc->bfe_tx_cnt += cnt; 1337 return (0); 1338} 1339 1340/* 1341 * Set up to transmit a packet 1342 */ 1343static void 1344bfe_start(struct ifnet *ifp) 1345{ 1346 struct bfe_softc *sc; 1347 struct mbuf *m_head = NULL; 1348 int idx; 1349 1350 sc = ifp->if_softc; 1351 idx = sc->bfe_tx_prod; 1352 1353 BFE_LOCK(sc); 1354 1355 /* 1356 * Not much point trying to send if the link is down 1357 * or we have nothing to send. 1358 */ 1359 if (!sc->bfe_link && ifp->if_snd.ifq_len < 10) { 1360 BFE_UNLOCK(sc); 1361 return; 1362 } 1363 1364 if (ifp->if_flags & IFF_OACTIVE) { 1365 BFE_UNLOCK(sc); 1366 return; 1367 } 1368 1369 while(sc->bfe_tx_ring[idx].bfe_mbuf == NULL) { 1370 IF_DEQUEUE(&ifp->if_snd, m_head); 1371 if(m_head == NULL) 1372 break; 1373 1374 /* 1375 * Pack the data into the tx ring. If we dont have 1376 * enough room, let the chip drain the ring. 1377 */ 1378 if(bfe_encap(sc, m_head, &idx)) { 1379 IF_PREPEND(&ifp->if_snd, m_head); 1380 ifp->if_flags |= IFF_OACTIVE; 1381 break; 1382 } 1383 1384 /* 1385 * If there's a BPF listener, bounce a copy of this frame 1386 * to him. 1387 */ 1388 BPF_MTAP(ifp, m_head); 1389 } 1390 1391 sc->bfe_tx_prod = idx; 1392 /* Transmit - twice due to apparent hardware bug */ 1393 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc)); 1394 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc)); 1395 1396 /* 1397 * Set a timeout in case the chip goes out to lunch. 1398 */ 1399 ifp->if_timer = 5; 1400 BFE_UNLOCK(sc); 1401} 1402 1403static void 1404bfe_init(void *xsc) 1405{ 1406 struct bfe_softc *sc = (struct bfe_softc*)xsc; 1407 struct ifnet *ifp = &sc->arpcom.ac_if; 1408 1409 BFE_LOCK(sc); 1410 1411 if (ifp->if_flags & IFF_RUNNING) { 1412 BFE_UNLOCK(sc); 1413 return; 1414 } 1415 1416 bfe_stop(sc); 1417 bfe_chip_reset(sc); 1418 1419 if (bfe_list_rx_init(sc) == ENOBUFS) { 1420 printf("bfe%d: bfe_init: Not enough memory for list buffers\n", 1421 sc->bfe_unit); 1422 bfe_stop(sc); 1423 return; 1424 } 1425 1426 bfe_set_rx_mode(sc); 1427 1428 /* Enable the chip and core */ 1429 BFE_OR(sc, BFE_ENET_CTRL, BFE_ENET_ENABLE); 1430 /* Enable interrupts */ 1431 CSR_WRITE_4(sc, BFE_IMASK, BFE_IMASK_DEF); 1432 1433 bfe_ifmedia_upd(ifp); 1434 ifp->if_flags |= IFF_RUNNING; 1435 ifp->if_flags &= ~IFF_OACTIVE; 1436 1437 sc->bfe_stat_ch = timeout(bfe_tick, sc, hz); 1438 BFE_UNLOCK(sc); 1439} 1440 1441/* 1442 * Set media options. 1443 */ 1444static int 1445bfe_ifmedia_upd(struct ifnet *ifp) 1446{ 1447 struct bfe_softc *sc; 1448 struct mii_data *mii; 1449 1450 sc = ifp->if_softc; 1451 1452 BFE_LOCK(sc); 1453 1454 mii = device_get_softc(sc->bfe_miibus); 1455 sc->bfe_link = 0; 1456 if (mii->mii_instance) { 1457 struct mii_softc *miisc; 1458 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1459 miisc = LIST_NEXT(miisc, mii_list)) 1460 mii_phy_reset(miisc); 1461 } 1462 mii_mediachg(mii); 1463 1464 BFE_UNLOCK(sc); 1465 return(0); 1466} 1467 1468/* 1469 * Report current media status. 1470 */ 1471static void 1472bfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1473{ 1474 struct bfe_softc *sc = ifp->if_softc; 1475 struct mii_data *mii; 1476 1477 BFE_LOCK(sc); 1478 1479 mii = device_get_softc(sc->bfe_miibus); 1480 mii_pollstat(mii); 1481 ifmr->ifm_active = mii->mii_media_active; 1482 ifmr->ifm_status = mii->mii_media_status; 1483 1484 BFE_UNLOCK(sc); 1485} 1486 1487static int 1488bfe_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1489{ 1490 struct bfe_softc *sc = ifp->if_softc; 1491 struct ifreq *ifr = (struct ifreq *) data; 1492 struct mii_data *mii; 1493 int error = 0; 1494 1495 BFE_LOCK(sc); 1496 1497 switch(command) { 1498 case SIOCSIFFLAGS: 1499 if(ifp->if_flags & IFF_UP) 1500 if(ifp->if_flags & IFF_RUNNING) 1501 bfe_set_rx_mode(sc); 1502 else 1503 bfe_init(sc); 1504 else if(ifp->if_flags & IFF_RUNNING) 1505 bfe_stop(sc); 1506 break; 1507 case SIOCADDMULTI: 1508 case SIOCDELMULTI: 1509 if(ifp->if_flags & IFF_RUNNING) 1510 bfe_set_rx_mode(sc); 1511 break; 1512 case SIOCGIFMEDIA: 1513 case SIOCSIFMEDIA: 1514 mii = device_get_softc(sc->bfe_miibus); 1515 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 1516 command); 1517 break; 1518 default: 1519 error = ether_ioctl(ifp, command, data); 1520 break; 1521 } 1522 1523 BFE_UNLOCK(sc); 1524 return error; 1525} 1526 1527static void 1528bfe_watchdog(struct ifnet *ifp) 1529{ 1530 struct bfe_softc *sc; 1531 1532 sc = ifp->if_softc; 1533 1534 BFE_LOCK(sc); 1535 1536 printf("bfe%d: watchdog timeout -- resetting\n", sc->bfe_unit); 1537 1538 ifp->if_flags &= ~IFF_RUNNING; 1539 bfe_init(sc); 1540 1541 ifp->if_oerrors++; 1542 1543 BFE_UNLOCK(sc); 1544} 1545 1546static void 1547bfe_tick(void *xsc) 1548{ 1549 struct bfe_softc *sc = xsc; 1550 struct mii_data *mii; 1551 1552 if (sc == NULL) 1553 return; 1554 1555 BFE_LOCK(sc); 1556 1557 mii = device_get_softc(sc->bfe_miibus); 1558 1559 bfe_stats_update(sc); 1560 sc->bfe_stat_ch = timeout(bfe_tick, sc, hz); 1561 1562 if(sc->bfe_link) { 1563 BFE_UNLOCK(sc); 1564 return; 1565 } 1566 1567 mii_tick(mii); 1568 if (!sc->bfe_link && mii->mii_media_status & IFM_ACTIVE && 1569 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1570 sc->bfe_link++; 1571 1572 BFE_UNLOCK(sc); 1573} 1574 1575/* 1576 * Stop the adapter and free any mbufs allocated to the 1577 * RX and TX lists. 1578 */ 1579static void 1580bfe_stop(struct bfe_softc *sc) 1581{ 1582 struct ifnet *ifp; 1583 1584 BFE_LOCK(sc); 1585 1586 untimeout(bfe_tick, sc, sc->bfe_stat_ch); 1587 1588 ifp = &sc->arpcom.ac_if; 1589 1590 bfe_chip_halt(sc); 1591 bfe_tx_ring_free(sc); 1592 bfe_rx_ring_free(sc); 1593 1594 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1595 1596 BFE_UNLOCK(sc); 1597} 1598