if_ath_tx.c revision 235491
1/*- 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 */ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: head/sys/dev/ath/if_ath_tx.c 235491 2012-05-15 23:39:37Z adrian $"); 32 33/* 34 * Driver for the Atheros Wireless LAN controller. 35 * 36 * This software is derived from work of Atsushi Onoe; his contribution 37 * is greatly appreciated. 38 */ 39 40#include "opt_inet.h" 41#include "opt_ath.h" 42#include "opt_wlan.h" 43 44#include <sys/param.h> 45#include <sys/systm.h> 46#include <sys/sysctl.h> 47#include <sys/mbuf.h> 48#include <sys/malloc.h> 49#include <sys/lock.h> 50#include <sys/mutex.h> 51#include <sys/kernel.h> 52#include <sys/socket.h> 53#include <sys/sockio.h> 54#include <sys/errno.h> 55#include <sys/callout.h> 56#include <sys/bus.h> 57#include <sys/endian.h> 58#include <sys/kthread.h> 59#include <sys/taskqueue.h> 60#include <sys/priv.h> 61 62#include <machine/bus.h> 63 64#include <net/if.h> 65#include <net/if_dl.h> 66#include <net/if_media.h> 67#include <net/if_types.h> 68#include <net/if_arp.h> 69#include <net/ethernet.h> 70#include <net/if_llc.h> 71 72#include <net80211/ieee80211_var.h> 73#include <net80211/ieee80211_regdomain.h> 74#ifdef IEEE80211_SUPPORT_SUPERG 75#include <net80211/ieee80211_superg.h> 76#endif 77#ifdef IEEE80211_SUPPORT_TDMA 78#include <net80211/ieee80211_tdma.h> 79#endif 80#include <net80211/ieee80211_ht.h> 81 82#include <net/bpf.h> 83 84#ifdef INET 85#include <netinet/in.h> 86#include <netinet/if_ether.h> 87#endif 88 89#include <dev/ath/if_athvar.h> 90#include <dev/ath/ath_hal/ah_devid.h> /* XXX for softled */ 91#include <dev/ath/ath_hal/ah_diagcodes.h> 92 93#include <dev/ath/if_ath_debug.h> 94 95#ifdef ATH_TX99_DIAG 96#include <dev/ath/ath_tx99/ath_tx99.h> 97#endif 98 99#include <dev/ath/if_ath_misc.h> 100#include <dev/ath/if_ath_tx.h> 101#include <dev/ath/if_ath_tx_ht.h> 102 103/* 104 * How many retries to perform in software 105 */ 106#define SWMAX_RETRIES 10 107 108static int ath_tx_ampdu_pending(struct ath_softc *sc, struct ath_node *an, 109 int tid); 110static int ath_tx_ampdu_running(struct ath_softc *sc, struct ath_node *an, 111 int tid); 112static int ath_tx_action_frame_override_queue(struct ath_softc *sc, 113 struct ieee80211_node *ni, struct mbuf *m0, int *tid); 114static int ath_tx_seqno_required(struct ath_softc *sc, 115 struct ieee80211_node *ni, struct ath_buf *bf, struct mbuf *m0); 116 117/* 118 * Whether to use the 11n rate scenario functions or not 119 */ 120static inline int 121ath_tx_is_11n(struct ath_softc *sc) 122{ 123 return (sc->sc_ah->ah_magic == 0x20065416); 124} 125 126/* 127 * Obtain the current TID from the given frame. 128 * 129 * Non-QoS frames need to go into TID 16 (IEEE80211_NONQOS_TID.) 130 * This has implications for which AC/priority the packet is placed 131 * in. 132 */ 133static int 134ath_tx_gettid(struct ath_softc *sc, const struct mbuf *m0) 135{ 136 const struct ieee80211_frame *wh; 137 int pri = M_WME_GETAC(m0); 138 139 wh = mtod(m0, const struct ieee80211_frame *); 140 if (! IEEE80211_QOS_HAS_SEQ(wh)) 141 return IEEE80211_NONQOS_TID; 142 else 143 return WME_AC_TO_TID(pri); 144} 145 146/* 147 * Determine what the correct AC queue for the given frame 148 * should be. 149 * 150 * This code assumes that the TIDs map consistently to 151 * the underlying hardware (or software) ath_txq. 152 * Since the sender may try to set an AC which is 153 * arbitrary, non-QoS TIDs may end up being put on 154 * completely different ACs. There's no way to put a 155 * TID into multiple ath_txq's for scheduling, so 156 * for now we override the AC/TXQ selection and set 157 * non-QOS TID frames into the BE queue. 158 * 159 * This may be completely incorrect - specifically, 160 * some management frames may end up out of order 161 * compared to the QoS traffic they're controlling. 162 * I'll look into this later. 163 */ 164static int 165ath_tx_getac(struct ath_softc *sc, const struct mbuf *m0) 166{ 167 const struct ieee80211_frame *wh; 168 int pri = M_WME_GETAC(m0); 169 wh = mtod(m0, const struct ieee80211_frame *); 170 if (IEEE80211_QOS_HAS_SEQ(wh)) 171 return pri; 172 173 return WME_AC_BE; 174} 175 176void 177ath_txfrag_cleanup(struct ath_softc *sc, 178 ath_bufhead *frags, struct ieee80211_node *ni) 179{ 180 struct ath_buf *bf, *next; 181 182 ATH_TXBUF_LOCK_ASSERT(sc); 183 184 TAILQ_FOREACH_SAFE(bf, frags, bf_list, next) { 185 /* NB: bf assumed clean */ 186 TAILQ_REMOVE(frags, bf, bf_list); 187 TAILQ_INSERT_HEAD(&sc->sc_txbuf, bf, bf_list); 188 ieee80211_node_decref(ni); 189 } 190} 191 192/* 193 * Setup xmit of a fragmented frame. Allocate a buffer 194 * for each frag and bump the node reference count to 195 * reflect the held reference to be setup by ath_tx_start. 196 */ 197int 198ath_txfrag_setup(struct ath_softc *sc, ath_bufhead *frags, 199 struct mbuf *m0, struct ieee80211_node *ni) 200{ 201 struct mbuf *m; 202 struct ath_buf *bf; 203 204 ATH_TXBUF_LOCK(sc); 205 for (m = m0->m_nextpkt; m != NULL; m = m->m_nextpkt) { 206 bf = _ath_getbuf_locked(sc); 207 if (bf == NULL) { /* out of buffers, cleanup */ 208 device_printf(sc->sc_dev, "%s: no buffer?\n", 209 __func__); 210 ath_txfrag_cleanup(sc, frags, ni); 211 break; 212 } 213 ieee80211_node_incref(ni); 214 TAILQ_INSERT_TAIL(frags, bf, bf_list); 215 } 216 ATH_TXBUF_UNLOCK(sc); 217 218 return !TAILQ_EMPTY(frags); 219} 220 221/* 222 * Reclaim mbuf resources. For fragmented frames we 223 * need to claim each frag chained with m_nextpkt. 224 */ 225void 226ath_freetx(struct mbuf *m) 227{ 228 struct mbuf *next; 229 230 do { 231 next = m->m_nextpkt; 232 m->m_nextpkt = NULL; 233 m_freem(m); 234 } while ((m = next) != NULL); 235} 236 237static int 238ath_tx_dmasetup(struct ath_softc *sc, struct ath_buf *bf, struct mbuf *m0) 239{ 240 struct mbuf *m; 241 int error; 242 243 /* 244 * Load the DMA map so any coalescing is done. This 245 * also calculates the number of descriptors we need. 246 */ 247 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m0, 248 bf->bf_segs, &bf->bf_nseg, 249 BUS_DMA_NOWAIT); 250 if (error == EFBIG) { 251 /* XXX packet requires too many descriptors */ 252 bf->bf_nseg = ATH_TXDESC+1; 253 } else if (error != 0) { 254 sc->sc_stats.ast_tx_busdma++; 255 ath_freetx(m0); 256 return error; 257 } 258 /* 259 * Discard null packets and check for packets that 260 * require too many TX descriptors. We try to convert 261 * the latter to a cluster. 262 */ 263 if (bf->bf_nseg > ATH_TXDESC) { /* too many desc's, linearize */ 264 sc->sc_stats.ast_tx_linear++; 265 m = m_collapse(m0, M_DONTWAIT, ATH_TXDESC); 266 if (m == NULL) { 267 ath_freetx(m0); 268 sc->sc_stats.ast_tx_nombuf++; 269 return ENOMEM; 270 } 271 m0 = m; 272 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m0, 273 bf->bf_segs, &bf->bf_nseg, 274 BUS_DMA_NOWAIT); 275 if (error != 0) { 276 sc->sc_stats.ast_tx_busdma++; 277 ath_freetx(m0); 278 return error; 279 } 280 KASSERT(bf->bf_nseg <= ATH_TXDESC, 281 ("too many segments after defrag; nseg %u", bf->bf_nseg)); 282 } else if (bf->bf_nseg == 0) { /* null packet, discard */ 283 sc->sc_stats.ast_tx_nodata++; 284 ath_freetx(m0); 285 return EIO; 286 } 287 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: m %p len %u\n", 288 __func__, m0, m0->m_pkthdr.len); 289 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE); 290 bf->bf_m = m0; 291 292 return 0; 293} 294 295/* 296 * Chain together segments+descriptors for a non-11n frame. 297 */ 298static void 299ath_tx_chaindesclist(struct ath_softc *sc, struct ath_buf *bf) 300{ 301 struct ath_hal *ah = sc->sc_ah; 302 struct ath_desc *ds, *ds0; 303 int i; 304 305 /* 306 * Fillin the remainder of the descriptor info. 307 */ 308 ds0 = ds = bf->bf_desc; 309 for (i = 0; i < bf->bf_nseg; i++, ds++) { 310 ds->ds_data = bf->bf_segs[i].ds_addr; 311 if (i == bf->bf_nseg - 1) 312 ds->ds_link = 0; 313 else 314 ds->ds_link = bf->bf_daddr + sizeof(*ds) * (i + 1); 315 ath_hal_filltxdesc(ah, ds 316 , bf->bf_segs[i].ds_len /* segment length */ 317 , i == 0 /* first segment */ 318 , i == bf->bf_nseg - 1 /* last segment */ 319 , ds0 /* first descriptor */ 320 ); 321 DPRINTF(sc, ATH_DEBUG_XMIT, 322 "%s: %d: %08x %08x %08x %08x %08x %08x\n", 323 __func__, i, ds->ds_link, ds->ds_data, 324 ds->ds_ctl0, ds->ds_ctl1, ds->ds_hw[0], ds->ds_hw[1]); 325 bf->bf_lastds = ds; 326 } 327 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE); 328} 329 330/* 331 * Fill in the descriptor list for a aggregate subframe. 332 * 333 * The subframe is returned with the ds_link field in the last subframe 334 * pointing to 0. 335 */ 336static void 337ath_tx_chaindesclist_subframe(struct ath_softc *sc, struct ath_buf *bf) 338{ 339 struct ath_hal *ah = sc->sc_ah; 340 struct ath_desc *ds, *ds0; 341 int i; 342 343 ds0 = ds = bf->bf_desc; 344 345 /* 346 * There's no need to call ath_hal_setupfirsttxdesc here; 347 * That's only going to occur for the first frame in an aggregate. 348 */ 349 for (i = 0; i < bf->bf_nseg; i++, ds++) { 350 ds->ds_data = bf->bf_segs[i].ds_addr; 351 if (i == bf->bf_nseg - 1) 352 ds->ds_link = 0; 353 else 354 ds->ds_link = bf->bf_daddr + sizeof(*ds) * (i + 1); 355 356 /* 357 * This performs the setup for an aggregate frame. 358 * This includes enabling the aggregate flags if needed. 359 */ 360 ath_hal_chaintxdesc(ah, ds, 361 bf->bf_state.bfs_pktlen, 362 bf->bf_state.bfs_hdrlen, 363 HAL_PKT_TYPE_AMPDU, /* forces aggregate bits to be set */ 364 bf->bf_state.bfs_keyix, 365 0, /* cipher, calculated from keyix */ 366 bf->bf_state.bfs_ndelim, 367 bf->bf_segs[i].ds_len, /* segment length */ 368 i == 0, /* first segment */ 369 i == bf->bf_nseg - 1, /* last segment */ 370 bf->bf_next == NULL /* last sub-frame in aggr */ 371 ); 372 373 DPRINTF(sc, ATH_DEBUG_XMIT, 374 "%s: %d: %08x %08x %08x %08x %08x %08x\n", 375 __func__, i, ds->ds_link, ds->ds_data, 376 ds->ds_ctl0, ds->ds_ctl1, ds->ds_hw[0], ds->ds_hw[1]); 377 bf->bf_lastds = ds; 378 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 379 BUS_DMASYNC_PREWRITE); 380 } 381} 382 383/* 384 * Setup segments+descriptors for an 11n aggregate. 385 * bf_first is the first buffer in the aggregate. 386 * The descriptor list must already been linked together using 387 * bf->bf_next. 388 */ 389static void 390ath_tx_setds_11n(struct ath_softc *sc, struct ath_buf *bf_first) 391{ 392 struct ath_buf *bf, *bf_prev = NULL; 393 394 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, "%s: nframes=%d, al=%d\n", 395 __func__, bf_first->bf_state.bfs_nframes, 396 bf_first->bf_state.bfs_al); 397 398 /* 399 * Setup all descriptors of all subframes. 400 */ 401 bf = bf_first; 402 while (bf != NULL) { 403 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, 404 "%s: bf=%p, nseg=%d, pktlen=%d, seqno=%d\n", 405 __func__, bf, bf->bf_nseg, bf->bf_state.bfs_pktlen, 406 SEQNO(bf->bf_state.bfs_seqno)); 407 408 /* Sub-frame setup */ 409 ath_tx_chaindesclist_subframe(sc, bf); 410 411 /* 412 * Link the last descriptor of the previous frame 413 * to the beginning descriptor of this frame. 414 */ 415 if (bf_prev != NULL) 416 bf_prev->bf_lastds->ds_link = bf->bf_daddr; 417 418 /* Save a copy so we can link the next descriptor in */ 419 bf_prev = bf; 420 bf = bf->bf_next; 421 } 422 423 /* 424 * Setup first descriptor of first frame. 425 * chaintxdesc() overwrites the descriptor entries; 426 * setupfirsttxdesc() merges in things. 427 * Otherwise various fields aren't set correctly (eg flags). 428 */ 429 ath_hal_setupfirsttxdesc(sc->sc_ah, 430 bf_first->bf_desc, 431 bf_first->bf_state.bfs_al, 432 bf_first->bf_state.bfs_txflags | HAL_TXDESC_INTREQ, 433 bf_first->bf_state.bfs_txpower, 434 bf_first->bf_state.bfs_txrate0, 435 bf_first->bf_state.bfs_try0, 436 bf_first->bf_state.bfs_txantenna, 437 bf_first->bf_state.bfs_ctsrate, 438 bf_first->bf_state.bfs_ctsduration); 439 440 /* 441 * Setup the last descriptor in the list. 442 * bf_prev points to the last; bf is NULL here. 443 */ 444 ath_hal_setuplasttxdesc(sc->sc_ah, bf_prev->bf_desc, 445 bf_first->bf_desc); 446 447 /* 448 * Set the first descriptor bf_lastds field to point to 449 * the last descriptor in the last subframe, that's where 450 * the status update will occur. 451 */ 452 bf_first->bf_lastds = bf_prev->bf_lastds; 453 454 /* 455 * And bf_last in the first descriptor points to the end of 456 * the aggregate list. 457 */ 458 bf_first->bf_last = bf_prev; 459 460 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, "%s: end\n", __func__); 461} 462 463static void 464ath_tx_handoff_mcast(struct ath_softc *sc, struct ath_txq *txq, 465 struct ath_buf *bf) 466{ 467 ATH_TXQ_LOCK_ASSERT(txq); 468 KASSERT((bf->bf_flags & ATH_BUF_BUSY) == 0, 469 ("%s: busy status 0x%x", __func__, bf->bf_flags)); 470 if (txq->axq_link != NULL) { 471 struct ath_buf *last = ATH_TXQ_LAST(txq, axq_q_s); 472 struct ieee80211_frame *wh; 473 474 /* mark previous frame */ 475 wh = mtod(last->bf_m, struct ieee80211_frame *); 476 wh->i_fc[1] |= IEEE80211_FC1_MORE_DATA; 477 bus_dmamap_sync(sc->sc_dmat, last->bf_dmamap, 478 BUS_DMASYNC_PREWRITE); 479 480 /* link descriptor */ 481 *txq->axq_link = bf->bf_daddr; 482 } 483 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list); 484 txq->axq_link = &bf->bf_lastds->ds_link; 485} 486 487/* 488 * Hand-off packet to a hardware queue. 489 */ 490static void 491ath_tx_handoff_hw(struct ath_softc *sc, struct ath_txq *txq, 492 struct ath_buf *bf) 493{ 494 struct ath_hal *ah = sc->sc_ah; 495 496 /* 497 * Insert the frame on the outbound list and pass it on 498 * to the hardware. Multicast frames buffered for power 499 * save stations and transmit from the CAB queue are stored 500 * on a s/w only queue and loaded on to the CAB queue in 501 * the SWBA handler since frames only go out on DTIM and 502 * to avoid possible races. 503 */ 504 ATH_TXQ_LOCK_ASSERT(txq); 505 KASSERT((bf->bf_flags & ATH_BUF_BUSY) == 0, 506 ("%s: busy status 0x%x", __func__, bf->bf_flags)); 507 KASSERT(txq->axq_qnum != ATH_TXQ_SWQ, 508 ("ath_tx_handoff_hw called for mcast queue")); 509 510#if 0 511 /* 512 * This causes a LOR. Find out where the PCU lock is being 513 * held whilst the TXQ lock is grabbed - that shouldn't 514 * be occuring. 515 */ 516 ATH_PCU_LOCK(sc); 517 if (sc->sc_inreset_cnt) { 518 ATH_PCU_UNLOCK(sc); 519 DPRINTF(sc, ATH_DEBUG_RESET, 520 "%s: called with sc_in_reset != 0\n", 521 __func__); 522 DPRINTF(sc, ATH_DEBUG_XMIT, 523 "%s: queued: TXDP[%u] = %p (%p) depth %d\n", 524 __func__, txq->axq_qnum, 525 (caddr_t)bf->bf_daddr, bf->bf_desc, 526 txq->axq_depth); 527 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list); 528 if (bf->bf_state.bfs_aggr) 529 txq->axq_aggr_depth++; 530 /* 531 * There's no need to update axq_link; the hardware 532 * is in reset and once the reset is complete, any 533 * non-empty queues will simply have DMA restarted. 534 */ 535 return; 536 } 537 ATH_PCU_UNLOCK(sc); 538#endif 539 540 /* For now, so not to generate whitespace diffs */ 541 if (1) { 542#ifdef IEEE80211_SUPPORT_TDMA 543 int qbusy; 544 545 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list); 546 qbusy = ath_hal_txqenabled(ah, txq->axq_qnum); 547 if (txq->axq_link == NULL) { 548 /* 549 * Be careful writing the address to TXDP. If 550 * the tx q is enabled then this write will be 551 * ignored. Normally this is not an issue but 552 * when tdma is in use and the q is beacon gated 553 * this race can occur. If the q is busy then 554 * defer the work to later--either when another 555 * packet comes along or when we prepare a beacon 556 * frame at SWBA. 557 */ 558 if (!qbusy) { 559 ath_hal_puttxbuf(ah, txq->axq_qnum, 560 bf->bf_daddr); 561 txq->axq_flags &= ~ATH_TXQ_PUTPENDING; 562 DPRINTF(sc, ATH_DEBUG_XMIT, 563 "%s: TXDP[%u] = %p (%p) depth %d\n", 564 __func__, txq->axq_qnum, 565 (caddr_t)bf->bf_daddr, bf->bf_desc, 566 txq->axq_depth); 567 } else { 568 txq->axq_flags |= ATH_TXQ_PUTPENDING; 569 DPRINTF(sc, ATH_DEBUG_TDMA | ATH_DEBUG_XMIT, 570 "%s: Q%u busy, defer enable\n", __func__, 571 txq->axq_qnum); 572 } 573 } else { 574 *txq->axq_link = bf->bf_daddr; 575 DPRINTF(sc, ATH_DEBUG_XMIT, 576 "%s: link[%u](%p)=%p (%p) depth %d\n", __func__, 577 txq->axq_qnum, txq->axq_link, 578 (caddr_t)bf->bf_daddr, bf->bf_desc, 579 txq->axq_depth); 580 if ((txq->axq_flags & ATH_TXQ_PUTPENDING) && !qbusy) { 581 /* 582 * The q was busy when we previously tried 583 * to write the address of the first buffer 584 * in the chain. Since it's not busy now 585 * handle this chore. We are certain the 586 * buffer at the front is the right one since 587 * axq_link is NULL only when the buffer list 588 * is/was empty. 589 */ 590 ath_hal_puttxbuf(ah, txq->axq_qnum, 591 TAILQ_FIRST(&txq->axq_q)->bf_daddr); 592 txq->axq_flags &= ~ATH_TXQ_PUTPENDING; 593 DPRINTF(sc, ATH_DEBUG_TDMA | ATH_DEBUG_XMIT, 594 "%s: Q%u restarted\n", __func__, 595 txq->axq_qnum); 596 } 597 } 598#else 599 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list); 600 if (txq->axq_link == NULL) { 601 ath_hal_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); 602 DPRINTF(sc, ATH_DEBUG_XMIT, 603 "%s: TXDP[%u] = %p (%p) depth %d\n", 604 __func__, txq->axq_qnum, 605 (caddr_t)bf->bf_daddr, bf->bf_desc, 606 txq->axq_depth); 607 } else { 608 *txq->axq_link = bf->bf_daddr; 609 DPRINTF(sc, ATH_DEBUG_XMIT, 610 "%s: link[%u](%p)=%p (%p) depth %d\n", __func__, 611 txq->axq_qnum, txq->axq_link, 612 (caddr_t)bf->bf_daddr, bf->bf_desc, 613 txq->axq_depth); 614 } 615#endif /* IEEE80211_SUPPORT_TDMA */ 616 if (bf->bf_state.bfs_aggr) 617 txq->axq_aggr_depth++; 618 txq->axq_link = &bf->bf_lastds->ds_link; 619 ath_hal_txstart(ah, txq->axq_qnum); 620 } 621} 622 623/* 624 * Restart TX DMA for the given TXQ. 625 * 626 * This must be called whether the queue is empty or not. 627 */ 628void 629ath_txq_restart_dma(struct ath_softc *sc, struct ath_txq *txq) 630{ 631 struct ath_hal *ah = sc->sc_ah; 632 struct ath_buf *bf, *bf_last; 633 634 ATH_TXQ_LOCK_ASSERT(txq); 635 636 /* This is always going to be cleared, empty or not */ 637 txq->axq_flags &= ~ATH_TXQ_PUTPENDING; 638 639 /* XXX make this ATH_TXQ_FIRST */ 640 bf = TAILQ_FIRST(&txq->axq_q); 641 bf_last = ATH_TXQ_LAST(txq, axq_q_s); 642 643 if (bf == NULL) 644 return; 645 646 ath_hal_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); 647 txq->axq_link = &bf_last->bf_lastds->ds_link; 648 ath_hal_txstart(ah, txq->axq_qnum); 649} 650 651/* 652 * Hand off a packet to the hardware (or mcast queue.) 653 * 654 * The relevant hardware txq should be locked. 655 */ 656static void 657ath_tx_handoff(struct ath_softc *sc, struct ath_txq *txq, struct ath_buf *bf) 658{ 659 ATH_TXQ_LOCK_ASSERT(txq); 660 661 if (txq->axq_qnum == ATH_TXQ_SWQ) 662 ath_tx_handoff_mcast(sc, txq, bf); 663 else 664 ath_tx_handoff_hw(sc, txq, bf); 665} 666 667static int 668ath_tx_tag_crypto(struct ath_softc *sc, struct ieee80211_node *ni, 669 struct mbuf *m0, int iswep, int isfrag, int *hdrlen, int *pktlen, 670 int *keyix) 671{ 672 DPRINTF(sc, ATH_DEBUG_XMIT, 673 "%s: hdrlen=%d, pktlen=%d, isfrag=%d, iswep=%d, m0=%p\n", 674 __func__, 675 *hdrlen, 676 *pktlen, 677 isfrag, 678 iswep, 679 m0); 680 681 if (iswep) { 682 const struct ieee80211_cipher *cip; 683 struct ieee80211_key *k; 684 685 /* 686 * Construct the 802.11 header+trailer for an encrypted 687 * frame. The only reason this can fail is because of an 688 * unknown or unsupported cipher/key type. 689 */ 690 k = ieee80211_crypto_encap(ni, m0); 691 if (k == NULL) { 692 /* 693 * This can happen when the key is yanked after the 694 * frame was queued. Just discard the frame; the 695 * 802.11 layer counts failures and provides 696 * debugging/diagnostics. 697 */ 698 return (0); 699 } 700 /* 701 * Adjust the packet + header lengths for the crypto 702 * additions and calculate the h/w key index. When 703 * a s/w mic is done the frame will have had any mic 704 * added to it prior to entry so m0->m_pkthdr.len will 705 * account for it. Otherwise we need to add it to the 706 * packet length. 707 */ 708 cip = k->wk_cipher; 709 (*hdrlen) += cip->ic_header; 710 (*pktlen) += cip->ic_header + cip->ic_trailer; 711 /* NB: frags always have any TKIP MIC done in s/w */ 712 if ((k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && !isfrag) 713 (*pktlen) += cip->ic_miclen; 714 (*keyix) = k->wk_keyix; 715 } else if (ni->ni_ucastkey.wk_cipher == &ieee80211_cipher_none) { 716 /* 717 * Use station key cache slot, if assigned. 718 */ 719 (*keyix) = ni->ni_ucastkey.wk_keyix; 720 if ((*keyix) == IEEE80211_KEYIX_NONE) 721 (*keyix) = HAL_TXKEYIX_INVALID; 722 } else 723 (*keyix) = HAL_TXKEYIX_INVALID; 724 725 return (1); 726} 727 728/* 729 * Calculate whether interoperability protection is required for 730 * this frame. 731 * 732 * This requires the rate control information be filled in, 733 * as the protection requirement depends upon the current 734 * operating mode / PHY. 735 */ 736static void 737ath_tx_calc_protection(struct ath_softc *sc, struct ath_buf *bf) 738{ 739 struct ieee80211_frame *wh; 740 uint8_t rix; 741 uint16_t flags; 742 int shortPreamble; 743 const HAL_RATE_TABLE *rt = sc->sc_currates; 744 struct ifnet *ifp = sc->sc_ifp; 745 struct ieee80211com *ic = ifp->if_l2com; 746 747 flags = bf->bf_state.bfs_txflags; 748 rix = bf->bf_state.bfs_rc[0].rix; 749 shortPreamble = bf->bf_state.bfs_shpream; 750 wh = mtod(bf->bf_m, struct ieee80211_frame *); 751 752 /* 753 * If 802.11g protection is enabled, determine whether 754 * to use RTS/CTS or just CTS. Note that this is only 755 * done for OFDM unicast frames. 756 */ 757 if ((ic->ic_flags & IEEE80211_F_USEPROT) && 758 rt->info[rix].phy == IEEE80211_T_OFDM && 759 (flags & HAL_TXDESC_NOACK) == 0) { 760 bf->bf_state.bfs_doprot = 1; 761 /* XXX fragments must use CCK rates w/ protection */ 762 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 763 flags |= HAL_TXDESC_RTSENA; 764 } else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 765 flags |= HAL_TXDESC_CTSENA; 766 } 767 /* 768 * For frags it would be desirable to use the 769 * highest CCK rate for RTS/CTS. But stations 770 * farther away may detect it at a lower CCK rate 771 * so use the configured protection rate instead 772 * (for now). 773 */ 774 sc->sc_stats.ast_tx_protect++; 775 } 776 777 /* 778 * If 11n protection is enabled and it's a HT frame, 779 * enable RTS. 780 * 781 * XXX ic_htprotmode or ic_curhtprotmode? 782 * XXX should it_htprotmode only matter if ic_curhtprotmode 783 * XXX indicates it's not a HT pure environment? 784 */ 785 if ((ic->ic_htprotmode == IEEE80211_PROT_RTSCTS) && 786 rt->info[rix].phy == IEEE80211_T_HT && 787 (flags & HAL_TXDESC_NOACK) == 0) { 788 flags |= HAL_TXDESC_RTSENA; 789 sc->sc_stats.ast_tx_htprotect++; 790 } 791 bf->bf_state.bfs_txflags = flags; 792} 793 794/* 795 * Update the frame duration given the currently selected rate. 796 * 797 * This also updates the frame duration value, so it will require 798 * a DMA flush. 799 */ 800static void 801ath_tx_calc_duration(struct ath_softc *sc, struct ath_buf *bf) 802{ 803 struct ieee80211_frame *wh; 804 uint8_t rix; 805 uint16_t flags; 806 int shortPreamble; 807 struct ath_hal *ah = sc->sc_ah; 808 const HAL_RATE_TABLE *rt = sc->sc_currates; 809 int isfrag = bf->bf_m->m_flags & M_FRAG; 810 811 flags = bf->bf_state.bfs_txflags; 812 rix = bf->bf_state.bfs_rc[0].rix; 813 shortPreamble = bf->bf_state.bfs_shpream; 814 wh = mtod(bf->bf_m, struct ieee80211_frame *); 815 816 /* 817 * Calculate duration. This logically belongs in the 802.11 818 * layer but it lacks sufficient information to calculate it. 819 */ 820 if ((flags & HAL_TXDESC_NOACK) == 0 && 821 (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_CTL) { 822 u_int16_t dur; 823 if (shortPreamble) 824 dur = rt->info[rix].spAckDuration; 825 else 826 dur = rt->info[rix].lpAckDuration; 827 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) { 828 dur += dur; /* additional SIFS+ACK */ 829 KASSERT(bf->bf_m->m_nextpkt != NULL, ("no fragment")); 830 /* 831 * Include the size of next fragment so NAV is 832 * updated properly. The last fragment uses only 833 * the ACK duration 834 */ 835 dur += ath_hal_computetxtime(ah, rt, 836 bf->bf_m->m_nextpkt->m_pkthdr.len, 837 rix, shortPreamble); 838 } 839 if (isfrag) { 840 /* 841 * Force hardware to use computed duration for next 842 * fragment by disabling multi-rate retry which updates 843 * duration based on the multi-rate duration table. 844 */ 845 bf->bf_state.bfs_ismrr = 0; 846 bf->bf_state.bfs_try0 = ATH_TXMGTTRY; 847 /* XXX update bfs_rc[0].try? */ 848 } 849 850 /* Update the duration field itself */ 851 *(u_int16_t *)wh->i_dur = htole16(dur); 852 } 853} 854 855static uint8_t 856ath_tx_get_rtscts_rate(struct ath_hal *ah, const HAL_RATE_TABLE *rt, 857 int cix, int shortPreamble) 858{ 859 uint8_t ctsrate; 860 861 /* 862 * CTS transmit rate is derived from the transmit rate 863 * by looking in the h/w rate table. We must also factor 864 * in whether or not a short preamble is to be used. 865 */ 866 /* NB: cix is set above where RTS/CTS is enabled */ 867 KASSERT(cix != 0xff, ("cix not setup")); 868 ctsrate = rt->info[cix].rateCode; 869 870 /* XXX this should only matter for legacy rates */ 871 if (shortPreamble) 872 ctsrate |= rt->info[cix].shortPreamble; 873 874 return (ctsrate); 875} 876 877/* 878 * Calculate the RTS/CTS duration for legacy frames. 879 */ 880static int 881ath_tx_calc_ctsduration(struct ath_hal *ah, int rix, int cix, 882 int shortPreamble, int pktlen, const HAL_RATE_TABLE *rt, 883 int flags) 884{ 885 int ctsduration = 0; 886 887 /* This mustn't be called for HT modes */ 888 if (rt->info[cix].phy == IEEE80211_T_HT) { 889 printf("%s: HT rate where it shouldn't be (0x%x)\n", 890 __func__, rt->info[cix].rateCode); 891 return (-1); 892 } 893 894 /* 895 * Compute the transmit duration based on the frame 896 * size and the size of an ACK frame. We call into the 897 * HAL to do the computation since it depends on the 898 * characteristics of the actual PHY being used. 899 * 900 * NB: CTS is assumed the same size as an ACK so we can 901 * use the precalculated ACK durations. 902 */ 903 if (shortPreamble) { 904 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ 905 ctsduration += rt->info[cix].spAckDuration; 906 ctsduration += ath_hal_computetxtime(ah, 907 rt, pktlen, rix, AH_TRUE); 908 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ 909 ctsduration += rt->info[rix].spAckDuration; 910 } else { 911 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ 912 ctsduration += rt->info[cix].lpAckDuration; 913 ctsduration += ath_hal_computetxtime(ah, 914 rt, pktlen, rix, AH_FALSE); 915 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ 916 ctsduration += rt->info[rix].lpAckDuration; 917 } 918 919 return (ctsduration); 920} 921 922/* 923 * Update the given ath_buf with updated rts/cts setup and duration 924 * values. 925 * 926 * To support rate lookups for each software retry, the rts/cts rate 927 * and cts duration must be re-calculated. 928 * 929 * This function assumes the RTS/CTS flags have been set as needed; 930 * mrr has been disabled; and the rate control lookup has been done. 931 * 932 * XXX TODO: MRR need only be disabled for the pre-11n NICs. 933 * XXX The 11n NICs support per-rate RTS/CTS configuration. 934 */ 935static void 936ath_tx_set_rtscts(struct ath_softc *sc, struct ath_buf *bf) 937{ 938 uint16_t ctsduration = 0; 939 uint8_t ctsrate = 0; 940 uint8_t rix = bf->bf_state.bfs_rc[0].rix; 941 uint8_t cix = 0; 942 const HAL_RATE_TABLE *rt = sc->sc_currates; 943 944 /* 945 * No RTS/CTS enabled? Don't bother. 946 */ 947 if ((bf->bf_state.bfs_txflags & 948 (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA)) == 0) { 949 /* XXX is this really needed? */ 950 bf->bf_state.bfs_ctsrate = 0; 951 bf->bf_state.bfs_ctsduration = 0; 952 return; 953 } 954 955 /* 956 * If protection is enabled, use the protection rix control 957 * rate. Otherwise use the rate0 control rate. 958 */ 959 if (bf->bf_state.bfs_doprot) 960 rix = sc->sc_protrix; 961 else 962 rix = bf->bf_state.bfs_rc[0].rix; 963 964 /* 965 * If the raw path has hard-coded ctsrate0 to something, 966 * use it. 967 */ 968 if (bf->bf_state.bfs_ctsrate0 != 0) 969 cix = ath_tx_findrix(sc, bf->bf_state.bfs_ctsrate0); 970 else 971 /* Control rate from above */ 972 cix = rt->info[rix].controlRate; 973 974 /* Calculate the rtscts rate for the given cix */ 975 ctsrate = ath_tx_get_rtscts_rate(sc->sc_ah, rt, cix, 976 bf->bf_state.bfs_shpream); 977 978 /* The 11n chipsets do ctsduration calculations for you */ 979 if (! ath_tx_is_11n(sc)) 980 ctsduration = ath_tx_calc_ctsduration(sc->sc_ah, rix, cix, 981 bf->bf_state.bfs_shpream, bf->bf_state.bfs_pktlen, 982 rt, bf->bf_state.bfs_txflags); 983 984 /* Squirrel away in ath_buf */ 985 bf->bf_state.bfs_ctsrate = ctsrate; 986 bf->bf_state.bfs_ctsduration = ctsduration; 987 988 /* 989 * Must disable multi-rate retry when using RTS/CTS. 990 * XXX TODO: only for pre-11n NICs. 991 */ 992 bf->bf_state.bfs_ismrr = 0; 993 bf->bf_state.bfs_try0 = 994 bf->bf_state.bfs_rc[0].tries = ATH_TXMGTTRY; /* XXX ew */ 995} 996 997/* 998 * Setup the descriptor chain for a normal or fast-frame 999 * frame. 1000 */ 1001static void 1002ath_tx_setds(struct ath_softc *sc, struct ath_buf *bf) 1003{ 1004 struct ath_desc *ds = bf->bf_desc; 1005 struct ath_hal *ah = sc->sc_ah; 1006 1007 ath_hal_setuptxdesc(ah, ds 1008 , bf->bf_state.bfs_pktlen /* packet length */ 1009 , bf->bf_state.bfs_hdrlen /* header length */ 1010 , bf->bf_state.bfs_atype /* Atheros packet type */ 1011 , bf->bf_state.bfs_txpower /* txpower */ 1012 , bf->bf_state.bfs_txrate0 1013 , bf->bf_state.bfs_try0 /* series 0 rate/tries */ 1014 , bf->bf_state.bfs_keyix /* key cache index */ 1015 , bf->bf_state.bfs_txantenna /* antenna mode */ 1016 , bf->bf_state.bfs_txflags /* flags */ 1017 , bf->bf_state.bfs_ctsrate /* rts/cts rate */ 1018 , bf->bf_state.bfs_ctsduration /* rts/cts duration */ 1019 ); 1020 1021 /* 1022 * This will be overriden when the descriptor chain is written. 1023 */ 1024 bf->bf_lastds = ds; 1025 bf->bf_last = bf; 1026 1027 /* XXX TODO: Setup descriptor chain */ 1028} 1029 1030/* 1031 * Do a rate lookup. 1032 * 1033 * This performs a rate lookup for the given ath_buf only if it's required. 1034 * Non-data frames and raw frames don't require it. 1035 * 1036 * This populates the primary and MRR entries; MRR values are 1037 * then disabled later on if something requires it (eg RTS/CTS on 1038 * pre-11n chipsets. 1039 * 1040 * This needs to be done before the RTS/CTS fields are calculated 1041 * as they may depend upon the rate chosen. 1042 */ 1043static void 1044ath_tx_do_ratelookup(struct ath_softc *sc, struct ath_buf *bf) 1045{ 1046 uint8_t rate, rix; 1047 int try0; 1048 1049 if (! bf->bf_state.bfs_doratelookup) 1050 return; 1051 1052 /* Get rid of any previous state */ 1053 bzero(bf->bf_state.bfs_rc, sizeof(bf->bf_state.bfs_rc)); 1054 1055 ATH_NODE_LOCK(ATH_NODE(bf->bf_node)); 1056 ath_rate_findrate(sc, ATH_NODE(bf->bf_node), bf->bf_state.bfs_shpream, 1057 bf->bf_state.bfs_pktlen, &rix, &try0, &rate); 1058 1059 /* In case MRR is disabled, make sure rc[0] is setup correctly */ 1060 bf->bf_state.bfs_rc[0].rix = rix; 1061 bf->bf_state.bfs_rc[0].ratecode = rate; 1062 bf->bf_state.bfs_rc[0].tries = try0; 1063 1064 if (bf->bf_state.bfs_ismrr && try0 != ATH_TXMAXTRY) 1065 ath_rate_getxtxrates(sc, ATH_NODE(bf->bf_node), rix, 1066 bf->bf_state.bfs_rc); 1067 ATH_NODE_UNLOCK(ATH_NODE(bf->bf_node)); 1068 1069 sc->sc_txrix = rix; /* for LED blinking */ 1070 sc->sc_lastdatarix = rix; /* for fast frames */ 1071 bf->bf_state.bfs_try0 = try0; 1072 bf->bf_state.bfs_txrate0 = rate; 1073} 1074 1075/* 1076 * Set the rate control fields in the given descriptor based on 1077 * the bf_state fields and node state. 1078 * 1079 * The bfs fields should already be set with the relevant rate 1080 * control information, including whether MRR is to be enabled. 1081 * 1082 * Since the FreeBSD HAL currently sets up the first TX rate 1083 * in ath_hal_setuptxdesc(), this will setup the MRR 1084 * conditionally for the pre-11n chips, and call ath_buf_set_rate 1085 * unconditionally for 11n chips. These require the 11n rate 1086 * scenario to be set if MCS rates are enabled, so it's easier 1087 * to just always call it. The caller can then only set rates 2, 3 1088 * and 4 if multi-rate retry is needed. 1089 */ 1090static void 1091ath_tx_set_ratectrl(struct ath_softc *sc, struct ieee80211_node *ni, 1092 struct ath_buf *bf) 1093{ 1094 struct ath_rc_series *rc = bf->bf_state.bfs_rc; 1095 1096 /* If mrr is disabled, blank tries 1, 2, 3 */ 1097 if (! bf->bf_state.bfs_ismrr) 1098 rc[1].tries = rc[2].tries = rc[3].tries = 0; 1099 1100 /* 1101 * Always call - that way a retried descriptor will 1102 * have the MRR fields overwritten. 1103 * 1104 * XXX TODO: see if this is really needed - setting up 1105 * the first descriptor should set the MRR fields to 0 1106 * for us anyway. 1107 */ 1108 if (ath_tx_is_11n(sc)) { 1109 ath_buf_set_rate(sc, ni, bf); 1110 } else { 1111 ath_hal_setupxtxdesc(sc->sc_ah, bf->bf_desc 1112 , rc[1].ratecode, rc[1].tries 1113 , rc[2].ratecode, rc[2].tries 1114 , rc[3].ratecode, rc[3].tries 1115 ); 1116 } 1117} 1118 1119/* 1120 * Transmit the given frame to the hardware. 1121 * 1122 * The frame must already be setup; rate control must already have 1123 * been done. 1124 * 1125 * XXX since the TXQ lock is being held here (and I dislike holding 1126 * it for this long when not doing software aggregation), later on 1127 * break this function into "setup_normal" and "xmit_normal". The 1128 * lock only needs to be held for the ath_tx_handoff call. 1129 */ 1130static void 1131ath_tx_xmit_normal(struct ath_softc *sc, struct ath_txq *txq, 1132 struct ath_buf *bf) 1133{ 1134 1135 ATH_TXQ_LOCK_ASSERT(txq); 1136 1137 /* Setup the descriptor before handoff */ 1138 ath_tx_do_ratelookup(sc, bf); 1139 ath_tx_calc_duration(sc, bf); 1140 ath_tx_calc_protection(sc, bf); 1141 ath_tx_set_rtscts(sc, bf); 1142 ath_tx_rate_fill_rcflags(sc, bf); 1143 ath_tx_setds(sc, bf); 1144 ath_tx_set_ratectrl(sc, bf->bf_node, bf); 1145 ath_tx_chaindesclist(sc, bf); 1146 1147 /* Hand off to hardware */ 1148 ath_tx_handoff(sc, txq, bf); 1149} 1150 1151 1152 1153static int 1154ath_tx_normal_setup(struct ath_softc *sc, struct ieee80211_node *ni, 1155 struct ath_buf *bf, struct mbuf *m0, struct ath_txq *txq) 1156{ 1157 struct ieee80211vap *vap = ni->ni_vap; 1158 struct ath_hal *ah = sc->sc_ah; 1159 struct ifnet *ifp = sc->sc_ifp; 1160 struct ieee80211com *ic = ifp->if_l2com; 1161 const struct chanAccParams *cap = &ic->ic_wme.wme_chanParams; 1162 int error, iswep, ismcast, isfrag, ismrr; 1163 int keyix, hdrlen, pktlen, try0 = 0; 1164 u_int8_t rix = 0, txrate = 0; 1165 struct ath_desc *ds; 1166 struct ieee80211_frame *wh; 1167 u_int subtype, flags; 1168 HAL_PKT_TYPE atype; 1169 const HAL_RATE_TABLE *rt; 1170 HAL_BOOL shortPreamble; 1171 struct ath_node *an; 1172 u_int pri; 1173 1174 wh = mtod(m0, struct ieee80211_frame *); 1175 iswep = wh->i_fc[1] & IEEE80211_FC1_WEP; 1176 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 1177 isfrag = m0->m_flags & M_FRAG; 1178 hdrlen = ieee80211_anyhdrsize(wh); 1179 /* 1180 * Packet length must not include any 1181 * pad bytes; deduct them here. 1182 */ 1183 pktlen = m0->m_pkthdr.len - (hdrlen & 3); 1184 1185 /* Handle encryption twiddling if needed */ 1186 if (! ath_tx_tag_crypto(sc, ni, m0, iswep, isfrag, &hdrlen, 1187 &pktlen, &keyix)) { 1188 ath_freetx(m0); 1189 return EIO; 1190 } 1191 1192 /* packet header may have moved, reset our local pointer */ 1193 wh = mtod(m0, struct ieee80211_frame *); 1194 1195 pktlen += IEEE80211_CRC_LEN; 1196 1197 /* 1198 * Load the DMA map so any coalescing is done. This 1199 * also calculates the number of descriptors we need. 1200 */ 1201 error = ath_tx_dmasetup(sc, bf, m0); 1202 if (error != 0) 1203 return error; 1204 bf->bf_node = ni; /* NB: held reference */ 1205 m0 = bf->bf_m; /* NB: may have changed */ 1206 wh = mtod(m0, struct ieee80211_frame *); 1207 1208 /* setup descriptors */ 1209 ds = bf->bf_desc; 1210 rt = sc->sc_currates; 1211 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); 1212 1213 /* 1214 * NB: the 802.11 layer marks whether or not we should 1215 * use short preamble based on the current mode and 1216 * negotiated parameters. 1217 */ 1218 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 1219 (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE)) { 1220 shortPreamble = AH_TRUE; 1221 sc->sc_stats.ast_tx_shortpre++; 1222 } else { 1223 shortPreamble = AH_FALSE; 1224 } 1225 1226 an = ATH_NODE(ni); 1227 flags = HAL_TXDESC_CLRDMASK; /* XXX needed for crypto errs */ 1228 ismrr = 0; /* default no multi-rate retry*/ 1229 pri = M_WME_GETAC(m0); /* honor classification */ 1230 /* XXX use txparams instead of fixed values */ 1231 /* 1232 * Calculate Atheros packet type from IEEE80211 packet header, 1233 * setup for rate calculations, and select h/w transmit queue. 1234 */ 1235 switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) { 1236 case IEEE80211_FC0_TYPE_MGT: 1237 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 1238 if (subtype == IEEE80211_FC0_SUBTYPE_BEACON) 1239 atype = HAL_PKT_TYPE_BEACON; 1240 else if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 1241 atype = HAL_PKT_TYPE_PROBE_RESP; 1242 else if (subtype == IEEE80211_FC0_SUBTYPE_ATIM) 1243 atype = HAL_PKT_TYPE_ATIM; 1244 else 1245 atype = HAL_PKT_TYPE_NORMAL; /* XXX */ 1246 rix = an->an_mgmtrix; 1247 txrate = rt->info[rix].rateCode; 1248 if (shortPreamble) 1249 txrate |= rt->info[rix].shortPreamble; 1250 try0 = ATH_TXMGTTRY; 1251 flags |= HAL_TXDESC_INTREQ; /* force interrupt */ 1252 break; 1253 case IEEE80211_FC0_TYPE_CTL: 1254 atype = HAL_PKT_TYPE_PSPOLL; /* stop setting of duration */ 1255 rix = an->an_mgmtrix; 1256 txrate = rt->info[rix].rateCode; 1257 if (shortPreamble) 1258 txrate |= rt->info[rix].shortPreamble; 1259 try0 = ATH_TXMGTTRY; 1260 flags |= HAL_TXDESC_INTREQ; /* force interrupt */ 1261 break; 1262 case IEEE80211_FC0_TYPE_DATA: 1263 atype = HAL_PKT_TYPE_NORMAL; /* default */ 1264 /* 1265 * Data frames: multicast frames go out at a fixed rate, 1266 * EAPOL frames use the mgmt frame rate; otherwise consult 1267 * the rate control module for the rate to use. 1268 */ 1269 if (ismcast) { 1270 rix = an->an_mcastrix; 1271 txrate = rt->info[rix].rateCode; 1272 if (shortPreamble) 1273 txrate |= rt->info[rix].shortPreamble; 1274 try0 = 1; 1275 } else if (m0->m_flags & M_EAPOL) { 1276 /* XXX? maybe always use long preamble? */ 1277 rix = an->an_mgmtrix; 1278 txrate = rt->info[rix].rateCode; 1279 if (shortPreamble) 1280 txrate |= rt->info[rix].shortPreamble; 1281 try0 = ATH_TXMAXTRY; /* XXX?too many? */ 1282 } else { 1283 /* 1284 * Do rate lookup on each TX, rather than using 1285 * the hard-coded TX information decided here. 1286 */ 1287 ismrr = 1; 1288 bf->bf_state.bfs_doratelookup = 1; 1289 } 1290 if (cap->cap_wmeParams[pri].wmep_noackPolicy) 1291 flags |= HAL_TXDESC_NOACK; 1292 break; 1293 default: 1294 if_printf(ifp, "bogus frame type 0x%x (%s)\n", 1295 wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK, __func__); 1296 /* XXX statistic */ 1297 ath_freetx(m0); 1298 return EIO; 1299 } 1300 1301 /* 1302 * Calculate miscellaneous flags. 1303 */ 1304 if (ismcast) { 1305 flags |= HAL_TXDESC_NOACK; /* no ack on broad/multicast */ 1306 } else if (pktlen > vap->iv_rtsthreshold && 1307 (ni->ni_ath_flags & IEEE80211_NODE_FF) == 0) { 1308 flags |= HAL_TXDESC_RTSENA; /* RTS based on frame length */ 1309 sc->sc_stats.ast_tx_rts++; 1310 } 1311 if (flags & HAL_TXDESC_NOACK) /* NB: avoid double counting */ 1312 sc->sc_stats.ast_tx_noack++; 1313#ifdef IEEE80211_SUPPORT_TDMA 1314 if (sc->sc_tdma && (flags & HAL_TXDESC_NOACK) == 0) { 1315 DPRINTF(sc, ATH_DEBUG_TDMA, 1316 "%s: discard frame, ACK required w/ TDMA\n", __func__); 1317 sc->sc_stats.ast_tdma_ack++; 1318 ath_freetx(m0); 1319 return EIO; 1320 } 1321#endif 1322 1323 /* 1324 * Determine if a tx interrupt should be generated for 1325 * this descriptor. We take a tx interrupt to reap 1326 * descriptors when the h/w hits an EOL condition or 1327 * when the descriptor is specifically marked to generate 1328 * an interrupt. We periodically mark descriptors in this 1329 * way to insure timely replenishing of the supply needed 1330 * for sending frames. Defering interrupts reduces system 1331 * load and potentially allows more concurrent work to be 1332 * done but if done to aggressively can cause senders to 1333 * backup. 1334 * 1335 * NB: use >= to deal with sc_txintrperiod changing 1336 * dynamically through sysctl. 1337 */ 1338 if (flags & HAL_TXDESC_INTREQ) { 1339 txq->axq_intrcnt = 0; 1340 } else if (++txq->axq_intrcnt >= sc->sc_txintrperiod) { 1341 flags |= HAL_TXDESC_INTREQ; 1342 txq->axq_intrcnt = 0; 1343 } 1344 1345 /* This point forward is actual TX bits */ 1346 1347 /* 1348 * At this point we are committed to sending the frame 1349 * and we don't need to look at m_nextpkt; clear it in 1350 * case this frame is part of frag chain. 1351 */ 1352 m0->m_nextpkt = NULL; 1353 1354 if (IFF_DUMPPKTS(sc, ATH_DEBUG_XMIT)) 1355 ieee80211_dump_pkt(ic, mtod(m0, const uint8_t *), m0->m_len, 1356 sc->sc_hwmap[rix].ieeerate, -1); 1357 1358 if (ieee80211_radiotap_active_vap(vap)) { 1359 u_int64_t tsf = ath_hal_gettsf64(ah); 1360 1361 sc->sc_tx_th.wt_tsf = htole64(tsf); 1362 sc->sc_tx_th.wt_flags = sc->sc_hwmap[rix].txflags; 1363 if (iswep) 1364 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 1365 if (isfrag) 1366 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_FRAG; 1367 sc->sc_tx_th.wt_rate = sc->sc_hwmap[rix].ieeerate; 1368 sc->sc_tx_th.wt_txpower = ni->ni_txpower; 1369 sc->sc_tx_th.wt_antenna = sc->sc_txantenna; 1370 1371 ieee80211_radiotap_tx(vap, m0); 1372 } 1373 1374 /* Blank the legacy rate array */ 1375 bzero(&bf->bf_state.bfs_rc, sizeof(bf->bf_state.bfs_rc)); 1376 1377 /* 1378 * ath_buf_set_rate needs at least one rate/try to setup 1379 * the rate scenario. 1380 */ 1381 bf->bf_state.bfs_rc[0].rix = rix; 1382 bf->bf_state.bfs_rc[0].tries = try0; 1383 bf->bf_state.bfs_rc[0].ratecode = txrate; 1384 1385 /* Store the decided rate index values away */ 1386 bf->bf_state.bfs_pktlen = pktlen; 1387 bf->bf_state.bfs_hdrlen = hdrlen; 1388 bf->bf_state.bfs_atype = atype; 1389 bf->bf_state.bfs_txpower = ni->ni_txpower; 1390 bf->bf_state.bfs_txrate0 = txrate; 1391 bf->bf_state.bfs_try0 = try0; 1392 bf->bf_state.bfs_keyix = keyix; 1393 bf->bf_state.bfs_txantenna = sc->sc_txantenna; 1394 bf->bf_state.bfs_txflags = flags; 1395 bf->bf_state.bfs_shpream = shortPreamble; 1396 1397 /* XXX this should be done in ath_tx_setrate() */ 1398 bf->bf_state.bfs_ctsrate0 = 0; /* ie, no hard-coded ctsrate */ 1399 bf->bf_state.bfs_ctsrate = 0; /* calculated later */ 1400 bf->bf_state.bfs_ctsduration = 0; 1401 bf->bf_state.bfs_ismrr = ismrr; 1402 1403 return 0; 1404} 1405 1406/* 1407 * Direct-dispatch the current frame to the hardware. 1408 * 1409 * This can be called by the net80211 code. 1410 * 1411 * XXX what about locking? Or, push the seqno assign into the 1412 * XXX aggregate scheduler so its serialised? 1413 */ 1414int 1415ath_tx_start(struct ath_softc *sc, struct ieee80211_node *ni, 1416 struct ath_buf *bf, struct mbuf *m0) 1417{ 1418 struct ieee80211vap *vap = ni->ni_vap; 1419 struct ath_vap *avp = ATH_VAP(vap); 1420 int r = 0; 1421 u_int pri; 1422 int tid; 1423 struct ath_txq *txq; 1424 int ismcast; 1425 const struct ieee80211_frame *wh; 1426 int is_ampdu, is_ampdu_tx, is_ampdu_pending; 1427 //ieee80211_seq seqno; 1428 uint8_t type, subtype; 1429 1430 /* 1431 * Determine the target hardware queue. 1432 * 1433 * For multicast frames, the txq gets overridden appropriately 1434 * depending upon the state of PS. 1435 * 1436 * For any other frame, we do a TID/QoS lookup inside the frame 1437 * to see what the TID should be. If it's a non-QoS frame, the 1438 * AC and TID are overridden. The TID/TXQ code assumes the 1439 * TID is on a predictable hardware TXQ, so we don't support 1440 * having a node TID queued to multiple hardware TXQs. 1441 * This may change in the future but would require some locking 1442 * fudgery. 1443 */ 1444 pri = ath_tx_getac(sc, m0); 1445 tid = ath_tx_gettid(sc, m0); 1446 1447 txq = sc->sc_ac2q[pri]; 1448 wh = mtod(m0, struct ieee80211_frame *); 1449 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 1450 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1451 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 1452 1453 /* 1454 * Enforce how deep the multicast queue can grow. 1455 * 1456 * XXX duplicated in ath_raw_xmit(). 1457 */ 1458 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1459 ATH_TXQ_LOCK(sc->sc_cabq); 1460 1461 if (sc->sc_cabq->axq_depth > sc->sc_txq_mcastq_maxdepth) { 1462 sc->sc_stats.ast_tx_mcastq_overflow++; 1463 r = ENOBUFS; 1464 } 1465 1466 ATH_TXQ_UNLOCK(sc->sc_cabq); 1467 1468 if (r != 0) { 1469 m_freem(m0); 1470 return r; 1471 } 1472 } 1473 1474 /* A-MPDU TX */ 1475 is_ampdu_tx = ath_tx_ampdu_running(sc, ATH_NODE(ni), tid); 1476 is_ampdu_pending = ath_tx_ampdu_pending(sc, ATH_NODE(ni), tid); 1477 is_ampdu = is_ampdu_tx | is_ampdu_pending; 1478 1479 DPRINTF(sc, ATH_DEBUG_SW_TX, 1480 "%s: bf=%p, tid=%d, ac=%d, is_ampdu=%d\n", 1481 __func__, bf, tid, pri, is_ampdu); 1482 1483 /* 1484 * When servicing one or more stations in power-save mode 1485 * (or) if there is some mcast data waiting on the mcast 1486 * queue (to prevent out of order delivery) multicast frames 1487 * must be bufferd until after the beacon. 1488 * 1489 * TODO: we should lock the mcastq before we check the length. 1490 */ 1491 if (ismcast && (vap->iv_ps_sta || avp->av_mcastq.axq_depth)) 1492 txq = &avp->av_mcastq; 1493 1494 /* Do the generic frame setup */ 1495 /* XXX should just bzero the bf_state? */ 1496 bf->bf_state.bfs_dobaw = 0; 1497 bf->bf_state.bfs_seqno_assigned = 0; 1498 bf->bf_state.bfs_need_seqno = 0; 1499 bf->bf_state.bfs_seqno = -1; /* XXX debugging */ 1500 1501 /* A-MPDU TX? Manually set sequence number */ 1502 /* Don't do it whilst pending; the net80211 layer still assigns them */ 1503 /* XXX do we need locking here? */ 1504 if (is_ampdu_tx) { 1505 ATH_TXQ_LOCK(txq); 1506 /* 1507 * Always call; this function will 1508 * handle making sure that null data frames 1509 * don't get a sequence number from the current 1510 * TID and thus mess with the BAW. 1511 */ 1512 //seqno = ath_tx_tid_seqno_assign(sc, ni, bf, m0); 1513 if (ath_tx_seqno_required(sc, ni, bf, m0)) { 1514 bf->bf_state.bfs_dobaw = 1; 1515 bf->bf_state.bfs_need_seqno = 1; 1516 } 1517 ATH_TXQ_UNLOCK(txq); 1518 } else { 1519 /* No AMPDU TX, we've been assigned a sequence number. */ 1520 if (IEEE80211_QOS_HAS_SEQ(wh)) { 1521 bf->bf_state.bfs_seqno_assigned = 1; 1522 /* XXX we should store the frag+seqno in bfs_seqno */ 1523 bf->bf_state.bfs_seqno = 1524 M_SEQNO_GET(m0) << IEEE80211_SEQ_SEQ_SHIFT; 1525 } 1526 } 1527 1528 /* 1529 * If needed, the sequence number has been assigned. 1530 * Squirrel it away somewhere easy to get to. 1531 */ 1532 //bf->bf_state.bfs_seqno = M_SEQNO_GET(m0) << IEEE80211_SEQ_SEQ_SHIFT; 1533 1534 /* Is ampdu pending? fetch the seqno and print it out */ 1535 if (is_ampdu_pending) 1536 DPRINTF(sc, ATH_DEBUG_SW_TX, 1537 "%s: tid %d: ampdu pending, seqno %d\n", 1538 __func__, tid, M_SEQNO_GET(m0)); 1539 1540 /* This also sets up the DMA map */ 1541 r = ath_tx_normal_setup(sc, ni, bf, m0, txq); 1542 1543 if (r != 0) 1544 return r; 1545 1546 /* At this point m0 could have changed! */ 1547 m0 = bf->bf_m; 1548 1549 DPRINTF(sc, ATH_DEBUG_SW_TX, 1550 "%s: DONE: bf=%p, tid=%d, ac=%d, is_ampdu=%d, dobaw=%d, seqno=%d\n", 1551 __func__, bf, tid, pri, is_ampdu, bf->bf_state.bfs_dobaw, M_SEQNO_GET(m0)); 1552 1553#if 1 1554 /* 1555 * If it's a multicast frame, do a direct-dispatch to the 1556 * destination hardware queue. Don't bother software 1557 * queuing it. 1558 */ 1559 /* 1560 * If it's a BAR frame, do a direct dispatch to the 1561 * destination hardware queue. Don't bother software 1562 * queuing it, as the TID will now be paused. 1563 * Sending a BAR frame can occur from the net80211 txa timer 1564 * (ie, retries) or from the ath txtask (completion call.) 1565 * It queues directly to hardware because the TID is paused 1566 * at this point (and won't be unpaused until the BAR has 1567 * either been TXed successfully or max retries has been 1568 * reached.) 1569 */ 1570 if (txq == &avp->av_mcastq) { 1571 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, 1572 "%s: bf=%p: mcastq: TX'ing\n", __func__, bf); 1573 ATH_TXQ_LOCK(txq); 1574 ath_tx_xmit_normal(sc, txq, bf); 1575 ATH_TXQ_UNLOCK(txq); 1576 } else if (type == IEEE80211_FC0_TYPE_CTL && 1577 subtype == IEEE80211_FC0_SUBTYPE_BAR) { 1578 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, 1579 "%s: BAR: TX'ing direct\n", __func__); 1580 ATH_TXQ_LOCK(txq); 1581 ath_tx_xmit_normal(sc, txq, bf); 1582 ATH_TXQ_UNLOCK(txq); 1583 } else { 1584 /* add to software queue */ 1585 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, 1586 "%s: bf=%p: swq: TX'ing\n", __func__, bf); 1587 ath_tx_swq(sc, ni, txq, bf); 1588 } 1589#else 1590 /* 1591 * For now, since there's no software queue, 1592 * direct-dispatch to the hardware. 1593 */ 1594 ATH_TXQ_LOCK(txq); 1595 ath_tx_xmit_normal(sc, txq, bf); 1596 ATH_TXQ_UNLOCK(txq); 1597#endif 1598 1599 return 0; 1600} 1601 1602static int 1603ath_tx_raw_start(struct ath_softc *sc, struct ieee80211_node *ni, 1604 struct ath_buf *bf, struct mbuf *m0, 1605 const struct ieee80211_bpf_params *params) 1606{ 1607 struct ifnet *ifp = sc->sc_ifp; 1608 struct ieee80211com *ic = ifp->if_l2com; 1609 struct ath_hal *ah = sc->sc_ah; 1610 struct ieee80211vap *vap = ni->ni_vap; 1611 int error, ismcast, ismrr; 1612 int keyix, hdrlen, pktlen, try0, txantenna; 1613 u_int8_t rix, txrate; 1614 struct ieee80211_frame *wh; 1615 u_int flags; 1616 HAL_PKT_TYPE atype; 1617 const HAL_RATE_TABLE *rt; 1618 struct ath_desc *ds; 1619 u_int pri; 1620 int o_tid = -1; 1621 int do_override; 1622 1623 wh = mtod(m0, struct ieee80211_frame *); 1624 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 1625 hdrlen = ieee80211_anyhdrsize(wh); 1626 /* 1627 * Packet length must not include any 1628 * pad bytes; deduct them here. 1629 */ 1630 /* XXX honor IEEE80211_BPF_DATAPAD */ 1631 pktlen = m0->m_pkthdr.len - (hdrlen & 3) + IEEE80211_CRC_LEN; 1632 1633 1634 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: ismcast=%d\n", 1635 __func__, ismcast); 1636 1637 /* Handle encryption twiddling if needed */ 1638 if (! ath_tx_tag_crypto(sc, ni, 1639 m0, params->ibp_flags & IEEE80211_BPF_CRYPTO, 0, 1640 &hdrlen, &pktlen, &keyix)) { 1641 ath_freetx(m0); 1642 return EIO; 1643 } 1644 /* packet header may have moved, reset our local pointer */ 1645 wh = mtod(m0, struct ieee80211_frame *); 1646 1647 /* Do the generic frame setup */ 1648 /* XXX should just bzero the bf_state? */ 1649 bf->bf_state.bfs_dobaw = 0; 1650 1651 error = ath_tx_dmasetup(sc, bf, m0); 1652 if (error != 0) 1653 return error; 1654 m0 = bf->bf_m; /* NB: may have changed */ 1655 wh = mtod(m0, struct ieee80211_frame *); 1656 bf->bf_node = ni; /* NB: held reference */ 1657 1658 flags = HAL_TXDESC_CLRDMASK; /* XXX needed for crypto errs */ 1659 flags |= HAL_TXDESC_INTREQ; /* force interrupt */ 1660 if (params->ibp_flags & IEEE80211_BPF_RTS) 1661 flags |= HAL_TXDESC_RTSENA; 1662 else if (params->ibp_flags & IEEE80211_BPF_CTS) { 1663 /* XXX assume 11g/11n protection? */ 1664 bf->bf_state.bfs_doprot = 1; 1665 flags |= HAL_TXDESC_CTSENA; 1666 } 1667 /* XXX leave ismcast to injector? */ 1668 if ((params->ibp_flags & IEEE80211_BPF_NOACK) || ismcast) 1669 flags |= HAL_TXDESC_NOACK; 1670 1671 rt = sc->sc_currates; 1672 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); 1673 rix = ath_tx_findrix(sc, params->ibp_rate0); 1674 txrate = rt->info[rix].rateCode; 1675 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE) 1676 txrate |= rt->info[rix].shortPreamble; 1677 sc->sc_txrix = rix; 1678 try0 = params->ibp_try0; 1679 ismrr = (params->ibp_try1 != 0); 1680 txantenna = params->ibp_pri >> 2; 1681 if (txantenna == 0) /* XXX? */ 1682 txantenna = sc->sc_txantenna; 1683 1684 /* 1685 * Since ctsrate is fixed, store it away for later 1686 * use when the descriptor fields are being set. 1687 */ 1688 if (flags & (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)) 1689 bf->bf_state.bfs_ctsrate0 = params->ibp_ctsrate; 1690 1691 pri = params->ibp_pri & 3; 1692 /* Override pri if the frame isn't a QoS one */ 1693 if (! IEEE80211_QOS_HAS_SEQ(wh)) 1694 pri = ath_tx_getac(sc, m0); 1695 1696 /* 1697 * NB: we mark all packets as type PSPOLL so the h/w won't 1698 * set the sequence number, duration, etc. 1699 */ 1700 atype = HAL_PKT_TYPE_PSPOLL; 1701 1702 if (IFF_DUMPPKTS(sc, ATH_DEBUG_XMIT)) 1703 ieee80211_dump_pkt(ic, mtod(m0, caddr_t), m0->m_len, 1704 sc->sc_hwmap[rix].ieeerate, -1); 1705 1706 if (ieee80211_radiotap_active_vap(vap)) { 1707 u_int64_t tsf = ath_hal_gettsf64(ah); 1708 1709 sc->sc_tx_th.wt_tsf = htole64(tsf); 1710 sc->sc_tx_th.wt_flags = sc->sc_hwmap[rix].txflags; 1711 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 1712 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 1713 if (m0->m_flags & M_FRAG) 1714 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_FRAG; 1715 sc->sc_tx_th.wt_rate = sc->sc_hwmap[rix].ieeerate; 1716 sc->sc_tx_th.wt_txpower = ni->ni_txpower; 1717 sc->sc_tx_th.wt_antenna = sc->sc_txantenna; 1718 1719 ieee80211_radiotap_tx(vap, m0); 1720 } 1721 1722 /* 1723 * Formulate first tx descriptor with tx controls. 1724 */ 1725 ds = bf->bf_desc; 1726 /* XXX check return value? */ 1727 1728 /* Store the decided rate index values away */ 1729 bf->bf_state.bfs_pktlen = pktlen; 1730 bf->bf_state.bfs_hdrlen = hdrlen; 1731 bf->bf_state.bfs_atype = atype; 1732 bf->bf_state.bfs_txpower = params->ibp_power; 1733 bf->bf_state.bfs_txrate0 = txrate; 1734 bf->bf_state.bfs_try0 = try0; 1735 bf->bf_state.bfs_keyix = keyix; 1736 bf->bf_state.bfs_txantenna = txantenna; 1737 bf->bf_state.bfs_txflags = flags; 1738 bf->bf_state.bfs_shpream = 1739 !! (params->ibp_flags & IEEE80211_BPF_SHORTPRE); 1740 1741 /* XXX this should be done in ath_tx_setrate() */ 1742 bf->bf_state.bfs_ctsrate = 0; 1743 bf->bf_state.bfs_ctsduration = 0; 1744 bf->bf_state.bfs_ismrr = ismrr; 1745 1746 /* Blank the legacy rate array */ 1747 bzero(&bf->bf_state.bfs_rc, sizeof(bf->bf_state.bfs_rc)); 1748 1749 bf->bf_state.bfs_rc[0].rix = 1750 ath_tx_findrix(sc, params->ibp_rate0); 1751 bf->bf_state.bfs_rc[0].tries = try0; 1752 bf->bf_state.bfs_rc[0].ratecode = txrate; 1753 1754 if (ismrr) { 1755 int rix; 1756 1757 rix = ath_tx_findrix(sc, params->ibp_rate1); 1758 bf->bf_state.bfs_rc[1].rix = rix; 1759 bf->bf_state.bfs_rc[1].tries = params->ibp_try1; 1760 1761 rix = ath_tx_findrix(sc, params->ibp_rate2); 1762 bf->bf_state.bfs_rc[2].rix = rix; 1763 bf->bf_state.bfs_rc[2].tries = params->ibp_try2; 1764 1765 rix = ath_tx_findrix(sc, params->ibp_rate3); 1766 bf->bf_state.bfs_rc[3].rix = rix; 1767 bf->bf_state.bfs_rc[3].tries = params->ibp_try3; 1768 } 1769 /* 1770 * All the required rate control decisions have been made; 1771 * fill in the rc flags. 1772 */ 1773 ath_tx_rate_fill_rcflags(sc, bf); 1774 1775 /* NB: no buffered multicast in power save support */ 1776 1777 /* XXX If it's an ADDBA, override the correct queue */ 1778 do_override = ath_tx_action_frame_override_queue(sc, ni, m0, &o_tid); 1779 1780 /* Map ADDBA to the correct priority */ 1781 if (do_override) { 1782#if 0 1783 device_printf(sc->sc_dev, 1784 "%s: overriding tid %d pri %d -> %d\n", 1785 __func__, o_tid, pri, TID_TO_WME_AC(o_tid)); 1786#endif 1787 pri = TID_TO_WME_AC(o_tid); 1788 } 1789 1790 /* 1791 * If we're overiding the ADDBA destination, dump directly 1792 * into the hardware queue, right after any pending 1793 * frames to that node are. 1794 */ 1795 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: dooverride=%d\n", 1796 __func__, do_override); 1797 1798 if (do_override) { 1799 ATH_TXQ_LOCK(sc->sc_ac2q[pri]); 1800 ath_tx_xmit_normal(sc, sc->sc_ac2q[pri], bf); 1801 ATH_TXQ_UNLOCK(sc->sc_ac2q[pri]); 1802 } else { 1803 /* Queue to software queue */ 1804 ath_tx_swq(sc, ni, sc->sc_ac2q[pri], bf); 1805 } 1806 1807 return 0; 1808} 1809 1810/* 1811 * Send a raw frame. 1812 * 1813 * This can be called by net80211. 1814 */ 1815int 1816ath_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 1817 const struct ieee80211_bpf_params *params) 1818{ 1819 struct ieee80211com *ic = ni->ni_ic; 1820 struct ifnet *ifp = ic->ic_ifp; 1821 struct ath_softc *sc = ifp->if_softc; 1822 struct ath_buf *bf; 1823 struct ieee80211_frame *wh = mtod(m, struct ieee80211_frame *); 1824 int error = 0; 1825 1826 ATH_PCU_LOCK(sc); 1827 if (sc->sc_inreset_cnt > 0) { 1828 device_printf(sc->sc_dev, "%s: sc_inreset_cnt > 0; bailing\n", 1829 __func__); 1830 error = EIO; 1831 ATH_PCU_UNLOCK(sc); 1832 goto bad0; 1833 } 1834 sc->sc_txstart_cnt++; 1835 ATH_PCU_UNLOCK(sc); 1836 1837 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || sc->sc_invalid) { 1838 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: discard frame, %s", __func__, 1839 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 ? 1840 "!running" : "invalid"); 1841 m_freem(m); 1842 error = ENETDOWN; 1843 goto bad; 1844 } 1845 1846 /* 1847 * Enforce how deep the multicast queue can grow. 1848 * 1849 * XXX duplicated in ath_tx_start(). 1850 */ 1851 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1852 ATH_TXQ_LOCK(sc->sc_cabq); 1853 1854 if (sc->sc_cabq->axq_depth > sc->sc_txq_mcastq_maxdepth) { 1855 sc->sc_stats.ast_tx_mcastq_overflow++; 1856 error = ENOBUFS; 1857 } 1858 1859 ATH_TXQ_UNLOCK(sc->sc_cabq); 1860 1861 if (error != 0) { 1862 m_freem(m); 1863 goto bad; 1864 } 1865 } 1866 1867 /* 1868 * Grab a TX buffer and associated resources. 1869 */ 1870 bf = ath_getbuf(sc); 1871 if (bf == NULL) { 1872 sc->sc_stats.ast_tx_nobuf++; 1873 m_freem(m); 1874 error = ENOBUFS; 1875 goto bad; 1876 } 1877 1878 if (params == NULL) { 1879 /* 1880 * Legacy path; interpret frame contents to decide 1881 * precisely how to send the frame. 1882 */ 1883 if (ath_tx_start(sc, ni, bf, m)) { 1884 error = EIO; /* XXX */ 1885 goto bad2; 1886 } 1887 } else { 1888 /* 1889 * Caller supplied explicit parameters to use in 1890 * sending the frame. 1891 */ 1892 if (ath_tx_raw_start(sc, ni, bf, m, params)) { 1893 error = EIO; /* XXX */ 1894 goto bad2; 1895 } 1896 } 1897 sc->sc_wd_timer = 5; 1898 ifp->if_opackets++; 1899 sc->sc_stats.ast_tx_raw++; 1900 1901 ATH_PCU_LOCK(sc); 1902 sc->sc_txstart_cnt--; 1903 ATH_PCU_UNLOCK(sc); 1904 1905 return 0; 1906bad2: 1907 ATH_TXBUF_LOCK(sc); 1908 TAILQ_INSERT_HEAD(&sc->sc_txbuf, bf, bf_list); 1909 ATH_TXBUF_UNLOCK(sc); 1910bad: 1911 ATH_PCU_LOCK(sc); 1912 sc->sc_txstart_cnt--; 1913 ATH_PCU_UNLOCK(sc); 1914bad0: 1915 ifp->if_oerrors++; 1916 sc->sc_stats.ast_tx_raw_fail++; 1917 ieee80211_free_node(ni); 1918 1919 return error; 1920} 1921 1922/* Some helper functions */ 1923 1924/* 1925 * ADDBA (and potentially others) need to be placed in the same 1926 * hardware queue as the TID/node it's relating to. This is so 1927 * it goes out after any pending non-aggregate frames to the 1928 * same node/TID. 1929 * 1930 * If this isn't done, the ADDBA can go out before the frames 1931 * queued in hardware. Even though these frames have a sequence 1932 * number -earlier- than the ADDBA can be transmitted (but 1933 * no frames whose sequence numbers are after the ADDBA should 1934 * be!) they'll arrive after the ADDBA - and the receiving end 1935 * will simply drop them as being out of the BAW. 1936 * 1937 * The frames can't be appended to the TID software queue - it'll 1938 * never be sent out. So these frames have to be directly 1939 * dispatched to the hardware, rather than queued in software. 1940 * So if this function returns true, the TXQ has to be 1941 * overridden and it has to be directly dispatched. 1942 * 1943 * It's a dirty hack, but someone's gotta do it. 1944 */ 1945 1946/* 1947 * XXX doesn't belong here! 1948 */ 1949static int 1950ieee80211_is_action(struct ieee80211_frame *wh) 1951{ 1952 /* Type: Management frame? */ 1953 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != 1954 IEEE80211_FC0_TYPE_MGT) 1955 return 0; 1956 1957 /* Subtype: Action frame? */ 1958 if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) != 1959 IEEE80211_FC0_SUBTYPE_ACTION) 1960 return 0; 1961 1962 return 1; 1963} 1964 1965#define MS(_v, _f) (((_v) & _f) >> _f##_S) 1966/* 1967 * Return an alternate TID for ADDBA request frames. 1968 * 1969 * Yes, this likely should be done in the net80211 layer. 1970 */ 1971static int 1972ath_tx_action_frame_override_queue(struct ath_softc *sc, 1973 struct ieee80211_node *ni, 1974 struct mbuf *m0, int *tid) 1975{ 1976 struct ieee80211_frame *wh = mtod(m0, struct ieee80211_frame *); 1977 struct ieee80211_action_ba_addbarequest *ia; 1978 uint8_t *frm; 1979 uint16_t baparamset; 1980 1981 /* Not action frame? Bail */ 1982 if (! ieee80211_is_action(wh)) 1983 return 0; 1984 1985 /* XXX Not needed for frames we send? */ 1986#if 0 1987 /* Correct length? */ 1988 if (! ieee80211_parse_action(ni, m)) 1989 return 0; 1990#endif 1991 1992 /* Extract out action frame */ 1993 frm = (u_int8_t *)&wh[1]; 1994 ia = (struct ieee80211_action_ba_addbarequest *) frm; 1995 1996 /* Not ADDBA? Bail */ 1997 if (ia->rq_header.ia_category != IEEE80211_ACTION_CAT_BA) 1998 return 0; 1999 if (ia->rq_header.ia_action != IEEE80211_ACTION_BA_ADDBA_REQUEST) 2000 return 0; 2001 2002 /* Extract TID, return it */ 2003 baparamset = le16toh(ia->rq_baparamset); 2004 *tid = (int) MS(baparamset, IEEE80211_BAPS_TID); 2005 2006 return 1; 2007} 2008#undef MS 2009 2010/* Per-node software queue operations */ 2011 2012/* 2013 * Add the current packet to the given BAW. 2014 * It is assumed that the current packet 2015 * 2016 * + fits inside the BAW; 2017 * + already has had a sequence number allocated. 2018 * 2019 * Since the BAW status may be modified by both the ath task and 2020 * the net80211/ifnet contexts, the TID must be locked. 2021 */ 2022void 2023ath_tx_addto_baw(struct ath_softc *sc, struct ath_node *an, 2024 struct ath_tid *tid, struct ath_buf *bf) 2025{ 2026 int index, cindex; 2027 struct ieee80211_tx_ampdu *tap; 2028 2029 ATH_TXQ_LOCK_ASSERT(sc->sc_ac2q[tid->ac]); 2030 2031 if (bf->bf_state.bfs_isretried) 2032 return; 2033 2034 /* 2035 * If this occurs we're in a lot of trouble. We should try to 2036 * recover from this without the session hanging? 2037 */ 2038 if (! bf->bf_state.bfs_seqno_assigned) { 2039 device_printf(sc->sc_dev, 2040 "%s: bf=%p, seqno_assigned is 0?!\n", __func__, bf); 2041 return; 2042 } 2043 2044 tap = ath_tx_get_tx_tid(an, tid->tid); 2045 2046 if (bf->bf_state.bfs_addedbaw) 2047 device_printf(sc->sc_dev, 2048 "%s: re-added? bf=%p, tid=%d, seqno %d; window %d:%d; " 2049 "baw head=%d tail=%d\n", 2050 __func__, bf, tid->tid, SEQNO(bf->bf_state.bfs_seqno), 2051 tap->txa_start, tap->txa_wnd, tid->baw_head, 2052 tid->baw_tail); 2053 2054 /* 2055 * Verify that the given sequence number is not outside of the 2056 * BAW. Complain loudly if that's the case. 2057 */ 2058 if (! BAW_WITHIN(tap->txa_start, tap->txa_wnd, 2059 SEQNO(bf->bf_state.bfs_seqno))) { 2060 device_printf(sc->sc_dev, 2061 "%s: bf=%p: outside of BAW?? tid=%d, seqno %d; window %d:%d; " 2062 "baw head=%d tail=%d\n", 2063 __func__, bf, tid->tid, SEQNO(bf->bf_state.bfs_seqno), 2064 tap->txa_start, tap->txa_wnd, tid->baw_head, 2065 tid->baw_tail); 2066 2067 } 2068 2069 /* 2070 * ni->ni_txseqs[] is the currently allocated seqno. 2071 * the txa state contains the current baw start. 2072 */ 2073 index = ATH_BA_INDEX(tap->txa_start, SEQNO(bf->bf_state.bfs_seqno)); 2074 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); 2075 DPRINTF(sc, ATH_DEBUG_SW_TX_BAW, 2076 "%s: bf=%p, tid=%d, seqno %d; window %d:%d; index=%d cindex=%d " 2077 "baw head=%d tail=%d\n", 2078 __func__, bf, tid->tid, SEQNO(bf->bf_state.bfs_seqno), 2079 tap->txa_start, tap->txa_wnd, index, cindex, tid->baw_head, 2080 tid->baw_tail); 2081 2082 2083#if 0 2084 assert(tid->tx_buf[cindex] == NULL); 2085#endif 2086 if (tid->tx_buf[cindex] != NULL) { 2087 device_printf(sc->sc_dev, 2088 "%s: ba packet dup (index=%d, cindex=%d, " 2089 "head=%d, tail=%d)\n", 2090 __func__, index, cindex, tid->baw_head, tid->baw_tail); 2091 device_printf(sc->sc_dev, 2092 "%s: BA bf: %p; seqno=%d ; new bf: %p; seqno=%d\n", 2093 __func__, 2094 tid->tx_buf[cindex], 2095 SEQNO(tid->tx_buf[cindex]->bf_state.bfs_seqno), 2096 bf, 2097 SEQNO(bf->bf_state.bfs_seqno) 2098 ); 2099 } 2100 tid->tx_buf[cindex] = bf; 2101 2102 if (index >= ((tid->baw_tail - tid->baw_head) & 2103 (ATH_TID_MAX_BUFS - 1))) { 2104 tid->baw_tail = cindex; 2105 INCR(tid->baw_tail, ATH_TID_MAX_BUFS); 2106 } 2107} 2108 2109/* 2110 * Flip the BAW buffer entry over from the existing one to the new one. 2111 * 2112 * When software retransmitting a (sub-)frame, it is entirely possible that 2113 * the frame ath_buf is marked as BUSY and can't be immediately reused. 2114 * In that instance the buffer is cloned and the new buffer is used for 2115 * retransmit. We thus need to update the ath_buf slot in the BAW buf 2116 * tracking array to maintain consistency. 2117 */ 2118static void 2119ath_tx_switch_baw_buf(struct ath_softc *sc, struct ath_node *an, 2120 struct ath_tid *tid, struct ath_buf *old_bf, struct ath_buf *new_bf) 2121{ 2122 int index, cindex; 2123 struct ieee80211_tx_ampdu *tap; 2124 int seqno = SEQNO(old_bf->bf_state.bfs_seqno); 2125 2126 ATH_TXQ_LOCK_ASSERT(sc->sc_ac2q[tid->ac]); 2127 2128 tap = ath_tx_get_tx_tid(an, tid->tid); 2129 index = ATH_BA_INDEX(tap->txa_start, seqno); 2130 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); 2131 2132 /* 2133 * Just warn for now; if it happens then we should find out 2134 * about it. It's highly likely the aggregation session will 2135 * soon hang. 2136 */ 2137 if (old_bf->bf_state.bfs_seqno != new_bf->bf_state.bfs_seqno) { 2138 device_printf(sc->sc_dev, "%s: retransmitted buffer" 2139 " has mismatching seqno's, BA session may hang.\n", 2140 __func__); 2141 device_printf(sc->sc_dev, "%s: old seqno=%d, new_seqno=%d\n", 2142 __func__, 2143 old_bf->bf_state.bfs_seqno, 2144 new_bf->bf_state.bfs_seqno); 2145 } 2146 2147 if (tid->tx_buf[cindex] != old_bf) { 2148 device_printf(sc->sc_dev, "%s: ath_buf pointer incorrect; " 2149 " has m BA session may hang.\n", 2150 __func__); 2151 device_printf(sc->sc_dev, "%s: old bf=%p, new bf=%p\n", 2152 __func__, 2153 old_bf, new_bf); 2154 } 2155 2156 tid->tx_buf[cindex] = new_bf; 2157} 2158 2159/* 2160 * seq_start - left edge of BAW 2161 * seq_next - current/next sequence number to allocate 2162 * 2163 * Since the BAW status may be modified by both the ath task and 2164 * the net80211/ifnet contexts, the TID must be locked. 2165 */ 2166static void 2167ath_tx_update_baw(struct ath_softc *sc, struct ath_node *an, 2168 struct ath_tid *tid, const struct ath_buf *bf) 2169{ 2170 int index, cindex; 2171 struct ieee80211_tx_ampdu *tap; 2172 int seqno = SEQNO(bf->bf_state.bfs_seqno); 2173 2174 ATH_TXQ_LOCK_ASSERT(sc->sc_ac2q[tid->ac]); 2175 2176 tap = ath_tx_get_tx_tid(an, tid->tid); 2177 index = ATH_BA_INDEX(tap->txa_start, seqno); 2178 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); 2179 2180 DPRINTF(sc, ATH_DEBUG_SW_TX_BAW, 2181 "%s: bf=%p: tid=%d, baw=%d:%d, seqno=%d, index=%d, cindex=%d, " 2182 "baw head=%d, tail=%d\n", 2183 __func__, bf, tid->tid, tap->txa_start, tap->txa_wnd, seqno, index, 2184 cindex, tid->baw_head, tid->baw_tail); 2185 2186 /* 2187 * If this occurs then we have a big problem - something else 2188 * has slid tap->txa_start along without updating the BAW 2189 * tracking start/end pointers. Thus the TX BAW state is now 2190 * completely busted. 2191 * 2192 * But for now, since I haven't yet fixed TDMA and buffer cloning, 2193 * it's quite possible that a cloned buffer is making its way 2194 * here and causing it to fire off. Disable TDMA for now. 2195 */ 2196 if (tid->tx_buf[cindex] != bf) { 2197 device_printf(sc->sc_dev, 2198 "%s: comp bf=%p, seq=%d; slot bf=%p, seqno=%d\n", 2199 __func__, 2200 bf, SEQNO(bf->bf_state.bfs_seqno), 2201 tid->tx_buf[cindex], 2202 SEQNO(tid->tx_buf[cindex]->bf_state.bfs_seqno)); 2203 } 2204 2205 tid->tx_buf[cindex] = NULL; 2206 2207 while (tid->baw_head != tid->baw_tail && 2208 !tid->tx_buf[tid->baw_head]) { 2209 INCR(tap->txa_start, IEEE80211_SEQ_RANGE); 2210 INCR(tid->baw_head, ATH_TID_MAX_BUFS); 2211 } 2212 DPRINTF(sc, ATH_DEBUG_SW_TX_BAW, 2213 "%s: baw is now %d:%d, baw head=%d\n", 2214 __func__, tap->txa_start, tap->txa_wnd, tid->baw_head); 2215} 2216 2217/* 2218 * Mark the current node/TID as ready to TX. 2219 * 2220 * This is done to make it easy for the software scheduler to 2221 * find which nodes have data to send. 2222 * 2223 * The TXQ lock must be held. 2224 */ 2225static void 2226ath_tx_tid_sched(struct ath_softc *sc, struct ath_tid *tid) 2227{ 2228 struct ath_txq *txq = sc->sc_ac2q[tid->ac]; 2229 2230 ATH_TXQ_LOCK_ASSERT(txq); 2231 2232 if (tid->paused) 2233 return; /* paused, can't schedule yet */ 2234 2235 if (tid->sched) 2236 return; /* already scheduled */ 2237 2238 tid->sched = 1; 2239 2240 TAILQ_INSERT_TAIL(&txq->axq_tidq, tid, axq_qelem); 2241} 2242 2243/* 2244 * Mark the current node as no longer needing to be polled for 2245 * TX packets. 2246 * 2247 * The TXQ lock must be held. 2248 */ 2249static void 2250ath_tx_tid_unsched(struct ath_softc *sc, struct ath_tid *tid) 2251{ 2252 struct ath_txq *txq = sc->sc_ac2q[tid->ac]; 2253 2254 ATH_TXQ_LOCK_ASSERT(txq); 2255 2256 if (tid->sched == 0) 2257 return; 2258 2259 tid->sched = 0; 2260 TAILQ_REMOVE(&txq->axq_tidq, tid, axq_qelem); 2261} 2262 2263/* 2264 * Return whether a sequence number is actually required. 2265 * 2266 * A sequence number must only be allocated at the time that a frame 2267 * is considered for addition to the BAW/aggregate and being TXed. 2268 * The sequence number must not be allocated before the frame 2269 * is added to the BAW (protected by the same lock instance) 2270 * otherwise a the multi-entrant TX path may result in a later seqno 2271 * being added to the BAW first. The subsequent addition of the 2272 * earlier seqno would then not go into the BAW as it's now outside 2273 * of said BAW. 2274 * 2275 * This routine is used by ath_tx_start() to mark whether the frame 2276 * should get a sequence number before adding it to the BAW. 2277 * 2278 * Then the actual aggregate TX routines will check whether this 2279 * flag is set and if the frame needs to go into the BAW, it'll 2280 * have a sequence number allocated for it. 2281 */ 2282static int 2283ath_tx_seqno_required(struct ath_softc *sc, struct ieee80211_node *ni, 2284 struct ath_buf *bf, struct mbuf *m0) 2285{ 2286 const struct ieee80211_frame *wh; 2287 uint8_t subtype; 2288 2289 wh = mtod(m0, const struct ieee80211_frame *); 2290 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 2291 2292 /* XXX assert txq lock */ 2293 /* XXX assert ampdu is set */ 2294 2295 return ((IEEE80211_QOS_HAS_SEQ(wh) && 2296 subtype != IEEE80211_FC0_SUBTYPE_QOS_NULL)); 2297} 2298 2299/* 2300 * Assign a sequence number manually to the given frame. 2301 * 2302 * This should only be called for A-MPDU TX frames. 2303 * 2304 * If this is called after the initial frame setup, make sure you've flushed 2305 * the DMA map or you'll risk sending stale data to the NIC. This routine 2306 * updates the actual frame contents with the relevant seqno. 2307 */ 2308int 2309ath_tx_tid_seqno_assign(struct ath_softc *sc, struct ieee80211_node *ni, 2310 struct ath_buf *bf, struct mbuf *m0) 2311{ 2312 struct ieee80211_frame *wh; 2313 int tid, pri; 2314 ieee80211_seq seqno; 2315 uint8_t subtype; 2316 2317 /* TID lookup */ 2318 wh = mtod(m0, struct ieee80211_frame *); 2319 pri = M_WME_GETAC(m0); /* honor classification */ 2320 tid = WME_AC_TO_TID(pri); 2321 DPRINTF(sc, ATH_DEBUG_SW_TX, 2322 "%s: bf=%p, pri=%d, tid=%d, qos has seq=%d\n", 2323 __func__, bf, pri, tid, IEEE80211_QOS_HAS_SEQ(wh)); 2324 2325 if (! bf->bf_state.bfs_need_seqno) { 2326 device_printf(sc->sc_dev, "%s: bf=%p: need_seqno not set?!\n", 2327 __func__, bf); 2328 return -1; 2329 } 2330 /* XXX check for bfs_need_seqno? */ 2331 if (bf->bf_state.bfs_seqno_assigned) { 2332 device_printf(sc->sc_dev, 2333 "%s: bf=%p: seqno already assigned (%d)?!\n", 2334 __func__, bf, SEQNO(bf->bf_state.bfs_seqno)); 2335 return bf->bf_state.bfs_seqno >> IEEE80211_SEQ_SEQ_SHIFT; 2336 } 2337 2338 /* XXX Is it a control frame? Ignore */ 2339 2340 /* Does the packet require a sequence number? */ 2341 if (! IEEE80211_QOS_HAS_SEQ(wh)) 2342 return -1; 2343 2344 /* 2345 * Is it a QOS NULL Data frame? Give it a sequence number from 2346 * the default TID (IEEE80211_NONQOS_TID.) 2347 * 2348 * The RX path of everything I've looked at doesn't include the NULL 2349 * data frame sequence number in the aggregation state updates, so 2350 * assigning it a sequence number there will cause a BAW hole on the 2351 * RX side. 2352 */ 2353 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 2354 if (subtype == IEEE80211_FC0_SUBTYPE_QOS_NULL) { 2355 seqno = ni->ni_txseqs[IEEE80211_NONQOS_TID]; 2356 INCR(ni->ni_txseqs[IEEE80211_NONQOS_TID], IEEE80211_SEQ_RANGE); 2357 } else { 2358 /* Manually assign sequence number */ 2359 seqno = ni->ni_txseqs[tid]; 2360 INCR(ni->ni_txseqs[tid], IEEE80211_SEQ_RANGE); 2361 } 2362 *(uint16_t *)&wh->i_seq[0] = htole16(seqno << IEEE80211_SEQ_SEQ_SHIFT); 2363 M_SEQNO_SET(m0, seqno); 2364 bf->bf_state.bfs_seqno = seqno << IEEE80211_SEQ_SEQ_SHIFT; 2365 bf->bf_state.bfs_seqno_assigned = 1; 2366 2367 /* Return so caller can do something with it if needed */ 2368 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: bf=%p: -> seqno=%d\n", 2369 __func__, 2370 bf, 2371 seqno); 2372 return seqno; 2373} 2374 2375/* 2376 * Attempt to direct dispatch an aggregate frame to hardware. 2377 * If the frame is out of BAW, queue. 2378 * Otherwise, schedule it as a single frame. 2379 */ 2380static void 2381ath_tx_xmit_aggr(struct ath_softc *sc, struct ath_node *an, struct ath_buf *bf) 2382{ 2383 struct ieee80211_node *ni = &an->an_node; 2384 struct ath_tid *tid = &an->an_tid[bf->bf_state.bfs_tid]; 2385 struct ath_txq *txq = bf->bf_state.bfs_txq; 2386 struct ieee80211_tx_ampdu *tap; 2387 2388 ATH_TXQ_LOCK_ASSERT(txq); 2389 2390 tap = ath_tx_get_tx_tid(an, tid->tid); 2391 2392 /* paused? queue */ 2393 if (tid->paused) { 2394 ATH_TXQ_INSERT_TAIL(tid, bf, bf_list); 2395 /* XXX don't sched - we're paused! */ 2396 return; 2397 } 2398 2399 /* 2400 * TODO: If it's _before_ the BAW left edge, complain very loudly. 2401 * This means something (else) has slid the left edge along 2402 * before we got a chance to be TXed. 2403 */ 2404 2405 /* 2406 * Is there space in this BAW for another frame? 2407 * If not, don't bother trying to schedule it; just 2408 * throw it back on the queue. 2409 * 2410 * If we allocate the sequence number before we add 2411 * it to the BAW, we risk racing with another TX 2412 * thread that gets in a frame into the BAW with 2413 * seqno greater than ours. We'd then fail the 2414 * below check and throw the frame on the tail of 2415 * the queue. The sender would then have a hole. 2416 * 2417 * XXX again, we're protecting ni->ni_txseqs[tid] 2418 * behind this hardware TXQ lock, like the rest of 2419 * the TIDs that map to it. Ugh. 2420 */ 2421 if (bf->bf_state.bfs_dobaw) { 2422 ieee80211_seq seqno; 2423 2424 /* 2425 * If the sequence number is allocated, use it. 2426 * Otherwise, use the sequence number we WOULD 2427 * allocate. 2428 */ 2429 if (bf->bf_state.bfs_seqno_assigned) 2430 seqno = SEQNO(bf->bf_state.bfs_seqno); 2431 else 2432 seqno = ni->ni_txseqs[bf->bf_state.bfs_tid]; 2433 2434 /* 2435 * Check whether either the currently allocated 2436 * sequence number _OR_ the to-be allocated 2437 * sequence number is inside the BAW. 2438 */ 2439 if (! BAW_WITHIN(tap->txa_start, tap->txa_wnd, seqno)) { 2440 ATH_TXQ_INSERT_TAIL(tid, bf, bf_list); 2441 ath_tx_tid_sched(sc, tid); 2442 return; 2443 } 2444 if (! bf->bf_state.bfs_seqno_assigned) { 2445 int seqno; 2446 2447 seqno = ath_tx_tid_seqno_assign(sc, ni, bf, bf->bf_m); 2448 if (seqno < 0) { 2449 device_printf(sc->sc_dev, 2450 "%s: bf=%p, huh, seqno=-1?\n", 2451 __func__, 2452 bf); 2453 /* XXX what can we even do here? */ 2454 } 2455 /* Flush seqno update to RAM */ 2456 /* 2457 * XXX This is required because the dmasetup 2458 * XXX is done early rather than at dispatch 2459 * XXX time. Ew, we should fix this! 2460 */ 2461 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 2462 BUS_DMASYNC_PREWRITE); 2463 } 2464 } 2465 2466 /* outside baw? queue */ 2467 if (bf->bf_state.bfs_dobaw && 2468 (! BAW_WITHIN(tap->txa_start, tap->txa_wnd, 2469 SEQNO(bf->bf_state.bfs_seqno)))) { 2470 device_printf(sc->sc_dev, 2471 "%s: bf=%p, shouldn't be outside BAW now?!\n", 2472 __func__, 2473 bf); 2474 ATH_TXQ_INSERT_TAIL(tid, bf, bf_list); 2475 ath_tx_tid_sched(sc, tid); 2476 return; 2477 } 2478 2479 /* Direct dispatch to hardware */ 2480 ath_tx_do_ratelookup(sc, bf); 2481 ath_tx_calc_duration(sc, bf); 2482 ath_tx_calc_protection(sc, bf); 2483 ath_tx_set_rtscts(sc, bf); 2484 ath_tx_rate_fill_rcflags(sc, bf); 2485 ath_tx_setds(sc, bf); 2486 ath_tx_set_ratectrl(sc, bf->bf_node, bf); 2487 ath_tx_chaindesclist(sc, bf); 2488 2489 /* Statistics */ 2490 sc->sc_aggr_stats.aggr_low_hwq_single_pkt++; 2491 2492 /* Track per-TID hardware queue depth correctly */ 2493 tid->hwq_depth++; 2494 2495 /* Add to BAW */ 2496 if (bf->bf_state.bfs_dobaw) { 2497 ath_tx_addto_baw(sc, an, tid, bf); 2498 bf->bf_state.bfs_addedbaw = 1; 2499 } 2500 2501 /* Set completion handler, multi-frame aggregate or not */ 2502 bf->bf_comp = ath_tx_aggr_comp; 2503 2504 /* Hand off to hardware */ 2505 ath_tx_handoff(sc, txq, bf); 2506} 2507 2508/* 2509 * Attempt to send the packet. 2510 * If the queue isn't busy, direct-dispatch. 2511 * If the queue is busy enough, queue the given packet on the 2512 * relevant software queue. 2513 */ 2514void 2515ath_tx_swq(struct ath_softc *sc, struct ieee80211_node *ni, struct ath_txq *txq, 2516 struct ath_buf *bf) 2517{ 2518 struct ath_node *an = ATH_NODE(ni); 2519 struct ieee80211_frame *wh; 2520 struct ath_tid *atid; 2521 int pri, tid; 2522 struct mbuf *m0 = bf->bf_m; 2523 2524 /* Fetch the TID - non-QoS frames get assigned to TID 16 */ 2525 wh = mtod(m0, struct ieee80211_frame *); 2526 pri = ath_tx_getac(sc, m0); 2527 tid = ath_tx_gettid(sc, m0); 2528 atid = &an->an_tid[tid]; 2529 2530 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: bf=%p, pri=%d, tid=%d, qos=%d, seqno=%d\n", 2531 __func__, bf, pri, tid, IEEE80211_QOS_HAS_SEQ(wh), SEQNO(bf->bf_state.bfs_seqno)); 2532 2533 /* Set local packet state, used to queue packets to hardware */ 2534 bf->bf_state.bfs_tid = tid; 2535 bf->bf_state.bfs_txq = txq; 2536 bf->bf_state.bfs_pri = pri; 2537 2538 /* 2539 * If the hardware queue isn't busy, queue it directly. 2540 * If the hardware queue is busy, queue it. 2541 * If the TID is paused or the traffic it outside BAW, software 2542 * queue it. 2543 */ 2544 ATH_TXQ_LOCK(txq); 2545 if (atid->paused) { 2546 /* TID is paused, queue */ 2547 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: bf=%p: paused\n", __func__, bf); 2548 ATH_TXQ_INSERT_TAIL(atid, bf, bf_list); 2549 } else if (ath_tx_ampdu_pending(sc, an, tid)) { 2550 /* AMPDU pending; queue */ 2551 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: bf=%p: pending\n", __func__, bf); 2552 ATH_TXQ_INSERT_TAIL(atid, bf, bf_list); 2553 /* XXX sched? */ 2554 } else if (ath_tx_ampdu_running(sc, an, tid)) { 2555 /* AMPDU running, attempt direct dispatch if possible */ 2556 if (txq->axq_depth < sc->sc_hwq_limit) { 2557 DPRINTF(sc, ATH_DEBUG_SW_TX, 2558 "%s: bf=%p: xmit_aggr\n", 2559 __func__, bf); 2560 ath_tx_xmit_aggr(sc, an, bf); 2561 } else { 2562 DPRINTF(sc, ATH_DEBUG_SW_TX, 2563 "%s: bf=%p: ampdu; swq'ing\n", 2564 __func__, bf); 2565 ATH_TXQ_INSERT_TAIL(atid, bf, bf_list); 2566 ath_tx_tid_sched(sc, atid); 2567 } 2568 } else if (txq->axq_depth < sc->sc_hwq_limit) { 2569 /* AMPDU not running, attempt direct dispatch */ 2570 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: bf=%p: xmit_normal\n", __func__, bf); 2571 ath_tx_xmit_normal(sc, txq, bf); 2572 } else { 2573 /* Busy; queue */ 2574 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: bf=%p: swq'ing\n", __func__, bf); 2575 ATH_TXQ_INSERT_TAIL(atid, bf, bf_list); 2576 ath_tx_tid_sched(sc, atid); 2577 } 2578 ATH_TXQ_UNLOCK(txq); 2579} 2580 2581/* 2582 * Do the basic frame setup stuff that's required before the frame 2583 * is added to a software queue. 2584 * 2585 * All frames get mostly the same treatment and it's done once. 2586 * Retransmits fiddle with things like the rate control setup, 2587 * setting the retransmit bit in the packet; doing relevant DMA/bus 2588 * syncing and relinking it (back) into the hardware TX queue. 2589 * 2590 * Note that this may cause the mbuf to be reallocated, so 2591 * m0 may not be valid. 2592 */ 2593 2594 2595/* 2596 * Configure the per-TID node state. 2597 * 2598 * This likely belongs in if_ath_node.c but I can't think of anywhere 2599 * else to put it just yet. 2600 * 2601 * This sets up the SLISTs and the mutex as appropriate. 2602 */ 2603void 2604ath_tx_tid_init(struct ath_softc *sc, struct ath_node *an) 2605{ 2606 int i, j; 2607 struct ath_tid *atid; 2608 2609 for (i = 0; i < IEEE80211_TID_SIZE; i++) { 2610 atid = &an->an_tid[i]; 2611 TAILQ_INIT(&atid->axq_q); 2612 atid->tid = i; 2613 atid->an = an; 2614 for (j = 0; j < ATH_TID_MAX_BUFS; j++) 2615 atid->tx_buf[j] = NULL; 2616 atid->baw_head = atid->baw_tail = 0; 2617 atid->paused = 0; 2618 atid->sched = 0; 2619 atid->hwq_depth = 0; 2620 atid->cleanup_inprogress = 0; 2621 if (i == IEEE80211_NONQOS_TID) 2622 atid->ac = WME_AC_BE; 2623 else 2624 atid->ac = TID_TO_WME_AC(i); 2625 } 2626} 2627 2628/* 2629 * Pause the current TID. This stops packets from being transmitted 2630 * on it. 2631 * 2632 * Since this is also called from upper layers as well as the driver, 2633 * it will get the TID lock. 2634 */ 2635static void 2636ath_tx_tid_pause(struct ath_softc *sc, struct ath_tid *tid) 2637{ 2638 2639 ATH_TXQ_LOCK_ASSERT(sc->sc_ac2q[tid->ac]); 2640 tid->paused++; 2641 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, "%s: paused = %d\n", 2642 __func__, tid->paused); 2643} 2644 2645/* 2646 * Unpause the current TID, and schedule it if needed. 2647 */ 2648static void 2649ath_tx_tid_resume(struct ath_softc *sc, struct ath_tid *tid) 2650{ 2651 ATH_TXQ_LOCK_ASSERT(sc->sc_ac2q[tid->ac]); 2652 2653 tid->paused--; 2654 2655 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, "%s: unpaused = %d\n", 2656 __func__, tid->paused); 2657 2658 if (tid->paused || tid->axq_depth == 0) { 2659 return; 2660 } 2661 2662 ath_tx_tid_sched(sc, tid); 2663 /* Punt some frames to the hardware if needed */ 2664 //ath_txq_sched(sc, sc->sc_ac2q[tid->ac]); 2665 taskqueue_enqueue(sc->sc_tq, &sc->sc_txqtask); 2666} 2667 2668/* 2669 * Suspend the queue because we need to TX a BAR. 2670 */ 2671static void 2672ath_tx_tid_bar_suspend(struct ath_softc *sc, struct ath_tid *tid) 2673{ 2674 ATH_TXQ_LOCK_ASSERT(sc->sc_ac2q[tid->ac]); 2675 2676 DPRINTF(sc, ATH_DEBUG_SW_TX_BAR, 2677 "%s: tid=%p, called\n", 2678 __func__, 2679 tid); 2680 2681 /* We shouldn't be called when bar_tx is 1 */ 2682 if (tid->bar_tx) { 2683 device_printf(sc->sc_dev, "%s: bar_tx is 1?!\n", 2684 __func__); 2685 } 2686 2687 /* If we've already been called, just be patient. */ 2688 if (tid->bar_wait) 2689 return; 2690 2691 /* Wait! */ 2692 tid->bar_wait = 1; 2693 2694 /* Only one pause, no matter how many frames fail */ 2695 ath_tx_tid_pause(sc, tid); 2696} 2697 2698/* 2699 * We've finished with BAR handling - either we succeeded or 2700 * failed. Either way, unsuspend TX. 2701 */ 2702static void 2703ath_tx_tid_bar_unsuspend(struct ath_softc *sc, struct ath_tid *tid) 2704{ 2705 ATH_TXQ_LOCK_ASSERT(sc->sc_ac2q[tid->ac]); 2706 2707 DPRINTF(sc, ATH_DEBUG_SW_TX_BAR, 2708 "%s: tid=%p, called\n", 2709 __func__, 2710 tid); 2711 2712 if (tid->bar_tx == 0 || tid->bar_wait == 0) { 2713 device_printf(sc->sc_dev, "%s: bar_tx=%d, bar_wait=%d: ?\n", 2714 __func__, tid->bar_tx, tid->bar_wait); 2715 } 2716 2717 tid->bar_tx = tid->bar_wait = 0; 2718 ath_tx_tid_resume(sc, tid); 2719} 2720 2721/* 2722 * Return whether we're ready to TX a BAR frame. 2723 * 2724 * Requires the TID lock be held. 2725 */ 2726static int 2727ath_tx_tid_bar_tx_ready(struct ath_softc *sc, struct ath_tid *tid) 2728{ 2729 2730 ATH_TXQ_LOCK_ASSERT(sc->sc_ac2q[tid->ac]); 2731 2732 if (tid->bar_wait == 0 || tid->hwq_depth > 0) 2733 return (0); 2734 2735 DPRINTF(sc, ATH_DEBUG_SW_TX_BAR, "%s: tid=%p (%d), bar ready\n", 2736 __func__, tid, tid->tid); 2737 2738 return (1); 2739} 2740 2741/* 2742 * Check whether the current TID is ready to have a BAR 2743 * TXed and if so, do the TX. 2744 * 2745 * Since the TID/TXQ lock can't be held during a call to 2746 * ieee80211_send_bar(), we have to do the dirty thing of unlocking it, 2747 * sending the BAR and locking it again. 2748 * 2749 * Eventually, the code to send the BAR should be broken out 2750 * from this routine so the lock doesn't have to be reacquired 2751 * just to be immediately dropped by the caller. 2752 */ 2753static void 2754ath_tx_tid_bar_tx(struct ath_softc *sc, struct ath_tid *tid) 2755{ 2756 struct ieee80211_tx_ampdu *tap; 2757 2758 ATH_TXQ_LOCK_ASSERT(sc->sc_ac2q[tid->ac]); 2759 2760 DPRINTF(sc, ATH_DEBUG_SW_TX_BAR, 2761 "%s: tid=%p, called\n", 2762 __func__, 2763 tid); 2764 2765 tap = ath_tx_get_tx_tid(tid->an, tid->tid); 2766 2767 /* 2768 * This is an error condition! 2769 */ 2770 if (tid->bar_wait == 0 || tid->bar_tx == 1) { 2771 device_printf(sc->sc_dev, 2772 "%s: tid=%p, bar_tx=%d, bar_wait=%d: ?\n", 2773 __func__, 2774 tid, 2775 tid->bar_tx, 2776 tid->bar_wait); 2777 return; 2778 } 2779 2780 /* Don't do anything if we still have pending frames */ 2781 if (tid->hwq_depth > 0) { 2782 DPRINTF(sc, ATH_DEBUG_SW_TX_BAR, 2783 "%s: tid=%p, hwq_depth=%d, waiting\n", 2784 __func__, 2785 tid, 2786 tid->hwq_depth); 2787 return; 2788 } 2789 2790 /* We're now about to TX */ 2791 tid->bar_tx = 1; 2792 2793 /* 2794 * Calculate new BAW left edge, now that all frames have either 2795 * succeeded or failed. 2796 * 2797 * XXX verify this is _actually_ the valid value to begin at! 2798 */ 2799 DPRINTF(sc, ATH_DEBUG_SW_TX_BAR, 2800 "%s: tid=%p, new BAW left edge=%d\n", 2801 __func__, 2802 tid, 2803 tap->txa_start); 2804 2805 /* Try sending the BAR frame */ 2806 /* We can't hold the lock here! */ 2807 2808 ATH_TXQ_UNLOCK(sc->sc_ac2q[tid->ac]); 2809 if (ieee80211_send_bar(&tid->an->an_node, tap, tap->txa_start) == 0) { 2810 /* Success? Now we wait for notification that it's done */ 2811 ATH_TXQ_LOCK(sc->sc_ac2q[tid->ac]); 2812 return; 2813 } 2814 2815 /* Failure? For now, warn loudly and continue */ 2816 ATH_TXQ_LOCK(sc->sc_ac2q[tid->ac]); 2817 device_printf(sc->sc_dev, "%s: tid=%p, failed to TX BAR, continue!\n", 2818 __func__, tid); 2819 ath_tx_tid_bar_unsuspend(sc, tid); 2820} 2821 2822 2823/* 2824 * Free any packets currently pending in the software TX queue. 2825 * 2826 * This will be called when a node is being deleted. 2827 * 2828 * It can also be called on an active node during an interface 2829 * reset or state transition. 2830 * 2831 * (From Linux/reference): 2832 * 2833 * TODO: For frame(s) that are in the retry state, we will reuse the 2834 * sequence number(s) without setting the retry bit. The 2835 * alternative is to give up on these and BAR the receiver's window 2836 * forward. 2837 */ 2838static void 2839ath_tx_tid_drain(struct ath_softc *sc, struct ath_node *an, 2840 struct ath_tid *tid, ath_bufhead *bf_cq) 2841{ 2842 struct ath_buf *bf; 2843 struct ieee80211_tx_ampdu *tap; 2844 struct ieee80211_node *ni = &an->an_node; 2845 int t = 0; 2846 struct ath_txq *txq = sc->sc_ac2q[tid->ac]; 2847 2848 tap = ath_tx_get_tx_tid(an, tid->tid); 2849 2850 ATH_TXQ_LOCK_ASSERT(sc->sc_ac2q[tid->ac]); 2851 2852 /* Walk the queue, free frames */ 2853 for (;;) { 2854 bf = TAILQ_FIRST(&tid->axq_q); 2855 if (bf == NULL) { 2856 break; 2857 } 2858 2859 if (t == 0) { 2860 device_printf(sc->sc_dev, 2861 "%s: node %p: bf=%p: addbaw=%d, dobaw=%d, " 2862 "seqno_assign=%d, seqno_required=%d, seqno=%d, retry=%d\n", 2863 __func__, ni, bf, 2864 bf->bf_state.bfs_addedbaw, 2865 bf->bf_state.bfs_dobaw, 2866 bf->bf_state.bfs_need_seqno, 2867 bf->bf_state.bfs_seqno_assigned, 2868 SEQNO(bf->bf_state.bfs_seqno), 2869 bf->bf_state.bfs_retries); 2870 device_printf(sc->sc_dev, 2871 "%s: node %p: bf=%p: tid txq_depth=%d hwq_depth=%d, bar_wait=%d\n", 2872 __func__, ni, bf, 2873 tid->axq_depth, 2874 tid->hwq_depth, 2875 tid->bar_wait); 2876 device_printf(sc->sc_dev, 2877 "%s: node %p: bf=%p: tid %d: txq_depth=%d, " 2878 "txq_aggr_depth=%d, sched=%d, paused=%d, " 2879 "hwq_depth=%d, incomp=%d, baw_head=%d, " 2880 "baw_tail=%d txa_start=%d, ni_txseqs=%d\n", 2881 __func__, ni, bf, tid->tid, txq->axq_depth, 2882 txq->axq_aggr_depth, tid->sched, tid->paused, 2883 tid->hwq_depth, tid->incomp, tid->baw_head, 2884 tid->baw_tail, tap == NULL ? -1 : tap->txa_start, 2885 ni->ni_txseqs[tid->tid]); 2886 2887 /* XXX Dump the frame, see what it is? */ 2888 ieee80211_dump_pkt(ni->ni_ic, 2889 mtod(bf->bf_m, const uint8_t *), 2890 bf->bf_m->m_len, 0, -1); 2891 2892 t = 1; 2893 } 2894 2895 2896 /* 2897 * If the current TID is running AMPDU, update 2898 * the BAW. 2899 */ 2900 if (ath_tx_ampdu_running(sc, an, tid->tid) && 2901 bf->bf_state.bfs_dobaw) { 2902 /* 2903 * Only remove the frame from the BAW if it's 2904 * been transmitted at least once; this means 2905 * the frame was in the BAW to begin with. 2906 */ 2907 if (bf->bf_state.bfs_retries > 0) { 2908 ath_tx_update_baw(sc, an, tid, bf); 2909 bf->bf_state.bfs_dobaw = 0; 2910 } 2911 /* 2912 * This has become a non-fatal error now 2913 */ 2914 if (! bf->bf_state.bfs_addedbaw) 2915 device_printf(sc->sc_dev, 2916 "%s: wasn't added: seqno %d\n", 2917 __func__, SEQNO(bf->bf_state.bfs_seqno)); 2918 } 2919 ATH_TXQ_REMOVE(tid, bf, bf_list); 2920 TAILQ_INSERT_TAIL(bf_cq, bf, bf_list); 2921 } 2922 2923 /* 2924 * Now that it's completed, grab the TID lock and update 2925 * the sequence number and BAW window. 2926 * Because sequence numbers have been assigned to frames 2927 * that haven't been sent yet, it's entirely possible 2928 * we'll be called with some pending frames that have not 2929 * been transmitted. 2930 * 2931 * The cleaner solution is to do the sequence number allocation 2932 * when the packet is first transmitted - and thus the "retries" 2933 * check above would be enough to update the BAW/seqno. 2934 */ 2935 2936 /* But don't do it for non-QoS TIDs */ 2937 if (tap) { 2938#if 0 2939 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, 2940 "%s: node %p: TID %d: sliding BAW left edge to %d\n", 2941 __func__, an, tid->tid, tap->txa_start); 2942#endif 2943 ni->ni_txseqs[tid->tid] = tap->txa_start; 2944 tid->baw_tail = tid->baw_head; 2945 } 2946} 2947 2948/* 2949 * Flush all software queued packets for the given node. 2950 * 2951 * This occurs when a completion handler frees the last buffer 2952 * for a node, and the node is thus freed. This causes the node 2953 * to be cleaned up, which ends up calling ath_tx_node_flush. 2954 */ 2955void 2956ath_tx_node_flush(struct ath_softc *sc, struct ath_node *an) 2957{ 2958 int tid; 2959 ath_bufhead bf_cq; 2960 struct ath_buf *bf; 2961 2962 TAILQ_INIT(&bf_cq); 2963 2964 for (tid = 0; tid < IEEE80211_TID_SIZE; tid++) { 2965 struct ath_tid *atid = &an->an_tid[tid]; 2966 struct ath_txq *txq = sc->sc_ac2q[atid->ac]; 2967 2968 /* Remove this tid from the list of active tids */ 2969 ATH_TXQ_LOCK(txq); 2970 ath_tx_tid_unsched(sc, atid); 2971 2972 /* Free packets */ 2973 ath_tx_tid_drain(sc, an, atid, &bf_cq); 2974 ATH_TXQ_UNLOCK(txq); 2975 } 2976 2977 /* Handle completed frames */ 2978 while ((bf = TAILQ_FIRST(&bf_cq)) != NULL) { 2979 TAILQ_REMOVE(&bf_cq, bf, bf_list); 2980 ath_tx_default_comp(sc, bf, 0); 2981 } 2982} 2983 2984/* 2985 * Drain all the software TXQs currently with traffic queued. 2986 */ 2987void 2988ath_tx_txq_drain(struct ath_softc *sc, struct ath_txq *txq) 2989{ 2990 struct ath_tid *tid; 2991 ath_bufhead bf_cq; 2992 struct ath_buf *bf; 2993 2994 TAILQ_INIT(&bf_cq); 2995 ATH_TXQ_LOCK(txq); 2996 2997 /* 2998 * Iterate over all active tids for the given txq, 2999 * flushing and unsched'ing them 3000 */ 3001 while (! TAILQ_EMPTY(&txq->axq_tidq)) { 3002 tid = TAILQ_FIRST(&txq->axq_tidq); 3003 ath_tx_tid_drain(sc, tid->an, tid, &bf_cq); 3004 ath_tx_tid_unsched(sc, tid); 3005 } 3006 3007 ATH_TXQ_UNLOCK(txq); 3008 3009 while ((bf = TAILQ_FIRST(&bf_cq)) != NULL) { 3010 TAILQ_REMOVE(&bf_cq, bf, bf_list); 3011 ath_tx_default_comp(sc, bf, 0); 3012 } 3013} 3014 3015/* 3016 * Handle completion of non-aggregate session frames. 3017 */ 3018void 3019ath_tx_normal_comp(struct ath_softc *sc, struct ath_buf *bf, int fail) 3020{ 3021 struct ieee80211_node *ni = bf->bf_node; 3022 struct ath_node *an = ATH_NODE(ni); 3023 int tid = bf->bf_state.bfs_tid; 3024 struct ath_tid *atid = &an->an_tid[tid]; 3025 struct ath_tx_status *ts = &bf->bf_status.ds_txstat; 3026 3027 /* The TID state is protected behind the TXQ lock */ 3028 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]); 3029 3030 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: bf=%p: fail=%d, hwq_depth now %d\n", 3031 __func__, bf, fail, atid->hwq_depth - 1); 3032 3033 atid->hwq_depth--; 3034 if (atid->hwq_depth < 0) 3035 device_printf(sc->sc_dev, "%s: hwq_depth < 0: %d\n", 3036 __func__, atid->hwq_depth); 3037 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 3038 3039 /* 3040 * punt to rate control if we're not being cleaned up 3041 * during a hw queue drain and the frame wanted an ACK. 3042 */ 3043 if (fail == 0 && ((bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) == 0)) 3044 ath_tx_update_ratectrl(sc, ni, bf->bf_state.bfs_rc, 3045 ts, bf->bf_state.bfs_pktlen, 3046 1, (ts->ts_status == 0) ? 0 : 1); 3047 3048 ath_tx_default_comp(sc, bf, fail); 3049} 3050 3051/* 3052 * Handle cleanup of aggregate session packets that aren't 3053 * an A-MPDU. 3054 * 3055 * There's no need to update the BAW here - the session is being 3056 * torn down. 3057 */ 3058static void 3059ath_tx_comp_cleanup_unaggr(struct ath_softc *sc, struct ath_buf *bf) 3060{ 3061 struct ieee80211_node *ni = bf->bf_node; 3062 struct ath_node *an = ATH_NODE(ni); 3063 int tid = bf->bf_state.bfs_tid; 3064 struct ath_tid *atid = &an->an_tid[tid]; 3065 3066 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, "%s: TID %d: incomp=%d\n", 3067 __func__, tid, atid->incomp); 3068 3069 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]); 3070 atid->incomp--; 3071 if (atid->incomp == 0) { 3072 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, 3073 "%s: TID %d: cleaned up! resume!\n", 3074 __func__, tid); 3075 atid->cleanup_inprogress = 0; 3076 ath_tx_tid_resume(sc, atid); 3077 } 3078 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 3079 3080 ath_tx_default_comp(sc, bf, 0); 3081} 3082 3083/* 3084 * Performs transmit side cleanup when TID changes from aggregated to 3085 * unaggregated. 3086 * 3087 * - Discard all retry frames from the s/w queue. 3088 * - Fix the tx completion function for all buffers in s/w queue. 3089 * - Count the number of unacked frames, and let transmit completion 3090 * handle it later. 3091 * 3092 * The caller is responsible for pausing the TID. 3093 */ 3094static void 3095ath_tx_cleanup(struct ath_softc *sc, struct ath_node *an, int tid) 3096{ 3097 struct ath_tid *atid = &an->an_tid[tid]; 3098 struct ieee80211_tx_ampdu *tap; 3099 struct ath_buf *bf, *bf_next; 3100 ath_bufhead bf_cq; 3101 3102 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, 3103 "%s: TID %d: called\n", __func__, tid); 3104 3105 TAILQ_INIT(&bf_cq); 3106 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]); 3107 3108 /* 3109 * Update the frames in the software TX queue: 3110 * 3111 * + Discard retry frames in the queue 3112 * + Fix the completion function to be non-aggregate 3113 */ 3114 bf = TAILQ_FIRST(&atid->axq_q); 3115 while (bf) { 3116 if (bf->bf_state.bfs_isretried) { 3117 bf_next = TAILQ_NEXT(bf, bf_list); 3118 TAILQ_REMOVE(&atid->axq_q, bf, bf_list); 3119 atid->axq_depth--; 3120 if (bf->bf_state.bfs_dobaw) { 3121 ath_tx_update_baw(sc, an, atid, bf); 3122 if (! bf->bf_state.bfs_addedbaw) 3123 device_printf(sc->sc_dev, 3124 "%s: wasn't added: seqno %d\n", 3125 __func__, 3126 SEQNO(bf->bf_state.bfs_seqno)); 3127 } 3128 bf->bf_state.bfs_dobaw = 0; 3129 /* 3130 * Call the default completion handler with "fail" just 3131 * so upper levels are suitably notified about this. 3132 */ 3133 TAILQ_INSERT_TAIL(&bf_cq, bf, bf_list); 3134 bf = bf_next; 3135 continue; 3136 } 3137 /* Give these the default completion handler */ 3138 bf->bf_comp = ath_tx_normal_comp; 3139 bf = TAILQ_NEXT(bf, bf_list); 3140 } 3141 3142 /* The caller is required to pause the TID */ 3143#if 0 3144 /* Pause the TID */ 3145 ath_tx_tid_pause(sc, atid); 3146#endif 3147 3148 /* 3149 * Calculate what hardware-queued frames exist based 3150 * on the current BAW size. Ie, what frames have been 3151 * added to the TX hardware queue for this TID but 3152 * not yet ACKed. 3153 */ 3154 tap = ath_tx_get_tx_tid(an, tid); 3155 /* Need the lock - fiddling with BAW */ 3156 while (atid->baw_head != atid->baw_tail) { 3157 if (atid->tx_buf[atid->baw_head]) { 3158 atid->incomp++; 3159 atid->cleanup_inprogress = 1; 3160 atid->tx_buf[atid->baw_head] = NULL; 3161 } 3162 INCR(atid->baw_head, ATH_TID_MAX_BUFS); 3163 INCR(tap->txa_start, IEEE80211_SEQ_RANGE); 3164 } 3165 3166 /* 3167 * If cleanup is required, defer TID scheduling 3168 * until all the HW queued packets have been 3169 * sent. 3170 */ 3171 if (! atid->cleanup_inprogress) 3172 ath_tx_tid_resume(sc, atid); 3173 3174 if (atid->cleanup_inprogress) 3175 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, 3176 "%s: TID %d: cleanup needed: %d packets\n", 3177 __func__, tid, atid->incomp); 3178 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 3179 3180 /* Handle completing frames and fail them */ 3181 while ((bf = TAILQ_FIRST(&bf_cq)) != NULL) { 3182 TAILQ_REMOVE(&bf_cq, bf, bf_list); 3183 ath_tx_default_comp(sc, bf, 1); 3184 } 3185} 3186 3187static void 3188ath_tx_set_retry(struct ath_softc *sc, struct ath_buf *bf) 3189{ 3190 struct ieee80211_frame *wh; 3191 3192 wh = mtod(bf->bf_m, struct ieee80211_frame *); 3193 /* Only update/resync if needed */ 3194 if (bf->bf_state.bfs_isretried == 0) { 3195 wh->i_fc[1] |= IEEE80211_FC1_RETRY; 3196 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 3197 BUS_DMASYNC_PREWRITE); 3198 } 3199 sc->sc_stats.ast_tx_swretries++; 3200 bf->bf_state.bfs_isretried = 1; 3201 bf->bf_state.bfs_retries ++; 3202} 3203 3204static struct ath_buf * 3205ath_tx_retry_clone(struct ath_softc *sc, struct ath_node *an, 3206 struct ath_tid *tid, struct ath_buf *bf) 3207{ 3208 struct ath_buf *nbf; 3209 int error; 3210 3211 nbf = ath_buf_clone(sc, bf); 3212 3213#if 0 3214 device_printf(sc->sc_dev, "%s: ATH_BUF_BUSY; cloning\n", 3215 __func__); 3216#endif 3217 3218 if (nbf == NULL) { 3219 /* Failed to clone */ 3220 device_printf(sc->sc_dev, 3221 "%s: failed to clone a busy buffer\n", 3222 __func__); 3223 return NULL; 3224 } 3225 3226 /* Setup the dma for the new buffer */ 3227 error = ath_tx_dmasetup(sc, nbf, nbf->bf_m); 3228 if (error != 0) { 3229 device_printf(sc->sc_dev, 3230 "%s: failed to setup dma for clone\n", 3231 __func__); 3232 /* 3233 * Put this at the head of the list, not tail; 3234 * that way it doesn't interfere with the 3235 * busy buffer logic (which uses the tail of 3236 * the list.) 3237 */ 3238 ATH_TXBUF_LOCK(sc); 3239 TAILQ_INSERT_HEAD(&sc->sc_txbuf, nbf, bf_list); 3240 ATH_TXBUF_UNLOCK(sc); 3241 return NULL; 3242 } 3243 3244 /* Update BAW if required, before we free the original buf */ 3245 if (bf->bf_state.bfs_dobaw) 3246 ath_tx_switch_baw_buf(sc, an, tid, bf, nbf); 3247 3248 /* Free current buffer; return the older buffer */ 3249 bf->bf_m = NULL; 3250 bf->bf_node = NULL; 3251 ath_freebuf(sc, bf); 3252 return nbf; 3253} 3254 3255/* 3256 * Handle retrying an unaggregate frame in an aggregate 3257 * session. 3258 * 3259 * If too many retries occur, pause the TID, wait for 3260 * any further retransmits (as there's no reason why 3261 * non-aggregate frames in an aggregate session are 3262 * transmitted in-order; they just have to be in-BAW) 3263 * and then queue a BAR. 3264 */ 3265static void 3266ath_tx_aggr_retry_unaggr(struct ath_softc *sc, struct ath_buf *bf) 3267{ 3268 struct ieee80211_node *ni = bf->bf_node; 3269 struct ath_node *an = ATH_NODE(ni); 3270 int tid = bf->bf_state.bfs_tid; 3271 struct ath_tid *atid = &an->an_tid[tid]; 3272 struct ieee80211_tx_ampdu *tap; 3273 3274 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]); 3275 3276 tap = ath_tx_get_tx_tid(an, tid); 3277 3278 /* 3279 * If the buffer is marked as busy, we can't directly 3280 * reuse it. Instead, try to clone the buffer. 3281 * If the clone is successful, recycle the old buffer. 3282 * If the clone is unsuccessful, set bfs_retries to max 3283 * to force the next bit of code to free the buffer 3284 * for us. 3285 */ 3286 if ((bf->bf_state.bfs_retries < SWMAX_RETRIES) && 3287 (bf->bf_flags & ATH_BUF_BUSY)) { 3288 struct ath_buf *nbf; 3289 nbf = ath_tx_retry_clone(sc, an, atid, bf); 3290 if (nbf) 3291 /* bf has been freed at this point */ 3292 bf = nbf; 3293 else 3294 bf->bf_state.bfs_retries = SWMAX_RETRIES + 1; 3295 } 3296 3297 if (bf->bf_state.bfs_retries >= SWMAX_RETRIES) { 3298 DPRINTF(sc, ATH_DEBUG_SW_TX_RETRIES, 3299 "%s: exceeded retries; seqno %d\n", 3300 __func__, SEQNO(bf->bf_state.bfs_seqno)); 3301 sc->sc_stats.ast_tx_swretrymax++; 3302 3303 /* Update BAW anyway */ 3304 if (bf->bf_state.bfs_dobaw) { 3305 ath_tx_update_baw(sc, an, atid, bf); 3306 if (! bf->bf_state.bfs_addedbaw) 3307 device_printf(sc->sc_dev, 3308 "%s: wasn't added: seqno %d\n", 3309 __func__, SEQNO(bf->bf_state.bfs_seqno)); 3310 } 3311 bf->bf_state.bfs_dobaw = 0; 3312 3313 /* Suspend the TX queue and get ready to send the BAR */ 3314 ath_tx_tid_bar_suspend(sc, atid); 3315 3316 /* Send the BAR if there are no other frames waiting */ 3317 if (ath_tx_tid_bar_tx_ready(sc, atid)) 3318 ath_tx_tid_bar_tx(sc, atid); 3319 3320 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 3321 3322 /* Free buffer, bf is free after this call */ 3323 ath_tx_default_comp(sc, bf, 0); 3324 return; 3325 } 3326 3327 /* 3328 * This increments the retry counter as well as 3329 * sets the retry flag in the ath_buf and packet 3330 * body. 3331 */ 3332 ath_tx_set_retry(sc, bf); 3333 3334 /* 3335 * Insert this at the head of the queue, so it's 3336 * retried before any current/subsequent frames. 3337 */ 3338 ATH_TXQ_INSERT_HEAD(atid, bf, bf_list); 3339 ath_tx_tid_sched(sc, atid); 3340 /* Send the BAR if there are no other frames waiting */ 3341 if (ath_tx_tid_bar_tx_ready(sc, atid)) 3342 ath_tx_tid_bar_tx(sc, atid); 3343 3344 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 3345} 3346 3347/* 3348 * Common code for aggregate excessive retry/subframe retry. 3349 * If retrying, queues buffers to bf_q. If not, frees the 3350 * buffers. 3351 * 3352 * XXX should unify this with ath_tx_aggr_retry_unaggr() 3353 */ 3354static int 3355ath_tx_retry_subframe(struct ath_softc *sc, struct ath_buf *bf, 3356 ath_bufhead *bf_q) 3357{ 3358 struct ieee80211_node *ni = bf->bf_node; 3359 struct ath_node *an = ATH_NODE(ni); 3360 int tid = bf->bf_state.bfs_tid; 3361 struct ath_tid *atid = &an->an_tid[tid]; 3362 3363 ATH_TXQ_LOCK_ASSERT(sc->sc_ac2q[atid->ac]); 3364 3365 ath_hal_clr11n_aggr(sc->sc_ah, bf->bf_desc); 3366 ath_hal_set11nburstduration(sc->sc_ah, bf->bf_desc, 0); 3367 /* ath_hal_set11n_virtualmorefrag(sc->sc_ah, bf->bf_desc, 0); */ 3368 3369 /* 3370 * If the buffer is marked as busy, we can't directly 3371 * reuse it. Instead, try to clone the buffer. 3372 * If the clone is successful, recycle the old buffer. 3373 * If the clone is unsuccessful, set bfs_retries to max 3374 * to force the next bit of code to free the buffer 3375 * for us. 3376 */ 3377 if ((bf->bf_state.bfs_retries < SWMAX_RETRIES) && 3378 (bf->bf_flags & ATH_BUF_BUSY)) { 3379 struct ath_buf *nbf; 3380 nbf = ath_tx_retry_clone(sc, an, atid, bf); 3381 if (nbf) 3382 /* bf has been freed at this point */ 3383 bf = nbf; 3384 else 3385 bf->bf_state.bfs_retries = SWMAX_RETRIES + 1; 3386 } 3387 3388 if (bf->bf_state.bfs_retries >= SWMAX_RETRIES) { 3389 sc->sc_stats.ast_tx_swretrymax++; 3390 DPRINTF(sc, ATH_DEBUG_SW_TX_RETRIES, 3391 "%s: max retries: seqno %d\n", 3392 __func__, SEQNO(bf->bf_state.bfs_seqno)); 3393 ath_tx_update_baw(sc, an, atid, bf); 3394 if (! bf->bf_state.bfs_addedbaw) 3395 device_printf(sc->sc_dev, 3396 "%s: wasn't added: seqno %d\n", 3397 __func__, SEQNO(bf->bf_state.bfs_seqno)); 3398 bf->bf_state.bfs_dobaw = 0; 3399 return 1; 3400 } 3401 3402 ath_tx_set_retry(sc, bf); 3403 bf->bf_next = NULL; /* Just to make sure */ 3404 3405 TAILQ_INSERT_TAIL(bf_q, bf, bf_list); 3406 return 0; 3407} 3408 3409/* 3410 * error pkt completion for an aggregate destination 3411 */ 3412static void 3413ath_tx_comp_aggr_error(struct ath_softc *sc, struct ath_buf *bf_first, 3414 struct ath_tid *tid) 3415{ 3416 struct ieee80211_node *ni = bf_first->bf_node; 3417 struct ath_node *an = ATH_NODE(ni); 3418 struct ath_buf *bf_next, *bf; 3419 ath_bufhead bf_q; 3420 int drops = 0; 3421 struct ieee80211_tx_ampdu *tap; 3422 ath_bufhead bf_cq; 3423 3424 TAILQ_INIT(&bf_q); 3425 TAILQ_INIT(&bf_cq); 3426 3427 /* 3428 * Update rate control - all frames have failed. 3429 * 3430 * XXX use the length in the first frame in the series; 3431 * XXX just so things are consistent for now. 3432 */ 3433 ath_tx_update_ratectrl(sc, ni, bf_first->bf_state.bfs_rc, 3434 &bf_first->bf_status.ds_txstat, 3435 bf_first->bf_state.bfs_pktlen, 3436 bf_first->bf_state.bfs_nframes, bf_first->bf_state.bfs_nframes); 3437 3438 ATH_TXQ_LOCK(sc->sc_ac2q[tid->ac]); 3439 tap = ath_tx_get_tx_tid(an, tid->tid); 3440 sc->sc_stats.ast_tx_aggr_failall++; 3441 3442 /* Retry all subframes */ 3443 bf = bf_first; 3444 while (bf) { 3445 bf_next = bf->bf_next; 3446 bf->bf_next = NULL; /* Remove it from the aggr list */ 3447 sc->sc_stats.ast_tx_aggr_fail++; 3448 if (ath_tx_retry_subframe(sc, bf, &bf_q)) { 3449 drops++; 3450 bf->bf_next = NULL; 3451 TAILQ_INSERT_TAIL(&bf_cq, bf, bf_list); 3452 } 3453 bf = bf_next; 3454 } 3455 3456 /* Prepend all frames to the beginning of the queue */ 3457 while ((bf = TAILQ_LAST(&bf_q, ath_bufhead_s)) != NULL) { 3458 TAILQ_REMOVE(&bf_q, bf, bf_list); 3459 ATH_TXQ_INSERT_HEAD(tid, bf, bf_list); 3460 } 3461 3462 /* 3463 * Schedule the TID to be re-tried. 3464 */ 3465 ath_tx_tid_sched(sc, tid); 3466 3467 /* 3468 * send bar if we dropped any frames 3469 * 3470 * Keep the txq lock held for now, as we need to ensure 3471 * that ni_txseqs[] is consistent (as it's being updated 3472 * in the ifnet TX context or raw TX context.) 3473 */ 3474 if (drops) { 3475 /* Suspend the TX queue and get ready to send the BAR */ 3476 ath_tx_tid_bar_suspend(sc, tid); 3477 } 3478 3479 /* 3480 * Send BAR if required 3481 */ 3482 if (ath_tx_tid_bar_tx_ready(sc, tid)) 3483 ath_tx_tid_bar_tx(sc, tid); 3484 ATH_TXQ_UNLOCK(sc->sc_ac2q[tid->ac]); 3485 3486 /* Complete frames which errored out */ 3487 while ((bf = TAILQ_FIRST(&bf_cq)) != NULL) { 3488 TAILQ_REMOVE(&bf_cq, bf, bf_list); 3489 ath_tx_default_comp(sc, bf, 0); 3490 } 3491} 3492 3493/* 3494 * Handle clean-up of packets from an aggregate list. 3495 * 3496 * There's no need to update the BAW here - the session is being 3497 * torn down. 3498 */ 3499static void 3500ath_tx_comp_cleanup_aggr(struct ath_softc *sc, struct ath_buf *bf_first) 3501{ 3502 struct ath_buf *bf, *bf_next; 3503 struct ieee80211_node *ni = bf_first->bf_node; 3504 struct ath_node *an = ATH_NODE(ni); 3505 int tid = bf_first->bf_state.bfs_tid; 3506 struct ath_tid *atid = &an->an_tid[tid]; 3507 3508 bf = bf_first; 3509 3510 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]); 3511 3512 /* update incomp */ 3513 while (bf) { 3514 atid->incomp--; 3515 bf = bf->bf_next; 3516 } 3517 3518 if (atid->incomp == 0) { 3519 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, 3520 "%s: TID %d: cleaned up! resume!\n", 3521 __func__, tid); 3522 atid->cleanup_inprogress = 0; 3523 ath_tx_tid_resume(sc, atid); 3524 } 3525 3526 /* Send BAR if required */ 3527 if (ath_tx_tid_bar_tx_ready(sc, atid)) 3528 ath_tx_tid_bar_tx(sc, atid); 3529 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 3530 3531 /* Handle frame completion */ 3532 while (bf) { 3533 bf_next = bf->bf_next; 3534 ath_tx_default_comp(sc, bf, 1); 3535 bf = bf_next; 3536 } 3537} 3538 3539/* 3540 * Handle completion of an set of aggregate frames. 3541 * 3542 * XXX for now, simply complete each sub-frame. 3543 * 3544 * Note: the completion handler is the last descriptor in the aggregate, 3545 * not the last descriptor in the first frame. 3546 */ 3547static void 3548ath_tx_aggr_comp_aggr(struct ath_softc *sc, struct ath_buf *bf_first, 3549 int fail) 3550{ 3551 //struct ath_desc *ds = bf->bf_lastds; 3552 struct ieee80211_node *ni = bf_first->bf_node; 3553 struct ath_node *an = ATH_NODE(ni); 3554 int tid = bf_first->bf_state.bfs_tid; 3555 struct ath_tid *atid = &an->an_tid[tid]; 3556 struct ath_tx_status ts; 3557 struct ieee80211_tx_ampdu *tap; 3558 ath_bufhead bf_q; 3559 ath_bufhead bf_cq; 3560 int seq_st, tx_ok; 3561 int hasba, isaggr; 3562 uint32_t ba[2]; 3563 struct ath_buf *bf, *bf_next; 3564 int ba_index; 3565 int drops = 0; 3566 int nframes = 0, nbad = 0, nf; 3567 int pktlen; 3568 /* XXX there's too much on the stack? */ 3569 struct ath_rc_series rc[4]; 3570 int txseq; 3571 3572 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, "%s: called; hwq_depth=%d\n", 3573 __func__, atid->hwq_depth); 3574 3575 /* The TID state is kept behind the TXQ lock */ 3576 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]); 3577 3578 atid->hwq_depth--; 3579 if (atid->hwq_depth < 0) 3580 device_printf(sc->sc_dev, "%s: hwq_depth < 0: %d\n", 3581 __func__, atid->hwq_depth); 3582 3583 /* 3584 * Punt cleanup to the relevant function, not our problem now 3585 */ 3586 if (atid->cleanup_inprogress) { 3587 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 3588 ath_tx_comp_cleanup_aggr(sc, bf_first); 3589 return; 3590 } 3591 3592 /* 3593 * Take a copy; this may be needed -after- bf_first 3594 * has been completed and freed. 3595 */ 3596 ts = bf_first->bf_status.ds_txstat; 3597 /* 3598 * XXX for now, use the first frame in the aggregate for 3599 * XXX rate control completion; it's at least consistent. 3600 */ 3601 pktlen = bf_first->bf_state.bfs_pktlen; 3602 3603 /* 3604 * Handle errors first! 3605 * 3606 * Here, handle _any_ error as a "exceeded retries" error. 3607 * Later on (when filtered frames are to be specially handled) 3608 * it'll have to be expanded. 3609 */ 3610#if 0 3611 if (ts.ts_status & HAL_TXERR_XRETRY) { 3612#endif 3613 if (ts.ts_status != 0) { 3614 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 3615 ath_tx_comp_aggr_error(sc, bf_first, atid); 3616 return; 3617 } 3618 3619 TAILQ_INIT(&bf_q); 3620 TAILQ_INIT(&bf_cq); 3621 tap = ath_tx_get_tx_tid(an, tid); 3622 3623 /* 3624 * extract starting sequence and block-ack bitmap 3625 */ 3626 /* XXX endian-ness of seq_st, ba? */ 3627 seq_st = ts.ts_seqnum; 3628 hasba = !! (ts.ts_flags & HAL_TX_BA); 3629 tx_ok = (ts.ts_status == 0); 3630 isaggr = bf_first->bf_state.bfs_aggr; 3631 ba[0] = ts.ts_ba_low; 3632 ba[1] = ts.ts_ba_high; 3633 3634 /* 3635 * Copy the TX completion status and the rate control 3636 * series from the first descriptor, as it may be freed 3637 * before the rate control code can get its grubby fingers 3638 * into things. 3639 */ 3640 memcpy(rc, bf_first->bf_state.bfs_rc, sizeof(rc)); 3641 3642 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, 3643 "%s: txa_start=%d, tx_ok=%d, status=%.8x, flags=%.8x, " 3644 "isaggr=%d, seq_st=%d, hasba=%d, ba=%.8x, %.8x\n", 3645 __func__, tap->txa_start, tx_ok, ts.ts_status, ts.ts_flags, 3646 isaggr, seq_st, hasba, ba[0], ba[1]); 3647 3648 /* Occasionally, the MAC sends a tx status for the wrong TID. */ 3649 if (tid != ts.ts_tid) { 3650 device_printf(sc->sc_dev, "%s: tid %d != hw tid %d\n", 3651 __func__, tid, ts.ts_tid); 3652 tx_ok = 0; 3653 } 3654 3655 /* AR5416 BA bug; this requires an interface reset */ 3656 if (isaggr && tx_ok && (! hasba)) { 3657 device_printf(sc->sc_dev, 3658 "%s: AR5416 bug: hasba=%d; txok=%d, isaggr=%d, " 3659 "seq_st=%d\n", 3660 __func__, hasba, tx_ok, isaggr, seq_st); 3661 /* XXX TODO: schedule an interface reset */ 3662 } 3663 3664 /* 3665 * Walk the list of frames, figure out which ones were correctly 3666 * sent and which weren't. 3667 */ 3668 bf = bf_first; 3669 nf = bf_first->bf_state.bfs_nframes; 3670 3671 /* bf_first is going to be invalid once this list is walked */ 3672 bf_first = NULL; 3673 3674 /* 3675 * Walk the list of completed frames and determine 3676 * which need to be completed and which need to be 3677 * retransmitted. 3678 * 3679 * For completed frames, the completion functions need 3680 * to be called at the end of this function as the last 3681 * node reference may free the node. 3682 * 3683 * Finally, since the TXQ lock can't be held during the 3684 * completion callback (to avoid lock recursion), 3685 * the completion calls have to be done outside of the 3686 * lock. 3687 */ 3688 while (bf) { 3689 nframes++; 3690 ba_index = ATH_BA_INDEX(seq_st, 3691 SEQNO(bf->bf_state.bfs_seqno)); 3692 bf_next = bf->bf_next; 3693 bf->bf_next = NULL; /* Remove it from the aggr list */ 3694 3695 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, 3696 "%s: checking bf=%p seqno=%d; ack=%d\n", 3697 __func__, bf, SEQNO(bf->bf_state.bfs_seqno), 3698 ATH_BA_ISSET(ba, ba_index)); 3699 3700 if (tx_ok && ATH_BA_ISSET(ba, ba_index)) { 3701 sc->sc_stats.ast_tx_aggr_ok++; 3702 ath_tx_update_baw(sc, an, atid, bf); 3703 bf->bf_state.bfs_dobaw = 0; 3704 if (! bf->bf_state.bfs_addedbaw) 3705 device_printf(sc->sc_dev, 3706 "%s: wasn't added: seqno %d\n", 3707 __func__, SEQNO(bf->bf_state.bfs_seqno)); 3708 bf->bf_next = NULL; 3709 TAILQ_INSERT_TAIL(&bf_cq, bf, bf_list); 3710 } else { 3711 sc->sc_stats.ast_tx_aggr_fail++; 3712 if (ath_tx_retry_subframe(sc, bf, &bf_q)) { 3713 drops++; 3714 bf->bf_next = NULL; 3715 TAILQ_INSERT_TAIL(&bf_cq, bf, bf_list); 3716 } 3717 nbad++; 3718 } 3719 bf = bf_next; 3720 } 3721 3722 /* 3723 * Now that the BAW updates have been done, unlock 3724 * 3725 * txseq is grabbed before the lock is released so we 3726 * have a consistent view of what -was- in the BAW. 3727 * Anything after this point will not yet have been 3728 * TXed. 3729 */ 3730 txseq = tap->txa_start; 3731 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 3732 3733 if (nframes != nf) 3734 device_printf(sc->sc_dev, 3735 "%s: num frames seen=%d; bf nframes=%d\n", 3736 __func__, nframes, nf); 3737 3738 /* 3739 * Now we know how many frames were bad, call the rate 3740 * control code. 3741 */ 3742 if (fail == 0) 3743 ath_tx_update_ratectrl(sc, ni, rc, &ts, pktlen, nframes, 3744 nbad); 3745 3746 /* 3747 * send bar if we dropped any frames 3748 */ 3749 if (drops) { 3750 /* Suspend the TX queue and get ready to send the BAR */ 3751 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]); 3752 ath_tx_tid_bar_suspend(sc, atid); 3753 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 3754 } 3755 3756 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, 3757 "%s: txa_start now %d\n", __func__, tap->txa_start); 3758 3759 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]); 3760 3761 /* Prepend all frames to the beginning of the queue */ 3762 while ((bf = TAILQ_LAST(&bf_q, ath_bufhead_s)) != NULL) { 3763 TAILQ_REMOVE(&bf_q, bf, bf_list); 3764 ATH_TXQ_INSERT_HEAD(atid, bf, bf_list); 3765 } 3766 3767 /* 3768 * Reschedule to grab some further frames. 3769 */ 3770 ath_tx_tid_sched(sc, atid); 3771 3772 /* 3773 * Send BAR if required 3774 */ 3775 if (ath_tx_tid_bar_tx_ready(sc, atid)) 3776 ath_tx_tid_bar_tx(sc, atid); 3777 3778 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 3779 3780 /* Do deferred completion */ 3781 while ((bf = TAILQ_FIRST(&bf_cq)) != NULL) { 3782 TAILQ_REMOVE(&bf_cq, bf, bf_list); 3783 ath_tx_default_comp(sc, bf, 0); 3784 } 3785} 3786 3787/* 3788 * Handle completion of unaggregated frames in an ADDBA 3789 * session. 3790 * 3791 * Fail is set to 1 if the entry is being freed via a call to 3792 * ath_tx_draintxq(). 3793 */ 3794static void 3795ath_tx_aggr_comp_unaggr(struct ath_softc *sc, struct ath_buf *bf, int fail) 3796{ 3797 struct ieee80211_node *ni = bf->bf_node; 3798 struct ath_node *an = ATH_NODE(ni); 3799 int tid = bf->bf_state.bfs_tid; 3800 struct ath_tid *atid = &an->an_tid[tid]; 3801 struct ath_tx_status *ts = &bf->bf_status.ds_txstat; 3802 3803 /* 3804 * Update rate control status here, before we possibly 3805 * punt to retry or cleanup. 3806 * 3807 * Do it outside of the TXQ lock. 3808 */ 3809 if (fail == 0 && ((bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) == 0)) 3810 ath_tx_update_ratectrl(sc, ni, bf->bf_state.bfs_rc, 3811 &bf->bf_status.ds_txstat, 3812 bf->bf_state.bfs_pktlen, 3813 1, (ts->ts_status == 0) ? 0 : 1); 3814 3815 /* 3816 * This is called early so atid->hwq_depth can be tracked. 3817 * This unfortunately means that it's released and regrabbed 3818 * during retry and cleanup. That's rather inefficient. 3819 */ 3820 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]); 3821 3822 if (tid == IEEE80211_NONQOS_TID) 3823 device_printf(sc->sc_dev, "%s: TID=16!\n", __func__); 3824 3825 DPRINTF(sc, ATH_DEBUG_SW_TX, 3826 "%s: bf=%p: tid=%d, hwq_depth=%d, seqno=%d\n", 3827 __func__, bf, bf->bf_state.bfs_tid, atid->hwq_depth, 3828 SEQNO(bf->bf_state.bfs_seqno)); 3829 3830 atid->hwq_depth--; 3831 if (atid->hwq_depth < 0) 3832 device_printf(sc->sc_dev, "%s: hwq_depth < 0: %d\n", 3833 __func__, atid->hwq_depth); 3834 3835 /* 3836 * If a cleanup is in progress, punt to comp_cleanup; 3837 * rather than handling it here. It's thus their 3838 * responsibility to clean up, call the completion 3839 * function in net80211, etc. 3840 */ 3841 if (atid->cleanup_inprogress) { 3842 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 3843 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: cleanup_unaggr\n", 3844 __func__); 3845 ath_tx_comp_cleanup_unaggr(sc, bf); 3846 return; 3847 } 3848 3849 /* 3850 * Don't bother with the retry check if all frames 3851 * are being failed (eg during queue deletion.) 3852 */ 3853#if 0 3854 if (fail == 0 && ts->ts_status & HAL_TXERR_XRETRY) { 3855#endif 3856 if (fail == 0 && ts->ts_status != 0) { 3857 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 3858 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: retry_unaggr\n", 3859 __func__); 3860 ath_tx_aggr_retry_unaggr(sc, bf); 3861 return; 3862 } 3863 3864 /* Success? Complete */ 3865 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: TID=%d, seqno %d\n", 3866 __func__, tid, SEQNO(bf->bf_state.bfs_seqno)); 3867 if (bf->bf_state.bfs_dobaw) { 3868 ath_tx_update_baw(sc, an, atid, bf); 3869 bf->bf_state.bfs_dobaw = 0; 3870 if (! bf->bf_state.bfs_addedbaw) 3871 device_printf(sc->sc_dev, 3872 "%s: wasn't added: seqno %d\n", 3873 __func__, SEQNO(bf->bf_state.bfs_seqno)); 3874 } 3875 3876 /* 3877 * Send BAR if required 3878 */ 3879 if (ath_tx_tid_bar_tx_ready(sc, atid)) 3880 ath_tx_tid_bar_tx(sc, atid); 3881 3882 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 3883 3884 ath_tx_default_comp(sc, bf, fail); 3885 /* bf is freed at this point */ 3886} 3887 3888void 3889ath_tx_aggr_comp(struct ath_softc *sc, struct ath_buf *bf, int fail) 3890{ 3891 if (bf->bf_state.bfs_aggr) 3892 ath_tx_aggr_comp_aggr(sc, bf, fail); 3893 else 3894 ath_tx_aggr_comp_unaggr(sc, bf, fail); 3895} 3896 3897/* 3898 * Schedule some packets from the given node/TID to the hardware. 3899 * 3900 * This is the aggregate version. 3901 */ 3902void 3903ath_tx_tid_hw_queue_aggr(struct ath_softc *sc, struct ath_node *an, 3904 struct ath_tid *tid) 3905{ 3906 struct ath_buf *bf; 3907 struct ath_txq *txq = sc->sc_ac2q[tid->ac]; 3908 struct ieee80211_tx_ampdu *tap; 3909 struct ieee80211_node *ni = &an->an_node; 3910 ATH_AGGR_STATUS status; 3911 ath_bufhead bf_q; 3912 3913 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: tid=%d\n", __func__, tid->tid); 3914 ATH_TXQ_LOCK_ASSERT(txq); 3915 3916 tap = ath_tx_get_tx_tid(an, tid->tid); 3917 3918 if (tid->tid == IEEE80211_NONQOS_TID) 3919 device_printf(sc->sc_dev, "%s: called for TID=NONQOS_TID?\n", 3920 __func__); 3921 3922 for (;;) { 3923 status = ATH_AGGR_DONE; 3924 3925 /* 3926 * If the upper layer has paused the TID, don't 3927 * queue any further packets. 3928 * 3929 * This can also occur from the completion task because 3930 * of packet loss; but as its serialised with this code, 3931 * it won't "appear" half way through queuing packets. 3932 */ 3933 if (tid->paused) 3934 break; 3935 3936 bf = TAILQ_FIRST(&tid->axq_q); 3937 if (bf == NULL) { 3938 break; 3939 } 3940 3941 /* 3942 * If the packet doesn't fall within the BAW (eg a NULL 3943 * data frame), schedule it directly; continue. 3944 */ 3945 if (! bf->bf_state.bfs_dobaw) { 3946 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, 3947 "%s: non-baw packet\n", 3948 __func__); 3949 ATH_TXQ_REMOVE(tid, bf, bf_list); 3950 bf->bf_state.bfs_aggr = 0; 3951 ath_tx_do_ratelookup(sc, bf); 3952 ath_tx_calc_duration(sc, bf); 3953 ath_tx_calc_protection(sc, bf); 3954 ath_tx_set_rtscts(sc, bf); 3955 ath_tx_rate_fill_rcflags(sc, bf); 3956 ath_tx_setds(sc, bf); 3957 ath_tx_chaindesclist(sc, bf); 3958 ath_hal_clr11n_aggr(sc->sc_ah, bf->bf_desc); 3959 ath_tx_set_ratectrl(sc, ni, bf); 3960 3961 sc->sc_aggr_stats.aggr_nonbaw_pkt++; 3962 3963 /* Queue the packet; continue */ 3964 goto queuepkt; 3965 } 3966 3967 TAILQ_INIT(&bf_q); 3968 3969 /* 3970 * Do a rate control lookup on the first frame in the 3971 * list. The rate control code needs that to occur 3972 * before it can determine whether to TX. 3973 * It's inaccurate because the rate control code doesn't 3974 * really "do" aggregate lookups, so it only considers 3975 * the size of the first frame. 3976 */ 3977 ath_tx_do_ratelookup(sc, bf); 3978 bf->bf_state.bfs_rc[3].rix = 0; 3979 bf->bf_state.bfs_rc[3].tries = 0; 3980 3981 ath_tx_calc_duration(sc, bf); 3982 ath_tx_calc_protection(sc, bf); 3983 3984 ath_tx_set_rtscts(sc, bf); 3985 ath_tx_rate_fill_rcflags(sc, bf); 3986 3987 status = ath_tx_form_aggr(sc, an, tid, &bf_q); 3988 3989 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, 3990 "%s: ath_tx_form_aggr() status=%d\n", __func__, status); 3991 3992 /* 3993 * No frames to be picked up - out of BAW 3994 */ 3995 if (TAILQ_EMPTY(&bf_q)) 3996 break; 3997 3998 /* 3999 * This assumes that the descriptor list in the ath_bufhead 4000 * are already linked together via bf_next pointers. 4001 */ 4002 bf = TAILQ_FIRST(&bf_q); 4003 4004 if (status == ATH_AGGR_8K_LIMITED) 4005 sc->sc_aggr_stats.aggr_rts_aggr_limited++; 4006 4007 /* 4008 * If it's the only frame send as non-aggregate 4009 * assume that ath_tx_form_aggr() has checked 4010 * whether it's in the BAW and added it appropriately. 4011 */ 4012 if (bf->bf_state.bfs_nframes == 1) { 4013 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, 4014 "%s: single-frame aggregate\n", __func__); 4015 bf->bf_state.bfs_aggr = 0; 4016 ath_tx_setds(sc, bf); 4017 ath_tx_chaindesclist(sc, bf); 4018 ath_hal_clr11n_aggr(sc->sc_ah, bf->bf_desc); 4019 ath_tx_set_ratectrl(sc, ni, bf); 4020 if (status == ATH_AGGR_BAW_CLOSED) 4021 sc->sc_aggr_stats.aggr_baw_closed_single_pkt++; 4022 else 4023 sc->sc_aggr_stats.aggr_single_pkt++; 4024 } else { 4025 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, 4026 "%s: multi-frame aggregate: %d frames, " 4027 "length %d\n", 4028 __func__, bf->bf_state.bfs_nframes, 4029 bf->bf_state.bfs_al); 4030 bf->bf_state.bfs_aggr = 1; 4031 sc->sc_aggr_stats.aggr_pkts[bf->bf_state.bfs_nframes]++; 4032 sc->sc_aggr_stats.aggr_aggr_pkt++; 4033 4034 /* 4035 * Calculate the duration/protection as required. 4036 */ 4037 ath_tx_calc_duration(sc, bf); 4038 ath_tx_calc_protection(sc, bf); 4039 4040 /* 4041 * Update the rate and rtscts information based on the 4042 * rate decision made by the rate control code; 4043 * the first frame in the aggregate needs it. 4044 */ 4045 ath_tx_set_rtscts(sc, bf); 4046 4047 /* 4048 * Setup the relevant descriptor fields 4049 * for aggregation. The first descriptor 4050 * already points to the rest in the chain. 4051 */ 4052 ath_tx_setds_11n(sc, bf); 4053 4054 /* 4055 * setup first desc with rate and aggr info 4056 */ 4057 ath_tx_set_ratectrl(sc, ni, bf); 4058 } 4059 queuepkt: 4060 //txq = bf->bf_state.bfs_txq; 4061 4062 /* Set completion handler, multi-frame aggregate or not */ 4063 bf->bf_comp = ath_tx_aggr_comp; 4064 4065 if (bf->bf_state.bfs_tid == IEEE80211_NONQOS_TID) 4066 device_printf(sc->sc_dev, "%s: TID=16?\n", __func__); 4067 4068 /* Punt to txq */ 4069 ath_tx_handoff(sc, txq, bf); 4070 4071 /* Track outstanding buffer count to hardware */ 4072 /* aggregates are "one" buffer */ 4073 tid->hwq_depth++; 4074 4075 /* 4076 * Break out if ath_tx_form_aggr() indicated 4077 * there can't be any further progress (eg BAW is full.) 4078 * Checking for an empty txq is done above. 4079 * 4080 * XXX locking on txq here? 4081 */ 4082 if (txq->axq_aggr_depth >= sc->sc_hwq_limit || 4083 status == ATH_AGGR_BAW_CLOSED) 4084 break; 4085 } 4086} 4087 4088/* 4089 * Schedule some packets from the given node/TID to the hardware. 4090 */ 4091void 4092ath_tx_tid_hw_queue_norm(struct ath_softc *sc, struct ath_node *an, 4093 struct ath_tid *tid) 4094{ 4095 struct ath_buf *bf; 4096 struct ath_txq *txq = sc->sc_ac2q[tid->ac]; 4097 struct ieee80211_node *ni = &an->an_node; 4098 4099 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: node %p: TID %d: called\n", 4100 __func__, an, tid->tid); 4101 4102 ATH_TXQ_LOCK_ASSERT(txq); 4103 4104 /* Check - is AMPDU pending or running? then print out something */ 4105 if (ath_tx_ampdu_pending(sc, an, tid->tid)) 4106 device_printf(sc->sc_dev, "%s: tid=%d, ampdu pending?\n", 4107 __func__, tid->tid); 4108 if (ath_tx_ampdu_running(sc, an, tid->tid)) 4109 device_printf(sc->sc_dev, "%s: tid=%d, ampdu running?\n", 4110 __func__, tid->tid); 4111 4112 for (;;) { 4113 4114 /* 4115 * If the upper layers have paused the TID, don't 4116 * queue any further packets. 4117 */ 4118 if (tid->paused) 4119 break; 4120 4121 bf = TAILQ_FIRST(&tid->axq_q); 4122 if (bf == NULL) { 4123 break; 4124 } 4125 4126 ATH_TXQ_REMOVE(tid, bf, bf_list); 4127 4128 KASSERT(txq == bf->bf_state.bfs_txq, ("txqs not equal!\n")); 4129 4130 /* Sanity check! */ 4131 if (tid->tid != bf->bf_state.bfs_tid) { 4132 device_printf(sc->sc_dev, "%s: bfs_tid %d !=" 4133 " tid %d\n", 4134 __func__, bf->bf_state.bfs_tid, tid->tid); 4135 } 4136 /* Normal completion handler */ 4137 bf->bf_comp = ath_tx_normal_comp; 4138 4139 /* Program descriptors + rate control */ 4140 ath_tx_do_ratelookup(sc, bf); 4141 ath_tx_calc_duration(sc, bf); 4142 ath_tx_calc_protection(sc, bf); 4143 ath_tx_set_rtscts(sc, bf); 4144 ath_tx_rate_fill_rcflags(sc, bf); 4145 ath_tx_setds(sc, bf); 4146 ath_tx_chaindesclist(sc, bf); 4147 ath_tx_set_ratectrl(sc, ni, bf); 4148 4149 /* Track outstanding buffer count to hardware */ 4150 /* aggregates are "one" buffer */ 4151 tid->hwq_depth++; 4152 4153 /* Punt to hardware or software txq */ 4154 ath_tx_handoff(sc, txq, bf); 4155 } 4156} 4157 4158/* 4159 * Schedule some packets to the given hardware queue. 4160 * 4161 * This function walks the list of TIDs (ie, ath_node TIDs 4162 * with queued traffic) and attempts to schedule traffic 4163 * from them. 4164 * 4165 * TID scheduling is implemented as a FIFO, with TIDs being 4166 * added to the end of the queue after some frames have been 4167 * scheduled. 4168 */ 4169void 4170ath_txq_sched(struct ath_softc *sc, struct ath_txq *txq) 4171{ 4172 struct ath_tid *tid, *next, *last; 4173 4174 ATH_TXQ_LOCK_ASSERT(txq); 4175 4176 /* 4177 * Don't schedule if the hardware queue is busy. 4178 * This (hopefully) gives some more time to aggregate 4179 * some packets in the aggregation queue. 4180 */ 4181 if (txq->axq_aggr_depth >= sc->sc_hwq_limit) { 4182 sc->sc_aggr_stats.aggr_sched_nopkt++; 4183 return; 4184 } 4185 4186 last = TAILQ_LAST(&txq->axq_tidq, axq_t_s); 4187 4188 TAILQ_FOREACH_SAFE(tid, &txq->axq_tidq, axq_qelem, next) { 4189 /* 4190 * Suspend paused queues here; they'll be resumed 4191 * once the addba completes or times out. 4192 */ 4193 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: tid=%d, paused=%d\n", 4194 __func__, tid->tid, tid->paused); 4195 ath_tx_tid_unsched(sc, tid); 4196 if (tid->paused) { 4197 continue; 4198 } 4199 if (ath_tx_ampdu_running(sc, tid->an, tid->tid)) 4200 ath_tx_tid_hw_queue_aggr(sc, tid->an, tid); 4201 else 4202 ath_tx_tid_hw_queue_norm(sc, tid->an, tid); 4203 4204 /* Not empty? Re-schedule */ 4205 if (tid->axq_depth != 0) 4206 ath_tx_tid_sched(sc, tid); 4207 4208 /* Give the software queue time to aggregate more packets */ 4209 if (txq->axq_aggr_depth >= sc->sc_hwq_limit) { 4210 break; 4211 } 4212 4213 /* 4214 * If this was the last entry on the original list, stop. 4215 * Otherwise nodes that have been rescheduled onto the end 4216 * of the TID FIFO list will just keep being rescheduled. 4217 */ 4218 if (tid == last) 4219 break; 4220 } 4221} 4222 4223/* 4224 * TX addba handling 4225 */ 4226 4227/* 4228 * Return net80211 TID struct pointer, or NULL for none 4229 */ 4230struct ieee80211_tx_ampdu * 4231ath_tx_get_tx_tid(struct ath_node *an, int tid) 4232{ 4233 struct ieee80211_node *ni = &an->an_node; 4234 struct ieee80211_tx_ampdu *tap; 4235 4236 if (tid == IEEE80211_NONQOS_TID) 4237 return NULL; 4238 4239 tap = &ni->ni_tx_ampdu[tid]; 4240 return tap; 4241} 4242 4243/* 4244 * Is AMPDU-TX running? 4245 */ 4246static int 4247ath_tx_ampdu_running(struct ath_softc *sc, struct ath_node *an, int tid) 4248{ 4249 struct ieee80211_tx_ampdu *tap; 4250 4251 if (tid == IEEE80211_NONQOS_TID) 4252 return 0; 4253 4254 tap = ath_tx_get_tx_tid(an, tid); 4255 if (tap == NULL) 4256 return 0; /* Not valid; default to not running */ 4257 4258 return !! (tap->txa_flags & IEEE80211_AGGR_RUNNING); 4259} 4260 4261/* 4262 * Is AMPDU-TX negotiation pending? 4263 */ 4264static int 4265ath_tx_ampdu_pending(struct ath_softc *sc, struct ath_node *an, int tid) 4266{ 4267 struct ieee80211_tx_ampdu *tap; 4268 4269 if (tid == IEEE80211_NONQOS_TID) 4270 return 0; 4271 4272 tap = ath_tx_get_tx_tid(an, tid); 4273 if (tap == NULL) 4274 return 0; /* Not valid; default to not pending */ 4275 4276 return !! (tap->txa_flags & IEEE80211_AGGR_XCHGPEND); 4277} 4278 4279/* 4280 * Is AMPDU-TX pending for the given TID? 4281 */ 4282 4283 4284/* 4285 * Method to handle sending an ADDBA request. 4286 * 4287 * We tap this so the relevant flags can be set to pause the TID 4288 * whilst waiting for the response. 4289 * 4290 * XXX there's no timeout handler we can override? 4291 */ 4292int 4293ath_addba_request(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap, 4294 int dialogtoken, int baparamset, int batimeout) 4295{ 4296 struct ath_softc *sc = ni->ni_ic->ic_ifp->if_softc; 4297 int tid = tap->txa_tid; 4298 struct ath_node *an = ATH_NODE(ni); 4299 struct ath_tid *atid = &an->an_tid[tid]; 4300 4301 /* 4302 * XXX danger Will Robinson! 4303 * 4304 * Although the taskqueue may be running and scheduling some more 4305 * packets, these should all be _before_ the addba sequence number. 4306 * However, net80211 will keep self-assigning sequence numbers 4307 * until addba has been negotiated. 4308 * 4309 * In the past, these packets would be "paused" (which still works 4310 * fine, as they're being scheduled to the driver in the same 4311 * serialised method which is calling the addba request routine) 4312 * and when the aggregation session begins, they'll be dequeued 4313 * as aggregate packets and added to the BAW. However, now there's 4314 * a "bf->bf_state.bfs_dobaw" flag, and this isn't set for these 4315 * packets. Thus they never get included in the BAW tracking and 4316 * this can cause the initial burst of packets after the addba 4317 * negotiation to "hang", as they quickly fall outside the BAW. 4318 * 4319 * The "eventual" solution should be to tag these packets with 4320 * dobaw. Although net80211 has given us a sequence number, 4321 * it'll be "after" the left edge of the BAW and thus it'll 4322 * fall within it. 4323 */ 4324 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]); 4325 ath_tx_tid_pause(sc, atid); 4326 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 4327 4328 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, 4329 "%s: called; dialogtoken=%d, baparamset=%d, batimeout=%d\n", 4330 __func__, dialogtoken, baparamset, batimeout); 4331 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, 4332 "%s: txa_start=%d, ni_txseqs=%d\n", 4333 __func__, tap->txa_start, ni->ni_txseqs[tid]); 4334 4335 return sc->sc_addba_request(ni, tap, dialogtoken, baparamset, 4336 batimeout); 4337} 4338 4339/* 4340 * Handle an ADDBA response. 4341 * 4342 * We unpause the queue so TX'ing can resume. 4343 * 4344 * Any packets TX'ed from this point should be "aggregate" (whether 4345 * aggregate or not) so the BAW is updated. 4346 * 4347 * Note! net80211 keeps self-assigning sequence numbers until 4348 * ampdu is negotiated. This means the initially-negotiated BAW left 4349 * edge won't match the ni->ni_txseq. 4350 * 4351 * So, being very dirty, the BAW left edge is "slid" here to match 4352 * ni->ni_txseq. 4353 * 4354 * What likely SHOULD happen is that all packets subsequent to the 4355 * addba request should be tagged as aggregate and queued as non-aggregate 4356 * frames; thus updating the BAW. For now though, I'll just slide the 4357 * window. 4358 */ 4359int 4360ath_addba_response(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap, 4361 int status, int code, int batimeout) 4362{ 4363 struct ath_softc *sc = ni->ni_ic->ic_ifp->if_softc; 4364 int tid = tap->txa_tid; 4365 struct ath_node *an = ATH_NODE(ni); 4366 struct ath_tid *atid = &an->an_tid[tid]; 4367 int r; 4368 4369 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, 4370 "%s: called; status=%d, code=%d, batimeout=%d\n", __func__, 4371 status, code, batimeout); 4372 4373 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, 4374 "%s: txa_start=%d, ni_txseqs=%d\n", 4375 __func__, tap->txa_start, ni->ni_txseqs[tid]); 4376 4377 /* 4378 * Call this first, so the interface flags get updated 4379 * before the TID is unpaused. Otherwise a race condition 4380 * exists where the unpaused TID still doesn't yet have 4381 * IEEE80211_AGGR_RUNNING set. 4382 */ 4383 r = sc->sc_addba_response(ni, tap, status, code, batimeout); 4384 4385 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]); 4386 /* 4387 * XXX dirty! 4388 * Slide the BAW left edge to wherever net80211 left it for us. 4389 * Read above for more information. 4390 */ 4391 tap->txa_start = ni->ni_txseqs[tid]; 4392 ath_tx_tid_resume(sc, atid); 4393 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 4394 return r; 4395} 4396 4397 4398/* 4399 * Stop ADDBA on a queue. 4400 */ 4401void 4402ath_addba_stop(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap) 4403{ 4404 struct ath_softc *sc = ni->ni_ic->ic_ifp->if_softc; 4405 int tid = tap->txa_tid; 4406 struct ath_node *an = ATH_NODE(ni); 4407 struct ath_tid *atid = &an->an_tid[tid]; 4408 4409 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, "%s: called\n", __func__); 4410 4411 /* Pause TID traffic early, so there aren't any races */ 4412 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]); 4413 ath_tx_tid_pause(sc, atid); 4414 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 4415 4416 /* There's no need to hold the TXQ lock here */ 4417 sc->sc_addba_stop(ni, tap); 4418 4419 /* 4420 * ath_tx_cleanup will resume the TID if possible, otherwise 4421 * it'll set the cleanup flag, and it'll be unpaused once 4422 * things have been cleaned up. 4423 */ 4424 ath_tx_cleanup(sc, an, tid); 4425} 4426 4427/* 4428 * Note: net80211 bar_timeout() doesn't call this function on BAR failure; 4429 * it simply tears down the aggregation session. Ew. 4430 * 4431 * It however will call ieee80211_ampdu_stop() which will call 4432 * ic->ic_addba_stop(). 4433 * 4434 * XXX This uses a hard-coded max BAR count value; the whole 4435 * XXX BAR TX success or failure should be better handled! 4436 */ 4437void 4438ath_bar_response(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap, 4439 int status) 4440{ 4441 struct ath_softc *sc = ni->ni_ic->ic_ifp->if_softc; 4442 int tid = tap->txa_tid; 4443 struct ath_node *an = ATH_NODE(ni); 4444 struct ath_tid *atid = &an->an_tid[tid]; 4445 int attempts = tap->txa_attempts; 4446 4447 DPRINTF(sc, ATH_DEBUG_SW_TX_BAR, 4448 "%s: called; status=%d, attempts=%d\n", 4449 __func__, 4450 status, 4451 attempts); 4452 4453 /* Note: This may update the BAW details */ 4454 sc->sc_bar_response(ni, tap, status); 4455 4456 /* Unpause the TID */ 4457 /* 4458 * XXX if this is attempt=50, the TID will be downgraded 4459 * XXX to a non-aggregate session. So we must unpause the 4460 * XXX TID here or it'll never be done. 4461 */ 4462 if (status == 0 || attempts == 50) { 4463 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]); 4464 ath_tx_tid_bar_unsuspend(sc, atid); 4465 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 4466 } 4467} 4468 4469/* 4470 * This is called whenever the pending ADDBA request times out. 4471 * Unpause and reschedule the TID. 4472 */ 4473void 4474ath_addba_response_timeout(struct ieee80211_node *ni, 4475 struct ieee80211_tx_ampdu *tap) 4476{ 4477 struct ath_softc *sc = ni->ni_ic->ic_ifp->if_softc; 4478 int tid = tap->txa_tid; 4479 struct ath_node *an = ATH_NODE(ni); 4480 struct ath_tid *atid = &an->an_tid[tid]; 4481 4482 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, 4483 "%s: called; resuming\n", __func__); 4484 4485 /* Note: This updates the aggregate state to (again) pending */ 4486 sc->sc_addba_response_timeout(ni, tap); 4487 4488 /* Unpause the TID; which reschedules it */ 4489 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]); 4490 ath_tx_tid_resume(sc, atid); 4491 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 4492} 4493