ar9280_olc.c revision 219393
1/* 2 * Copyright (c) 2011 Adrian Chadd, Xenion Pty Ltd. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD: head/sys/dev/ath/ath_hal/ar9002/ar9280_olc.c 219393 2011-03-08 06:59:59Z adrian $ 26 */ 27#include "opt_ah.h" 28 29#include "ah.h" 30#include "ah_internal.h" 31 32#include "ah_eeprom_v14.h" 33 34#include "ar9002/ar9280.h" 35#include "ar5416/ar5416reg.h" 36#include "ar5416/ar5416phy.h" 37#include "ar9002/ar9002phy.h" 38 39#include "ar9002/ar9280_olc.h" 40 41void 42ar9280olcInit(struct ath_hal *ah) 43{ 44 uint32_t i; 45 46 for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++) 47 AH9280(ah)->originalGain[i] = MS(OS_REG_READ(ah, 48 AR_PHY_TX_GAIN_TBL1 + i * 4), AR_PHY_TX_GAIN); 49 50 AH9280(ah)->PDADCdelta = 0; 51} 52 53void 54ar9280olcGetTxGainIndex(struct ath_hal *ah, 55 const struct ieee80211_channel *chan, 56 struct calDataPerFreqOpLoop *rawDatasetOpLoop, 57 uint8_t *calChans, uint16_t availPiers, uint8_t *pwr, uint8_t *pcdacIdx) 58{ 59 uint8_t pcdac, i = 0; 60 uint16_t idxL = 0, idxR = 0, numPiers; 61 HAL_BOOL match; 62 CHAN_CENTERS centers; 63 64 ar5416GetChannelCenters(ah, chan, ¢ers); 65 66 for (numPiers = 0; numPiers < availPiers; numPiers++) 67 if (calChans[numPiers] == AR5416_BCHAN_UNUSED) 68 break; 69 70 match = getLowerUpperIndex((uint8_t)FREQ2FBIN(centers.synth_center, 71 IEEE80211_IS_CHAN_2GHZ(chan)), calChans, numPiers, 72 &idxL, &idxR); 73 if (match) { 74 pcdac = rawDatasetOpLoop[idxL].pcdac[0][0]; 75 *pwr = rawDatasetOpLoop[idxL].pwrPdg[0][0]; 76 } else { 77 pcdac = rawDatasetOpLoop[idxR].pcdac[0][0]; 78 *pwr = (rawDatasetOpLoop[idxL].pwrPdg[0][0] + 79 rawDatasetOpLoop[idxR].pwrPdg[0][0])/2; 80 } 81 while (pcdac > AH9280(ah)->originalGain[i] && 82 i < (AR9280_TX_GAIN_TABLE_SIZE - 1)) 83 i++; 84 85 *pcdacIdx = i; 86} 87 88/* 89 * XXX txPower here is likely not the target txPower in the traditional 90 * XXX sense, but is set by a call to ar9280olcGetTxGainIndex(). 91 * XXX Thus, be careful if you're trying to use this routine yourself. 92 */ 93void 94ar9280olcGetPDADCs(struct ath_hal *ah, uint32_t initTxGain, int txPower, 95 uint8_t *pPDADCValues) 96{ 97 uint32_t i; 98 uint32_t offset; 99 100 OS_REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL6_0, AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3); 101 OS_REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL6_1, AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3); 102 103 OS_REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL7, AR_PHY_TX_PWRCTRL_INIT_TX_GAIN, initTxGain); 104 105 offset = txPower; 106 for (i = 0; i < AR5416_NUM_PDADC_VALUES; i++) 107 if (i < offset) 108 pPDADCValues[i] = 0x0; 109 else 110 pPDADCValues[i] = 0xFF; 111} 112 113/* 114 * Run temperature compensation calibration. 115 * 116 * The TX gain table is adjusted depending upon the difference 117 * between the initial PDADC value and the currently read 118 * average TX power sample value. This value is only valid if 119 * frames have been transmitted, so currPDADC will be 0 if 120 * no frames have yet been transmitted. 121 */ 122void 123ar9280olcTemperatureCompensation(struct ath_hal *ah) 124{ 125 uint32_t rddata, i; 126 int delta, currPDADC, regval; 127 uint8_t hpwr_5g = 0; 128 129 rddata = OS_REG_READ(ah, AR_PHY_TX_PWRCTRL4); 130 currPDADC = MS(rddata, AR_PHY_TX_PWRCTRL_PD_AVG_OUT); 131 132 HALDEBUG(ah, HAL_DEBUG_PERCAL, 133 "%s: called: initPDADC=%d, currPDADC=%d\n", 134 __func__, AH5416(ah)->initPDADC, currPDADC); 135 136 if (AH5416(ah)->initPDADC == 0 || currPDADC == 0) 137 return; 138 139 (void) (ath_hal_eepromGet(ah, AR_EEP_DAC_HPWR_5G, &hpwr_5g)); 140 141 if (hpwr_5g) 142 delta = (currPDADC - AH5416(ah)->initPDADC + 4) / 8; 143 else 144 delta = (currPDADC - AH5416(ah)->initPDADC + 5) / 10; 145 146 HALDEBUG(ah, HAL_DEBUG_PERCAL, "%s: delta=%d, PDADCdelta=%d\n", 147 __func__, delta, AH9280(ah)->PDADCdelta); 148 149 if (delta != AH9280(ah)->PDADCdelta) { 150 AH9280(ah)->PDADCdelta = delta; 151 for (i = 1; i < AR9280_TX_GAIN_TABLE_SIZE; i++) { 152 regval = AH9280(ah)->originalGain[i] - delta; 153 if (regval < 0) 154 regval = 0; 155 156 OS_REG_RMW_FIELD(ah, 157 AR_PHY_TX_GAIN_TBL1 + i * 4, 158 AR_PHY_TX_GAIN, regval); 159 } 160 } 161} 162 163/* 164 * This effectively disables the gain boundaries leaving it 165 * to the open-loop TX power control. 166 */ 167static void 168ar9280SetGainBoundariesOpenLoop(struct ath_hal *ah, int regChainOffset, 169 uint16_t pdGainOverlap_t2, uint16_t gainBoundaries[]) 170{ 171 /* These are unused for OLC */ 172 (void) pdGainOverlap_t2; 173 (void) gainBoundaries; 174 175 OS_REG_WRITE(ah, AR_PHY_TPCRG5 + regChainOffset, 176 SM(0x6, AR_PHY_TPCRG5_PD_GAIN_OVERLAP) | 177 SM(0x38, AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1) | 178 SM(0x38, AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2) | 179 SM(0x38, AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3) | 180 SM(0x38, AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4)); 181} 182 183/* Eeprom versioning macros. Returns true if the version is equal or newer than the ver specified */ 184/* XXX shouldn't be here! */ 185#define EEP_MINOR(_ah) \ 186 (AH_PRIVATE(_ah)->ah_eeversion & AR5416_EEP_VER_MINOR_MASK) 187#define IS_EEP_MINOR_V2(_ah) (EEP_MINOR(_ah) >= AR5416_EEP_MINOR_VER_2) 188#define IS_EEP_MINOR_V3(_ah) (EEP_MINOR(_ah) >= AR5416_EEP_MINOR_VER_3) 189 190/************************************************************** 191 * ar9280SetPowerCalTable 192 * 193 * Pull the PDADC piers from cal data and interpolate them across the given 194 * points as well as from the nearest pier(s) to get a power detector 195 * linear voltage to power level table. 196 * 197 * Handle OLC for Merlin where required. 198 */ 199HAL_BOOL 200ar9280SetPowerCalTable(struct ath_hal *ah, struct ar5416eeprom *pEepData, 201 const struct ieee80211_channel *chan, int16_t *pTxPowerIndexOffset) 202{ 203 CAL_DATA_PER_FREQ *pRawDataset; 204 uint8_t *pCalBChans = AH_NULL; 205 uint16_t pdGainOverlap_t2; 206 static uint8_t pdadcValues[AR5416_NUM_PDADC_VALUES]; 207 uint16_t gainBoundaries[AR5416_PD_GAINS_IN_MASK]; 208 uint16_t numPiers, i; 209 int16_t tMinCalPower; 210 uint16_t numXpdGain, xpdMask; 211 uint16_t xpdGainValues[AR5416_NUM_PD_GAINS]; 212 uint32_t regChainOffset; 213 214 OS_MEMZERO(xpdGainValues, sizeof(xpdGainValues)); 215 216 xpdMask = pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].xpdGain; 217 218 if (IS_EEP_MINOR_V2(ah)) { 219 pdGainOverlap_t2 = pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].pdGainOverlap; 220 } else { 221 pdGainOverlap_t2 = (uint16_t)(MS(OS_REG_READ(ah, AR_PHY_TPCRG5), AR_PHY_TPCRG5_PD_GAIN_OVERLAP)); 222 } 223 224 if (IEEE80211_IS_CHAN_2GHZ(chan)) { 225 pCalBChans = pEepData->calFreqPier2G; 226 numPiers = AR5416_NUM_2G_CAL_PIERS; 227 } else { 228 pCalBChans = pEepData->calFreqPier5G; 229 numPiers = AR5416_NUM_5G_CAL_PIERS; 230 } 231 232 /* If OLC is being done, set the init PDADC value appropriately */ 233 if (IEEE80211_IS_CHAN_2GHZ(chan) && AR_SREV_MERLIN_20_OR_LATER(ah) && 234 ath_hal_eepromGetFlag(ah, AR_EEP_OL_PWRCTRL)) { 235 struct calDataPerFreq *pRawDataset = pEepData->calPierData2G[0]; 236 AH5416(ah)->initPDADC = ((struct calDataPerFreqOpLoop *) pRawDataset)->vpdPdg[0][0]; 237 } else { 238 /* 239 * XXX ath9k doesn't clear this for 5ghz mode if 240 * it were set in 2ghz mode before! 241 * The Merlin OLC temperature compensation code 242 * uses this to calculate the PDADC delta during 243 * calibration ; 0 here effectively stops the 244 * temperature compensation calibration from 245 * occuring. 246 */ 247 AH5416(ah)->initPDADC = 0; 248 } 249 250 /* Calculate the value of xpdgains from the xpdGain Mask */ 251 numXpdGain = ar5416GetXpdGainValues(ah, xpdMask, xpdGainValues); 252 253 /* Write the detector gain biases and their number */ 254 ar5416WriteDetectorGainBiases(ah, numXpdGain, xpdGainValues); 255 256 for (i = 0; i < AR5416_MAX_CHAINS; i++) { 257 regChainOffset = ar5416GetRegChainOffset(ah, i); 258 if (pEepData->baseEepHeader.txMask & (1 << i)) { 259 if (IEEE80211_IS_CHAN_2GHZ(chan)) { 260 pRawDataset = pEepData->calPierData2G[i]; 261 } else { 262 pRawDataset = pEepData->calPierData5G[i]; 263 } 264 265 /* Fetch the gain boundaries and the PDADC values */ 266 if (AR_SREV_MERLIN_20_OR_LATER(ah) && 267 ath_hal_eepromGetFlag(ah, AR_EEP_OL_PWRCTRL)) { 268 uint8_t pcdacIdx; 269 uint8_t txPower; 270 271 ar9280olcGetTxGainIndex(ah, chan, 272 (struct calDataPerFreqOpLoop *) pRawDataset, 273 pCalBChans, numPiers, &txPower, &pcdacIdx); 274 ar9280olcGetPDADCs(ah, pcdacIdx, txPower / 2, pdadcValues); 275 } else { 276 ar5416GetGainBoundariesAndPdadcs(ah, chan, 277 pRawDataset, pCalBChans, numPiers, 278 pdGainOverlap_t2, &tMinCalPower, 279 gainBoundaries, pdadcValues, numXpdGain); 280 } 281 282 /* 283 * Prior to writing the boundaries or the pdadc vs. power table 284 * into the chip registers the default starting point on the pdadc 285 * vs. power table needs to be checked and the curve boundaries 286 * adjusted accordingly 287 */ 288 // XXX ath9k_change_gain_boundary_setting(); 289 290 if ((i == 0) || AR_SREV_OWL_20_OR_LATER(ah)) { 291 /* Set gain boundaries for either open- or closed-loop TPC */ 292 if (AR_SREV_MERLIN_20_OR_LATER(ah) && 293 ath_hal_eepromGetFlag(ah, AR_EEP_OL_PWRCTRL)) 294 ar9280SetGainBoundariesOpenLoop(ah, 295 regChainOffset, pdGainOverlap_t2, 296 gainBoundaries); 297 else 298 ar5416SetGainBoundariesClosedLoop(ah, 299 regChainOffset, pdGainOverlap_t2, 300 gainBoundaries); 301 } 302 303 /* 304 * If this is a board that has a pwrTableOffset that differs from 305 * the default AR5416_PWR_TABLE_OFFSET_DB then the start of the 306 * pdadc vs pwr table needs to be adjusted prior to writing to the 307 * chip. 308 */ 309 /* XXX ath9k_adjust_pdadc_values() */ 310 311 /* Write the power values into the baseband power table */ 312 ar5416WritePdadcValues(ah, regChainOffset, pdadcValues); 313 } 314 } 315 *pTxPowerIndexOffset = 0; 316 317 return AH_TRUE; 318} 319