ar5416reg.h revision 225925
1/* 2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ar5416/ar5416reg.h 225925 2011-10-02 14:08:56Z adrian $ 18 */ 19#ifndef _DEV_ATH_AR5416REG_H 20#define _DEV_ATH_AR5416REG_H 21 22#include <dev/ath/ath_hal/ar5212/ar5212reg.h> 23 24/* 25 * Register added starting with the AR5416 26 */ 27#define AR_MIRT 0x0020 /* interrupt rate threshold */ 28#define AR_TIMT 0x0028 /* Tx Interrupt mitigation threshold */ 29#define AR_RIMT 0x002C /* Rx Interrupt mitigation threshold */ 30#define AR_GTXTO 0x0064 /* global transmit timeout */ 31#define AR_GTTM 0x0068 /* global transmit timeout mode */ 32#define AR_CST 0x006C /* carrier sense timeout */ 33#define AR_MAC_LED 0x1f04 /* LED control */ 34#define AR_WA 0x4004 /* PCIE work-arounds */ 35#define AR_PCIE_PM_CTRL 0x4014 36#define AR_AHB_MODE 0x4024 /* AHB mode for dma */ 37#define AR_INTR_SYNC_CAUSE_CLR 0x4028 /* clear interrupt */ 38#define AR_INTR_SYNC_CAUSE 0x4028 /* check pending interrupts */ 39#define AR_INTR_SYNC_ENABLE 0x402c /* enable interrupts */ 40#define AR_INTR_ASYNC_MASK 0x4030 /* asynchronous interrupt mask */ 41#define AR_INTR_SYNC_MASK 0x4034 /* synchronous interrupt mask */ 42#define AR_INTR_ASYNC_CAUSE 0x4038 /* check pending interrupts */ 43#define AR_INTR_ASYNC_CAUSE_CLR 0x4038 /* clear pending interrupts */ 44#define AR_INTR_ASYNC_ENABLE 0x403c /* enable interrupts */ 45#define AR5416_PCIE_SERDES 0x4040 46#define AR5416_PCIE_SERDES2 0x4044 47#define AR_GPIO_IN_OUT 0x4048 /* GPIO input/output register */ 48#define AR_GPIO_OE_OUT 0x404c /* GPIO output enable register */ 49#define AR_GPIO_INTR_POL 0x4050 /* GPIO interrupt polarity */ 50#define AR_GPIO_INPUT_EN_VAL 0x4054 /* GPIO input enable and value */ 51#define AR_GPIO_INPUT_MUX1 0x4058 52#define AR_GPIO_INPUT_MUX2 0x405c 53#define AR_GPIO_OUTPUT_MUX1 0x4060 54#define AR_GPIO_OUTPUT_MUX2 0x4064 55#define AR_GPIO_OUTPUT_MUX3 0x4068 56#define AR_EEPROM_STATUS_DATA 0x407c 57#define AR_OBS 0x4080 58 59#ifdef AH_SUPPORT_AR9130 60#define AR_RTC_BASE 0x20000 61#else 62#define AR_RTC_BASE 0x7000 63#endif /* AH_SUPPORT_AR9130 */ 64 65#define AR_RTC_RC AR_RTC_BASE + 0x00 /* reset control */ 66#define AR_RTC_PLL_CONTROL AR_RTC_BASE + 0x14 67#define AR_RTC_RESET AR_RTC_BASE + 0x40 /* RTC reset register */ 68#define AR_RTC_STATUS AR_RTC_BASE + 0x44 /* system sleep status */ 69#define AR_RTC_SLEEP_CLK AR_RTC_BASE + 0x48 70#define AR_RTC_FORCE_WAKE AR_RTC_BASE + 0x4c /* control MAC force wake */ 71#define AR_RTC_INTR_CAUSE AR_RTC_BASE + 0x50 /* RTC interrupt cause/clear */ 72#define AR_RTC_INTR_ENABLE AR_RTC_BASE + 0x54 /* RTC interrupt enable */ 73#define AR_RTC_INTR_MASK AR_RTC_BASE + 0x58 /* RTC interrupt mask */ 74 75#ifdef AH_SUPPORT_AR9130 76/* RTC_DERIVED_* - only for AR9130 */ 77#define AR_RTC_DERIVED_CLK (AR_RTC_BASE + 0x0038) 78#define AR_RTC_DERIVED_CLK_PERIOD 0x0000fffe 79#define AR_RTC_DERIVED_CLK_PERIOD_S 1 80#endif /* AH_SUPPORT_AR9130 */ 81 82#define AR_RESET_TSF 0x8020 83 84/* 85 * AR_SLEEP1 / AR_SLEEP2 are in the same place as in 86 * AR5212, however the fields have changed. 87 */ 88#define AR5416_SLEEP1 0x80d4 89#define AR5416_SLEEP2 0x80d8 90#define AR_RXFIFO_CFG 0x8114 91#define AR_PHY_ERR_1 0x812c 92#define AR_PHY_ERR_MASK_1 0x8130 /* mask for AR_PHY_ERR_1 */ 93#define AR_PHY_ERR_2 0x8134 94#define AR_PHY_ERR_MASK_2 0x8138 /* mask for AR_PHY_ERR_2 */ 95#define AR_TSFOOR_THRESHOLD 0x813c 96#define AR_PHY_ERR_3 0x8168 97#define AR_PHY_ERR_MASK_3 0x816c /* mask for AR_PHY_ERR_3 */ 98#define AR_TXOP_X 0x81ec /* txop for legacy non-qos */ 99#define AR_TXOP_0_3 0x81f0 /* txop for various tid's */ 100#define AR_TXOP_4_7 0x81f4 101#define AR_TXOP_8_11 0x81f8 102#define AR_TXOP_12_15 0x81fc 103/* generic timers based on tsf - all uS */ 104#define AR_NEXT_TBTT 0x8200 105#define AR_NEXT_DBA 0x8204 106#define AR_NEXT_SWBA 0x8208 107#define AR_NEXT_CFP 0x8208 108#define AR_NEXT_HCF 0x820C 109#define AR_NEXT_TIM 0x8210 110#define AR_NEXT_DTIM 0x8214 111#define AR_NEXT_QUIET 0x8218 112#define AR_NEXT_NDP 0x821C 113#define AR5416_BEACON_PERIOD 0x8220 114#define AR_DBA_PERIOD 0x8224 115#define AR_SWBA_PERIOD 0x8228 116#define AR_HCF_PERIOD 0x822C 117#define AR_TIM_PERIOD 0x8230 118#define AR_DTIM_PERIOD 0x8234 119#define AR_QUIET_PERIOD 0x8238 120#define AR_NDP_PERIOD 0x823C 121#define AR_TIMER_MODE 0x8240 122#define AR_SLP32_MODE 0x8244 123#define AR_SLP32_WAKE 0x8248 124#define AR_SLP32_INC 0x824c 125#define AR_SLP_CNT 0x8250 /* 32kHz cycles with mac asleep */ 126#define AR_SLP_CYCLE_CNT 0x8254 /* absolute number of 32kHz cycles */ 127#define AR_SLP_MIB_CTRL 0x8258 128#define AR_2040_MODE 0x8318 129#define AR_EXTRCCNT 0x8328 /* extension channel rx clear count */ 130#define AR_SELFGEN_MASK 0x832c /* rx and cal chain masks */ 131#define AR_PCU_TXBUF_CTRL 0x8340 132#define AR_PCU_MISC_MODE2 0x8344 133 134/* DMA & PCI Registers in PCI space (usable during sleep)*/ 135#define AR_RC_AHB 0x00000001 /* AHB reset */ 136#define AR_RC_APB 0x00000002 /* APB reset */ 137#define AR_RC_HOSTIF 0x00000100 /* host interface reset */ 138 139#define AR_MIRT_VAL 0x0000ffff /* in uS */ 140#define AR_MIRT_VAL_S 16 141 142#define AR_TIMT_LAST 0x0000ffff /* Last packet threshold */ 143#define AR_TIMT_LAST_S 0 144#define AR_TIMT_FIRST 0xffff0000 /* First packet threshold */ 145#define AR_TIMT_FIRST_S 16 146 147#define AR_RIMT_LAST 0x0000ffff /* Last packet threshold */ 148#define AR_RIMT_LAST_S 0 149#define AR_RIMT_FIRST 0xffff0000 /* First packet threshold */ 150#define AR_RIMT_FIRST_S 16 151 152#define AR_GTXTO_TIMEOUT_COUNTER 0x0000FFFF // Mask for timeout counter (in TUs) 153#define AR_GTXTO_TIMEOUT_LIMIT 0xFFFF0000 // Mask for timeout limit (in TUs) 154#define AR_GTXTO_TIMEOUT_LIMIT_S 16 // Shift for timeout limit 155 156#define AR_GTTM_USEC 0x00000001 // usec strobe 157#define AR_GTTM_IGNORE_IDLE 0x00000002 // ignore channel idle 158#define AR_GTTM_RESET_IDLE 0x00000004 // reset counter on channel idle low 159#define AR_GTTM_CST_USEC 0x00000008 // CST usec strobe 160 161#define AR_CST_TIMEOUT_COUNTER 0x0000FFFF // Mask for timeout counter (in TUs) 162#define AR_CST_TIMEOUT_LIMIT 0xFFFF0000 // Mask for timeout limit (in TUs) 163#define AR_CST_TIMEOUT_LIMIT_S 16 // Shift for timeout limit 164 165/* MAC tx DMA size config */ 166#define AR_TXCFG_DMASZ_MASK 0x00000003 167#define AR_TXCFG_DMASZ_4B 0 168#define AR_TXCFG_DMASZ_8B 1 169#define AR_TXCFG_DMASZ_16B 2 170#define AR_TXCFG_DMASZ_32B 3 171#define AR_TXCFG_DMASZ_64B 4 172#define AR_TXCFG_DMASZ_128B 5 173#define AR_TXCFG_DMASZ_256B 6 174#define AR_TXCFG_DMASZ_512B 7 175#define AR_TXCFG_ATIM_TXPOLICY 0x00000800 176 177/* MAC rx DMA size config */ 178#define AR_RXCFG_DMASZ_MASK 0x00000007 179#define AR_RXCFG_DMASZ_4B 0 180#define AR_RXCFG_DMASZ_8B 1 181#define AR_RXCFG_DMASZ_16B 2 182#define AR_RXCFG_DMASZ_32B 3 183#define AR_RXCFG_DMASZ_64B 4 184#define AR_RXCFG_DMASZ_128B 5 185#define AR_RXCFG_DMASZ_256B 6 186#define AR_RXCFG_DMASZ_512B 7 187 188/* MAC Led registers */ 189#define AR_CFG_SCLK_RATE_IND 0x00000003 /* sleep clock indication */ 190#define AR_CFG_SCLK_RATE_IND_S 0 191#define AR_CFG_SCLK_32MHZ 0x00000000 /* Sleep clock rate */ 192#define AR_CFG_SCLK_4MHZ 0x00000001 /* Sleep clock rate */ 193#define AR_CFG_SCLK_1MHZ 0x00000002 /* Sleep clock rate */ 194#define AR_CFG_SCLK_32KHZ 0x00000003 /* Sleep clock rate */ 195#define AR_MAC_LED_BLINK_SLOW 0x00000008 /* LED slowest blink rate mode */ 196#define AR_MAC_LED_BLINK_THRESH_SEL 0x00000070 /* LED blink threshold select */ 197#define AR_MAC_LED_MODE 0x00000380 /* LED mode select */ 198#define AR_MAC_LED_MODE_S 7 199#define AR_MAC_LED_MODE_PROP 0 /* Blink prop to filtered tx/rx */ 200#define AR_MAC_LED_MODE_RPROP 1 /* Blink prop to unfiltered tx/rx */ 201#define AR_MAC_LED_MODE_SPLIT 2 /* Blink power for tx/net for rx */ 202#define AR_MAC_LED_MODE_RAND 3 /* Blink randomly */ 203#define AR_MAC_LED_MODE_POWON 5 /* Power LED on (s/w control) */ 204#define AR_MAC_LED_MODE_NETON 6 /* Network LED on (s/w control) */ 205#define AR_MAC_LED_ASSOC 0x00000c00 206#define AR_MAC_LED_ASSOC_NONE 0x00000000 /* STA is not associated or trying */ 207#define AR_MAC_LED_ASSOC_ACTIVE 0x00000400 /* STA is associated */ 208#define AR_MAC_LED_ASSOC_PEND 0x00000800 /* STA is trying to associate */ 209#define AR_MAC_LED_ASSOC_S 10 210 211#define AR_WA_UNTIE_RESET_EN 0x00008000 /* ena PCI reset to POR */ 212#define AR_WA_RESET_EN 0x00040000 /* ena AR_WA_UNTIE_RESET_EN */ 213#define AR_WA_ANALOG_SHIFT 0x00100000 214#define AR_WA_POR_SHORT 0x00200000 /* PCIE phy reset control */ 215 216#define AR_WA_DEFAULT 0x0000073f 217#define AR9280_WA_DEFAULT 0x0040073f 218#define AR9285_WA_DEFAULT 0x004a05cb 219 220#define AR_PCIE_PM_CTRL_ENA 0x00080000 221 222#define AR_AHB_EXACT_WR_EN 0x00000000 /* write exact bytes */ 223#define AR_AHB_BUF_WR_EN 0x00000001 /* buffer write upto cacheline*/ 224#define AR_AHB_EXACT_RD_EN 0x00000000 /* read exact bytes */ 225#define AR_AHB_CACHELINE_RD_EN 0x00000002 /* read upto end of cacheline */ 226#define AR_AHB_PREFETCH_RD_EN 0x00000004 /* prefetch upto page boundary*/ 227#define AR_AHB_PAGE_SIZE_1K 0x00000000 /* set page-size as 1k */ 228#define AR_AHB_PAGE_SIZE_2K 0x00000008 /* set page-size as 2k */ 229#define AR_AHB_PAGE_SIZE_4K 0x00000010 /* set page-size as 4k */ 230/* Kiwi */ 231#define AR_AHB_CUSTOM_BURST_EN 0x000000C0 /* set Custom Burst Mode */ 232#define AR_AHB_CUSTOM_BURST_EN_S 6 /* set Custom Burst Mode */ 233#define AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL 3 /* set both bits in Async FIFO mode */ 234 235/* MAC PCU Registers */ 236#define AR_STA_ID1_PRESERVE_SEQNUM 0x20000000 /* Don't replace seq num */ 237 238/* Extended PCU DIAG_SW control fields */ 239#define AR_DIAG_DUAL_CHAIN_INFO 0x01000000 /* dual chain channel info */ 240#define AR_DIAG_RX_ABORT 0x02000000 /* abort rx */ 241#define AR_DIAG_SATURATE_CCNT 0x04000000 /* sat. cycle cnts (no shift) */ 242#define AR_DIAG_OBS_PT_SEL2 0x08000000 /* observation point sel */ 243#define AR_DIAG_RXCLEAR_CTL_LOW 0x10000000 /* force rx_clear(ctl) low/busy */ 244#define AR_DIAG_RXCLEAR_EXT_LOW 0x20000000 /* force rx_clear(ext) low/busy */ 245 246#define AR_TXOP_X_VAL 0x000000FF 247 248#define AR_RESET_TSF_ONCE 0x01000000 /* reset tsf once; self-clears*/ 249 250/* Interrupts */ 251#define AR_ISR_TXMINTR 0x00080000 /* Maximum interrupt tx rate */ 252#define AR_ISR_RXMINTR 0x01000000 /* Maximum interrupt rx rate */ 253#define AR_ISR_GENTMR 0x10000000 /* OR of generic timer bits in S5 */ 254#define AR_ISR_TXINTM 0x40000000 /* Tx int after mitigation */ 255#define AR_ISR_RXINTM 0x80000000 /* Rx int after mitigation */ 256 257#define AR_ISR_S2_CST 0x00400000 /* Carrier sense timeout */ 258#define AR_ISR_S2_GTT 0x00800000 /* Global transmit timeout */ 259#define AR_ISR_S2_TSFOOR 0x40000000 /* RX TSF out of range */ 260 261#define AR_ISR_S5 0x0098 262#define AR_ISR_S5_S 0x00d8 263#define AR_ISR_S5_TIM_TIMER 0x00000010 264 265#define AR_INTR_SPURIOUS 0xffffffff 266#define AR_INTR_RTC_IRQ 0x00000001 /* rtc in shutdown state */ 267#define AR_INTR_MAC_IRQ 0x00000002 /* pending mac interrupt */ 268#define AR_INTR_EEP_PROT_ACCESS 0x00000004 /* eeprom protected access */ 269#define AR_INTR_MAC_AWAKE 0x00020000 /* mac is awake */ 270#define AR_INTR_MAC_ASLEEP 0x00040000 /* mac is asleep */ 271 272/* Interrupt Mask Registers */ 273#define AR_IMR_TXMINTR 0x00080000 /* Maximum interrupt tx rate */ 274#define AR_IMR_RXMINTR 0x01000000 /* Maximum interrupt rx rate */ 275#define AR_IMR_TXINTM 0x40000000 /* Tx int after mitigation */ 276#define AR_IMR_RXINTM 0x80000000 /* Rx int after mitigation */ 277 278#define AR_IMR_S2_CST 0x00400000 /* Carrier sense timeout */ 279#define AR_IMR_S2_GTT 0x00800000 /* Global transmit timeout */ 280 281/* synchronous interrupt signals */ 282#define AR_INTR_SYNC_RTC_IRQ 0x00000001 283#define AR_INTR_SYNC_MAC_IRQ 0x00000002 284#define AR_INTR_SYNC_EEPROM_ILLEGAL_ACCESS 0x00000004 285#define AR_INTR_SYNC_APB_TIMEOUT 0x00000008 286#define AR_INTR_SYNC_PCI_MODE_CONFLICT 0x00000010 287#define AR_INTR_SYNC_HOST1_FATAL 0x00000020 288#define AR_INTR_SYNC_HOST1_PERR 0x00000040 289#define AR_INTR_SYNC_TRCV_FIFO_PERR 0x00000080 290#define AR_INTR_SYNC_RADM_CPL_EP 0x00000100 291#define AR_INTR_SYNC_RADM_CPL_DLLP_ABORT 0x00000200 292#define AR_INTR_SYNC_RADM_CPL_TLP_ABORT 0x00000400 293#define AR_INTR_SYNC_RADM_CPL_ECRC_ERR 0x00000800 294#define AR_INTR_SYNC_RADM_CPL_TIMEOUT 0x00001000 295#define AR_INTR_SYNC_LOCAL_TIMEOUT 0x00002000 296#define AR_INTR_SYNC_PM_ACCESS 0x00004000 297#define AR_INTR_SYNC_MAC_AWAKE 0x00008000 298#define AR_INTR_SYNC_MAC_ASLEEP 0x00010000 299#define AR_INTR_SYNC_MAC_SLEEP_ACCESS 0x00020000 300#define AR_INTR_SYNC_ALL 0x0003FFFF 301 302/* default synchronous interrupt signals enabled */ 303#define AR_INTR_SYNC_DEFAULT \ 304 (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR | \ 305 AR_INTR_SYNC_RADM_CPL_EP | AR_INTR_SYNC_RADM_CPL_DLLP_ABORT | \ 306 AR_INTR_SYNC_RADM_CPL_TLP_ABORT | AR_INTR_SYNC_RADM_CPL_ECRC_ERR | \ 307 AR_INTR_SYNC_RADM_CPL_TIMEOUT | AR_INTR_SYNC_LOCAL_TIMEOUT | \ 308 AR_INTR_SYNC_MAC_SLEEP_ACCESS) 309 310#define AR_INTR_SYNC_MASK_GPIO 0xFFFC0000 311#define AR_INTR_SYNC_MASK_GPIO_S 18 312 313#define AR_INTR_SYNC_ENABLE_GPIO 0xFFFC0000 314#define AR_INTR_SYNC_ENABLE_GPIO_S 18 315 316#define AR_INTR_ASYNC_MASK_GPIO 0xFFFC0000 /* async int mask */ 317#define AR_INTR_ASYNC_MASK_GPIO_S 18 318 319#define AR_INTR_ASYNC_CAUSE_GPIO 0xFFFC0000 /* GPIO interrupts */ 320#define AR_INTR_ASYNC_USED (AR_INTR_MAC_IRQ | AR_INTR_ASYNC_CAUSE_GPIO) 321 322#define AR_INTR_ASYNC_ENABLE_GPIO 0xFFFC0000 /* enable interrupts */ 323#define AR_INTR_ASYNC_ENABLE_GPIO_S 18 324 325/* RTC registers */ 326#define AR_RTC_RC_M 0x00000003 327#define AR_RTC_RC_MAC_WARM 0x00000001 328#define AR_RTC_RC_MAC_COLD 0x00000002 329#ifdef AH_SUPPORT_AR9130 330#define AR_RTC_RC_COLD_RESET 0x00000004 331#define AR_RTC_RC_WARM_RESET 0x00000008 332#endif /* AH_SUPPORT_AR9130 */ 333#define AR_RTC_PLL_DIV 0x0000001f 334#define AR_RTC_PLL_DIV_S 0 335#define AR_RTC_PLL_DIV2 0x00000020 336#define AR_RTC_PLL_REFDIV_5 0x000000c0 337 338#define AR_RTC_SOWL_PLL_DIV 0x000003ff 339#define AR_RTC_SOWL_PLL_DIV_S 0 340#define AR_RTC_SOWL_PLL_REFDIV 0x00003C00 341#define AR_RTC_SOWL_PLL_REFDIV_S 10 342#define AR_RTC_SOWL_PLL_CLKSEL 0x0000C000 343#define AR_RTC_SOWL_PLL_CLKSEL_S 14 344 345#define AR_RTC_RESET_EN 0x00000001 /* Reset RTC bit */ 346 347#define AR_RTC_PM_STATUS_M 0x0000000f /* Pwr Mgmt Status */ 348#ifdef AH_SUPPORT_AR9130 349#define AR_RTC_STATUS_M 0x0000000f /* RTC Status */ 350#else 351#define AR_RTC_STATUS_M 0x0000003f /* RTC Status */ 352#endif /* AH_SUPPORT_AR9130 */ 353#define AR_RTC_STATUS_SHUTDOWN 0x00000001 354#define AR_RTC_STATUS_ON 0x00000002 355#define AR_RTC_STATUS_SLEEP 0x00000004 356#define AR_RTC_STATUS_WAKEUP 0x00000008 357#define AR_RTC_STATUS_COLDRESET 0x00000010 /* Not currently used */ 358#define AR_RTC_STATUS_PLLCHANGE 0x00000020 /* Not currently used */ 359 360#define AR_RTC_SLEEP_DERIVED_CLK 0x2 361 362#define AR_RTC_FORCE_WAKE_EN 0x00000001 /* enable force wake */ 363#define AR_RTC_FORCE_WAKE_ON_INT 0x00000002 /* auto-wake on MAC interrupt */ 364 365#define AR_RTC_PLL_CLKSEL 0x00000300 366#define AR_RTC_PLL_CLKSEL_S 8 367 368/* AR9280: rf long shift registers */ 369#define AR_AN_RF2G1_CH0 0x7810 370#define AR_AN_RF5G1_CH0 0x7818 371#define AR_AN_RF2G1_CH1 0x7834 372#define AR_AN_RF5G1_CH1 0x783C 373#define AR_AN_TOP2 0x7894 374#define AR_AN_SYNTH9 0x7868 375 376#define AR_AN_RF2G1_CH0_OB 0x03800000 377#define AR_AN_RF2G1_CH0_OB_S 23 378#define AR_AN_RF2G1_CH0_DB 0x1C000000 379#define AR_AN_RF2G1_CH0_DB_S 26 380 381#define AR_AN_RF5G1_CH0_OB5 0x00070000 382#define AR_AN_RF5G1_CH0_OB5_S 16 383#define AR_AN_RF5G1_CH0_DB5 0x00380000 384#define AR_AN_RF5G1_CH0_DB5_S 19 385 386#define AR_AN_RF2G1_CH1_OB 0x03800000 387#define AR_AN_RF2G1_CH1_OB_S 23 388#define AR_AN_RF2G1_CH1_DB 0x1C000000 389#define AR_AN_RF2G1_CH1_DB_S 26 390 391#define AR_AN_RF5G1_CH1_OB5 0x00070000 392#define AR_AN_RF5G1_CH1_OB5_S 16 393#define AR_AN_RF5G1_CH1_DB5 0x00380000 394#define AR_AN_RF5G1_CH1_DB5_S 19 395 396#define AR_AN_TOP1 0x7890 397#define AR_AN_TOP1_DACIPMODE 0x00040000 398#define AR_AN_TOP1_DACIPMODE_S 18 399 400#define AR_AN_TOP2_XPABIAS_LVL 0xC0000000 401#define AR_AN_TOP2_XPABIAS_LVL_S 30 402#define AR_AN_TOP2_LOCALBIAS 0x00200000 403#define AR_AN_TOP2_LOCALBIAS_S 21 404#define AR_AN_TOP2_PWDCLKIND 0x00400000 405#define AR_AN_TOP2_PWDCLKIND_S 22 406 407#define AR_AN_SYNTH9_REFDIVA 0xf8000000 408#define AR_AN_SYNTH9_REFDIVA_S 27 409 410#define AR9271_AN_RF2G6_OFFS 0x07f00000 411#define AR9271_AN_RF2G6_OFFS_S 20 412 413/* Sleep control */ 414#define AR5416_SLEEP1_ASSUME_DTIM 0x00080000 415#define AR5416_SLEEP1_CAB_TIMEOUT 0xFFE00000 /* Cab timeout (TU) */ 416#define AR5416_SLEEP1_CAB_TIMEOUT_S 22 417 418#define AR5416_SLEEP2_BEACON_TIMEOUT 0xFFE00000 /* Beacon timeout (TU)*/ 419#define AR5416_SLEEP2_BEACON_TIMEOUT_S 22 420 421/* Sleep Registers */ 422#define AR_SLP32_HALFCLK_LATENCY 0x000FFFFF /* rising <-> falling edge */ 423#define AR_SLP32_ENA 0x00100000 424#define AR_SLP32_TSF_WRITE_STATUS 0x00200000 /* tsf update in progress */ 425 426#define AR_SLP32_WAKE_XTL_TIME 0x0000FFFF /* time to wake crystal */ 427 428#define AR_SLP32_TST_INC 0x000FFFFF 429 430#define AR_SLP_MIB_CLEAR 0x00000001 /* clear pending */ 431#define AR_SLP_MIB_PENDING 0x00000002 /* clear counters */ 432 433#define AR_TIMER_MODE_TBTT 0x00000001 434#define AR_TIMER_MODE_DBA 0x00000002 435#define AR_TIMER_MODE_SWBA 0x00000004 436#define AR_TIMER_MODE_HCF 0x00000008 437#define AR_TIMER_MODE_TIM 0x00000010 438#define AR_TIMER_MODE_DTIM 0x00000020 439#define AR_TIMER_MODE_QUIET 0x00000040 440#define AR_TIMER_MODE_NDP 0x00000080 441#define AR_TIMER_MODE_OVERFLOW_INDEX 0x00000700 442#define AR_TIMER_MODE_OVERFLOW_INDEX_S 8 443#define AR_TIMER_MODE_THRESH 0xFFFFF000 444#define AR_TIMER_MODE_THRESH_S 12 445 446/* PCU Misc modes */ 447#define AR_PCU_FORCE_BSSID_MATCH 0x00000001 /* force bssid to match */ 448#define AR_PCU_MIC_NEW_LOC_ENA 0x00000004 /* tx/rx mic keys together */ 449#define AR_PCU_TX_ADD_TSF 0x00000008 /* add tx_tsf + int_tsf */ 450#define AR_PCU_CCK_SIFS_MODE 0x00000010 /* assume 11b sifs */ 451#define AR_PCU_RX_ANT_UPDT 0x00000800 /* KC_RX_ANT_UPDATE */ 452#define AR_PCU_TXOP_TBTT_LIMIT_ENA 0x00001000 /* enforce txop / tbtt */ 453#define AR_PCU_MISS_BCN_IN_SLEEP 0x00004000 /* count bmiss's when sleeping */ 454#define AR_PCU_BUG_12306_FIX_ENA 0x00020000 /* use rx_clear to count sifs */ 455#define AR_PCU_FORCE_QUIET_COLL 0x00040000 /* kill xmit for channel change */ 456#define AR_PCU_TBTT_PROTECT 0x00200000 /* no xmit upto tbtt+20 uS */ 457#define AR_PCU_CLEAR_VMF 0x01000000 /* clear vmf mode (fast cc)*/ 458#define AR_PCU_CLEAR_BA_VALID 0x04000000 /* clear ba state */ 459 460#define AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE 0x00000002 461#define AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT 0x00000004 462/* 463 * This bit enables the Multicast search based on both MAC Address and Key ID. 464 * If bit is 0, then Multicast search is based on MAC address only. 465 * For Merlin and above only. 466 */ 467#define AR_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE 0x00000040 468#define AR_PCU_MISC_MODE2_ENABLE_AGGWEP 0x00020000 /* Kiwi or later? */ 469#define AR_PCU_MISC_MODE2_HWWAR1 0x00100000 470#define AR_PCU_MISC_MODE2_HWWAR2 0x02000000 471 472/* For Kiwi */ 473#define AR_MAC_PCU_ASYNC_FIFO_REG3 0x8358 474#define AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL 0x00000400 475#define AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET 0x80000000 476 477/* TSF2. For Kiwi only */ 478#define AR_TSF2_L32 0x8390 479#define AR_TSF2_U32 0x8394 480 481/* MAC Direct Connect Control. For Kiwi only */ 482#define AR_DIRECT_CONNECT 0x83A0 483#define AR_DC_AP_STA_EN 0x00000001 484 485/* GPIO Interrupt */ 486#define AR_INTR_GPIO 0x3FF00000 /* gpio interrupted */ 487#define AR_INTR_GPIO_S 20 488 489#define AR_GPIO_OUT_CTRL 0x000003FF /* 0 = out, 1 = in */ 490#define AR_GPIO_OUT_VAL 0x000FFC00 491#define AR_GPIO_OUT_VAL_S 10 492#define AR_GPIO_INTR_CTRL 0x3FF00000 493#define AR_GPIO_INTR_CTRL_S 20 494 495#define AR_GPIO_IN_VAL 0x0FFFC000 /* pre-9280 */ 496#define AR_GPIO_IN_VAL_S 14 497#define AR928X_GPIO_IN_VAL 0x000FFC00 498#define AR928X_GPIO_IN_VAL_S 10 499#define AR9285_GPIO_IN_VAL 0x00FFF000 500#define AR9285_GPIO_IN_VAL_S 12 501 502#define AR_GPIO_OE_OUT_DRV 0x3 /* 2 bit mask shifted by 2*bitpos */ 503#define AR_GPIO_OE_OUT_DRV_NO 0x0 /* tristate */ 504#define AR_GPIO_OE_OUT_DRV_LOW 0x1 /* drive if low */ 505#define AR_GPIO_OE_OUT_DRV_HI 0x2 /* drive if high */ 506#define AR_GPIO_OE_OUT_DRV_ALL 0x3 /* drive always */ 507 508#define AR_GPIO_INTR_POL_VAL 0x1FFF 509#define AR_GPIO_INTR_POL_VAL_S 0 510 511#define AR_GPIO_JTAG_DISABLE 0x00020000 512 513#define AR_2040_JOINED_RX_CLEAR 0x00000001 /* use ctl + ext rx_clear for cca */ 514 515#define AR_PCU_TXBUF_CTRL_SIZE_MASK 0x7FF 516#define AR_PCU_TXBUF_CTRL_USABLE_SIZE 0x700 517#define AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE 0x380 518 519/* IFS, SIFS, slot, etc for Async FIFO mode (Kiwi) */ 520#define AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR 0x000003AB 521#define AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR 0x16001D56 522#define AR_USEC_ASYNC_FIFO_DUR 0x12e00074 523#define AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR 0x00000420 524#define AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR 0x0000A5EB 525 526/* Used by Kiwi Async FIFO */ 527#define AR_MAC_PCU_LOGIC_ANALYZER 0x8264 528#define AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768 0x20000000 529 530/* Eeprom defines */ 531#define AR_EEPROM_STATUS_DATA_VAL 0x0000ffff 532#define AR_EEPROM_STATUS_DATA_VAL_S 0 533#define AR_EEPROM_STATUS_DATA_BUSY 0x00010000 534#define AR_EEPROM_STATUS_DATA_BUSY_ACCESS 0x00020000 535#define AR_EEPROM_STATUS_DATA_PROT_ACCESS 0x00040000 536#define AR_EEPROM_STATUS_DATA_ABSENT_ACCESS 0x00080000 537 538/* 539 * AR5212 defines the MAC revision mask as 0xF, but both ath9k and 540 * the Atheros HAL define it as 0x7. 541 * 542 * What this means however is AR5416 silicon revisions have 543 * changed. The below macros are for what is contained in the 544 * lower four bits; if the lower three bits are taken into account 545 * the revisions become 1.0 => 0x0, 2.0 => 0x1, 2.2 => 0x2. 546 */ 547 548/* These are the legacy revisions, with a four bit AR_SREV_REVISION mask */ 549#define AR_SREV_REVISION_OWL_10 0x08 550#define AR_SREV_REVISION_OWL_20 0x09 551#define AR_SREV_REVISION_OWL_22 0x0a 552 553#define AR_RAD5133_SREV_MAJOR 0xc0 /* Fowl: 2+5G/3x3 */ 554#define AR_RAD2133_SREV_MAJOR 0xd0 /* Fowl: 2G/3x3 */ 555#define AR_RAD5122_SREV_MAJOR 0xe0 /* Fowl: 5G/2x2 */ 556#define AR_RAD2122_SREV_MAJOR 0xf0 /* Fowl: 2+5G/2x2 */ 557 558/* Test macro for owl 1.0 */ 559#define IS_5416V1(_ah) (AR_SREV_OWL((_ah)) && AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_OWL_10) 560#define IS_5416V2(_ah) (AR_SREV_OWL((_ah)) && AH_PRIVATE((_ah))->ah_macRev >= AR_SREV_REVISION_OWL_20) 561#define IS_5416V2_2(_ah) (AR_SREV_OWL((_ah)) && AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_OWL_22) 562 563/* Misc; compatibility with Atheros HAL */ 564#define AR_SREV_5416_V20_OR_LATER(_ah) (AR_SREV_HOWL((_ah)) || AR_SREV_OWL_20_OR_LATER(_ah)) 565#define AR_SREV_5416_V22_OR_LATER(_ah) (AR_SREV_HOWL((_ah)) || AR_SREV_OWL_22_OR_LATER(_ah)) 566 567/* Expanded Mac Silicon Rev (16 bits starting with Sowl) */ 568#define AR_XSREV_ID 0xFFFFFFFF /* Chip ID */ 569#define AR_XSREV_ID_S 0 570#define AR_XSREV_VERSION 0xFFFC0000 /* Chip version */ 571#define AR_XSREV_VERSION_S 18 572#define AR_XSREV_TYPE 0x0003F000 /* Chip type */ 573#define AR_XSREV_TYPE_S 12 574#define AR_XSREV_TYPE_CHAIN 0x00001000 /* Chain Mode (1:3 chains, 575 * 0:2 chains) */ 576#define AR_XSREV_TYPE_HOST_MODE 0x00002000 /* Host Mode (1:PCI, 0:PCIe) */ 577#define AR_XSREV_REVISION 0x00000F00 578#define AR_XSREV_REVISION_S 8 579 580#define AR_XSREV_VERSION_OWL_PCI 0x0D 581#define AR_XSREV_VERSION_OWL_PCIE 0x0C 582 583 584/* 585 * These are from ath9k/Atheros and assume an AR_SREV version mask 586 * of 0x07, rather than 0x0F which is being used in the FreeBSD HAL. 587 * Thus, don't use these values as they're incorrect here; use 588 * AR_SREV_REVISION_OWL_{10,20,22}. 589 */ 590#if 0 591#define AR_XSREV_REVISION_OWL_10 0 /* Owl 1.0 */ 592#define AR_XSREV_REVISION_OWL_20 1 /* Owl 2.0/2.1 */ 593#define AR_XSREV_REVISION_OWL_22 2 /* Owl 2.2 */ 594#endif 595 596#define AR_XSREV_VERSION_HOWL 0x14 /* Howl (AR9130) */ 597#define AR_XSREV_VERSION_SOWL 0x40 /* Sowl (AR9160) */ 598#define AR_XSREV_REVISION_SOWL_10 0 /* Sowl 1.0 */ 599#define AR_XSREV_REVISION_SOWL_11 1 /* Sowl 1.1 */ 600#define AR_XSREV_VERSION_MERLIN 0x80 /* Merlin Version */ 601#define AR_XSREV_REVISION_MERLIN_10 0 /* Merlin 1.0 */ 602#define AR_XSREV_REVISION_MERLIN_20 1 /* Merlin 2.0 */ 603#define AR_XSREV_REVISION_MERLIN_21 2 /* Merlin 2.1 */ 604#define AR_XSREV_VERSION_KITE 0xC0 /* Kite Version */ 605#define AR_XSREV_REVISION_KITE_10 0 /* Kite 1.0 */ 606#define AR_XSREV_REVISION_KITE_11 1 /* Kite 1.1 */ 607#define AR_XSREV_REVISION_KITE_12 2 /* Kite 1.2 */ 608#define AR_XSREV_VERSION_KIWI 0x180 /* Kiwi (AR9287) */ 609#define AR_XSREV_REVISION_KIWI_10 0 610#define AR_XSREV_REVISION_KIWI_11 1 611#define AR_XSREV_REVISION_KIWI_12 2 612#define AR_XSREV_REVISION_KIWI_13 3 613 614/* Owl (AR5416) */ 615#define AR_SREV_OWL(_ah) \ 616 ((AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_OWL_PCI) || \ 617 (AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_OWL_PCIE)) 618 619#define AR_SREV_OWL_20_OR_LATER(_ah) \ 620 ((AR_SREV_OWL(_ah) && \ 621 AH_PRIVATE((_ah))->ah_macRev >= AR_SREV_REVISION_OWL_20) || \ 622 AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_HOWL) 623 624#define AR_SREV_OWL_22_OR_LATER(_ah) \ 625 ((AR_SREV_OWL(_ah) && \ 626 AH_PRIVATE((_ah))->ah_macRev >= AR_SREV_REVISION_OWL_22) || \ 627 AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_HOWL) 628 629/* Howl (AR9130) */ 630 631#define AR_SREV_HOWL(_ah) \ 632 (AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_HOWL) 633 634#define AR_SREV_9100(_ah) AR_SREV_HOWL(_ah) 635 636/* Sowl (AR9160) */ 637 638#define AR_SREV_SOWL(_ah) \ 639 (AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_SOWL) 640 641#define AR_SREV_SOWL_10_OR_LATER(_ah) \ 642 (AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_SOWL) 643 644#define AR_SREV_SOWL_11(_ah) \ 645 (AR_SREV_SOWL(_ah) && \ 646 AH_PRIVATE((_ah))->ah_macRev == AR_XSREV_REVISION_SOWL_11) 647 648/* Merlin (AR9280) */ 649 650#define AR_SREV_MERLIN(_ah) \ 651 (AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_MERLIN) 652 653#define AR_SREV_MERLIN_10_OR_LATER(_ah) \ 654 (AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_MERLIN) 655 656#define AR_SREV_MERLIN_20(_ah) \ 657 (AR_SREV_MERLIN(_ah) && \ 658 AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_MERLIN_20) 659 660#define AR_SREV_MERLIN_20_OR_LATER(_ah) \ 661 ((AH_PRIVATE((_ah))->ah_macVersion > AR_XSREV_VERSION_MERLIN) || \ 662 (AR_SREV_MERLIN((_ah)) && \ 663 AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_MERLIN_20)) 664 665/* Kite (AR9285) */ 666 667#define AR_SREV_KITE(_ah) \ 668 (AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_KITE) 669 670#define AR_SREV_KITE_10_OR_LATER(_ah) \ 671 (AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_KITE) 672 673#define AR_SREV_KITE_11(_ah) \ 674 (AR_SREV_KITE(ah) && \ 675 AH_PRIVATE((_ah))->ah_macRev == AR_XSREV_REVISION_KITE_11) 676 677#define AR_SREV_KITE_11_OR_LATER(_ah) \ 678 ((AH_PRIVATE((_ah))->ah_macVersion > AR_XSREV_VERSION_KITE) || \ 679 (AR_SREV_KITE((_ah)) && \ 680 AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_KITE_11)) 681 682#define AR_SREV_KITE_12(_ah) \ 683 (AR_SREV_KITE(ah) && \ 684 AH_PRIVATE((_ah))->ah_macRev == AR_XSREV_REVISION_KITE_12) 685 686#define AR_SREV_KITE_12_OR_LATER(_ah) \ 687 ((AH_PRIVATE((_ah))->ah_macVersion > AR_XSREV_VERSION_KITE) || \ 688 (AR_SREV_KITE((_ah)) && \ 689 AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_KITE_12)) 690 691#define AR_SREV_9285E_20(_ah) \ 692 (AR_SREV_KITE_12_OR_LATER(_ah) && \ 693 ((OS_REG_READ(_ah, AR_AN_SYNTH9) & 0x7) == 0x1)) 694 695#define AR_SREV_KIWI(_ah) \ 696 (AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_KIWI) 697 698#define AR_SREV_KIWI_11_OR_LATER(_ah) \ 699 (AR_SREV_KIWI(_ah) && \ 700 AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_KIWI_11) 701 702#define AR_SREV_KIWI_11(_ah) \ 703 (AR_SREV_KIWI(_ah) && \ 704 AH_PRIVATE((_ah))->ah_macRev == AR_XSREV_REVISION_KIWI_11) 705 706#define AR_SREV_KIWI_12(_ah) \ 707 (AR_SREV_KIWI(_ah) && \ 708 AH_PRIVATE((_ah))->ah_macRev == AR_XSREV_REVISION_KIWI_12) 709 710#define AR_SREV_KIWI_12_OR_LATER(_ah) \ 711 (AR_SREV_KIWI(_ah) && \ 712 AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_KIWI_12) 713 714#define AR_SREV_KIWI_13_OR_LATER(_ah) \ 715 (AR_SREV_KIWI(_ah) && \ 716 AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_KIWI_13) 717 718 719/* Not yet implemented chips */ 720#define AR_SREV_9271(_ah) 0 721 722#endif /* _DEV_ATH_AR5416REG_H */ 723