ar5416reg.h revision 221163
1185377Ssam/* 2185377Ssam * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3185377Ssam * Copyright (c) 2002-2008 Atheros Communications, Inc. 4185377Ssam * 5185377Ssam * Permission to use, copy, modify, and/or distribute this software for any 6185377Ssam * purpose with or without fee is hereby granted, provided that the above 7185377Ssam * copyright notice and this permission notice appear in all copies. 8185377Ssam * 9185377Ssam * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10185377Ssam * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11185377Ssam * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12185377Ssam * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13185377Ssam * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14185377Ssam * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15185377Ssam * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16185377Ssam * 17188968Ssam * $FreeBSD: head/sys/dev/ath/ath_hal/ar5416/ar5416reg.h 221163 2011-04-28 12:47:40Z adrian $ 18185377Ssam */ 19185377Ssam#ifndef _DEV_ATH_AR5416REG_H 20185377Ssam#define _DEV_ATH_AR5416REG_H 21185377Ssam 22188968Ssam#include <dev/ath/ath_hal/ar5212/ar5212reg.h> 23185377Ssam 24185377Ssam/* 25185377Ssam * Register added starting with the AR5416 26185377Ssam */ 27185377Ssam#define AR_MIRT 0x0020 /* interrupt rate threshold */ 28185377Ssam#define AR_TIMT 0x0028 /* Tx Interrupt mitigation threshold */ 29185377Ssam#define AR_RIMT 0x002C /* Rx Interrupt mitigation threshold */ 30185377Ssam#define AR_GTXTO 0x0064 /* global transmit timeout */ 31185377Ssam#define AR_GTTM 0x0068 /* global transmit timeout mode */ 32185377Ssam#define AR_CST 0x006C /* carrier sense timeout */ 33185377Ssam#define AR_MAC_LED 0x1f04 /* LED control */ 34188979Ssam#define AR_WA 0x4004 /* PCIE work-arounds */ 35188979Ssam#define AR_PCIE_PM_CTRL 0x4014 36185377Ssam#define AR_AHB_MODE 0x4024 /* AHB mode for dma */ 37185377Ssam#define AR_INTR_SYNC_CAUSE_CLR 0x4028 /* clear interrupt */ 38185377Ssam#define AR_INTR_SYNC_CAUSE 0x4028 /* check pending interrupts */ 39185377Ssam#define AR_INTR_SYNC_ENABLE 0x402c /* enable interrupts */ 40185377Ssam#define AR_INTR_ASYNC_MASK 0x4030 /* asynchronous interrupt mask */ 41185377Ssam#define AR_INTR_SYNC_MASK 0x4034 /* synchronous interrupt mask */ 42185377Ssam#define AR_INTR_ASYNC_CAUSE 0x4038 /* check pending interrupts */ 43185377Ssam#define AR_INTR_ASYNC_ENABLE 0x403c /* enable interrupts */ 44185377Ssam#define AR5416_PCIE_SERDES 0x4040 45185377Ssam#define AR5416_PCIE_SERDES2 0x4044 46188976Ssam#define AR_GPIO_IN_OUT 0x4048 /* GPIO input/output register */ 47188976Ssam#define AR_GPIO_OE_OUT 0x404c /* GPIO output enable register */ 48188976Ssam#define AR_GPIO_INTR_POL 0x4050 /* GPIO interrupt polarity */ 49188976Ssam#define AR_GPIO_INPUT_EN_VAL 0x4054 /* GPIO input enable and value */ 50188976Ssam#define AR_GPIO_INPUT_MUX1 0x4058 51188976Ssam#define AR_GPIO_INPUT_MUX2 0x405c 52188976Ssam#define AR_GPIO_OUTPUT_MUX1 0x4060 53188976Ssam#define AR_GPIO_OUTPUT_MUX2 0x4064 54188976Ssam#define AR_GPIO_OUTPUT_MUX3 0x4068 55185377Ssam#define AR_EEPROM_STATUS_DATA 0x407c 56185377Ssam#define AR_OBS 0x4080 57221163Sadrian 58221163Sadrian#ifdef AH_SUPPORT_AR9130 59221163Sadrian#define AR_RTC_BASE 0x20000 60221163Sadrian#else 61221163Sadrian#define AR_RTC_BASE 0x7000 62221163Sadrian#endif /* AH_SUPPORT_AR9130 */ 63221163Sadrian 64221163Sadrian#define AR_RTC_RC AR_RTC_BASE + 0x00 /* reset control */ 65221163Sadrian#define AR_RTC_PLL_CONTROL AR_RTC_BASE + 0x14 66221163Sadrian#define AR_RTC_RESET AR_RTC_BASE + 0x40 /* RTC reset register */ 67221163Sadrian#define AR_RTC_STATUS AR_RTC_BASE + 0x44 /* system sleep status */ 68221163Sadrian#define AR_RTC_SLEEP_CLK AR_RTC_BASE + 0x48 69221163Sadrian#define AR_RTC_FORCE_WAKE AR_RTC_BASE + 0x4c /* control MAC force wake */ 70221163Sadrian#define AR_RTC_INTR_CAUSE AR_RTC_BASE + 0x50 /* RTC interrupt cause/clear */ 71221163Sadrian#define AR_RTC_INTR_ENABLE AR_RTC_BASE + 0x54 /* RTC interrupt enable */ 72221163Sadrian#define AR_RTC_INTR_MASK AR_RTC_BASE + 0x58 /* RTC interrupt mask */ 73221163Sadrian 74221163Sadrian#ifdef AH_SUPPORT_AR9130 75221163Sadrian/* RTC_DERIVED_* - only for AR9130 */ 76221163Sadrian#define AR_RTC_DERIVED_CLK (AR_RTC_BASE + 0x0038) 77221163Sadrian#define AR_RTC_DERIVED_CLK_PERIOD 0x0000fffe 78221163Sadrian#define AR_RTC_DERIVED_CLK_PERIOD_S 1 79221163Sadrian#endif /* AH_SUPPORT_AR9130 */ 80221163Sadrian 81185377Ssam/* AR9280: rf long shift registers */ 82185377Ssam#define AR_AN_RF2G1_CH0 0x7810 83185377Ssam#define AR_AN_RF5G1_CH0 0x7818 84185377Ssam#define AR_AN_RF2G1_CH1 0x7834 85185377Ssam#define AR_AN_RF5G1_CH1 0x783C 86185377Ssam#define AR_AN_TOP2 0x7894 87185377Ssam#define AR_AN_SYNTH9 0x7868 88203159Srpaulo#define AR9285_AN_RF2G1 0x7820 89203159Srpaulo#define AR9285_AN_RF2G2 0x7824 90203159Srpaulo#define AR9285_AN_RF2G3 0x7828 91203159Srpaulo#define AR9285_AN_RF2G4 0x782C 92203159Srpaulo#define AR9285_AN_RF2G6 0x7834 93203159Srpaulo#define AR9285_AN_RF2G7 0x7838 94203159Srpaulo#define AR9285_AN_RF2G8 0x783C 95203159Srpaulo#define AR9285_AN_RF2G9 0x7840 96203159Srpaulo#define AR9285_AN_RXTXBB1 0x7854 97203159Srpaulo#define AR9285_AN_TOP2 0x7868 98185377Ssam#define AR9285_AN_TOP3 0x786c 99203159Srpaulo#define AR9285_AN_TOP4 0x7870 100203159Srpaulo#define AR9285_AN_TOP4_DEFAULT 0x10142c00 101203159Srpaulo 102185377Ssam#define AR_RESET_TSF 0x8020 103185377Ssam#define AR_RXFIFO_CFG 0x8114 104185377Ssam#define AR_PHY_ERR_1 0x812c 105185377Ssam#define AR_PHY_ERR_MASK_1 0x8130 /* mask for AR_PHY_ERR_1 */ 106185377Ssam#define AR_PHY_ERR_2 0x8134 107185377Ssam#define AR_PHY_ERR_MASK_2 0x8138 /* mask for AR_PHY_ERR_2 */ 108185377Ssam#define AR_TSFOOR_THRESHOLD 0x813c 109185377Ssam#define AR_PHY_ERR_3 0x8168 110185377Ssam#define AR_PHY_ERR_MASK_3 0x816c /* mask for AR_PHY_ERR_3 */ 111185377Ssam#define AR_TXOP_X 0x81ec /* txop for legacy non-qos */ 112185377Ssam#define AR_TXOP_0_3 0x81f0 /* txop for various tid's */ 113185377Ssam#define AR_TXOP_4_7 0x81f4 114185377Ssam#define AR_TXOP_8_11 0x81f8 115185377Ssam#define AR_TXOP_12_15 0x81fc 116185377Ssam/* generic timers based on tsf - all uS */ 117185377Ssam#define AR_NEXT_TBTT 0x8200 118185377Ssam#define AR_NEXT_DBA 0x8204 119185377Ssam#define AR_NEXT_SWBA 0x8208 120185377Ssam#define AR_NEXT_CFP 0x8208 121185377Ssam#define AR_NEXT_HCF 0x820C 122185377Ssam#define AR_NEXT_TIM 0x8210 123185377Ssam#define AR_NEXT_DTIM 0x8214 124185377Ssam#define AR_NEXT_QUIET 0x8218 125185377Ssam#define AR_NEXT_NDP 0x821C 126185377Ssam#define AR5416_BEACON_PERIOD 0x8220 127185377Ssam#define AR_DBA_PERIOD 0x8224 128185377Ssam#define AR_SWBA_PERIOD 0x8228 129185377Ssam#define AR_HCF_PERIOD 0x822C 130185377Ssam#define AR_TIM_PERIOD 0x8230 131185377Ssam#define AR_DTIM_PERIOD 0x8234 132185377Ssam#define AR_QUIET_PERIOD 0x8238 133185377Ssam#define AR_NDP_PERIOD 0x823C 134185377Ssam#define AR_TIMER_MODE 0x8240 135185377Ssam#define AR_SLP32_MODE 0x8244 136185377Ssam#define AR_SLP32_WAKE 0x8248 137185377Ssam#define AR_SLP32_INC 0x824c 138185377Ssam#define AR_SLP_CNT 0x8250 /* 32kHz cycles with mac asleep */ 139185377Ssam#define AR_SLP_CYCLE_CNT 0x8254 /* absolute number of 32kHz cycles */ 140185377Ssam#define AR_SLP_MIB_CTRL 0x8258 141185377Ssam#define AR_2040_MODE 0x8318 142185377Ssam#define AR_EXTRCCNT 0x8328 /* extension channel rx clear count */ 143185377Ssam#define AR_SELFGEN_MASK 0x832c /* rx and cal chain masks */ 144185377Ssam#define AR_PCU_TXBUF_CTRL 0x8340 145208711Srpaulo#define AR_PCU_MISC_MODE2 0x8344 146185377Ssam 147185377Ssam/* DMA & PCI Registers in PCI space (usable during sleep)*/ 148185377Ssam#define AR_RC_AHB 0x00000001 /* AHB reset */ 149185377Ssam#define AR_RC_APB 0x00000002 /* APB reset */ 150185377Ssam#define AR_RC_HOSTIF 0x00000100 /* host interface reset */ 151185377Ssam 152185377Ssam#define AR_MIRT_VAL 0x0000ffff /* in uS */ 153185377Ssam#define AR_MIRT_VAL_S 16 154185377Ssam 155185377Ssam#define AR_TIMT_LAST 0x0000ffff /* Last packet threshold */ 156185377Ssam#define AR_TIMT_LAST_S 0 157185377Ssam#define AR_TIMT_FIRST 0xffff0000 /* First packet threshold */ 158185377Ssam#define AR_TIMT_FIRST_S 16 159185377Ssam 160185377Ssam#define AR_RIMT_LAST 0x0000ffff /* Last packet threshold */ 161185377Ssam#define AR_RIMT_LAST_S 0 162185377Ssam#define AR_RIMT_FIRST 0xffff0000 /* First packet threshold */ 163185377Ssam#define AR_RIMT_FIRST_S 16 164185377Ssam 165185377Ssam#define AR_GTXTO_TIMEOUT_COUNTER 0x0000FFFF // Mask for timeout counter (in TUs) 166185377Ssam#define AR_GTXTO_TIMEOUT_LIMIT 0xFFFF0000 // Mask for timeout limit (in TUs) 167185377Ssam#define AR_GTXTO_TIMEOUT_LIMIT_S 16 // Shift for timeout limit 168185377Ssam 169185377Ssam#define AR_GTTM_USEC 0x00000001 // usec strobe 170185377Ssam#define AR_GTTM_IGNORE_IDLE 0x00000002 // ignore channel idle 171185377Ssam#define AR_GTTM_RESET_IDLE 0x00000004 // reset counter on channel idle low 172185377Ssam#define AR_GTTM_CST_USEC 0x00000008 // CST usec strobe 173185377Ssam 174185377Ssam#define AR_CST_TIMEOUT_COUNTER 0x0000FFFF // Mask for timeout counter (in TUs) 175185377Ssam#define AR_CST_TIMEOUT_LIMIT 0xFFFF0000 // Mask for timeout limit (in TUs) 176185377Ssam#define AR_CST_TIMEOUT_LIMIT_S 16 // Shift for timeout limit 177185377Ssam 178185377Ssam/* MAC tx DMA size config */ 179185377Ssam#define AR_TXCFG_DMASZ_MASK 0x00000003 180185377Ssam#define AR_TXCFG_DMASZ_4B 0 181185377Ssam#define AR_TXCFG_DMASZ_8B 1 182185377Ssam#define AR_TXCFG_DMASZ_16B 2 183185377Ssam#define AR_TXCFG_DMASZ_32B 3 184185377Ssam#define AR_TXCFG_DMASZ_64B 4 185185377Ssam#define AR_TXCFG_DMASZ_128B 5 186185377Ssam#define AR_TXCFG_DMASZ_256B 6 187185377Ssam#define AR_TXCFG_DMASZ_512B 7 188185377Ssam#define AR_TXCFG_ATIM_TXPOLICY 0x00000800 189185377Ssam 190185377Ssam/* MAC rx DMA size config */ 191185377Ssam#define AR_RXCFG_DMASZ_MASK 0x00000007 192185377Ssam#define AR_RXCFG_DMASZ_4B 0 193185377Ssam#define AR_RXCFG_DMASZ_8B 1 194185377Ssam#define AR_RXCFG_DMASZ_16B 2 195185377Ssam#define AR_RXCFG_DMASZ_32B 3 196185377Ssam#define AR_RXCFG_DMASZ_64B 4 197185377Ssam#define AR_RXCFG_DMASZ_128B 5 198185377Ssam#define AR_RXCFG_DMASZ_256B 6 199185377Ssam#define AR_RXCFG_DMASZ_512B 7 200185377Ssam 201185377Ssam/* MAC Led registers */ 202185377Ssam#define AR_MAC_LED_BLINK_SLOW 0x00000008 /* LED slowest blink rate mode */ 203185377Ssam#define AR_MAC_LED_BLINK_THRESH_SEL 0x00000070 /* LED blink threshold select */ 204185377Ssam#define AR_MAC_LED_MODE 0x00000380 /* LED mode select */ 205185377Ssam#define AR_MAC_LED_MODE_S 7 206185377Ssam#define AR_MAC_LED_MODE_PROP 0 /* Blink prop to filtered tx/rx */ 207185377Ssam#define AR_MAC_LED_MODE_RPROP 1 /* Blink prop to unfiltered tx/rx */ 208185377Ssam#define AR_MAC_LED_MODE_SPLIT 2 /* Blink power for tx/net for rx */ 209185377Ssam#define AR_MAC_LED_MODE_RAND 3 /* Blink randomly */ 210185377Ssam#define AR_MAC_LED_MODE_POWON 5 /* Power LED on (s/w control) */ 211185377Ssam#define AR_MAC_LED_MODE_NETON 6 /* Network LED on (s/w control) */ 212185377Ssam#define AR_MAC_LED_ASSOC 0x00000c00 213185377Ssam#define AR_MAC_LED_ASSOC_NONE 0x00000000 /* STA is not associated or trying */ 214185377Ssam#define AR_MAC_LED_ASSOC_ACTIVE 0x00000400 /* STA is associated */ 215185377Ssam#define AR_MAC_LED_ASSOC_PEND 0x00000800 /* STA is trying to associate */ 216185377Ssam#define AR_MAC_LED_ASSOC_S 10 217185377Ssam 218188979Ssam#define AR_WA_UNTIE_RESET_EN 0x00008000 /* ena PCI reset to POR */ 219188979Ssam#define AR_WA_RESET_EN 0x00040000 /* ena AR_WA_UNTIE_RESET_EN */ 220188979Ssam#define AR_WA_ANALOG_SHIFT 0x00100000 221188979Ssam#define AR_WA_POR_SHORT 0x00200000 /* PCIE phy reset control */ 222188979Ssam 223188979Ssam#define AR_WA_DEFAULT 0x0000073f 224188979Ssam#define AR9280_WA_DEFAULT 0x0040073f 225188979Ssam#define AR9285_WA_DEFAULT 0x004a05cb 226188979Ssam 227188979Ssam#define AR_PCIE_PM_CTRL_ENA 0x00080000 228188979Ssam 229185377Ssam#define AR_AHB_EXACT_WR_EN 0x00000000 /* write exact bytes */ 230185377Ssam#define AR_AHB_BUF_WR_EN 0x00000001 /* buffer write upto cacheline*/ 231185377Ssam#define AR_AHB_EXACT_RD_EN 0x00000000 /* read exact bytes */ 232185377Ssam#define AR_AHB_CACHELINE_RD_EN 0x00000002 /* read upto end of cacheline */ 233185377Ssam#define AR_AHB_PREFETCH_RD_EN 0x00000004 /* prefetch upto page boundary*/ 234185377Ssam#define AR_AHB_PAGE_SIZE_1K 0x00000000 /* set page-size as 1k */ 235185377Ssam#define AR_AHB_PAGE_SIZE_2K 0x00000008 /* set page-size as 2k */ 236185377Ssam#define AR_AHB_PAGE_SIZE_4K 0x00000010 /* set page-size as 4k */ 237185377Ssam 238185377Ssam/* MAC PCU Registers */ 239185377Ssam#define AR_STA_ID1_PRESERVE_SEQNUM 0x20000000 /* Don't replace seq num */ 240185377Ssam 241185377Ssam/* Extended PCU DIAG_SW control fields */ 242185377Ssam#define AR_DIAG_DUAL_CHAIN_INFO 0x01000000 /* dual chain channel info */ 243185377Ssam#define AR_DIAG_RX_ABORT 0x02000000 /* abort rx */ 244185377Ssam#define AR_DIAG_SATURATE_CCNT 0x04000000 /* sat. cycle cnts (no shift) */ 245185377Ssam#define AR_DIAG_OBS_PT_SEL2 0x08000000 /* observation point sel */ 246185377Ssam#define AR_DIAG_RXCLEAR_CTL_LOW 0x10000000 /* force rx_clear(ctl) low/busy */ 247185377Ssam#define AR_DIAG_RXCLEAR_EXT_LOW 0x20000000 /* force rx_clear(ext) low/busy */ 248185377Ssam 249185377Ssam#define AR_TXOP_X_VAL 0x000000FF 250185377Ssam 251185377Ssam#define AR_RESET_TSF_ONCE 0x01000000 /* reset tsf once; self-clears*/ 252185377Ssam 253185377Ssam/* Interrupts */ 254185377Ssam#define AR_ISR_TXMINTR 0x00080000 /* Maximum interrupt tx rate */ 255185377Ssam#define AR_ISR_RXMINTR 0x01000000 /* Maximum interrupt rx rate */ 256185377Ssam#define AR_ISR_TXINTM 0x40000000 /* Tx int after mitigation */ 257185377Ssam#define AR_ISR_RXINTM 0x80000000 /* Rx int after mitigation */ 258185377Ssam 259185377Ssam#define AR_ISR_S2_CST 0x00400000 /* Carrier sense timeout */ 260185377Ssam#define AR_ISR_S2_GTT 0x00800000 /* Global transmit timeout */ 261185377Ssam#define AR_ISR_S2_TSFOOR 0x40000000 /* RX TSF out of range */ 262185377Ssam 263208711Srpaulo#define AR_ISR_S5 0x0098 264208711Srpaulo#define AR_ISR_S5_S 0x00d8 265208711Srpaulo#define AR_ISR_S5_TIM_TIMER 0x00000010 266208711Srpaulo 267185377Ssam#define AR_INTR_SPURIOUS 0xffffffff 268185377Ssam#define AR_INTR_RTC_IRQ 0x00000001 /* rtc in shutdown state */ 269185377Ssam#define AR_INTR_MAC_IRQ 0x00000002 /* pending mac interrupt */ 270185377Ssam#define AR_INTR_EEP_PROT_ACCESS 0x00000004 /* eeprom protected access */ 271185377Ssam#define AR_INTR_MAC_AWAKE 0x00020000 /* mac is awake */ 272185377Ssam#define AR_INTR_MAC_ASLEEP 0x00040000 /* mac is asleep */ 273185377Ssam 274185377Ssam/* Interrupt Mask Registers */ 275185377Ssam#define AR_IMR_TXMINTR 0x00080000 /* Maximum interrupt tx rate */ 276185377Ssam#define AR_IMR_RXMINTR 0x01000000 /* Maximum interrupt rx rate */ 277185377Ssam#define AR_IMR_TXINTM 0x40000000 /* Tx int after mitigation */ 278185377Ssam#define AR_IMR_RXINTM 0x80000000 /* Rx int after mitigation */ 279185377Ssam 280185377Ssam#define AR_IMR_S2_CST 0x00400000 /* Carrier sense timeout */ 281185377Ssam#define AR_IMR_S2_GTT 0x00800000 /* Global transmit timeout */ 282185377Ssam 283185377Ssam/* synchronous interrupt signals */ 284185377Ssam#define AR_INTR_SYNC_RTC_IRQ 0x00000001 285185377Ssam#define AR_INTR_SYNC_MAC_IRQ 0x00000002 286185377Ssam#define AR_INTR_SYNC_EEPROM_ILLEGAL_ACCESS 0x00000004 287185377Ssam#define AR_INTR_SYNC_APB_TIMEOUT 0x00000008 288185377Ssam#define AR_INTR_SYNC_PCI_MODE_CONFLICT 0x00000010 289185377Ssam#define AR_INTR_SYNC_HOST1_FATAL 0x00000020 290185377Ssam#define AR_INTR_SYNC_HOST1_PERR 0x00000040 291185377Ssam#define AR_INTR_SYNC_TRCV_FIFO_PERR 0x00000080 292185377Ssam#define AR_INTR_SYNC_RADM_CPL_EP 0x00000100 293185377Ssam#define AR_INTR_SYNC_RADM_CPL_DLLP_ABORT 0x00000200 294185377Ssam#define AR_INTR_SYNC_RADM_CPL_TLP_ABORT 0x00000400 295185377Ssam#define AR_INTR_SYNC_RADM_CPL_ECRC_ERR 0x00000800 296185377Ssam#define AR_INTR_SYNC_RADM_CPL_TIMEOUT 0x00001000 297185377Ssam#define AR_INTR_SYNC_LOCAL_TIMEOUT 0x00002000 298185377Ssam#define AR_INTR_SYNC_PM_ACCESS 0x00004000 299185377Ssam#define AR_INTR_SYNC_MAC_AWAKE 0x00008000 300185377Ssam#define AR_INTR_SYNC_MAC_ASLEEP 0x00010000 301185377Ssam#define AR_INTR_SYNC_MAC_SLEEP_ACCESS 0x00020000 302185377Ssam#define AR_INTR_SYNC_ALL 0x0003FFFF 303185377Ssam 304185377Ssam/* default synchronous interrupt signals enabled */ 305185377Ssam#define AR_INTR_SYNC_DEFAULT \ 306185377Ssam (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR | \ 307185377Ssam AR_INTR_SYNC_RADM_CPL_EP | AR_INTR_SYNC_RADM_CPL_DLLP_ABORT | \ 308185377Ssam AR_INTR_SYNC_RADM_CPL_TLP_ABORT | AR_INTR_SYNC_RADM_CPL_ECRC_ERR | \ 309185377Ssam AR_INTR_SYNC_RADM_CPL_TIMEOUT | AR_INTR_SYNC_LOCAL_TIMEOUT | \ 310185377Ssam AR_INTR_SYNC_MAC_SLEEP_ACCESS) 311185377Ssam 312188976Ssam#define AR_INTR_SYNC_MASK_GPIO 0xFFFC0000 313188976Ssam#define AR_INTR_SYNC_MASK_GPIO_S 18 314188976Ssam 315188976Ssam#define AR_INTR_SYNC_ENABLE_GPIO 0xFFFC0000 316188976Ssam#define AR_INTR_SYNC_ENABLE_GPIO_S 18 317188976Ssam 318188976Ssam#define AR_INTR_ASYNC_MASK_GPIO 0xFFFC0000 /* async int mask */ 319188976Ssam#define AR_INTR_ASYNC_MASK_GPIO_S 18 320188976Ssam 321188976Ssam#define AR_INTR_ASYNC_CAUSE_GPIO 0xFFFC0000 /* GPIO interrupts */ 322188976Ssam#define AR_INTR_ASYNC_USED (AR_INTR_MAC_IRQ | AR_INTR_ASYNC_CAUSE_GPIO) 323188976Ssam 324188976Ssam#define AR_INTR_ASYNC_ENABLE_GPIO 0xFFFC0000 /* enable interrupts */ 325188976Ssam#define AR_INTR_ASYNC_ENABLE_GPIO_S 18 326188976Ssam 327185377Ssam/* RTC registers */ 328185377Ssam#define AR_RTC_RC_M 0x00000003 329185377Ssam#define AR_RTC_RC_MAC_WARM 0x00000001 330185377Ssam#define AR_RTC_RC_MAC_COLD 0x00000002 331221163Sadrian#ifdef AH_SUPPORT_AR9130 332221163Sadrian#define AR_RTC_RC_COLD_RESET 0x00000004 333221163Sadrian#define AR_RTC_RC_WARM_RESET 0x00000008 334221163Sadrian#endif /* AH_SUPPORT_AR9130 */ 335185377Ssam#define AR_RTC_PLL_DIV 0x0000001f 336185377Ssam#define AR_RTC_PLL_DIV_S 0 337185377Ssam#define AR_RTC_PLL_DIV2 0x00000020 338185377Ssam#define AR_RTC_PLL_REFDIV_5 0x000000c0 339185377Ssam 340185377Ssam#define AR_RTC_SOWL_PLL_DIV 0x000003ff 341185377Ssam#define AR_RTC_SOWL_PLL_DIV_S 0 342185377Ssam#define AR_RTC_SOWL_PLL_REFDIV 0x00003C00 343185377Ssam#define AR_RTC_SOWL_PLL_REFDIV_S 10 344185377Ssam#define AR_RTC_SOWL_PLL_CLKSEL 0x0000C000 345185377Ssam#define AR_RTC_SOWL_PLL_CLKSEL_S 14 346185377Ssam 347185377Ssam#define AR_RTC_RESET_EN 0x00000001 /* Reset RTC bit */ 348185377Ssam 349185377Ssam#define AR_RTC_PM_STATUS_M 0x0000000f /* Pwr Mgmt Status */ 350221163Sadrian#ifdef AH_SUPPORT_AR9130 351221163Sadrian#define AR_RTC_STATUS_M 0x0000000f /* RTC Status */ 352221163Sadrian#else 353185377Ssam#define AR_RTC_STATUS_M 0x0000003f /* RTC Status */ 354221163Sadrian#endif /* AH_SUPPORT_AR9130 */ 355185377Ssam#define AR_RTC_STATUS_SHUTDOWN 0x00000001 356185377Ssam#define AR_RTC_STATUS_ON 0x00000002 357185377Ssam#define AR_RTC_STATUS_SLEEP 0x00000004 358185377Ssam#define AR_RTC_STATUS_WAKEUP 0x00000008 359185377Ssam#define AR_RTC_STATUS_COLDRESET 0x00000010 /* Not currently used */ 360185377Ssam#define AR_RTC_STATUS_PLLCHANGE 0x00000020 /* Not currently used */ 361185377Ssam 362185377Ssam#define AR_RTC_SLEEP_DERIVED_CLK 0x2 363185377Ssam 364185377Ssam#define AR_RTC_FORCE_WAKE_EN 0x00000001 /* enable force wake */ 365185377Ssam#define AR_RTC_FORCE_WAKE_ON_INT 0x00000002 /* auto-wake on MAC interrupt */ 366185377Ssam 367185377Ssam#define AR_RTC_PLL_CLKSEL 0x00000300 368185377Ssam#define AR_RTC_PLL_CLKSEL_S 8 369185377Ssam 370185377Ssam/* AR9280: rf long shift registers */ 371185377Ssam#define AR_AN_RF2G1_CH0_OB 0x03800000 372185377Ssam#define AR_AN_RF2G1_CH0_OB_S 23 373185377Ssam#define AR_AN_RF2G1_CH0_DB 0x1C000000 374185377Ssam#define AR_AN_RF2G1_CH0_DB_S 26 375185377Ssam 376185377Ssam#define AR_AN_RF5G1_CH0_OB5 0x00070000 377185377Ssam#define AR_AN_RF5G1_CH0_OB5_S 16 378185377Ssam#define AR_AN_RF5G1_CH0_DB5 0x00380000 379185377Ssam#define AR_AN_RF5G1_CH0_DB5_S 19 380185377Ssam 381185377Ssam#define AR_AN_RF2G1_CH1_OB 0x03800000 382185377Ssam#define AR_AN_RF2G1_CH1_OB_S 23 383185377Ssam#define AR_AN_RF2G1_CH1_DB 0x1C000000 384185377Ssam#define AR_AN_RF2G1_CH1_DB_S 26 385185377Ssam 386185377Ssam#define AR_AN_RF5G1_CH1_OB5 0x00070000 387185377Ssam#define AR_AN_RF5G1_CH1_OB5_S 16 388185377Ssam#define AR_AN_RF5G1_CH1_DB5 0x00380000 389185377Ssam#define AR_AN_RF5G1_CH1_DB5_S 19 390185377Ssam 391218420Sadrian#define AR_AN_TOP1 0x7890 392218420Sadrian#define AR_AN_TOP1_DACIPMODE 0x00040000 393218420Sadrian#define AR_AN_TOP1_DACIPMODE_S 18 394218420Sadrian 395185377Ssam#define AR_AN_TOP2_XPABIAS_LVL 0xC0000000 396185377Ssam#define AR_AN_TOP2_XPABIAS_LVL_S 30 397185377Ssam#define AR_AN_TOP2_LOCALBIAS 0x00200000 398185377Ssam#define AR_AN_TOP2_LOCALBIAS_S 21 399185377Ssam#define AR_AN_TOP2_PWDCLKIND 0x00400000 400185377Ssam#define AR_AN_TOP2_PWDCLKIND_S 22 401185377Ssam 402185377Ssam#define AR_AN_SYNTH9_REFDIVA 0xf8000000 403185377Ssam#define AR_AN_SYNTH9_REFDIVA_S 27 404185377Ssam 405185377Ssam/* AR9285 Analog registers */ 406203159Srpaulo#define AR9285_AN_RF2G1_ENPACAL 0x00000800 407203159Srpaulo#define AR9285_AN_RF2G1_ENPACAL_S 11 408203159Srpaulo#define AR9285_AN_RF2G1_PDPADRV1 0x02000000 409203159Srpaulo#define AR9285_AN_RF2G1_PDPADRV1_S 25 410203159Srpaulo#define AR9285_AN_RF2G1_PDPADRV2 0x01000000 411203159Srpaulo#define AR9285_AN_RF2G1_PDPADRV2_S 24 412203159Srpaulo#define AR9285_AN_RF2G1_PDPAOUT 0x00800000 413203159Srpaulo#define AR9285_AN_RF2G1_PDPAOUT_S 23 414185377Ssam 415203159Srpaulo#define AR9285_AN_RF2G2_OFFCAL 0x00001000 416203159Srpaulo#define AR9285_AN_RF2G2_OFFCAL_S 12 417185377Ssam 418203159Srpaulo#define AR9285_AN_RF2G3_PDVCCOMP 0x02000000 419203159Srpaulo#define AR9285_AN_RF2G3_PDVCCOMP_S 25 420203159Srpaulo#define AR9285_AN_RF2G3_OB_0 0x00E00000 421203159Srpaulo#define AR9285_AN_RF2G3_OB_0_S 21 422203159Srpaulo#define AR9285_AN_RF2G3_OB_1 0x001C0000 423203159Srpaulo#define AR9285_AN_RF2G3_OB_1_S 18 424203159Srpaulo#define AR9285_AN_RF2G3_OB_2 0x00038000 425203159Srpaulo#define AR9285_AN_RF2G3_OB_2_S 15 426203159Srpaulo#define AR9285_AN_RF2G3_OB_3 0x00007000 427203159Srpaulo#define AR9285_AN_RF2G3_OB_3_S 12 428203159Srpaulo#define AR9285_AN_RF2G3_OB_4 0x00000E00 429203159Srpaulo#define AR9285_AN_RF2G3_OB_4_S 9 430185377Ssam 431203159Srpaulo#define AR9285_AN_RF2G3_DB1_0 0x000001C0 432203159Srpaulo#define AR9285_AN_RF2G3_DB1_0_S 6 433203159Srpaulo#define AR9285_AN_RF2G3_DB1_1 0x00000038 434203159Srpaulo#define AR9285_AN_RF2G3_DB1_1_S 3 435203159Srpaulo#define AR9285_AN_RF2G3_DB1_2 0x00000007 436203159Srpaulo#define AR9285_AN_RF2G3_DB1_2_S 0 437203159Srpaulo 438203159Srpaulo#define AR9285_AN_RF2G4_DB1_3 0xE0000000 439203159Srpaulo#define AR9285_AN_RF2G4_DB1_3_S 29 440203159Srpaulo#define AR9285_AN_RF2G4_DB1_4 0x1C000000 441203159Srpaulo#define AR9285_AN_RF2G4_DB1_4_S 26 442203159Srpaulo 443203159Srpaulo#define AR9285_AN_RF2G4_DB2_0 0x03800000 444203159Srpaulo#define AR9285_AN_RF2G4_DB2_0_S 23 445203159Srpaulo#define AR9285_AN_RF2G4_DB2_1 0x00700000 446203159Srpaulo#define AR9285_AN_RF2G4_DB2_1_S 20 447203159Srpaulo#define AR9285_AN_RF2G4_DB2_2 0x000E0000 448203159Srpaulo#define AR9285_AN_RF2G4_DB2_2_S 17 449203159Srpaulo#define AR9285_AN_RF2G4_DB2_3 0x0001C000 450203159Srpaulo#define AR9285_AN_RF2G4_DB2_3_S 14 451203159Srpaulo#define AR9285_AN_RF2G4_DB2_4 0x00003800 452203159Srpaulo#define AR9285_AN_RF2G4_DB2_4_S 11 453203159Srpaulo 454203159Srpaulo#define AR9285_AN_RF2G6_CCOMP 0x00007800 455203159Srpaulo#define AR9285_AN_RF2G6_CCOMP_S 11 456203159Srpaulo#define AR9285_AN_RF2G6_OFFS 0x03f00000 457203159Srpaulo#define AR9285_AN_RF2G6_OFFS_S 20 458203159Srpaulo 459203159Srpaulo#define AR9271_AN_RF2G6_OFFS 0x07f00000 460203159Srpaulo#define AR9271_AN_RF2G6_OFFS_S 20 461203159Srpaulo 462203159Srpaulo#define AR9285_AN_RF2G7_PWDDB 0x00000002 463203159Srpaulo#define AR9285_AN_RF2G7_PWDDB_S 1 464203159Srpaulo#define AR9285_AN_RF2G7_PADRVGN2TAB0 0xE0000000 465203159Srpaulo#define AR9285_AN_RF2G7_PADRVGN2TAB0_S 29 466203159Srpaulo 467203159Srpaulo#define AR9285_AN_RF2G8_PADRVGN2TAB0 0x0001C000 468203159Srpaulo#define AR9285_AN_RF2G8_PADRVGN2TAB0_S 14 469203159Srpaulo 470203159Srpaulo#define AR9285_AN_RXTXBB1_PDRXTXBB1 0x00000020 471203159Srpaulo#define AR9285_AN_RXTXBB1_PDRXTXBB1_S 5 472203159Srpaulo#define AR9285_AN_RXTXBB1_PDV2I 0x00000080 473203159Srpaulo#define AR9285_AN_RXTXBB1_PDV2I_S 7 474203159Srpaulo#define AR9285_AN_RXTXBB1_PDDACIF 0x00000100 475203159Srpaulo#define AR9285_AN_RXTXBB1_PDDACIF_S 8 476203159Srpaulo#define AR9285_AN_RXTXBB1_SPARE9 0x00000001 477203159Srpaulo#define AR9285_AN_RXTXBB1_SPARE9_S 0 478203159Srpaulo 479185377Ssam#define AR9285_AN_TOP3_XPABIAS_LVL 0x0000000C 480185377Ssam#define AR9285_AN_TOP3_XPABIAS_LVL_S 2 481203159Srpaulo#define AR9285_AN_TOP3_PWDDAC 0x00800000 482203159Srpaulo#define AR9285_AN_TOP3_PWDDAC_S 23 483185377Ssam 484185377Ssam/* Sleep control */ 485185377Ssam#define AR5416_SLEEP1_CAB_TIMEOUT 0xFFE00000 /* Cab timeout (TU) */ 486185377Ssam#define AR5416_SLEEP1_CAB_TIMEOUT_S 22 487185377Ssam 488185377Ssam#define AR5416_SLEEP2_BEACON_TIMEOUT 0xFFE00000 /* Beacon timeout (TU)*/ 489185377Ssam#define AR5416_SLEEP2_BEACON_TIMEOUT_S 22 490185377Ssam 491185377Ssam/* Sleep Registers */ 492185377Ssam#define AR_SLP32_HALFCLK_LATENCY 0x000FFFFF /* rising <-> falling edge */ 493185377Ssam#define AR_SLP32_ENA 0x00100000 494185377Ssam#define AR_SLP32_TSF_WRITE_STATUS 0x00200000 /* tsf update in progress */ 495185377Ssam 496185377Ssam#define AR_SLP32_WAKE_XTL_TIME 0x0000FFFF /* time to wake crystal */ 497185377Ssam 498185377Ssam#define AR_SLP32_TST_INC 0x000FFFFF 499185377Ssam 500185377Ssam#define AR_SLP_MIB_CLEAR 0x00000001 /* clear pending */ 501185377Ssam#define AR_SLP_MIB_PENDING 0x00000002 /* clear counters */ 502185377Ssam 503185377Ssam#define AR_TIMER_MODE_TBTT 0x00000001 504185377Ssam#define AR_TIMER_MODE_DBA 0x00000002 505185377Ssam#define AR_TIMER_MODE_SWBA 0x00000004 506185377Ssam#define AR_TIMER_MODE_HCF 0x00000008 507185377Ssam#define AR_TIMER_MODE_TIM 0x00000010 508185377Ssam#define AR_TIMER_MODE_DTIM 0x00000020 509185377Ssam#define AR_TIMER_MODE_QUIET 0x00000040 510185377Ssam#define AR_TIMER_MODE_NDP 0x00000080 511185377Ssam#define AR_TIMER_MODE_OVERFLOW_INDEX 0x00000700 512185377Ssam#define AR_TIMER_MODE_OVERFLOW_INDEX_S 8 513185377Ssam#define AR_TIMER_MODE_THRESH 0xFFFFF000 514185377Ssam#define AR_TIMER_MODE_THRESH_S 12 515185377Ssam 516185377Ssam/* PCU Misc modes */ 517185377Ssam#define AR_PCU_FORCE_BSSID_MATCH 0x00000001 /* force bssid to match */ 518185377Ssam#define AR_PCU_MIC_NEW_LOC_ENA 0x00000004 /* tx/rx mic keys together */ 519185377Ssam#define AR_PCU_TX_ADD_TSF 0x00000008 /* add tx_tsf + int_tsf */ 520185377Ssam#define AR_PCU_CCK_SIFS_MODE 0x00000010 /* assume 11b sifs */ 521185377Ssam#define AR_PCU_RX_ANT_UPDT 0x00000800 /* KC_RX_ANT_UPDATE */ 522185377Ssam#define AR_PCU_TXOP_TBTT_LIMIT_ENA 0x00001000 /* enforce txop / tbtt */ 523185377Ssam#define AR_PCU_MISS_BCN_IN_SLEEP 0x00004000 /* count bmiss's when sleeping */ 524185377Ssam#define AR_PCU_BUG_12306_FIX_ENA 0x00020000 /* use rx_clear to count sifs */ 525185377Ssam#define AR_PCU_FORCE_QUIET_COLL 0x00040000 /* kill xmit for channel change */ 526185377Ssam#define AR_PCU_TBTT_PROTECT 0x00200000 /* no xmit upto tbtt+20 uS */ 527185377Ssam#define AR_PCU_CLEAR_VMF 0x01000000 /* clear vmf mode (fast cc)*/ 528185377Ssam#define AR_PCU_CLEAR_BA_VALID 0x04000000 /* clear ba state */ 529185377Ssam 530219978Sadrian#define AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE 0x00000002 531219978Sadrian#define AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT 0x00000004 532208711Srpaulo#define AR_PCU_MISC_MODE2_HWWAR1 0x00100000 533219217Sadrian#define AR_PCU_MISC_MODE2_HWWAR2 0x02000000 534208711Srpaulo 535185377Ssam/* GPIO Interrupt */ 536185377Ssam#define AR_INTR_GPIO 0x3FF00000 /* gpio interrupted */ 537185377Ssam#define AR_INTR_GPIO_S 20 538185377Ssam 539185377Ssam#define AR_GPIO_OUT_CTRL 0x000003FF /* 0 = out, 1 = in */ 540185377Ssam#define AR_GPIO_OUT_VAL 0x000FFC00 541185377Ssam#define AR_GPIO_OUT_VAL_S 10 542185377Ssam#define AR_GPIO_INTR_CTRL 0x3FF00000 543185377Ssam#define AR_GPIO_INTR_CTRL_S 20 544185377Ssam 545188976Ssam#define AR_GPIO_IN_VAL 0x0FFFC000 /* pre-9280 */ 546188976Ssam#define AR_GPIO_IN_VAL_S 14 547188976Ssam#define AR928X_GPIO_IN_VAL 0x000FFC00 548188976Ssam#define AR928X_GPIO_IN_VAL_S 10 549188976Ssam#define AR9285_GPIO_IN_VAL 0x00FFF000 550188976Ssam#define AR9285_GPIO_IN_VAL_S 12 551188976Ssam 552188976Ssam#define AR_GPIO_OE_OUT_DRV 0x3 /* 2 bit mask shifted by 2*bitpos */ 553188976Ssam#define AR_GPIO_OE_OUT_DRV_NO 0x0 /* tristate */ 554188976Ssam#define AR_GPIO_OE_OUT_DRV_LOW 0x1 /* drive if low */ 555188976Ssam#define AR_GPIO_OE_OUT_DRV_HI 0x2 /* drive if high */ 556188976Ssam#define AR_GPIO_OE_OUT_DRV_ALL 0x3 /* drive always */ 557188976Ssam 558188976Ssam#define AR_GPIO_INTR_POL_VAL 0x1FFF 559188976Ssam#define AR_GPIO_INTR_POL_VAL_S 0 560188976Ssam 561208711Srpaulo#define AR_GPIO_JTAG_DISABLE 0x00020000 562208711Srpaulo 563185377Ssam#define AR_2040_JOINED_RX_CLEAR 0x00000001 /* use ctl + ext rx_clear for cca */ 564185377Ssam 565185377Ssam#define AR_PCU_TXBUF_CTRL_SIZE_MASK 0x7FF 566185377Ssam#define AR_PCU_TXBUF_CTRL_USABLE_SIZE 0x700 567203159Srpaulo#define AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE 0x380 568185377Ssam 569185377Ssam/* Eeprom defines */ 570185377Ssam#define AR_EEPROM_STATUS_DATA_VAL 0x0000ffff 571185377Ssam#define AR_EEPROM_STATUS_DATA_VAL_S 0 572185377Ssam#define AR_EEPROM_STATUS_DATA_BUSY 0x00010000 573185377Ssam#define AR_EEPROM_STATUS_DATA_BUSY_ACCESS 0x00020000 574185377Ssam#define AR_EEPROM_STATUS_DATA_PROT_ACCESS 0x00040000 575185377Ssam#define AR_EEPROM_STATUS_DATA_ABSENT_ACCESS 0x00080000 576185377Ssam 577185377Ssam#define AR_SREV_REVISION_OWL_10 0x08 578185377Ssam#define AR_SREV_REVISION_OWL_20 0x09 579185377Ssam#define AR_SREV_REVISION_OWL_22 0x0a 580185377Ssam 581185377Ssam#define AR_RAD5133_SREV_MAJOR 0xc0 /* Fowl: 2+5G/3x3 */ 582185377Ssam#define AR_RAD2133_SREV_MAJOR 0xd0 /* Fowl: 2G/3x3 */ 583185377Ssam#define AR_RAD5122_SREV_MAJOR 0xe0 /* Fowl: 5G/2x2 */ 584185377Ssam#define AR_RAD2122_SREV_MAJOR 0xf0 /* Fowl: 2+5G/2x2 */ 585185377Ssam 586185377Ssam/* Test macro for owl 1.0 */ 587185377Ssam#define IS_5416V1(_ah) ((_ah)->ah_macRev == AR_SREV_REVISION_OWL_10) 588185377Ssam#define IS_5416V2(_ah) ((_ah)->ah_macRev >= AR_SREV_REVISION_OWL_20) 589185377Ssam#define IS_5416V2_2(_ah) ((_ah)->ah_macRev == AR_SREV_REVISION_OWL_22) 590185377Ssam 591185377Ssam/* Expanded Mac Silicon Rev (16 bits starting with Sowl) */ 592185377Ssam#define AR_XSREV_ID 0xFFFFFFFF /* Chip ID */ 593185377Ssam#define AR_XSREV_ID_S 0 594185377Ssam#define AR_XSREV_VERSION 0xFFFC0000 /* Chip version */ 595185377Ssam#define AR_XSREV_VERSION_S 18 596185377Ssam#define AR_XSREV_TYPE 0x0003F000 /* Chip type */ 597185377Ssam#define AR_XSREV_TYPE_S 12 598185377Ssam#define AR_XSREV_TYPE_CHAIN 0x00001000 /* Chain Mode (1:3 chains, 599185377Ssam * 0:2 chains) */ 600185377Ssam#define AR_XSREV_TYPE_HOST_MODE 0x00002000 /* Host Mode (1:PCI, 0:PCIe) */ 601185377Ssam#define AR_XSREV_REVISION 0x00000F00 602185377Ssam#define AR_XSREV_REVISION_S 8 603185377Ssam 604185377Ssam#define AR_XSREV_VERSION_OWL_PCI 0x0D 605185377Ssam#define AR_XSREV_VERSION_OWL_PCIE 0x0C 606185377Ssam#define AR_XSREV_REVISION_OWL_10 0 /* Owl 1.0 */ 607185377Ssam#define AR_XSREV_REVISION_OWL_20 1 /* Owl 2.0/2.1 */ 608185377Ssam#define AR_XSREV_REVISION_OWL_22 2 /* Owl 2.2 */ 609219217Sadrian#define AR_XSREV_VERSION_HOWL 0x14 /* Howl (AR9130) */ 610221163Sadrian#define AR_XSREV_VERSION_SOWL 0x40 /* Sowl (AR9160) */ 611185377Ssam#define AR_XSREV_REVISION_SOWL_10 0 /* Sowl 1.0 */ 612185377Ssam#define AR_XSREV_REVISION_SOWL_11 1 /* Sowl 1.1 */ 613185377Ssam#define AR_XSREV_VERSION_MERLIN 0x80 /* Merlin Version */ 614185377Ssam#define AR_XSREV_REVISION_MERLIN_10 0 /* Merlin 1.0 */ 615185377Ssam#define AR_XSREV_REVISION_MERLIN_20 1 /* Merlin 2.0 */ 616185377Ssam#define AR_XSREV_REVISION_MERLIN_21 2 /* Merlin 2.1 */ 617185377Ssam#define AR_XSREV_VERSION_KITE 0xC0 /* Kite Version */ 618185377Ssam#define AR_XSREV_REVISION_KITE_10 0 /* Kite 1.0 */ 619203159Srpaulo#define AR_XSREV_REVISION_KITE_11 1 /* Kite 1.1 */ 620203159Srpaulo#define AR_XSREV_REVISION_KITE_12 2 /* Kite 1.2 */ 621185377Ssam 622217881Sadrian#define AR_SREV_OWL(_ah) \ 623217881Sadrian ((AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_OWL_PCI) || \ 624217881Sadrian (AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_OWL_PCIE)) 625217881Sadrian 626185377Ssam#define AR_SREV_OWL_20_OR_LATER(_ah) \ 627219217Sadrian ((AR_SREV_OWL(_ah) && AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_OWL_20) || \ 628219217Sadrian AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_HOWL) 629185377Ssam#define AR_SREV_OWL_22_OR_LATER(_ah) \ 630219217Sadrian ((AR_SREV_OWL(_ah) && AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_OWL_22) || \ 631219217Sadrian AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_HOWL) 632185377Ssam 633221163Sadrian#define AR_SREV_HOWL(_ah) \ 634221163Sadrian (AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_HOWL) 635221163Sadrian#define AR_SREV_9100(_ah) AR_SREV_HOWL(_ah) 636221163Sadrian 637185377Ssam#define AR_SREV_SOWL(_ah) \ 638185377Ssam (AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_SOWL) 639185377Ssam#define AR_SREV_SOWL_10_OR_LATER(_ah) \ 640185377Ssam (AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_SOWL) 641185377Ssam#define AR_SREV_SOWL_11(_ah) \ 642185377Ssam (AR_SREV_SOWL(_ah) && \ 643185377Ssam AH_PRIVATE((_ah))->ah_macRev == AR_XSREV_REVISION_SOWL_11) 644185377Ssam 645185377Ssam#define AR_SREV_MERLIN(_ah) \ 646185377Ssam (AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_MERLIN) 647185377Ssam#define AR_SREV_MERLIN_10_OR_LATER(_ah) \ 648185377Ssam (AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_MERLIN) 649185377Ssam#define AR_SREV_MERLIN_20(_ah) \ 650185377Ssam (AR_SREV_MERLIN(_ah) && \ 651203959Srpaulo AH_PRIVATE((_ah))->ah_macRev == AR_XSREV_REVISION_MERLIN_20) 652185377Ssam#define AR_SREV_MERLIN_20_OR_LATER(_ah) \ 653185377Ssam (AR_SREV_MERLIN_20(_ah) || \ 654209548Srpaulo AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_MERLIN) 655185377Ssam 656185377Ssam#define AR_SREV_KITE(_ah) \ 657185377Ssam (AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_KITE) 658185377Ssam#define AR_SREV_KITE_10_OR_LATER(_ah) \ 659185377Ssam (AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_KITE) 660203159Srpaulo#define AR_SREV_KITE_11(_ah) \ 661203159Srpaulo (AR_SREV_KITE(ah) && \ 662203159Srpaulo AH_PRIVATE((_ah))->ah_macRev == AR_XSREV_REVISION_KITE_11) 663203159Srpaulo#define AR_SREV_KITE_11_OR_LATER(_ah) \ 664203933Srpaulo (AR_SREV_KITE_11(_ah) || \ 665203159Srpaulo AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_KITE_11) 666203159Srpaulo#define AR_SREV_KITE_12(_ah) \ 667203159Srpaulo (AR_SREV_KITE(ah) && \ 668203959Srpaulo AH_PRIVATE((_ah))->ah_macRev == AR_XSREV_REVISION_KITE_12) 669203159Srpaulo#define AR_SREV_KITE_12_OR_LATER(_ah) \ 670203933Srpaulo (AR_SREV_KITE_12(_ah) || \ 671203159Srpaulo AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_KITE_12) 672218061Sadrian#define AR_SREV_9285E_20(_ah) \ 673218061Sadrian (AR_SREV_KITE_12_OR_LATER(_ah) && \ 674218061Sadrian ((OS_REG_READ(_ah, AR_AN_SYNTH9) & 0x7) == 0x1)) 675218061Sadrian 676219217Sadrian/* Not yet implemented chips */ 677219217Sadrian#define AR_SREV_9271(_ah) 0 678219217Sadrian#define AR_SREV_9287_11_OR_LATER(_ah) 0 679219217Sadrian 680185377Ssam#endif /* _DEV_ATH_AR5416REG_H */ 681