1185377Ssam/* 2185377Ssam * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3185377Ssam * Copyright (c) 2002-2008 Atheros Communications, Inc. 4185377Ssam * 5185377Ssam * Permission to use, copy, modify, and/or distribute this software for any 6185377Ssam * purpose with or without fee is hereby granted, provided that the above 7185377Ssam * copyright notice and this permission notice appear in all copies. 8185377Ssam * 9185377Ssam * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10185377Ssam * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11185377Ssam * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12185377Ssam * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13185377Ssam * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14185377Ssam * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15185377Ssam * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16185377Ssam * 17188968Ssam * $FreeBSD$ 18185377Ssam */ 19185377Ssam#ifndef _DEV_ATH_AR5416REG_H 20185377Ssam#define _DEV_ATH_AR5416REG_H 21185377Ssam 22188968Ssam#include <dev/ath/ath_hal/ar5212/ar5212reg.h> 23185377Ssam 24185377Ssam/* 25185377Ssam * Register added starting with the AR5416 26185377Ssam */ 27185377Ssam#define AR_MIRT 0x0020 /* interrupt rate threshold */ 28185377Ssam#define AR_TIMT 0x0028 /* Tx Interrupt mitigation threshold */ 29185377Ssam#define AR_RIMT 0x002C /* Rx Interrupt mitigation threshold */ 30185377Ssam#define AR_GTXTO 0x0064 /* global transmit timeout */ 31185377Ssam#define AR_GTTM 0x0068 /* global transmit timeout mode */ 32185377Ssam#define AR_CST 0x006C /* carrier sense timeout */ 33185377Ssam#define AR_MAC_LED 0x1f04 /* LED control */ 34188979Ssam#define AR_WA 0x4004 /* PCIE work-arounds */ 35188979Ssam#define AR_PCIE_PM_CTRL 0x4014 36185377Ssam#define AR_AHB_MODE 0x4024 /* AHB mode for dma */ 37185377Ssam#define AR_INTR_SYNC_CAUSE_CLR 0x4028 /* clear interrupt */ 38185377Ssam#define AR_INTR_SYNC_CAUSE 0x4028 /* check pending interrupts */ 39185377Ssam#define AR_INTR_SYNC_ENABLE 0x402c /* enable interrupts */ 40185377Ssam#define AR_INTR_ASYNC_MASK 0x4030 /* asynchronous interrupt mask */ 41185377Ssam#define AR_INTR_SYNC_MASK 0x4034 /* synchronous interrupt mask */ 42185377Ssam#define AR_INTR_ASYNC_CAUSE 0x4038 /* check pending interrupts */ 43225431Sadrian#define AR_INTR_ASYNC_CAUSE_CLR 0x4038 /* clear pending interrupts */ 44185377Ssam#define AR_INTR_ASYNC_ENABLE 0x403c /* enable interrupts */ 45185377Ssam#define AR5416_PCIE_SERDES 0x4040 46185377Ssam#define AR5416_PCIE_SERDES2 0x4044 47188976Ssam#define AR_GPIO_IN_OUT 0x4048 /* GPIO input/output register */ 48188976Ssam#define AR_GPIO_OE_OUT 0x404c /* GPIO output enable register */ 49188976Ssam#define AR_GPIO_INTR_POL 0x4050 /* GPIO interrupt polarity */ 50234692Sadrian 51188976Ssam#define AR_GPIO_INPUT_EN_VAL 0x4054 /* GPIO input enable and value */ 52234692Sadrian#define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF 0x00000004 53234692Sadrian#define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_S 2 54234692Sadrian#define AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF 0x00000008 55234692Sadrian#define AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_S 3 56234692Sadrian#define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_DEF 0x00000010 57234692Sadrian#define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_S 4 58234692Sadrian#define AR_GPIO_INPUT_EN_VAL_RFSILENT_DEF 0x00000080 59234692Sadrian#define AR_GPIO_INPUT_EN_VAL_RFSILENT_DEF_S 7 60234692Sadrian#define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB 0x00000400 61234692Sadrian#define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB_S 10 62234692Sadrian#define AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_BB 0x00000800 63234692Sadrian#define AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_BB_S 11 64234692Sadrian#define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB 0x00001000 65234692Sadrian#define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB_S 12 66234692Sadrian#define AR_GPIO_INPUT_EN_VAL_RFSILENT_BB 0x00008000 67234692Sadrian#define AR_GPIO_INPUT_EN_VAL_RFSILENT_BB_S 15 68234692Sadrian#define AR_GPIO_RTC_RESET_OVERRIDE_ENABLE 0x00010000 69234692Sadrian#define AR_GPIO_JTAG_DISABLE 0x00020000 70234692Sadrian 71188976Ssam#define AR_GPIO_INPUT_MUX1 0x4058 72234692Sadrian#define AR_GPIO_INPUT_MUX1_BT_PRIORITY 0x00000f00 73234692Sadrian#define AR_GPIO_INPUT_MUX1_BT_PRIORITY_S 8 74234692Sadrian#define AR_GPIO_INPUT_MUX1_BT_FREQUENCY 0x0000f000 75234692Sadrian#define AR_GPIO_INPUT_MUX1_BT_FREQUENCY_S 12 76234692Sadrian#define AR_GPIO_INPUT_MUX1_BT_ACTIVE 0x000f0000 77234692Sadrian#define AR_GPIO_INPUT_MUX1_BT_ACTIVE_S 16 78234692Sadrian 79188976Ssam#define AR_GPIO_INPUT_MUX2 0x405c 80234692Sadrian#define AR_GPIO_INPUT_MUX2_CLK25 0x0000000f 81234692Sadrian#define AR_GPIO_INPUT_MUX2_CLK25_S 0 82234692Sadrian#define AR_GPIO_INPUT_MUX2_RFSILENT 0x000000f0 83234692Sadrian#define AR_GPIO_INPUT_MUX2_RFSILENT_S 4 84234692Sadrian#define AR_GPIO_INPUT_MUX2_RTC_RESET 0x00000f00 85234692Sadrian#define AR_GPIO_INPUT_MUX2_RTC_RESET_S 8 86234692Sadrian 87188976Ssam#define AR_GPIO_OUTPUT_MUX1 0x4060 88188976Ssam#define AR_GPIO_OUTPUT_MUX2 0x4064 89188976Ssam#define AR_GPIO_OUTPUT_MUX3 0x4068 90234692Sadrian 91234692Sadrian#define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0 92234692Sadrian#define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1 93234692Sadrian#define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2 94234692Sadrian#define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3 95234692Sadrian#define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4 96234692Sadrian#define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5 97234692Sadrian#define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6 98234692Sadrian 99185377Ssam#define AR_EEPROM_STATUS_DATA 0x407c 100185377Ssam#define AR_OBS 0x4080 101234692Sadrian#define AR_GPIO_PDPU 0x4088 102221163Sadrian 103221163Sadrian#ifdef AH_SUPPORT_AR9130 104221163Sadrian#define AR_RTC_BASE 0x20000 105221163Sadrian#else 106221163Sadrian#define AR_RTC_BASE 0x7000 107221163Sadrian#endif /* AH_SUPPORT_AR9130 */ 108221163Sadrian 109221163Sadrian#define AR_RTC_RC AR_RTC_BASE + 0x00 /* reset control */ 110221163Sadrian#define AR_RTC_PLL_CONTROL AR_RTC_BASE + 0x14 111221163Sadrian#define AR_RTC_RESET AR_RTC_BASE + 0x40 /* RTC reset register */ 112221163Sadrian#define AR_RTC_STATUS AR_RTC_BASE + 0x44 /* system sleep status */ 113221163Sadrian#define AR_RTC_SLEEP_CLK AR_RTC_BASE + 0x48 114221163Sadrian#define AR_RTC_FORCE_WAKE AR_RTC_BASE + 0x4c /* control MAC force wake */ 115221163Sadrian#define AR_RTC_INTR_CAUSE AR_RTC_BASE + 0x50 /* RTC interrupt cause/clear */ 116221163Sadrian#define AR_RTC_INTR_ENABLE AR_RTC_BASE + 0x54 /* RTC interrupt enable */ 117221163Sadrian#define AR_RTC_INTR_MASK AR_RTC_BASE + 0x58 /* RTC interrupt mask */ 118221163Sadrian 119221163Sadrian#ifdef AH_SUPPORT_AR9130 120221163Sadrian/* RTC_DERIVED_* - only for AR9130 */ 121221163Sadrian#define AR_RTC_DERIVED_CLK (AR_RTC_BASE + 0x0038) 122221163Sadrian#define AR_RTC_DERIVED_CLK_PERIOD 0x0000fffe 123221163Sadrian#define AR_RTC_DERIVED_CLK_PERIOD_S 1 124221163Sadrian#endif /* AH_SUPPORT_AR9130 */ 125221163Sadrian 126240445Sadrian/* AR_USEC: 0x801c */ 127240445Sadrian#define AR5416_USEC_TX_LAT 0x007FC000 /* tx latency to start of SIGNAL (usec) */ 128240445Sadrian#define AR5416_USEC_TX_LAT_S 14 /* tx latency to start of SIGNAL (usec) */ 129240445Sadrian#define AR5416_USEC_RX_LAT 0x1F800000 /* rx latency to start of SIGNAL (usec) */ 130240445Sadrian#define AR5416_USEC_RX_LAT_S 23 /* rx latency to start of SIGNAL (usec) */ 131240445Sadrian 132185377Ssam#define AR_RESET_TSF 0x8020 133225125Sadrian 134225125Sadrian/* 135225125Sadrian * AR_SLEEP1 / AR_SLEEP2 are in the same place as in 136225125Sadrian * AR5212, however the fields have changed. 137225125Sadrian */ 138225125Sadrian#define AR5416_SLEEP1 0x80d4 139225125Sadrian#define AR5416_SLEEP2 0x80d8 140185377Ssam#define AR_RXFIFO_CFG 0x8114 141185377Ssam#define AR_PHY_ERR_1 0x812c 142185377Ssam#define AR_PHY_ERR_MASK_1 0x8130 /* mask for AR_PHY_ERR_1 */ 143185377Ssam#define AR_PHY_ERR_2 0x8134 144185377Ssam#define AR_PHY_ERR_MASK_2 0x8138 /* mask for AR_PHY_ERR_2 */ 145185377Ssam#define AR_TSFOOR_THRESHOLD 0x813c 146185377Ssam#define AR_PHY_ERR_3 0x8168 147185377Ssam#define AR_PHY_ERR_MASK_3 0x816c /* mask for AR_PHY_ERR_3 */ 148234692Sadrian#define AR_BT_COEX_WEIGHT2 0x81c4 149185377Ssam#define AR_TXOP_X 0x81ec /* txop for legacy non-qos */ 150185377Ssam#define AR_TXOP_0_3 0x81f0 /* txop for various tid's */ 151185377Ssam#define AR_TXOP_4_7 0x81f4 152185377Ssam#define AR_TXOP_8_11 0x81f8 153185377Ssam#define AR_TXOP_12_15 0x81fc 154185377Ssam/* generic timers based on tsf - all uS */ 155185377Ssam#define AR_NEXT_TBTT 0x8200 156185377Ssam#define AR_NEXT_DBA 0x8204 157185377Ssam#define AR_NEXT_SWBA 0x8208 158185377Ssam#define AR_NEXT_CFP 0x8208 159185377Ssam#define AR_NEXT_HCF 0x820C 160185377Ssam#define AR_NEXT_TIM 0x8210 161185377Ssam#define AR_NEXT_DTIM 0x8214 162185377Ssam#define AR_NEXT_QUIET 0x8218 163185377Ssam#define AR_NEXT_NDP 0x821C 164185377Ssam#define AR5416_BEACON_PERIOD 0x8220 165185377Ssam#define AR_DBA_PERIOD 0x8224 166185377Ssam#define AR_SWBA_PERIOD 0x8228 167185377Ssam#define AR_HCF_PERIOD 0x822C 168185377Ssam#define AR_TIM_PERIOD 0x8230 169185377Ssam#define AR_DTIM_PERIOD 0x8234 170185377Ssam#define AR_QUIET_PERIOD 0x8238 171185377Ssam#define AR_NDP_PERIOD 0x823C 172185377Ssam#define AR_TIMER_MODE 0x8240 173185377Ssam#define AR_SLP32_MODE 0x8244 174185377Ssam#define AR_SLP32_WAKE 0x8248 175185377Ssam#define AR_SLP32_INC 0x824c 176185377Ssam#define AR_SLP_CNT 0x8250 /* 32kHz cycles with mac asleep */ 177185377Ssam#define AR_SLP_CYCLE_CNT 0x8254 /* absolute number of 32kHz cycles */ 178185377Ssam#define AR_SLP_MIB_CTRL 0x8258 179185377Ssam#define AR_2040_MODE 0x8318 180185377Ssam#define AR_EXTRCCNT 0x8328 /* extension channel rx clear count */ 181185377Ssam#define AR_SELFGEN_MASK 0x832c /* rx and cal chain masks */ 182244943Sadrian#define AR_PHY_ERR_MASK_REG 0x8338 183185377Ssam#define AR_PCU_TXBUF_CTRL 0x8340 184208711Srpaulo#define AR_PCU_MISC_MODE2 0x8344 185185377Ssam 186185377Ssam/* DMA & PCI Registers in PCI space (usable during sleep)*/ 187185377Ssam#define AR_RC_AHB 0x00000001 /* AHB reset */ 188185377Ssam#define AR_RC_APB 0x00000002 /* APB reset */ 189185377Ssam#define AR_RC_HOSTIF 0x00000100 /* host interface reset */ 190185377Ssam 191185377Ssam#define AR_MIRT_VAL 0x0000ffff /* in uS */ 192185377Ssam#define AR_MIRT_VAL_S 16 193185377Ssam 194185377Ssam#define AR_TIMT_LAST 0x0000ffff /* Last packet threshold */ 195185377Ssam#define AR_TIMT_LAST_S 0 196185377Ssam#define AR_TIMT_FIRST 0xffff0000 /* First packet threshold */ 197185377Ssam#define AR_TIMT_FIRST_S 16 198185377Ssam 199185377Ssam#define AR_RIMT_LAST 0x0000ffff /* Last packet threshold */ 200185377Ssam#define AR_RIMT_LAST_S 0 201185377Ssam#define AR_RIMT_FIRST 0xffff0000 /* First packet threshold */ 202185377Ssam#define AR_RIMT_FIRST_S 16 203185377Ssam 204185377Ssam#define AR_GTXTO_TIMEOUT_COUNTER 0x0000FFFF // Mask for timeout counter (in TUs) 205185377Ssam#define AR_GTXTO_TIMEOUT_LIMIT 0xFFFF0000 // Mask for timeout limit (in TUs) 206185377Ssam#define AR_GTXTO_TIMEOUT_LIMIT_S 16 // Shift for timeout limit 207185377Ssam 208185377Ssam#define AR_GTTM_USEC 0x00000001 // usec strobe 209185377Ssam#define AR_GTTM_IGNORE_IDLE 0x00000002 // ignore channel idle 210185377Ssam#define AR_GTTM_RESET_IDLE 0x00000004 // reset counter on channel idle low 211185377Ssam#define AR_GTTM_CST_USEC 0x00000008 // CST usec strobe 212185377Ssam 213185377Ssam#define AR_CST_TIMEOUT_COUNTER 0x0000FFFF // Mask for timeout counter (in TUs) 214185377Ssam#define AR_CST_TIMEOUT_LIMIT 0xFFFF0000 // Mask for timeout limit (in TUs) 215185377Ssam#define AR_CST_TIMEOUT_LIMIT_S 16 // Shift for timeout limit 216185377Ssam 217185377Ssam/* MAC tx DMA size config */ 218185377Ssam#define AR_TXCFG_DMASZ_MASK 0x00000003 219185377Ssam#define AR_TXCFG_DMASZ_4B 0 220185377Ssam#define AR_TXCFG_DMASZ_8B 1 221185377Ssam#define AR_TXCFG_DMASZ_16B 2 222185377Ssam#define AR_TXCFG_DMASZ_32B 3 223185377Ssam#define AR_TXCFG_DMASZ_64B 4 224185377Ssam#define AR_TXCFG_DMASZ_128B 5 225185377Ssam#define AR_TXCFG_DMASZ_256B 6 226185377Ssam#define AR_TXCFG_DMASZ_512B 7 227185377Ssam#define AR_TXCFG_ATIM_TXPOLICY 0x00000800 228185377Ssam 229185377Ssam/* MAC rx DMA size config */ 230185377Ssam#define AR_RXCFG_DMASZ_MASK 0x00000007 231185377Ssam#define AR_RXCFG_DMASZ_4B 0 232185377Ssam#define AR_RXCFG_DMASZ_8B 1 233185377Ssam#define AR_RXCFG_DMASZ_16B 2 234185377Ssam#define AR_RXCFG_DMASZ_32B 3 235185377Ssam#define AR_RXCFG_DMASZ_64B 4 236185377Ssam#define AR_RXCFG_DMASZ_128B 5 237185377Ssam#define AR_RXCFG_DMASZ_256B 6 238185377Ssam#define AR_RXCFG_DMASZ_512B 7 239185377Ssam 240185377Ssam/* MAC Led registers */ 241221479Sadrian#define AR_CFG_SCLK_RATE_IND 0x00000003 /* sleep clock indication */ 242221479Sadrian#define AR_CFG_SCLK_RATE_IND_S 0 243221479Sadrian#define AR_CFG_SCLK_32MHZ 0x00000000 /* Sleep clock rate */ 244221479Sadrian#define AR_CFG_SCLK_4MHZ 0x00000001 /* Sleep clock rate */ 245221479Sadrian#define AR_CFG_SCLK_1MHZ 0x00000002 /* Sleep clock rate */ 246221479Sadrian#define AR_CFG_SCLK_32KHZ 0x00000003 /* Sleep clock rate */ 247185377Ssam#define AR_MAC_LED_BLINK_SLOW 0x00000008 /* LED slowest blink rate mode */ 248185377Ssam#define AR_MAC_LED_BLINK_THRESH_SEL 0x00000070 /* LED blink threshold select */ 249185377Ssam#define AR_MAC_LED_MODE 0x00000380 /* LED mode select */ 250185377Ssam#define AR_MAC_LED_MODE_S 7 251185377Ssam#define AR_MAC_LED_MODE_PROP 0 /* Blink prop to filtered tx/rx */ 252185377Ssam#define AR_MAC_LED_MODE_RPROP 1 /* Blink prop to unfiltered tx/rx */ 253185377Ssam#define AR_MAC_LED_MODE_SPLIT 2 /* Blink power for tx/net for rx */ 254185377Ssam#define AR_MAC_LED_MODE_RAND 3 /* Blink randomly */ 255185377Ssam#define AR_MAC_LED_MODE_POWON 5 /* Power LED on (s/w control) */ 256185377Ssam#define AR_MAC_LED_MODE_NETON 6 /* Network LED on (s/w control) */ 257185377Ssam#define AR_MAC_LED_ASSOC 0x00000c00 258228834Sadrian#define AR_MAC_LED_ASSOC_NONE 0x0 /* STA is not associated or trying */ 259228834Sadrian#define AR_MAC_LED_ASSOC_ACTIVE 0x1 /* STA is associated */ 260228834Sadrian#define AR_MAC_LED_ASSOC_PEND 0x2 /* STA is trying to associate */ 261185377Ssam#define AR_MAC_LED_ASSOC_S 10 262185377Ssam 263236009Sadrian#define AR_WA_BIT6 0x00000040 264236009Sadrian#define AR_WA_BIT7 0x00000080 265236009Sadrian#define AR_WA_D3_L1_DISABLE 0x00004000 /* */ 266188979Ssam#define AR_WA_UNTIE_RESET_EN 0x00008000 /* ena PCI reset to POR */ 267188979Ssam#define AR_WA_RESET_EN 0x00040000 /* ena AR_WA_UNTIE_RESET_EN */ 268188979Ssam#define AR_WA_ANALOG_SHIFT 0x00100000 269188979Ssam#define AR_WA_POR_SHORT 0x00200000 /* PCIE phy reset control */ 270236009Sadrian#define AR_WA_BIT22 0x00400000 271236009Sadrian#define AR_WA_BIT23 0x00800000 272188979Ssam 273188979Ssam#define AR_WA_DEFAULT 0x0000073f 274233885Sadrian#define AR9280_WA_DEFAULT 0x0040073b /* disable bit 2, see commit */ 275188979Ssam#define AR9285_WA_DEFAULT 0x004a05cb 276188979Ssam 277188979Ssam#define AR_PCIE_PM_CTRL_ENA 0x00080000 278188979Ssam 279185377Ssam#define AR_AHB_EXACT_WR_EN 0x00000000 /* write exact bytes */ 280185377Ssam#define AR_AHB_BUF_WR_EN 0x00000001 /* buffer write upto cacheline*/ 281185377Ssam#define AR_AHB_EXACT_RD_EN 0x00000000 /* read exact bytes */ 282185377Ssam#define AR_AHB_CACHELINE_RD_EN 0x00000002 /* read upto end of cacheline */ 283185377Ssam#define AR_AHB_PREFETCH_RD_EN 0x00000004 /* prefetch upto page boundary*/ 284185377Ssam#define AR_AHB_PAGE_SIZE_1K 0x00000000 /* set page-size as 1k */ 285185377Ssam#define AR_AHB_PAGE_SIZE_2K 0x00000008 /* set page-size as 2k */ 286185377Ssam#define AR_AHB_PAGE_SIZE_4K 0x00000010 /* set page-size as 4k */ 287222301Sadrian/* Kiwi */ 288222301Sadrian#define AR_AHB_CUSTOM_BURST_EN 0x000000C0 /* set Custom Burst Mode */ 289222301Sadrian#define AR_AHB_CUSTOM_BURST_EN_S 6 /* set Custom Burst Mode */ 290222301Sadrian#define AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL 3 /* set both bits in Async FIFO mode */ 291185377Ssam 292185377Ssam/* MAC PCU Registers */ 293185377Ssam#define AR_STA_ID1_PRESERVE_SEQNUM 0x20000000 /* Don't replace seq num */ 294185377Ssam 295185377Ssam/* Extended PCU DIAG_SW control fields */ 296185377Ssam#define AR_DIAG_DUAL_CHAIN_INFO 0x01000000 /* dual chain channel info */ 297185377Ssam#define AR_DIAG_RX_ABORT 0x02000000 /* abort rx */ 298185377Ssam#define AR_DIAG_SATURATE_CCNT 0x04000000 /* sat. cycle cnts (no shift) */ 299185377Ssam#define AR_DIAG_OBS_PT_SEL2 0x08000000 /* observation point sel */ 300185377Ssam#define AR_DIAG_RXCLEAR_CTL_LOW 0x10000000 /* force rx_clear(ctl) low/busy */ 301185377Ssam#define AR_DIAG_RXCLEAR_EXT_LOW 0x20000000 /* force rx_clear(ext) low/busy */ 302185377Ssam 303185377Ssam#define AR_TXOP_X_VAL 0x000000FF 304185377Ssam 305185377Ssam#define AR_RESET_TSF_ONCE 0x01000000 /* reset tsf once; self-clears*/ 306185377Ssam 307185377Ssam/* Interrupts */ 308185377Ssam#define AR_ISR_TXMINTR 0x00080000 /* Maximum interrupt tx rate */ 309185377Ssam#define AR_ISR_RXMINTR 0x01000000 /* Maximum interrupt rx rate */ 310225925Sadrian#define AR_ISR_GENTMR 0x10000000 /* OR of generic timer bits in S5 */ 311185377Ssam#define AR_ISR_TXINTM 0x40000000 /* Tx int after mitigation */ 312185377Ssam#define AR_ISR_RXINTM 0x80000000 /* Rx int after mitigation */ 313185377Ssam 314185377Ssam#define AR_ISR_S2_CST 0x00400000 /* Carrier sense timeout */ 315185377Ssam#define AR_ISR_S2_GTT 0x00800000 /* Global transmit timeout */ 316185377Ssam#define AR_ISR_S2_TSFOOR 0x40000000 /* RX TSF out of range */ 317185377Ssam 318208711Srpaulo#define AR_ISR_S5 0x0098 319208711Srpaulo#define AR_ISR_S5_S 0x00d8 320226759Sadrian#define AR_ISR_S5_GENTIMER7 0x00000080 // Mask for timer 7 trigger 321226759Sadrian#define AR_ISR_S5_TIM_TIMER 0x00000010 // TIM Timer ISR 322226759Sadrian#define AR_ISR_S5_DTIM_TIMER 0x00000020 // DTIM Timer ISR 323226759Sadrian#define AR_ISR_S5_GENTIMER_TRIG 0x0000FF80 // ISR for generic timer trigger 7-15 324226759Sadrian#define AR_ISR_S5_GENTIMER_TRIG_S 0 325226759Sadrian#define AR_ISR_S5_GENTIMER_THRESH 0xFF800000 // ISR for generic timer threshold 7-15 326226759Sadrian#define AR_ISR_S5_GENTIMER_THRESH_S 16 327208711Srpaulo 328185377Ssam#define AR_INTR_SPURIOUS 0xffffffff 329185377Ssam#define AR_INTR_RTC_IRQ 0x00000001 /* rtc in shutdown state */ 330185377Ssam#define AR_INTR_MAC_IRQ 0x00000002 /* pending mac interrupt */ 331185377Ssam#define AR_INTR_EEP_PROT_ACCESS 0x00000004 /* eeprom protected access */ 332185377Ssam#define AR_INTR_MAC_AWAKE 0x00020000 /* mac is awake */ 333185377Ssam#define AR_INTR_MAC_ASLEEP 0x00040000 /* mac is asleep */ 334185377Ssam 335185377Ssam/* Interrupt Mask Registers */ 336185377Ssam#define AR_IMR_TXMINTR 0x00080000 /* Maximum interrupt tx rate */ 337185377Ssam#define AR_IMR_RXMINTR 0x01000000 /* Maximum interrupt rx rate */ 338185377Ssam#define AR_IMR_TXINTM 0x40000000 /* Tx int after mitigation */ 339185377Ssam#define AR_IMR_RXINTM 0x80000000 /* Rx int after mitigation */ 340185377Ssam 341185377Ssam#define AR_IMR_S2_CST 0x00400000 /* Carrier sense timeout */ 342185377Ssam#define AR_IMR_S2_GTT 0x00800000 /* Global transmit timeout */ 343185377Ssam 344185377Ssam/* synchronous interrupt signals */ 345185377Ssam#define AR_INTR_SYNC_RTC_IRQ 0x00000001 346185377Ssam#define AR_INTR_SYNC_MAC_IRQ 0x00000002 347185377Ssam#define AR_INTR_SYNC_EEPROM_ILLEGAL_ACCESS 0x00000004 348185377Ssam#define AR_INTR_SYNC_APB_TIMEOUT 0x00000008 349185377Ssam#define AR_INTR_SYNC_PCI_MODE_CONFLICT 0x00000010 350185377Ssam#define AR_INTR_SYNC_HOST1_FATAL 0x00000020 351185377Ssam#define AR_INTR_SYNC_HOST1_PERR 0x00000040 352185377Ssam#define AR_INTR_SYNC_TRCV_FIFO_PERR 0x00000080 353185377Ssam#define AR_INTR_SYNC_RADM_CPL_EP 0x00000100 354185377Ssam#define AR_INTR_SYNC_RADM_CPL_DLLP_ABORT 0x00000200 355185377Ssam#define AR_INTR_SYNC_RADM_CPL_TLP_ABORT 0x00000400 356185377Ssam#define AR_INTR_SYNC_RADM_CPL_ECRC_ERR 0x00000800 357185377Ssam#define AR_INTR_SYNC_RADM_CPL_TIMEOUT 0x00001000 358185377Ssam#define AR_INTR_SYNC_LOCAL_TIMEOUT 0x00002000 359185377Ssam#define AR_INTR_SYNC_PM_ACCESS 0x00004000 360185377Ssam#define AR_INTR_SYNC_MAC_AWAKE 0x00008000 361185377Ssam#define AR_INTR_SYNC_MAC_ASLEEP 0x00010000 362185377Ssam#define AR_INTR_SYNC_MAC_SLEEP_ACCESS 0x00020000 363185377Ssam#define AR_INTR_SYNC_ALL 0x0003FFFF 364185377Ssam 365185377Ssam/* default synchronous interrupt signals enabled */ 366185377Ssam#define AR_INTR_SYNC_DEFAULT \ 367185377Ssam (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR | \ 368185377Ssam AR_INTR_SYNC_RADM_CPL_EP | AR_INTR_SYNC_RADM_CPL_DLLP_ABORT | \ 369185377Ssam AR_INTR_SYNC_RADM_CPL_TLP_ABORT | AR_INTR_SYNC_RADM_CPL_ECRC_ERR | \ 370185377Ssam AR_INTR_SYNC_RADM_CPL_TIMEOUT | AR_INTR_SYNC_LOCAL_TIMEOUT | \ 371185377Ssam AR_INTR_SYNC_MAC_SLEEP_ACCESS) 372185377Ssam 373188976Ssam#define AR_INTR_SYNC_MASK_GPIO 0xFFFC0000 374188976Ssam#define AR_INTR_SYNC_MASK_GPIO_S 18 375188976Ssam 376188976Ssam#define AR_INTR_SYNC_ENABLE_GPIO 0xFFFC0000 377188976Ssam#define AR_INTR_SYNC_ENABLE_GPIO_S 18 378188976Ssam 379188976Ssam#define AR_INTR_ASYNC_MASK_GPIO 0xFFFC0000 /* async int mask */ 380188976Ssam#define AR_INTR_ASYNC_MASK_GPIO_S 18 381188976Ssam 382188976Ssam#define AR_INTR_ASYNC_CAUSE_GPIO 0xFFFC0000 /* GPIO interrupts */ 383188976Ssam#define AR_INTR_ASYNC_USED (AR_INTR_MAC_IRQ | AR_INTR_ASYNC_CAUSE_GPIO) 384188976Ssam 385188976Ssam#define AR_INTR_ASYNC_ENABLE_GPIO 0xFFFC0000 /* enable interrupts */ 386188976Ssam#define AR_INTR_ASYNC_ENABLE_GPIO_S 18 387188976Ssam 388185377Ssam/* RTC registers */ 389185377Ssam#define AR_RTC_RC_M 0x00000003 390185377Ssam#define AR_RTC_RC_MAC_WARM 0x00000001 391185377Ssam#define AR_RTC_RC_MAC_COLD 0x00000002 392221163Sadrian#ifdef AH_SUPPORT_AR9130 393221163Sadrian#define AR_RTC_RC_COLD_RESET 0x00000004 394221163Sadrian#define AR_RTC_RC_WARM_RESET 0x00000008 395221163Sadrian#endif /* AH_SUPPORT_AR9130 */ 396185377Ssam#define AR_RTC_PLL_DIV 0x0000001f 397185377Ssam#define AR_RTC_PLL_DIV_S 0 398185377Ssam#define AR_RTC_PLL_DIV2 0x00000020 399185377Ssam#define AR_RTC_PLL_REFDIV_5 0x000000c0 400185377Ssam 401185377Ssam#define AR_RTC_SOWL_PLL_DIV 0x000003ff 402185377Ssam#define AR_RTC_SOWL_PLL_DIV_S 0 403185377Ssam#define AR_RTC_SOWL_PLL_REFDIV 0x00003C00 404185377Ssam#define AR_RTC_SOWL_PLL_REFDIV_S 10 405185377Ssam#define AR_RTC_SOWL_PLL_CLKSEL 0x0000C000 406185377Ssam#define AR_RTC_SOWL_PLL_CLKSEL_S 14 407185377Ssam 408185377Ssam#define AR_RTC_RESET_EN 0x00000001 /* Reset RTC bit */ 409185377Ssam 410185377Ssam#define AR_RTC_PM_STATUS_M 0x0000000f /* Pwr Mgmt Status */ 411221163Sadrian#ifdef AH_SUPPORT_AR9130 412221163Sadrian#define AR_RTC_STATUS_M 0x0000000f /* RTC Status */ 413221163Sadrian#else 414185377Ssam#define AR_RTC_STATUS_M 0x0000003f /* RTC Status */ 415221163Sadrian#endif /* AH_SUPPORT_AR9130 */ 416185377Ssam#define AR_RTC_STATUS_SHUTDOWN 0x00000001 417185377Ssam#define AR_RTC_STATUS_ON 0x00000002 418185377Ssam#define AR_RTC_STATUS_SLEEP 0x00000004 419185377Ssam#define AR_RTC_STATUS_WAKEUP 0x00000008 420185377Ssam#define AR_RTC_STATUS_COLDRESET 0x00000010 /* Not currently used */ 421185377Ssam#define AR_RTC_STATUS_PLLCHANGE 0x00000020 /* Not currently used */ 422185377Ssam 423185377Ssam#define AR_RTC_SLEEP_DERIVED_CLK 0x2 424185377Ssam 425185377Ssam#define AR_RTC_FORCE_WAKE_EN 0x00000001 /* enable force wake */ 426185377Ssam#define AR_RTC_FORCE_WAKE_ON_INT 0x00000002 /* auto-wake on MAC interrupt */ 427185377Ssam 428185377Ssam#define AR_RTC_PLL_CLKSEL 0x00000300 429185377Ssam#define AR_RTC_PLL_CLKSEL_S 8 430185377Ssam 431185377Ssam/* AR9280: rf long shift registers */ 432221806Sadrian#define AR_AN_RF2G1_CH0 0x7810 433221806Sadrian#define AR_AN_RF5G1_CH0 0x7818 434221806Sadrian#define AR_AN_RF2G1_CH1 0x7834 435221806Sadrian#define AR_AN_RF5G1_CH1 0x783C 436221806Sadrian#define AR_AN_TOP2 0x7894 437221806Sadrian#define AR_AN_SYNTH9 0x7868 438221806Sadrian 439185377Ssam#define AR_AN_RF2G1_CH0_OB 0x03800000 440185377Ssam#define AR_AN_RF2G1_CH0_OB_S 23 441185377Ssam#define AR_AN_RF2G1_CH0_DB 0x1C000000 442185377Ssam#define AR_AN_RF2G1_CH0_DB_S 26 443185377Ssam 444185377Ssam#define AR_AN_RF5G1_CH0_OB5 0x00070000 445185377Ssam#define AR_AN_RF5G1_CH0_OB5_S 16 446185377Ssam#define AR_AN_RF5G1_CH0_DB5 0x00380000 447185377Ssam#define AR_AN_RF5G1_CH0_DB5_S 19 448185377Ssam 449185377Ssam#define AR_AN_RF2G1_CH1_OB 0x03800000 450185377Ssam#define AR_AN_RF2G1_CH1_OB_S 23 451185377Ssam#define AR_AN_RF2G1_CH1_DB 0x1C000000 452185377Ssam#define AR_AN_RF2G1_CH1_DB_S 26 453185377Ssam 454185377Ssam#define AR_AN_RF5G1_CH1_OB5 0x00070000 455185377Ssam#define AR_AN_RF5G1_CH1_OB5_S 16 456185377Ssam#define AR_AN_RF5G1_CH1_DB5 0x00380000 457185377Ssam#define AR_AN_RF5G1_CH1_DB5_S 19 458185377Ssam 459218420Sadrian#define AR_AN_TOP1 0x7890 460218420Sadrian#define AR_AN_TOP1_DACIPMODE 0x00040000 461218420Sadrian#define AR_AN_TOP1_DACIPMODE_S 18 462218420Sadrian 463185377Ssam#define AR_AN_TOP2_XPABIAS_LVL 0xC0000000 464185377Ssam#define AR_AN_TOP2_XPABIAS_LVL_S 30 465185377Ssam#define AR_AN_TOP2_LOCALBIAS 0x00200000 466185377Ssam#define AR_AN_TOP2_LOCALBIAS_S 21 467185377Ssam#define AR_AN_TOP2_PWDCLKIND 0x00400000 468185377Ssam#define AR_AN_TOP2_PWDCLKIND_S 22 469185377Ssam 470185377Ssam#define AR_AN_SYNTH9_REFDIVA 0xf8000000 471185377Ssam#define AR_AN_SYNTH9_REFDIVA_S 27 472185377Ssam 473203159Srpaulo#define AR9271_AN_RF2G6_OFFS 0x07f00000 474203159Srpaulo#define AR9271_AN_RF2G6_OFFS_S 20 475203159Srpaulo 476185377Ssam/* Sleep control */ 477225125Sadrian#define AR5416_SLEEP1_ASSUME_DTIM 0x00080000 478185377Ssam#define AR5416_SLEEP1_CAB_TIMEOUT 0xFFE00000 /* Cab timeout (TU) */ 479185377Ssam#define AR5416_SLEEP1_CAB_TIMEOUT_S 22 480185377Ssam 481185377Ssam#define AR5416_SLEEP2_BEACON_TIMEOUT 0xFFE00000 /* Beacon timeout (TU)*/ 482185377Ssam#define AR5416_SLEEP2_BEACON_TIMEOUT_S 22 483185377Ssam 484185377Ssam/* Sleep Registers */ 485185377Ssam#define AR_SLP32_HALFCLK_LATENCY 0x000FFFFF /* rising <-> falling edge */ 486185377Ssam#define AR_SLP32_ENA 0x00100000 487185377Ssam#define AR_SLP32_TSF_WRITE_STATUS 0x00200000 /* tsf update in progress */ 488185377Ssam 489185377Ssam#define AR_SLP32_WAKE_XTL_TIME 0x0000FFFF /* time to wake crystal */ 490185377Ssam 491185377Ssam#define AR_SLP32_TST_INC 0x000FFFFF 492185377Ssam 493185377Ssam#define AR_SLP_MIB_CLEAR 0x00000001 /* clear pending */ 494185377Ssam#define AR_SLP_MIB_PENDING 0x00000002 /* clear counters */ 495185377Ssam 496185377Ssam#define AR_TIMER_MODE_TBTT 0x00000001 497185377Ssam#define AR_TIMER_MODE_DBA 0x00000002 498185377Ssam#define AR_TIMER_MODE_SWBA 0x00000004 499185377Ssam#define AR_TIMER_MODE_HCF 0x00000008 500185377Ssam#define AR_TIMER_MODE_TIM 0x00000010 501185377Ssam#define AR_TIMER_MODE_DTIM 0x00000020 502185377Ssam#define AR_TIMER_MODE_QUIET 0x00000040 503185377Ssam#define AR_TIMER_MODE_NDP 0x00000080 504185377Ssam#define AR_TIMER_MODE_OVERFLOW_INDEX 0x00000700 505185377Ssam#define AR_TIMER_MODE_OVERFLOW_INDEX_S 8 506185377Ssam#define AR_TIMER_MODE_THRESH 0xFFFFF000 507185377Ssam#define AR_TIMER_MODE_THRESH_S 12 508185377Ssam 509185377Ssam/* PCU Misc modes */ 510185377Ssam#define AR_PCU_FORCE_BSSID_MATCH 0x00000001 /* force bssid to match */ 511185377Ssam#define AR_PCU_MIC_NEW_LOC_ENA 0x00000004 /* tx/rx mic keys together */ 512185377Ssam#define AR_PCU_TX_ADD_TSF 0x00000008 /* add tx_tsf + int_tsf */ 513185377Ssam#define AR_PCU_CCK_SIFS_MODE 0x00000010 /* assume 11b sifs */ 514185377Ssam#define AR_PCU_RX_ANT_UPDT 0x00000800 /* KC_RX_ANT_UPDATE */ 515185377Ssam#define AR_PCU_TXOP_TBTT_LIMIT_ENA 0x00001000 /* enforce txop / tbtt */ 516185377Ssam#define AR_PCU_MISS_BCN_IN_SLEEP 0x00004000 /* count bmiss's when sleeping */ 517185377Ssam#define AR_PCU_BUG_12306_FIX_ENA 0x00020000 /* use rx_clear to count sifs */ 518185377Ssam#define AR_PCU_FORCE_QUIET_COLL 0x00040000 /* kill xmit for channel change */ 519234692Sadrian#define AR_PCU_BT_ANT_PREVENT_RX 0x00100000 520234692Sadrian#define AR_PCU_BT_ANT_PREVENT_RX_S 20 521185377Ssam#define AR_PCU_TBTT_PROTECT 0x00200000 /* no xmit upto tbtt+20 uS */ 522185377Ssam#define AR_PCU_CLEAR_VMF 0x01000000 /* clear vmf mode (fast cc)*/ 523185377Ssam#define AR_PCU_CLEAR_BA_VALID 0x04000000 /* clear ba state */ 524248129Sadrian#define AR_PCU_SEL_EVM 0x08000000 /* select EVM data or PLCP header */ 525185377Ssam 526219978Sadrian#define AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE 0x00000002 527219978Sadrian#define AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT 0x00000004 528221617Sadrian/* 529221617Sadrian * This bit enables the Multicast search based on both MAC Address and Key ID. 530221617Sadrian * If bit is 0, then Multicast search is based on MAC address only. 531221617Sadrian * For Merlin and above only. 532221617Sadrian */ 533221617Sadrian#define AR_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE 0x00000040 534222301Sadrian#define AR_PCU_MISC_MODE2_ENABLE_AGGWEP 0x00020000 /* Kiwi or later? */ 535208711Srpaulo#define AR_PCU_MISC_MODE2_HWWAR1 0x00100000 536219217Sadrian#define AR_PCU_MISC_MODE2_HWWAR2 0x02000000 537208711Srpaulo 538222301Sadrian/* For Kiwi */ 539222301Sadrian#define AR_MAC_PCU_ASYNC_FIFO_REG3 0x8358 540222301Sadrian#define AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL 0x00000400 541222301Sadrian#define AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET 0x80000000 542222301Sadrian 543222301Sadrian/* TSF2. For Kiwi only */ 544222301Sadrian#define AR_TSF2_L32 0x8390 545222301Sadrian#define AR_TSF2_U32 0x8394 546222301Sadrian 547222301Sadrian/* MAC Direct Connect Control. For Kiwi only */ 548222301Sadrian#define AR_DIRECT_CONNECT 0x83A0 549222301Sadrian#define AR_DC_AP_STA_EN 0x00000001 550222301Sadrian 551185377Ssam/* GPIO Interrupt */ 552185377Ssam#define AR_INTR_GPIO 0x3FF00000 /* gpio interrupted */ 553185377Ssam#define AR_INTR_GPIO_S 20 554185377Ssam 555185377Ssam#define AR_GPIO_OUT_CTRL 0x000003FF /* 0 = out, 1 = in */ 556185377Ssam#define AR_GPIO_OUT_VAL 0x000FFC00 557185377Ssam#define AR_GPIO_OUT_VAL_S 10 558185377Ssam#define AR_GPIO_INTR_CTRL 0x3FF00000 559185377Ssam#define AR_GPIO_INTR_CTRL_S 20 560185377Ssam 561188976Ssam#define AR_GPIO_IN_VAL 0x0FFFC000 /* pre-9280 */ 562188976Ssam#define AR_GPIO_IN_VAL_S 14 563188976Ssam#define AR928X_GPIO_IN_VAL 0x000FFC00 564188976Ssam#define AR928X_GPIO_IN_VAL_S 10 565188976Ssam#define AR9285_GPIO_IN_VAL 0x00FFF000 566188976Ssam#define AR9285_GPIO_IN_VAL_S 12 567228834Sadrian#define AR9287_GPIO_IN_VAL 0x003FF800 568228834Sadrian#define AR9287_GPIO_IN_VAL_S 11 569188976Ssam 570188976Ssam#define AR_GPIO_OE_OUT_DRV 0x3 /* 2 bit mask shifted by 2*bitpos */ 571188976Ssam#define AR_GPIO_OE_OUT_DRV_NO 0x0 /* tristate */ 572188976Ssam#define AR_GPIO_OE_OUT_DRV_LOW 0x1 /* drive if low */ 573188976Ssam#define AR_GPIO_OE_OUT_DRV_HI 0x2 /* drive if high */ 574188976Ssam#define AR_GPIO_OE_OUT_DRV_ALL 0x3 /* drive always */ 575188976Ssam 576188976Ssam#define AR_GPIO_INTR_POL_VAL 0x1FFF 577188976Ssam#define AR_GPIO_INTR_POL_VAL_S 0 578188976Ssam 579208711Srpaulo#define AR_GPIO_JTAG_DISABLE 0x00020000 580208711Srpaulo 581185377Ssam#define AR_2040_JOINED_RX_CLEAR 0x00000001 /* use ctl + ext rx_clear for cca */ 582185377Ssam 583185377Ssam#define AR_PCU_TXBUF_CTRL_SIZE_MASK 0x7FF 584185377Ssam#define AR_PCU_TXBUF_CTRL_USABLE_SIZE 0x700 585203159Srpaulo#define AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE 0x380 586185377Ssam 587222301Sadrian/* IFS, SIFS, slot, etc for Async FIFO mode (Kiwi) */ 588222301Sadrian#define AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR 0x000003AB 589222301Sadrian#define AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR 0x16001D56 590222301Sadrian#define AR_USEC_ASYNC_FIFO_DUR 0x12e00074 591222301Sadrian#define AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR 0x00000420 592222301Sadrian#define AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR 0x0000A5EB 593222301Sadrian 594222301Sadrian/* Used by Kiwi Async FIFO */ 595222301Sadrian#define AR_MAC_PCU_LOGIC_ANALYZER 0x8264 596222301Sadrian#define AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768 0x20000000 597222301Sadrian 598185377Ssam/* Eeprom defines */ 599185377Ssam#define AR_EEPROM_STATUS_DATA_VAL 0x0000ffff 600185377Ssam#define AR_EEPROM_STATUS_DATA_VAL_S 0 601185377Ssam#define AR_EEPROM_STATUS_DATA_BUSY 0x00010000 602185377Ssam#define AR_EEPROM_STATUS_DATA_BUSY_ACCESS 0x00020000 603185377Ssam#define AR_EEPROM_STATUS_DATA_PROT_ACCESS 0x00040000 604185377Ssam#define AR_EEPROM_STATUS_DATA_ABSENT_ACCESS 0x00080000 605185377Ssam 606249516Sadrian/* K2 (9271) */ 607249516Sadrian#define AR9271_CLOCK_CONTROL 0x50040 608249516Sadrian#define AR9271_CLOCK_SELECTION_22 0x0 609249516Sadrian#define AR9271_CLOCK_SELECTION_88 0x1 610249516Sadrian#define AR9271_CLOCK_SELECTION_44 0x2 611249516Sadrian#define AR9271_CLOCK_SELECTION_117 0x4 612249516Sadrian#define AR9271_CLOCK_SELECTION_OSC_40 0x6 613249516Sadrian#define AR9271_CLOCK_SELECTION_RTC 0x7 614249516Sadrian#define AR9271_SPI_SEL 0x100 615249516Sadrian#define AR9271_UART_SEL 0x200 616249516Sadrian 617249516Sadrian#define AR9271_RESET_POWER_DOWN_CONTROL 0x50044 618249516Sadrian#define AR9271_RADIO_RF_RST 0x20 619249516Sadrian#define AR9271_GATE_MAC_CTL 0x4000 620249516Sadrian#define AR9271_MAIN_PLL_PWD_CTL 0x40000 621249516Sadrian 622249516Sadrian#define AR9271_CLKMISC 0x4090 623249516Sadrian#define AR9271_OSC_to_10M_EN 0x00000001 624249516Sadrian 625221573Sadrian/* 626221573Sadrian * AR5212 defines the MAC revision mask as 0xF, but both ath9k and 627221573Sadrian * the Atheros HAL define it as 0x7. 628221573Sadrian * 629221573Sadrian * What this means however is AR5416 silicon revisions have 630221573Sadrian * changed. The below macros are for what is contained in the 631221573Sadrian * lower four bits; if the lower three bits are taken into account 632221573Sadrian * the revisions become 1.0 => 0x0, 2.0 => 0x1, 2.2 => 0x2. 633221573Sadrian */ 634221573Sadrian 635221573Sadrian/* These are the legacy revisions, with a four bit AR_SREV_REVISION mask */ 636185377Ssam#define AR_SREV_REVISION_OWL_10 0x08 637185377Ssam#define AR_SREV_REVISION_OWL_20 0x09 638185377Ssam#define AR_SREV_REVISION_OWL_22 0x0a 639185377Ssam 640185377Ssam#define AR_RAD5133_SREV_MAJOR 0xc0 /* Fowl: 2+5G/3x3 */ 641185377Ssam#define AR_RAD2133_SREV_MAJOR 0xd0 /* Fowl: 2G/3x3 */ 642185377Ssam#define AR_RAD5122_SREV_MAJOR 0xe0 /* Fowl: 5G/2x2 */ 643185377Ssam#define AR_RAD2122_SREV_MAJOR 0xf0 /* Fowl: 2+5G/2x2 */ 644185377Ssam 645185377Ssam/* Test macro for owl 1.0 */ 646221608Sadrian#define IS_5416V1(_ah) (AR_SREV_OWL((_ah)) && AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_OWL_10) 647221608Sadrian#define IS_5416V2(_ah) (AR_SREV_OWL((_ah)) && AH_PRIVATE((_ah))->ah_macRev >= AR_SREV_REVISION_OWL_20) 648221608Sadrian#define IS_5416V2_2(_ah) (AR_SREV_OWL((_ah)) && AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_OWL_22) 649185377Ssam 650221573Sadrian/* Misc; compatibility with Atheros HAL */ 651221573Sadrian#define AR_SREV_5416_V20_OR_LATER(_ah) (AR_SREV_HOWL((_ah)) || AR_SREV_OWL_20_OR_LATER(_ah)) 652221573Sadrian#define AR_SREV_5416_V22_OR_LATER(_ah) (AR_SREV_HOWL((_ah)) || AR_SREV_OWL_22_OR_LATER(_ah)) 653221573Sadrian 654185377Ssam/* Expanded Mac Silicon Rev (16 bits starting with Sowl) */ 655185377Ssam#define AR_XSREV_ID 0xFFFFFFFF /* Chip ID */ 656185377Ssam#define AR_XSREV_ID_S 0 657185377Ssam#define AR_XSREV_VERSION 0xFFFC0000 /* Chip version */ 658185377Ssam#define AR_XSREV_VERSION_S 18 659185377Ssam#define AR_XSREV_TYPE 0x0003F000 /* Chip type */ 660185377Ssam#define AR_XSREV_TYPE_S 12 661185377Ssam#define AR_XSREV_TYPE_CHAIN 0x00001000 /* Chain Mode (1:3 chains, 662185377Ssam * 0:2 chains) */ 663185377Ssam#define AR_XSREV_TYPE_HOST_MODE 0x00002000 /* Host Mode (1:PCI, 0:PCIe) */ 664185377Ssam#define AR_XSREV_REVISION 0x00000F00 665185377Ssam#define AR_XSREV_REVISION_S 8 666185377Ssam 667185377Ssam#define AR_XSREV_VERSION_OWL_PCI 0x0D 668185377Ssam#define AR_XSREV_VERSION_OWL_PCIE 0x0C 669221573Sadrian 670221573Sadrian 671221573Sadrian/* 672221573Sadrian * These are from ath9k/Atheros and assume an AR_SREV version mask 673221573Sadrian * of 0x07, rather than 0x0F which is being used in the FreeBSD HAL. 674221573Sadrian * Thus, don't use these values as they're incorrect here; use 675221573Sadrian * AR_SREV_REVISION_OWL_{10,20,22}. 676221573Sadrian */ 677221573Sadrian#if 0 678185377Ssam#define AR_XSREV_REVISION_OWL_10 0 /* Owl 1.0 */ 679185377Ssam#define AR_XSREV_REVISION_OWL_20 1 /* Owl 2.0/2.1 */ 680185377Ssam#define AR_XSREV_REVISION_OWL_22 2 /* Owl 2.2 */ 681221573Sadrian#endif 682221573Sadrian 683219217Sadrian#define AR_XSREV_VERSION_HOWL 0x14 /* Howl (AR9130) */ 684221163Sadrian#define AR_XSREV_VERSION_SOWL 0x40 /* Sowl (AR9160) */ 685185377Ssam#define AR_XSREV_REVISION_SOWL_10 0 /* Sowl 1.0 */ 686185377Ssam#define AR_XSREV_REVISION_SOWL_11 1 /* Sowl 1.1 */ 687185377Ssam#define AR_XSREV_VERSION_MERLIN 0x80 /* Merlin Version */ 688185377Ssam#define AR_XSREV_REVISION_MERLIN_10 0 /* Merlin 1.0 */ 689185377Ssam#define AR_XSREV_REVISION_MERLIN_20 1 /* Merlin 2.0 */ 690185377Ssam#define AR_XSREV_REVISION_MERLIN_21 2 /* Merlin 2.1 */ 691185377Ssam#define AR_XSREV_VERSION_KITE 0xC0 /* Kite Version */ 692185377Ssam#define AR_XSREV_REVISION_KITE_10 0 /* Kite 1.0 */ 693203159Srpaulo#define AR_XSREV_REVISION_KITE_11 1 /* Kite 1.1 */ 694203159Srpaulo#define AR_XSREV_REVISION_KITE_12 2 /* Kite 1.2 */ 695222301Sadrian#define AR_XSREV_VERSION_KIWI 0x180 /* Kiwi (AR9287) */ 696227408Sadrian#define AR_XSREV_REVISION_KIWI_10 0 /* Kiwi 1.0 */ 697227408Sadrian#define AR_XSREV_REVISION_KIWI_11 1 /* Kiwi 1.1 */ 698227408Sadrian#define AR_XSREV_REVISION_KIWI_12 2 /* Kiwi 1.2 */ 699227408Sadrian#define AR_XSREV_REVISION_KIWI_13 3 /* Kiwi 1.3 */ 700185377Ssam 701221480Sadrian/* Owl (AR5416) */ 702217881Sadrian#define AR_SREV_OWL(_ah) \ 703217881Sadrian ((AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_OWL_PCI) || \ 704217881Sadrian (AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_OWL_PCIE)) 705217881Sadrian 706185377Ssam#define AR_SREV_OWL_20_OR_LATER(_ah) \ 707221480Sadrian ((AR_SREV_OWL(_ah) && \ 708221573Sadrian AH_PRIVATE((_ah))->ah_macRev >= AR_SREV_REVISION_OWL_20) || \ 709221480Sadrian AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_HOWL) 710221480Sadrian 711185377Ssam#define AR_SREV_OWL_22_OR_LATER(_ah) \ 712221480Sadrian ((AR_SREV_OWL(_ah) && \ 713221573Sadrian AH_PRIVATE((_ah))->ah_macRev >= AR_SREV_REVISION_OWL_22) || \ 714221480Sadrian AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_HOWL) 715185377Ssam 716221480Sadrian/* Howl (AR9130) */ 717221480Sadrian 718221163Sadrian#define AR_SREV_HOWL(_ah) \ 719221163Sadrian (AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_HOWL) 720221480Sadrian 721221163Sadrian#define AR_SREV_9100(_ah) AR_SREV_HOWL(_ah) 722221163Sadrian 723221480Sadrian/* Sowl (AR9160) */ 724221480Sadrian 725185377Ssam#define AR_SREV_SOWL(_ah) \ 726185377Ssam (AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_SOWL) 727221480Sadrian 728185377Ssam#define AR_SREV_SOWL_10_OR_LATER(_ah) \ 729185377Ssam (AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_SOWL) 730221480Sadrian 731185377Ssam#define AR_SREV_SOWL_11(_ah) \ 732185377Ssam (AR_SREV_SOWL(_ah) && \ 733185377Ssam AH_PRIVATE((_ah))->ah_macRev == AR_XSREV_REVISION_SOWL_11) 734185377Ssam 735221480Sadrian/* Merlin (AR9280) */ 736221480Sadrian 737185377Ssam#define AR_SREV_MERLIN(_ah) \ 738185377Ssam (AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_MERLIN) 739221480Sadrian 740185377Ssam#define AR_SREV_MERLIN_10_OR_LATER(_ah) \ 741185377Ssam (AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_MERLIN) 742221480Sadrian 743185377Ssam#define AR_SREV_MERLIN_20(_ah) \ 744185377Ssam (AR_SREV_MERLIN(_ah) && \ 745221666Sadrian AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_MERLIN_20) 746221480Sadrian 747185377Ssam#define AR_SREV_MERLIN_20_OR_LATER(_ah) \ 748221480Sadrian ((AH_PRIVATE((_ah))->ah_macVersion > AR_XSREV_VERSION_MERLIN) || \ 749221480Sadrian (AR_SREV_MERLIN((_ah)) && \ 750221480Sadrian AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_MERLIN_20)) 751185377Ssam 752221480Sadrian/* Kite (AR9285) */ 753221480Sadrian 754185377Ssam#define AR_SREV_KITE(_ah) \ 755185377Ssam (AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_KITE) 756221480Sadrian 757185377Ssam#define AR_SREV_KITE_10_OR_LATER(_ah) \ 758185377Ssam (AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_KITE) 759221480Sadrian 760203159Srpaulo#define AR_SREV_KITE_11(_ah) \ 761203159Srpaulo (AR_SREV_KITE(ah) && \ 762203159Srpaulo AH_PRIVATE((_ah))->ah_macRev == AR_XSREV_REVISION_KITE_11) 763221480Sadrian 764203159Srpaulo#define AR_SREV_KITE_11_OR_LATER(_ah) \ 765221480Sadrian ((AH_PRIVATE((_ah))->ah_macVersion > AR_XSREV_VERSION_KITE) || \ 766221480Sadrian (AR_SREV_KITE((_ah)) && \ 767221480Sadrian AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_KITE_11)) 768221480Sadrian 769203159Srpaulo#define AR_SREV_KITE_12(_ah) \ 770203159Srpaulo (AR_SREV_KITE(ah) && \ 771203959Srpaulo AH_PRIVATE((_ah))->ah_macRev == AR_XSREV_REVISION_KITE_12) 772221480Sadrian 773203159Srpaulo#define AR_SREV_KITE_12_OR_LATER(_ah) \ 774221480Sadrian ((AH_PRIVATE((_ah))->ah_macVersion > AR_XSREV_VERSION_KITE) || \ 775221480Sadrian (AR_SREV_KITE((_ah)) && \ 776221480Sadrian AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_KITE_12)) 777221480Sadrian 778218061Sadrian#define AR_SREV_9285E_20(_ah) \ 779218061Sadrian (AR_SREV_KITE_12_OR_LATER(_ah) && \ 780218061Sadrian ((OS_REG_READ(_ah, AR_AN_SYNTH9) & 0x7) == 0x1)) 781218061Sadrian 782222300Sadrian#define AR_SREV_KIWI(_ah) \ 783222300Sadrian (AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_KIWI) 784222300Sadrian 785227408Sadrian#define AR_SREV_KIWI_10_OR_LATER(_ah) \ 786227408Sadrian (AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_KIWI) 787227408Sadrian 788227408Sadrian/* XXX TODO: make these handle macVersion > Kiwi */ 789222300Sadrian#define AR_SREV_KIWI_11_OR_LATER(_ah) \ 790222300Sadrian (AR_SREV_KIWI(_ah) && \ 791222300Sadrian AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_KIWI_11) 792222300Sadrian 793222300Sadrian#define AR_SREV_KIWI_11(_ah) \ 794222300Sadrian (AR_SREV_KIWI(_ah) && \ 795222300Sadrian AH_PRIVATE((_ah))->ah_macRev == AR_XSREV_REVISION_KIWI_11) 796222300Sadrian 797222300Sadrian#define AR_SREV_KIWI_12(_ah) \ 798222300Sadrian (AR_SREV_KIWI(_ah) && \ 799222300Sadrian AH_PRIVATE((_ah))->ah_macRev == AR_XSREV_REVISION_KIWI_12) 800222300Sadrian 801222300Sadrian#define AR_SREV_KIWI_12_OR_LATER(_ah) \ 802222300Sadrian (AR_SREV_KIWI(_ah) && \ 803222300Sadrian AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_KIWI_12) 804222300Sadrian 805222300Sadrian#define AR_SREV_KIWI_13_OR_LATER(_ah) \ 806222300Sadrian (AR_SREV_KIWI(_ah) && \ 807222300Sadrian AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_KIWI_13) 808222300Sadrian 809222300Sadrian 810219217Sadrian/* Not yet implemented chips */ 811219217Sadrian#define AR_SREV_9271(_ah) 0 812219217Sadrian 813185377Ssam#endif /* _DEV_ATH_AR5416REG_H */ 814