ar5416_attach.c revision 226767
1/* 2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ar5416/ar5416_attach.c 226767 2011-10-25 23:33:54Z adrian $ 18 */ 19#include "opt_ah.h" 20 21#include "ah.h" 22#include "ah_internal.h" 23#include "ah_devid.h" 24 25#include "ah_eeprom_v14.h" 26 27#include "ar5416/ar5416.h" 28#include "ar5416/ar5416reg.h" 29#include "ar5416/ar5416phy.h" 30 31#include "ar5416/ar5416.ini" 32 33static void ar5416ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore); 34static void ar5416WriteIni(struct ath_hal *ah, 35 const struct ieee80211_channel *chan); 36static void ar5416SpurMitigate(struct ath_hal *ah, 37 const struct ieee80211_channel *chan); 38 39static void 40ar5416AniSetup(struct ath_hal *ah) 41{ 42 static const struct ar5212AniParams aniparams = { 43 .maxNoiseImmunityLevel = 4, /* levels 0..4 */ 44 .totalSizeDesired = { -55, -55, -55, -55, -62 }, 45 .coarseHigh = { -14, -14, -14, -14, -12 }, 46 .coarseLow = { -64, -64, -64, -64, -70 }, 47 .firpwr = { -78, -78, -78, -78, -80 }, 48 .maxSpurImmunityLevel = 2, 49 .cycPwrThr1 = { 2, 4, 6 }, 50 .maxFirstepLevel = 2, /* levels 0..2 */ 51 .firstep = { 0, 4, 8 }, 52 .ofdmTrigHigh = 500, 53 .ofdmTrigLow = 200, 54 .cckTrigHigh = 200, 55 .cckTrigLow = 100, 56 .rssiThrHigh = 40, 57 .rssiThrLow = 7, 58 .period = 100, 59 }; 60 /* NB: disable ANI noise immmunity for reliable RIFS rx */ 61 AH5416(ah)->ah_ani_function &= ~(1 << HAL_ANI_NOISE_IMMUNITY_LEVEL); 62 ar5416AniAttach(ah, &aniparams, &aniparams, AH_TRUE); 63} 64 65/* 66 * AR5416 doesn't do OLC or temperature compensation. 67 */ 68static void 69ar5416olcInit(struct ath_hal *ah) 70{ 71} 72 73static void 74ar5416olcTempCompensation(struct ath_hal *ah) 75{ 76} 77 78/* 79 * Attach for an AR5416 part. 80 */ 81void 82ar5416InitState(struct ath_hal_5416 *ahp5416, uint16_t devid, HAL_SOFTC sc, 83 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status) 84{ 85 struct ath_hal_5212 *ahp; 86 struct ath_hal *ah; 87 88 ahp = &ahp5416->ah_5212; 89 ar5212InitState(ahp, devid, sc, st, sh, status); 90 ah = &ahp->ah_priv.h; 91 92 /* override 5212 methods for our needs */ 93 ah->ah_magic = AR5416_MAGIC; 94 ah->ah_getRateTable = ar5416GetRateTable; 95 ah->ah_detach = ar5416Detach; 96 97 /* Reset functions */ 98 ah->ah_reset = ar5416Reset; 99 ah->ah_phyDisable = ar5416PhyDisable; 100 ah->ah_disable = ar5416Disable; 101 ah->ah_configPCIE = ar5416ConfigPCIE; 102 ah->ah_perCalibration = ar5416PerCalibration; 103 ah->ah_perCalibrationN = ar5416PerCalibrationN, 104 ah->ah_resetCalValid = ar5416ResetCalValid, 105 ah->ah_setTxPowerLimit = ar5416SetTxPowerLimit; 106 ah->ah_setTxPower = ar5416SetTransmitPower; 107 ah->ah_setBoardValues = ar5416SetBoardValues; 108 109 /* Transmit functions */ 110 ah->ah_stopTxDma = ar5416StopTxDma; 111 ah->ah_setupTxDesc = ar5416SetupTxDesc; 112 ah->ah_setupXTxDesc = ar5416SetupXTxDesc; 113 ah->ah_fillTxDesc = ar5416FillTxDesc; 114 ah->ah_procTxDesc = ar5416ProcTxDesc; 115 ah->ah_getTxCompletionRates = ar5416GetTxCompletionRates; 116 ah->ah_setupTxQueue = ar5416SetupTxQueue; 117 ah->ah_resetTxQueue = ar5416ResetTxQueue; 118 119 /* Receive Functions */ 120 ah->ah_getRxFilter = ar5416GetRxFilter; 121 ah->ah_setRxFilter = ar5416SetRxFilter; 122 ah->ah_startPcuReceive = ar5416StartPcuReceive; 123 ah->ah_stopPcuReceive = ar5416StopPcuReceive; 124 ah->ah_setupRxDesc = ar5416SetupRxDesc; 125 ah->ah_procRxDesc = ar5416ProcRxDesc; 126 ah->ah_rxMonitor = ar5416RxMonitor; 127 ah->ah_aniPoll = ar5416AniPoll; 128 ah->ah_procMibEvent = ar5416ProcessMibIntr; 129 130 /* Misc Functions */ 131 ah->ah_getCapability = ar5416GetCapability; 132 ah->ah_getDiagState = ar5416GetDiagState; 133 ah->ah_setLedState = ar5416SetLedState; 134 ah->ah_gpioCfgOutput = ar5416GpioCfgOutput; 135 ah->ah_gpioCfgInput = ar5416GpioCfgInput; 136 ah->ah_gpioGet = ar5416GpioGet; 137 ah->ah_gpioSet = ar5416GpioSet; 138 ah->ah_gpioSetIntr = ar5416GpioSetIntr; 139 ah->ah_getTsf64 = ar5416GetTsf64; 140 ah->ah_resetTsf = ar5416ResetTsf; 141 ah->ah_getRfGain = ar5416GetRfgain; 142 ah->ah_setAntennaSwitch = ar5416SetAntennaSwitch; 143 ah->ah_setDecompMask = ar5416SetDecompMask; 144 ah->ah_setCoverageClass = ar5416SetCoverageClass; 145 ah->ah_setQuiet = ar5416SetQuiet; 146 147 ah->ah_resetKeyCacheEntry = ar5416ResetKeyCacheEntry; 148 ah->ah_setKeyCacheEntry = ar5416SetKeyCacheEntry; 149 150 /* DFS Functions */ 151 ah->ah_enableDfs = ar5416EnableDfs; 152 ah->ah_getDfsThresh = ar5416GetDfsThresh; 153 ah->ah_procRadarEvent = ar5416ProcessRadarEvent; 154 ah->ah_isFastClockEnabled = ar5416IsFastClockEnabled; 155 156 /* Power Management Functions */ 157 ah->ah_setPowerMode = ar5416SetPowerMode; 158 159 /* Beacon Management Functions */ 160 ah->ah_setBeaconTimers = ar5416SetBeaconTimers; 161 ah->ah_beaconInit = ar5416BeaconInit; 162 ah->ah_setStationBeaconTimers = ar5416SetStaBeaconTimers; 163 ah->ah_resetStationBeaconTimers = ar5416ResetStaBeaconTimers; 164 ah->ah_getNextTBTT = ar5416GetNextTBTT; 165 166 /* 802.11n Functions */ 167 ah->ah_chainTxDesc = ar5416ChainTxDesc; 168 ah->ah_setupFirstTxDesc = ar5416SetupFirstTxDesc; 169 ah->ah_setupLastTxDesc = ar5416SetupLastTxDesc; 170 ah->ah_set11nRateScenario = ar5416Set11nRateScenario; 171 ah->ah_set11nAggrFirst = ar5416Set11nAggrFirst; 172 ah->ah_set11nAggrMiddle = ar5416Set11nAggrMiddle; 173 ah->ah_set11nAggrLast = ar5416Set11nAggrLast; 174 ah->ah_clr11nAggr = ar5416Clr11nAggr; 175 ah->ah_set11nBurstDuration = ar5416Set11nBurstDuration; 176 ah->ah_get11nExtBusy = ar5416Get11nExtBusy; 177 ah->ah_set11nMac2040 = ar5416Set11nMac2040; 178 ah->ah_get11nRxClear = ar5416Get11nRxClear; 179 ah->ah_set11nRxClear = ar5416Set11nRxClear; 180 181 /* Interrupt functions */ 182 ah->ah_isInterruptPending = ar5416IsInterruptPending; 183 ah->ah_getPendingInterrupts = ar5416GetPendingInterrupts; 184 ah->ah_setInterrupts = ar5416SetInterrupts; 185 186 ahp->ah_priv.ah_getWirelessModes= ar5416GetWirelessModes; 187 ahp->ah_priv.ah_eepromRead = ar5416EepromRead; 188#ifdef AH_SUPPORT_WRITE_EEPROM 189 ahp->ah_priv.ah_eepromWrite = ar5416EepromWrite; 190#endif 191 ahp->ah_priv.ah_getChipPowerLimits = ar5416GetChipPowerLimits; 192 193 /* Internal ops */ 194 AH5416(ah)->ah_writeIni = ar5416WriteIni; 195 AH5416(ah)->ah_spurMitigate = ar5416SpurMitigate; 196 197 /* Internal baseband ops */ 198 AH5416(ah)->ah_initPLL = ar5416InitPLL; 199 200 /* Internal calibration ops */ 201 AH5416(ah)->ah_cal_initcal = ar5416InitCalHardware; 202 203 /* Internal TX power control related operations */ 204 AH5416(ah)->ah_olcInit = ar5416olcInit; 205 AH5416(ah)->ah_olcTempCompensation = ar5416olcTempCompensation; 206 AH5416(ah)->ah_setPowerCalTable = ar5416SetPowerCalTable; 207 208 /* 209 * Start by setting all Owl devices to 2x2 210 */ 211 AH5416(ah)->ah_rx_chainmask = AR5416_DEFAULT_RXCHAINMASK; 212 AH5416(ah)->ah_tx_chainmask = AR5416_DEFAULT_TXCHAINMASK; 213 214 /* Enable all ANI functions to begin with */ 215 AH5416(ah)->ah_ani_function = 0xffffffff; 216 217 /* Set overridable ANI methods */ 218 AH5212(ah)->ah_aniControl = ar5416AniControl; 219} 220 221uint32_t 222ar5416GetRadioRev(struct ath_hal *ah) 223{ 224 uint32_t val; 225 int i; 226 227 /* Read Radio Chip Rev Extract */ 228 OS_REG_WRITE(ah, AR_PHY(0x36), 0x00007058); 229 for (i = 0; i < 8; i++) 230 OS_REG_WRITE(ah, AR_PHY(0x20), 0x00010000); 231 val = (OS_REG_READ(ah, AR_PHY(256)) >> 24) & 0xff; 232 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4); 233 return ath_hal_reverseBits(val, 8); 234} 235 236/* 237 * Attach for an AR5416 part. 238 */ 239static struct ath_hal * 240ar5416Attach(uint16_t devid, HAL_SOFTC sc, 241 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata, 242 HAL_STATUS *status) 243{ 244 struct ath_hal_5416 *ahp5416; 245 struct ath_hal_5212 *ahp; 246 struct ath_hal *ah; 247 uint32_t val; 248 HAL_STATUS ecode; 249 HAL_BOOL rfStatus; 250 251 HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n", 252 __func__, sc, (void*) st, (void*) sh); 253 254 /* NB: memory is returned zero'd */ 255 ahp5416 = ath_hal_malloc(sizeof (struct ath_hal_5416) + 256 /* extra space for Owl 2.1/2.2 WAR */ 257 sizeof(ar5416Addac) 258 ); 259 if (ahp5416 == AH_NULL) { 260 HALDEBUG(AH_NULL, HAL_DEBUG_ANY, 261 "%s: cannot allocate memory for state block\n", __func__); 262 *status = HAL_ENOMEM; 263 return AH_NULL; 264 } 265 ar5416InitState(ahp5416, devid, sc, st, sh, status); 266 ahp = &ahp5416->ah_5212; 267 ah = &ahp->ah_priv.h; 268 269 if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) { 270 /* reset chip */ 271 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n", __func__); 272 ecode = HAL_EIO; 273 goto bad; 274 } 275 276 if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) { 277 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n", __func__); 278 ecode = HAL_EIO; 279 goto bad; 280 } 281 /* Read Revisions from Chips before taking out of reset */ 282 val = OS_REG_READ(ah, AR_SREV) & AR_SREV_ID; 283 AH_PRIVATE(ah)->ah_macVersion = val >> AR_SREV_ID_S; 284 AH_PRIVATE(ah)->ah_macRev = val & AR_SREV_REVISION; 285 AH_PRIVATE(ah)->ah_ispcie = (devid == AR5416_DEVID_PCIE); 286 287 /* setup common ini data; rf backends handle remainder */ 288 HAL_INI_INIT(&ahp->ah_ini_modes, ar5416Modes, 6); 289 HAL_INI_INIT(&ahp->ah_ini_common, ar5416Common, 2); 290 291 HAL_INI_INIT(&AH5416(ah)->ah_ini_bb_rfgain, ar5416BB_RfGain, 3); 292 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank0, ar5416Bank0, 2); 293 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank1, ar5416Bank1, 2); 294 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank2, ar5416Bank2, 2); 295 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank3, ar5416Bank3, 3); 296 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank6, ar5416Bank6, 3); 297 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank7, ar5416Bank7, 2); 298 HAL_INI_INIT(&AH5416(ah)->ah_ini_addac, ar5416Addac, 2); 299 300 if (! IS_5416V2_2(ah)) { /* Owl 2.1/2.0 */ 301 ath_hal_printf(ah, "[ath] Enabling CLKDRV workaround for AR5416 < v2.2\n"); 302 struct ini { 303 uint32_t *data; /* NB: !const */ 304 int rows, cols; 305 }; 306 /* override CLKDRV value */ 307 OS_MEMCPY(&AH5416(ah)[1], ar5416Addac, sizeof(ar5416Addac)); 308 AH5416(ah)->ah_ini_addac.data = (uint32_t *) &AH5416(ah)[1]; 309 HAL_INI_VAL((struct ini *)&AH5416(ah)->ah_ini_addac, 31, 1) = 0; 310 } 311 312 HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes, ar5416PciePhy, 2); 313 ar5416AttachPCIE(ah); 314 315 ecode = ath_hal_v14EepromAttach(ah); 316 if (ecode != HAL_OK) 317 goto bad; 318 319 if (!ar5416ChipReset(ah, AH_NULL)) { /* reset chip */ 320 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", 321 __func__); 322 ecode = HAL_EIO; 323 goto bad; 324 } 325 326 AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID); 327 328 if (!ar5212ChipTest(ah)) { 329 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n", 330 __func__); 331 ecode = HAL_ESELFTEST; 332 goto bad; 333 } 334 335 /* 336 * Set correct Baseband to analog shift 337 * setting to access analog chips. 338 */ 339 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 340 341 /* Read Radio Chip Rev Extract */ 342 AH_PRIVATE(ah)->ah_analog5GhzRev = ar5212GetRadioRev(ah); 343 switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) { 344 case AR_RAD5122_SREV_MAJOR: /* Fowl: 5G/2x2 */ 345 case AR_RAD2122_SREV_MAJOR: /* Fowl: 2+5G/2x2 */ 346 case AR_RAD2133_SREV_MAJOR: /* Fowl: 2G/3x3 */ 347 case AR_RAD5133_SREV_MAJOR: /* Fowl: 2+5G/3x3 */ 348 break; 349 default: 350 if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) { 351 /* 352 * When RF_Silen is used the analog chip is reset. 353 * So when the system boots with radio switch off 354 * the RF chip rev reads back as zero and we need 355 * to use the mac+phy revs to set the radio rev. 356 */ 357 AH_PRIVATE(ah)->ah_analog5GhzRev = 358 AR_RAD5133_SREV_MAJOR; 359 break; 360 } 361 /* NB: silently accept anything in release code per Atheros */ 362#ifdef AH_DEBUG 363 HALDEBUG(ah, HAL_DEBUG_ANY, 364 "%s: 5G Radio Chip Rev 0x%02X is not supported by " 365 "this driver\n", __func__, 366 AH_PRIVATE(ah)->ah_analog5GhzRev); 367 ecode = HAL_ENOTSUPP; 368 goto bad; 369#endif 370 } 371 372 /* 373 * Got everything we need now to setup the capabilities. 374 */ 375 if (!ar5416FillCapabilityInfo(ah)) { 376 ecode = HAL_EEREAD; 377 goto bad; 378 } 379 380 ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr); 381 if (ecode != HAL_OK) { 382 HALDEBUG(ah, HAL_DEBUG_ANY, 383 "%s: error getting mac address from EEPROM\n", __func__); 384 goto bad; 385 } 386 /* XXX How about the serial number ? */ 387 /* Read Reg Domain */ 388 AH_PRIVATE(ah)->ah_currentRD = 389 ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL); 390 AH_PRIVATE(ah)->ah_currentRDext = 391 ath_hal_eepromGet(ah, AR_EEP_REGDMN_1, AH_NULL); 392 393 /* 394 * ah_miscMode is populated by ar5416FillCapabilityInfo() 395 * starting from griffin. Set here to make sure that 396 * AR_MISC_MODE_MIC_NEW_LOC_ENABLE is set before a GTK is 397 * placed into hardware. 398 */ 399 if (ahp->ah_miscMode != 0) 400 OS_REG_WRITE(ah, AR_MISC_MODE, OS_REG_READ(ah, AR_MISC_MODE) | ahp->ah_miscMode); 401 402 rfStatus = ar2133RfAttach(ah, &ecode); 403 if (!rfStatus) { 404 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n", 405 __func__, ecode); 406 goto bad; 407 } 408 409 ar5416AniSetup(ah); /* Anti Noise Immunity */ 410 411 AH5416(ah)->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_2GHZ; 412 AH5416(ah)->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_2GHZ; 413 AH5416(ah)->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_5416_2GHZ; 414 AH5416(ah)->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_5GHZ; 415 AH5416(ah)->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_5GHZ; 416 AH5416(ah)->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_5416_5GHZ; 417 418 ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist); 419 420 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__); 421 422 return ah; 423bad: 424 if (ahp) 425 ar5416Detach((struct ath_hal *) ahp); 426 if (status) 427 *status = ecode; 428 return AH_NULL; 429} 430 431void 432ar5416Detach(struct ath_hal *ah) 433{ 434 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s:\n", __func__); 435 436 HALASSERT(ah != AH_NULL); 437 HALASSERT(ah->ah_magic == AR5416_MAGIC); 438 439 /* Make sure that chip is awake before writing to it */ 440 if (! ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) 441 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, 442 "%s: failed to wake up chip\n", 443 __func__); 444 445 ar5416AniDetach(ah); 446 ar5212RfDetach(ah); 447 ah->ah_disable(ah); 448 ar5416SetPowerMode(ah, HAL_PM_FULL_SLEEP, AH_TRUE); 449 ath_hal_eepromDetach(ah); 450 ath_hal_free(ah); 451} 452 453void 454ar5416AttachPCIE(struct ath_hal *ah) 455{ 456 if (AH_PRIVATE(ah)->ah_ispcie) 457 ath_hal_configPCIE(ah, AH_FALSE); 458 else 459 ath_hal_disablePCIE(ah); 460} 461 462static void 463ar5416ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore) 464{ 465 if (AH_PRIVATE(ah)->ah_ispcie && !restore) { 466 ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0); 467 OS_DELAY(1000); 468 OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 469 OS_REG_WRITE(ah, AR_WA, AR_WA_DEFAULT); 470 } 471} 472 473static void 474ar5416WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan) 475{ 476 u_int modesIndex, freqIndex; 477 int regWrites = 0; 478 479 /* Setup the indices for the next set of register array writes */ 480 /* XXX Ignore 11n dynamic mode on the AR5416 for the moment */ 481 if (IEEE80211_IS_CHAN_2GHZ(chan)) { 482 freqIndex = 2; 483 if (IEEE80211_IS_CHAN_HT40(chan)) 484 modesIndex = 3; 485 else if (IEEE80211_IS_CHAN_108G(chan)) 486 modesIndex = 5; 487 else 488 modesIndex = 4; 489 } else { 490 freqIndex = 1; 491 if (IEEE80211_IS_CHAN_HT40(chan) || 492 IEEE80211_IS_CHAN_TURBO(chan)) 493 modesIndex = 2; 494 else 495 modesIndex = 1; 496 } 497 498 /* Set correct Baseband to analog shift setting to access analog chips. */ 499 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 500 501 /* 502 * Write addac shifts 503 */ 504 OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO); 505 506 /* NB: only required for Sowl */ 507 if (AR_SREV_SOWL(ah)) 508 ar5416EepromSetAddac(ah, chan); 509 510 regWrites = ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_addac, 1, 511 regWrites); 512 OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC); 513 514 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes, 515 modesIndex, regWrites); 516 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common, 517 1, regWrites); 518 519 /* XXX updated regWrites? */ 520 AH5212(ah)->ah_rfHal->writeRegs(ah, modesIndex, freqIndex, regWrites); 521} 522 523/* 524 * Convert to baseband spur frequency given input channel frequency 525 * and compute register settings below. 526 */ 527 528static void 529ar5416SpurMitigate(struct ath_hal *ah, const struct ieee80211_channel *chan) 530{ 531 uint16_t freq = ath_hal_gethwchannel(ah, chan); 532 static const int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8, 533 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60 }; 534 static const int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10, 535 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60 }; 536 static const int inc[4] = { 0, 100, 0, 0 }; 537 538 int bb_spur = AR_NO_SPUR; 539 int bin, cur_bin; 540 int spur_freq_sd; 541 int spur_delta_phase; 542 int denominator; 543 int upper, lower, cur_vit_mask; 544 int tmp, new; 545 int i; 546 547 int8_t mask_m[123]; 548 int8_t mask_p[123]; 549 int8_t mask_amt; 550 int tmp_mask; 551 int cur_bb_spur; 552 HAL_BOOL is2GHz = IEEE80211_IS_CHAN_2GHZ(chan); 553 554 OS_MEMZERO(mask_m, sizeof(mask_m)); 555 OS_MEMZERO(mask_p, sizeof(mask_p)); 556 557 /* 558 * Need to verify range +/- 9.5 for static ht20, otherwise spur 559 * is out-of-band and can be ignored. 560 */ 561 /* XXX ath9k changes */ 562 for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) { 563 cur_bb_spur = ath_hal_getSpurChan(ah, i, is2GHz); 564 if (AR_NO_SPUR == cur_bb_spur) 565 break; 566 cur_bb_spur = cur_bb_spur - (freq * 10); 567 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) { 568 bb_spur = cur_bb_spur; 569 break; 570 } 571 } 572 if (AR_NO_SPUR == bb_spur) 573 return; 574 575 bin = bb_spur * 32; 576 577 tmp = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4_CHAIN(0)); 578 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI | 579 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER | 580 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK | 581 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK); 582 583 OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4_CHAIN(0), new); 584 585 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL | 586 AR_PHY_SPUR_REG_ENABLE_MASK_PPM | 587 AR_PHY_SPUR_REG_MASK_RATE_SELECT | 588 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI | 589 SM(AR5416_SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH)); 590 OS_REG_WRITE(ah, AR_PHY_SPUR_REG, new); 591 /* 592 * Should offset bb_spur by +/- 10 MHz for dynamic 2040 MHz 593 * config, no offset for HT20. 594 * spur_delta_phase = bb_spur/40 * 2**21 for static ht20, 595 * /80 for dyn2040. 596 */ 597 spur_delta_phase = ((bb_spur * 524288) / 100) & 598 AR_PHY_TIMING11_SPUR_DELTA_PHASE; 599 /* 600 * in 11A mode the denominator of spur_freq_sd should be 40 and 601 * it should be 44 in 11G 602 */ 603 denominator = IEEE80211_IS_CHAN_2GHZ(chan) ? 440 : 400; 604 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff; 605 606 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC | 607 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) | 608 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE)); 609 OS_REG_WRITE(ah, AR_PHY_TIMING11, new); 610 611 612 /* 613 * ============================================ 614 * pilot mask 1 [31:0] = +6..-26, no 0 bin 615 * pilot mask 2 [19:0] = +26..+7 616 * 617 * channel mask 1 [31:0] = +6..-26, no 0 bin 618 * channel mask 2 [19:0] = +26..+7 619 */ 620 //cur_bin = -26; 621 cur_bin = -6000; 622 upper = bin + 100; 623 lower = bin - 100; 624 625 for (i = 0; i < 4; i++) { 626 int pilot_mask = 0; 627 int chan_mask = 0; 628 int bp = 0; 629 for (bp = 0; bp < 30; bp++) { 630 if ((cur_bin > lower) && (cur_bin < upper)) { 631 pilot_mask = pilot_mask | 0x1 << bp; 632 chan_mask = chan_mask | 0x1 << bp; 633 } 634 cur_bin += 100; 635 } 636 cur_bin += inc[i]; 637 OS_REG_WRITE(ah, pilot_mask_reg[i], pilot_mask); 638 OS_REG_WRITE(ah, chan_mask_reg[i], chan_mask); 639 } 640 641 /* ================================================= 642 * viterbi mask 1 based on channel magnitude 643 * four levels 0-3 644 * - mask (-27 to 27) (reg 64,0x9900 to 67,0x990c) 645 * [1 2 2 1] for -9.6 or [1 2 1] for +16 646 * - enable_mask_ppm, all bins move with freq 647 * 648 * - mask_select, 8 bits for rates (reg 67,0x990c) 649 * - mask_rate_cntl, 8 bits for rates (reg 67,0x990c) 650 * choose which mask to use mask or mask2 651 */ 652 653 /* 654 * viterbi mask 2 2nd set for per data rate puncturing 655 * four levels 0-3 656 * - mask_select, 8 bits for rates (reg 67) 657 * - mask (-27 to 27) (reg 98,0x9988 to 101,0x9994) 658 * [1 2 2 1] for -9.6 or [1 2 1] for +16 659 */ 660 cur_vit_mask = 6100; 661 upper = bin + 120; 662 lower = bin - 120; 663 664 for (i = 0; i < 123; i++) { 665 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) { 666 if ((abs(cur_vit_mask - bin)) < 75) { 667 mask_amt = 1; 668 } else { 669 mask_amt = 0; 670 } 671 if (cur_vit_mask < 0) { 672 mask_m[abs(cur_vit_mask / 100)] = mask_amt; 673 } else { 674 mask_p[cur_vit_mask / 100] = mask_amt; 675 } 676 } 677 cur_vit_mask -= 100; 678 } 679 680 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28) 681 | (mask_m[48] << 26) | (mask_m[49] << 24) 682 | (mask_m[50] << 22) | (mask_m[51] << 20) 683 | (mask_m[52] << 18) | (mask_m[53] << 16) 684 | (mask_m[54] << 14) | (mask_m[55] << 12) 685 | (mask_m[56] << 10) | (mask_m[57] << 8) 686 | (mask_m[58] << 6) | (mask_m[59] << 4) 687 | (mask_m[60] << 2) | (mask_m[61] << 0); 688 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask); 689 OS_REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask); 690 691 tmp_mask = (mask_m[31] << 28) 692 | (mask_m[32] << 26) | (mask_m[33] << 24) 693 | (mask_m[34] << 22) | (mask_m[35] << 20) 694 | (mask_m[36] << 18) | (mask_m[37] << 16) 695 | (mask_m[48] << 14) | (mask_m[39] << 12) 696 | (mask_m[40] << 10) | (mask_m[41] << 8) 697 | (mask_m[42] << 6) | (mask_m[43] << 4) 698 | (mask_m[44] << 2) | (mask_m[45] << 0); 699 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask); 700 OS_REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask); 701 702 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28) 703 | (mask_m[18] << 26) | (mask_m[18] << 24) 704 | (mask_m[20] << 22) | (mask_m[20] << 20) 705 | (mask_m[22] << 18) | (mask_m[22] << 16) 706 | (mask_m[24] << 14) | (mask_m[24] << 12) 707 | (mask_m[25] << 10) | (mask_m[26] << 8) 708 | (mask_m[27] << 6) | (mask_m[28] << 4) 709 | (mask_m[29] << 2) | (mask_m[30] << 0); 710 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask); 711 OS_REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask); 712 713 tmp_mask = (mask_m[ 0] << 30) | (mask_m[ 1] << 28) 714 | (mask_m[ 2] << 26) | (mask_m[ 3] << 24) 715 | (mask_m[ 4] << 22) | (mask_m[ 5] << 20) 716 | (mask_m[ 6] << 18) | (mask_m[ 7] << 16) 717 | (mask_m[ 8] << 14) | (mask_m[ 9] << 12) 718 | (mask_m[10] << 10) | (mask_m[11] << 8) 719 | (mask_m[12] << 6) | (mask_m[13] << 4) 720 | (mask_m[14] << 2) | (mask_m[15] << 0); 721 OS_REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask); 722 OS_REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask); 723 724 tmp_mask = (mask_p[15] << 28) 725 | (mask_p[14] << 26) | (mask_p[13] << 24) 726 | (mask_p[12] << 22) | (mask_p[11] << 20) 727 | (mask_p[10] << 18) | (mask_p[ 9] << 16) 728 | (mask_p[ 8] << 14) | (mask_p[ 7] << 12) 729 | (mask_p[ 6] << 10) | (mask_p[ 5] << 8) 730 | (mask_p[ 4] << 6) | (mask_p[ 3] << 4) 731 | (mask_p[ 2] << 2) | (mask_p[ 1] << 0); 732 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask); 733 OS_REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask); 734 735 tmp_mask = (mask_p[30] << 28) 736 | (mask_p[29] << 26) | (mask_p[28] << 24) 737 | (mask_p[27] << 22) | (mask_p[26] << 20) 738 | (mask_p[25] << 18) | (mask_p[24] << 16) 739 | (mask_p[23] << 14) | (mask_p[22] << 12) 740 | (mask_p[21] << 10) | (mask_p[20] << 8) 741 | (mask_p[19] << 6) | (mask_p[18] << 4) 742 | (mask_p[17] << 2) | (mask_p[16] << 0); 743 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask); 744 OS_REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask); 745 746 tmp_mask = (mask_p[45] << 28) 747 | (mask_p[44] << 26) | (mask_p[43] << 24) 748 | (mask_p[42] << 22) | (mask_p[41] << 20) 749 | (mask_p[40] << 18) | (mask_p[39] << 16) 750 | (mask_p[38] << 14) | (mask_p[37] << 12) 751 | (mask_p[36] << 10) | (mask_p[35] << 8) 752 | (mask_p[34] << 6) | (mask_p[33] << 4) 753 | (mask_p[32] << 2) | (mask_p[31] << 0); 754 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask); 755 OS_REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask); 756 757 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28) 758 | (mask_p[59] << 26) | (mask_p[58] << 24) 759 | (mask_p[57] << 22) | (mask_p[56] << 20) 760 | (mask_p[55] << 18) | (mask_p[54] << 16) 761 | (mask_p[53] << 14) | (mask_p[52] << 12) 762 | (mask_p[51] << 10) | (mask_p[50] << 8) 763 | (mask_p[49] << 6) | (mask_p[48] << 4) 764 | (mask_p[47] << 2) | (mask_p[46] << 0); 765 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask); 766 OS_REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); 767} 768 769/* 770 * Fill all software cached or static hardware state information. 771 * Return failure if capabilities are to come from EEPROM and 772 * cannot be read. 773 */ 774HAL_BOOL 775ar5416FillCapabilityInfo(struct ath_hal *ah) 776{ 777 struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 778 HAL_CAPABILITIES *pCap = &ahpriv->ah_caps; 779 uint16_t val; 780 781 /* Construct wireless mode from EEPROM */ 782 pCap->halWirelessModes = 0; 783 if (ath_hal_eepromGetFlag(ah, AR_EEP_AMODE)) { 784 pCap->halWirelessModes |= HAL_MODE_11A 785 | HAL_MODE_11NA_HT20 786 | HAL_MODE_11NA_HT40PLUS 787 | HAL_MODE_11NA_HT40MINUS 788 ; 789 } 790 if (ath_hal_eepromGetFlag(ah, AR_EEP_GMODE)) { 791 pCap->halWirelessModes |= HAL_MODE_11G 792 | HAL_MODE_11NG_HT20 793 | HAL_MODE_11NG_HT40PLUS 794 | HAL_MODE_11NG_HT40MINUS 795 ; 796 pCap->halWirelessModes |= HAL_MODE_11A 797 | HAL_MODE_11NA_HT20 798 | HAL_MODE_11NA_HT40PLUS 799 | HAL_MODE_11NA_HT40MINUS 800 ; 801 } 802 803 pCap->halLow2GhzChan = 2312; 804 pCap->halHigh2GhzChan = 2732; 805 806 pCap->halLow5GhzChan = 4915; 807 pCap->halHigh5GhzChan = 6100; 808 809 pCap->halCipherCkipSupport = AH_FALSE; 810 pCap->halCipherTkipSupport = AH_TRUE; 811 pCap->halCipherAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES); 812 813 pCap->halMicCkipSupport = AH_FALSE; 814 pCap->halMicTkipSupport = AH_TRUE; 815 pCap->halMicAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES); 816 /* 817 * Starting with Griffin TX+RX mic keys can be combined 818 * in one key cache slot. 819 */ 820 pCap->halTkipMicTxRxKeySupport = AH_TRUE; 821 pCap->halChanSpreadSupport = AH_TRUE; 822 pCap->halSleepAfterBeaconBroken = AH_TRUE; 823 824 pCap->halCompressSupport = AH_FALSE; 825 pCap->halBurstSupport = AH_TRUE; 826 pCap->halFastFramesSupport = AH_FALSE; /* XXX? */ 827 pCap->halChapTuningSupport = AH_TRUE; 828 pCap->halTurboPrimeSupport = AH_TRUE; 829 830 pCap->halTurboGSupport = pCap->halWirelessModes & HAL_MODE_108G; 831 832 pCap->halPSPollBroken = AH_TRUE; /* XXX fixed in later revs? */ 833 pCap->halVEOLSupport = AH_TRUE; 834 pCap->halBssIdMaskSupport = AH_TRUE; 835 pCap->halMcastKeySrchSupport = AH_TRUE; /* Works on AR5416 and later */ 836 pCap->halTsfAddSupport = AH_TRUE; 837 pCap->hal4AddrAggrSupport = AH_FALSE; /* Broken in Owl */ 838 839 if (ath_hal_eepromGet(ah, AR_EEP_MAXQCU, &val) == HAL_OK) 840 pCap->halTotalQueues = val; 841 else 842 pCap->halTotalQueues = HAL_NUM_TX_QUEUES; 843 844 if (ath_hal_eepromGet(ah, AR_EEP_KCENTRIES, &val) == HAL_OK) 845 pCap->halKeyCacheSize = val; 846 else 847 pCap->halKeyCacheSize = AR5416_KEYTABLE_SIZE; 848 849 /* XXX not needed */ 850 pCap->halChanHalfRate = AH_FALSE; /* XXX ? */ 851 pCap->halChanQuarterRate = AH_FALSE; /* XXX ? */ 852 853 pCap->halTstampPrecision = 32; 854 pCap->halHwPhyCounterSupport = AH_TRUE; 855 pCap->halIntrMask = HAL_INT_COMMON 856 | HAL_INT_RX 857 | HAL_INT_TX 858 | HAL_INT_FATAL 859 | HAL_INT_BNR 860 | HAL_INT_BMISC 861 | HAL_INT_DTIMSYNC 862 | HAL_INT_TSFOOR 863 | HAL_INT_CST 864 | HAL_INT_GTT 865 ; 866 867 pCap->halFastCCSupport = AH_TRUE; 868 pCap->halNumGpioPins = 6; 869 pCap->halWowSupport = AH_FALSE; 870 pCap->halWowMatchPatternExact = AH_FALSE; 871 pCap->halBtCoexSupport = AH_FALSE; /* XXX need support */ 872 pCap->halAutoSleepSupport = AH_FALSE; 873 pCap->hal4kbSplitTransSupport = AH_TRUE; 874 /* Disable this so Block-ACK works correctly */ 875 pCap->halHasRxSelfLinkedTail = AH_FALSE; 876#if 0 /* XXX not yet */ 877 pCap->halNumAntCfg2GHz = ar5416GetNumAntConfig(ahp, HAL_FREQ_BAND_2GHZ); 878 pCap->halNumAntCfg5GHz = ar5416GetNumAntConfig(ahp, HAL_FREQ_BAND_5GHZ); 879#endif 880 pCap->halHTSupport = AH_TRUE; 881 pCap->halTxChainMask = ath_hal_eepromGet(ah, AR_EEP_TXMASK, AH_NULL); 882 /* XXX CB71 uses GPIO 0 to indicate 3 rx chains */ 883 pCap->halRxChainMask = ath_hal_eepromGet(ah, AR_EEP_RXMASK, AH_NULL); 884 /* AR5416 may have 3 antennas but is a 2x2 stream device */ 885 pCap->halTxStreams = 2; 886 pCap->halRxStreams = 2; 887 pCap->halRtsAggrLimit = 8*1024; /* Owl 2.0 limit */ 888 pCap->halMbssidAggrSupport = AH_FALSE; /* Broken on Owl */ 889 pCap->halForcePpmSupport = AH_TRUE; 890 pCap->halEnhancedPmSupport = AH_TRUE; 891 pCap->halBssidMatchSupport = AH_TRUE; 892 pCap->halGTTSupport = AH_TRUE; 893 pCap->halCSTSupport = AH_TRUE; 894 pCap->halEnhancedDfsSupport = AH_FALSE; 895 /* Hardware supports 32 bit TSF values in the RX descriptor */ 896 pCap->halHasLongRxDescTsf = AH_TRUE; 897 /* 898 * BB Read WAR: this is only for AR5008/AR9001 NICs 899 * It is also set individually in the AR91xx attach functions. 900 */ 901 if (AR_SREV_OWL(ah)) 902 pCap->halHasBBReadWar = AH_TRUE; 903 904 if (ath_hal_eepromGetFlag(ah, AR_EEP_RFKILL) && 905 ath_hal_eepromGet(ah, AR_EEP_RFSILENT, &ahpriv->ah_rfsilent) == HAL_OK) { 906 /* NB: enabled by default */ 907 ahpriv->ah_rfkillEnabled = AH_TRUE; 908 pCap->halRfSilentSupport = AH_TRUE; 909 } 910 911 ahpriv->ah_rxornIsFatal = AH_FALSE; 912 913 return AH_TRUE; 914} 915 916static const char* 917ar5416Probe(uint16_t vendorid, uint16_t devid) 918{ 919 if (vendorid == ATHEROS_VENDOR_ID && 920 (devid == AR5416_DEVID_PCI || devid == AR5416_DEVID_PCIE)) 921 return "Atheros 5416"; 922 return AH_NULL; 923} 924AH_CHIP(AR5416, ar5416Probe, ar5416Attach); 925