1185377Ssam/* 2185377Ssam * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3185377Ssam * Copyright (c) 2002-2008 Atheros Communications, Inc. 4185377Ssam * 5185377Ssam * Permission to use, copy, modify, and/or distribute this software for any 6185377Ssam * purpose with or without fee is hereby granted, provided that the above 7185377Ssam * copyright notice and this permission notice appear in all copies. 8185377Ssam * 9185377Ssam * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10185377Ssam * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11185377Ssam * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12185377Ssam * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13185377Ssam * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14185377Ssam * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15185377Ssam * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16185377Ssam * 17204644Srpaulo * $FreeBSD$ 18185377Ssam */ 19185377Ssam#ifndef _ATH_AR5212_DESC_H_ 20185377Ssam#define _ATH_AR5212_DESC_H_ 21185377Ssam 22185377Ssam/* 23185377Ssam * Hardware-specific descriptor structures. 24185377Ssam */ 25185377Ssam 26185377Ssam/* 27185377Ssam * AR5212-specific tx/rx descriptor definition. 28185377Ssam */ 29185377Ssamstruct ar5212_desc { 30185377Ssam uint32_t ds_link; /* link pointer */ 31185377Ssam uint32_t ds_data; /* data buffer pointer */ 32185377Ssam uint32_t ds_ctl0; /* DMA control 0 */ 33185377Ssam uint32_t ds_ctl1; /* DMA control 1 */ 34185377Ssam union { 35185377Ssam struct { /* xmit format */ 36185377Ssam uint32_t ctl2; /* DMA control 2 */ 37185377Ssam uint32_t ctl3; /* DMA control 3 */ 38185377Ssam uint32_t status0;/* DMA status 0 */ 39185377Ssam uint32_t status1;/* DMA status 1 */ 40185377Ssam } tx; 41185377Ssam struct { /* recv format */ 42185377Ssam uint32_t status0;/* DMA status 0 */ 43185377Ssam uint32_t status1;/* DMA status 1 */ 44185377Ssam } rx; 45185377Ssam } u; 46185377Ssam} __packed; 47185377Ssam#define AR5212DESC(_ds) ((struct ar5212_desc *)(_ds)) 48185377Ssam#define AR5212DESC_CONST(_ds) ((const struct ar5212_desc *)(_ds)) 49185377Ssam 50185377Ssam#define ds_ctl2 u.tx.ctl2 51185377Ssam#define ds_ctl3 u.tx.ctl3 52185377Ssam#define ds_txstatus0 u.tx.status0 53185377Ssam#define ds_txstatus1 u.tx.status1 54185377Ssam#define ds_rxstatus0 u.rx.status0 55185377Ssam#define ds_rxstatus1 u.rx.status1 56185377Ssam 57185377Ssam/* TX ds_ctl0 */ 58185377Ssam#define AR_FrameLen 0x00000fff /* frame length */ 59185377Ssam/* bits 12-15 are reserved */ 60185377Ssam#define AR_XmitPower 0x003f0000 /* transmit power control */ 61185377Ssam#define AR_XmitPower_S 16 62185377Ssam#define AR_RTSCTSEnable 0x00400000 /* RTS/CTS protocol enable */ 63185377Ssam#define AR_VEOL 0x00800000 /* virtual end-of-list */ 64185377Ssam#define AR_ClearDestMask 0x01000000 /* Clear destination mask bit */ 65185377Ssam#define AR_AntModeXmit 0x1e000000 /* TX antenna seslection */ 66185377Ssam#define AR_AntModeXmit_S 25 67185377Ssam#define AR_TxInterReq 0x20000000 /* TX interrupt request */ 68185377Ssam#define AR_DestIdxValid 0x40000000 /* destination index valid */ 69185377Ssam#define AR_CTSEnable 0x80000000 /* precede frame with CTS */ 70185377Ssam 71185377Ssam/* TX ds_ctl1 */ 72185377Ssam#define AR_BufLen 0x00000fff /* data buffer length */ 73185377Ssam#define AR_More 0x00001000 /* more desc in this frame */ 74185377Ssam#define AR_DestIdx 0x000fe000 /* destination table index */ 75185377Ssam#define AR_DestIdx_S 13 76185377Ssam#define AR_FrmType 0x00f00000 /* frame type indication */ 77185377Ssam#define AR_FrmType_S 20 78185377Ssam#define AR_NoAck 0x01000000 /* No ACK flag */ 79185377Ssam#define AR_CompProc 0x06000000 /* compression processing */ 80185377Ssam#define AR_CompProc_S 25 81185377Ssam#define AR_CompIVLen 0x18000000 /* length of frame IV */ 82185377Ssam#define AR_CompIVLen_S 27 83185377Ssam#define AR_CompICVLen 0x60000000 /* length of frame ICV */ 84185377Ssam#define AR_CompICVLen_S 29 85185377Ssam/* bit 31 is reserved */ 86185377Ssam 87185377Ssam/* TX ds_ctl2 */ 88185377Ssam#define AR_RTSCTSDuration 0x00007fff /* RTS/CTS duration */ 89185377Ssam#define AR_RTSCTSDuration_S 0 90185377Ssam#define AR_DurUpdateEna 0x00008000 /* frame duration update ctl */ 91185377Ssam#define AR_XmitDataTries0 0x000f0000 /* series 0 max attempts */ 92185377Ssam#define AR_XmitDataTries0_S 16 93185377Ssam#define AR_XmitDataTries1 0x00f00000 /* series 1 max attempts */ 94185377Ssam#define AR_XmitDataTries1_S 20 95185377Ssam#define AR_XmitDataTries2 0x0f000000 /* series 2 max attempts */ 96185377Ssam#define AR_XmitDataTries2_S 24 97185377Ssam#define AR_XmitDataTries3 0xf0000000 /* series 3 max attempts */ 98185377Ssam#define AR_XmitDataTries3_S 28 99185377Ssam 100185377Ssam/* TX ds_ctl3 */ 101185377Ssam#define AR_XmitRate0 0x0000001f /* series 0 tx rate */ 102185377Ssam#define AR_XmitRate0_S 0 103185377Ssam#define AR_XmitRate1 0x000003e0 /* series 1 tx rate */ 104185377Ssam#define AR_XmitRate1_S 5 105185377Ssam#define AR_XmitRate2 0x00007c00 /* series 2 tx rate */ 106185377Ssam#define AR_XmitRate2_S 10 107185377Ssam#define AR_XmitRate3 0x000f8000 /* series 3 tx rate */ 108185377Ssam#define AR_XmitRate3_S 15 109185377Ssam#define AR_RTSCTSRate 0x01f00000 /* RTS or CTS rate */ 110185377Ssam#define AR_RTSCTSRate_S 20 111185377Ssam/* bits 25-31 are reserved */ 112185377Ssam 113185377Ssam/* RX ds_ctl1 */ 114185377Ssam/* AR_BufLen 0x00000fff data buffer length */ 115185377Ssam/* bit 12 is reserved */ 116185377Ssam#define AR_RxInterReq 0x00002000 /* RX interrupt request */ 117185377Ssam/* bits 14-31 are reserved */ 118185377Ssam 119185377Ssam/* TX ds_txstatus0 */ 120185377Ssam#define AR_FrmXmitOK 0x00000001 /* TX success */ 121185377Ssam#define AR_ExcessiveRetries 0x00000002 /* excessive retries */ 122185377Ssam#define AR_FIFOUnderrun 0x00000004 /* TX FIFO underrun */ 123185377Ssam#define AR_Filtered 0x00000008 /* TX filter indication */ 124185377Ssam#define AR_RTSFailCnt 0x000000f0 /* RTS failure count */ 125185377Ssam#define AR_RTSFailCnt_S 4 126185377Ssam#define AR_DataFailCnt 0x00000f00 /* Data failure count */ 127185377Ssam#define AR_DataFailCnt_S 8 128185377Ssam#define AR_VirtCollCnt 0x0000f000 /* virtual collision count */ 129185377Ssam#define AR_VirtCollCnt_S 12 130185377Ssam#define AR_SendTimestamp 0xffff0000 /* TX timestamp */ 131185377Ssam#define AR_SendTimestamp_S 16 132185377Ssam 133185377Ssam/* RX ds_rxstatus0 */ 134185377Ssam#define AR_DataLen 0x00000fff /* RX data length */ 135185377Ssam/* AR_More 0x00001000 more desc in this frame */ 136185377Ssam#define AR_DecompCRCErr 0x00002000 /* decompression CRC error */ 137185377Ssam/* bit 14 is reserved */ 138185377Ssam#define AR_RcvRate 0x000f8000 /* reception rate */ 139185377Ssam#define AR_RcvRate_S 15 140185377Ssam#define AR_RcvSigStrength 0x0ff00000 /* receive signal strength */ 141185377Ssam#define AR_RcvSigStrength_S 20 142185377Ssam#define AR_RcvAntenna 0xf0000000 /* receive antenaa */ 143185377Ssam#define AR_RcvAntenna_S 28 144185377Ssam 145185377Ssam/* TX ds_txstatus1 */ 146185377Ssam#define AR_Done 0x00000001 /* descripter complete */ 147185377Ssam#define AR_SeqNum 0x00001ffe /* TX sequence number */ 148185377Ssam#define AR_SeqNum_S 1 149185377Ssam#define AR_AckSigStrength 0x001fe000 /* strength of ACK */ 150185377Ssam#define AR_AckSigStrength_S 13 151185377Ssam#define AR_FinalTSIndex 0x00600000 /* final TX attempt series ix */ 152185377Ssam#define AR_FinalTSIndex_S 21 153185377Ssam#define AR_CompSuccess 0x00800000 /* compression status */ 154185377Ssam#define AR_XmitAtenna 0x01000000 /* transmit antenna */ 155185377Ssam/* bits 25-31 are reserved */ 156185377Ssam 157185377Ssam/* RX ds_rxstatus1 */ 158185377Ssam/* AR_Done 0x00000001 descripter complete */ 159185377Ssam#define AR_FrmRcvOK 0x00000002 /* frame reception success */ 160185377Ssam#define AR_CRCErr 0x00000004 /* CRC error */ 161185377Ssam#define AR_DecryptCRCErr 0x00000008 /* Decryption CRC fiailure */ 162185377Ssam#define AR_PHYErr 0x00000010 /* PHY error */ 163185377Ssam#define AR_MichaelErr 0x00000020 /* Michae MIC decrypt error */ 164185377Ssam/* bits 6-7 are reserved */ 165185377Ssam#define AR_KeyIdxValid 0x00000100 /* decryption key index valid */ 166185377Ssam#define AR_KeyIdx 0x0000fe00 /* Decryption key index */ 167185377Ssam#define AR_KeyIdx_S 9 168185377Ssam#define AR_RcvTimestamp 0x7fff0000 /* timestamp */ 169185377Ssam#define AR_RcvTimestamp_S 16 170185377Ssam#define AR_KeyCacheMiss 0x80000000 /* key cache miss indication */ 171185377Ssam 172185377Ssam/* NB: phy error code overlays key index and valid fields */ 173185377Ssam#define AR_PHYErrCode 0x0000ff00 /* PHY error code */ 174185377Ssam#define AR_PHYErrCode_S 8 175185377Ssam 176185377Ssam#endif /* _ATH_AR5212_DESC_H_ */ 177