ar5212_reset.c revision 187831
1/* 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ar5212/ar5212_reset.c 187831 2009-01-28 18:00:22Z sam $ 18 */ 19#include "opt_ah.h" 20 21#include "ah.h" 22#include "ah_internal.h" 23#include "ah_devid.h" 24 25#include "ar5212/ar5212.h" 26#include "ar5212/ar5212reg.h" 27#include "ar5212/ar5212phy.h" 28 29#include "ah_eeprom_v3.h" 30 31/* Additional Time delay to wait after activiting the Base band */ 32#define BASE_ACTIVATE_DELAY 100 /* 100 usec */ 33#define PLL_SETTLE_DELAY 300 /* 300 usec */ 34 35static HAL_BOOL ar5212SetResetReg(struct ath_hal *, uint32_t resetMask); 36/* NB: public for 5312 use */ 37HAL_BOOL ar5212IsSpurChannel(struct ath_hal *, 38 const struct ieee80211_channel *); 39HAL_BOOL ar5212ChannelChange(struct ath_hal *, 40 const struct ieee80211_channel *); 41int16_t ar5212GetNf(struct ath_hal *, struct ieee80211_channel *); 42HAL_BOOL ar5212SetBoardValues(struct ath_hal *, 43 const struct ieee80211_channel *); 44void ar5212SetDeltaSlope(struct ath_hal *, 45 const struct ieee80211_channel *); 46HAL_BOOL ar5212SetTransmitPower(struct ath_hal *ah, 47 const struct ieee80211_channel *chan, uint16_t *rfXpdGain); 48static HAL_BOOL ar5212SetRateTable(struct ath_hal *, 49 const struct ieee80211_channel *, int16_t tpcScaleReduction, 50 int16_t powerLimit, 51 HAL_BOOL commit, int16_t *minPower, int16_t *maxPower); 52static void ar5212CorrectGainDelta(struct ath_hal *, int twiceOfdmCckDelta); 53static void ar5212GetTargetPowers(struct ath_hal *, 54 const struct ieee80211_channel *, 55 const TRGT_POWER_INFO *pPowerInfo, uint16_t numChannels, 56 TRGT_POWER_INFO *pNewPower); 57static uint16_t ar5212GetMaxEdgePower(uint16_t channel, 58 const RD_EDGES_POWER *pRdEdgesPower); 59void ar5212SetRateDurationTable(struct ath_hal *, 60 const struct ieee80211_channel *); 61void ar5212SetIFSTiming(struct ath_hal *, 62 const struct ieee80211_channel *); 63 64/* NB: public for RF backend use */ 65void ar5212GetLowerUpperValues(uint16_t value, 66 uint16_t *pList, uint16_t listSize, 67 uint16_t *pLowerValue, uint16_t *pUpperValue); 68void ar5212ModifyRfBuffer(uint32_t *rfBuf, uint32_t reg32, 69 uint32_t numBits, uint32_t firstBit, uint32_t column); 70 71static int 72write_common(struct ath_hal *ah, const HAL_INI_ARRAY *ia, 73 HAL_BOOL bChannelChange, int writes) 74{ 75#define IS_NO_RESET_TIMER_ADDR(x) \ 76 ( (((x) >= AR_BEACON) && ((x) <= AR_CFP_DUR)) || \ 77 (((x) >= AR_SLEEP1) && ((x) <= AR_SLEEP3))) 78#define V(r, c) (ia)->data[((r)*(ia)->cols) + (c)] 79 int r; 80 81 /* Write Common Array Parameters */ 82 for (r = 0; r < ia->rows; r++) { 83 uint32_t reg = V(r, 0); 84 /* XXX timer/beacon setup registers? */ 85 /* On channel change, don't reset the PCU registers */ 86 if (!(bChannelChange && IS_NO_RESET_TIMER_ADDR(reg))) { 87 OS_REG_WRITE(ah, reg, V(r, 1)); 88 DMA_YIELD(writes); 89 } 90 } 91 return writes; 92#undef IS_NO_RESET_TIMER_ADDR 93#undef V 94} 95 96#define IS_DISABLE_FAST_ADC_CHAN(x) (((x) == 2462) || ((x) == 2467)) 97 98/* 99 * Places the device in and out of reset and then places sane 100 * values in the registers based on EEPROM config, initialization 101 * vectors (as determined by the mode), and station configuration 102 * 103 * bChannelChange is used to preserve DMA/PCU registers across 104 * a HW Reset during channel change. 105 */ 106HAL_BOOL 107ar5212Reset(struct ath_hal *ah, HAL_OPMODE opmode, 108 struct ieee80211_channel *chan, 109 HAL_BOOL bChannelChange, HAL_STATUS *status) 110{ 111#define N(a) (sizeof (a) / sizeof (a[0])) 112#define FAIL(_code) do { ecode = _code; goto bad; } while (0) 113 struct ath_hal_5212 *ahp = AH5212(ah); 114 HAL_CHANNEL_INTERNAL *ichan = AH_NULL; 115 const HAL_EEPROM *ee; 116 uint32_t softLedCfg, softLedState; 117 uint32_t saveFrameSeqCount, saveDefAntenna, saveLedState; 118 uint32_t macStaId1, synthDelay, txFrm2TxDStart; 119 uint16_t rfXpdGain[MAX_NUM_PDGAINS_PER_CHANNEL]; 120 int16_t cckOfdmPwrDelta = 0; 121 u_int modesIndex, freqIndex; 122 HAL_STATUS ecode; 123 int i, regWrites; 124 uint32_t testReg, powerVal; 125 int8_t twiceAntennaGain, twiceAntennaReduction; 126 uint32_t ackTpcPow, ctsTpcPow, chirpTpcPow; 127 HAL_BOOL isBmode = AH_FALSE; 128 129 HALASSERT(ah->ah_magic == AR5212_MAGIC); 130 ee = AH_PRIVATE(ah)->ah_eeprom; 131 132 OS_MARK(ah, AH_MARK_RESET, bChannelChange); 133 134 /* Bring out of sleep mode */ 135 if (!ar5212SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) { 136 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip did not wakeup\n", 137 __func__); 138 FAIL(HAL_EIO); 139 } 140 141 /* 142 * Map public channel to private. 143 */ 144 ichan = ath_hal_checkchannel(ah, chan); 145 if (ichan == AH_NULL) 146 FAIL(HAL_EINVAL); 147 switch (opmode) { 148 case HAL_M_STA: 149 case HAL_M_IBSS: 150 case HAL_M_HOSTAP: 151 case HAL_M_MONITOR: 152 break; 153 default: 154 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid operating mode %u\n", 155 __func__, opmode); 156 FAIL(HAL_EINVAL); 157 break; 158 } 159 HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER3); 160 161 SAVE_CCK(ah, chan, isBmode); 162 163 /* Preserve certain DMA hardware registers on a channel change */ 164 if (bChannelChange) { 165 /* 166 * On Venice, the TSF is almost preserved across a reset; 167 * it requires doubling writes to the RESET_TSF 168 * bit in the AR_BEACON register; it also has the quirk 169 * of the TSF going back in time on the station (station 170 * latches onto the last beacon's tsf during a reset 50% 171 * of the times); the latter is not a problem for adhoc 172 * stations since as long as the TSF is behind, it will 173 * get resynchronized on receiving the next beacon; the 174 * TSF going backwards in time could be a problem for the 175 * sleep operation (supported on infrastructure stations 176 * only) - the best and most general fix for this situation 177 * is to resynchronize the various sleep/beacon timers on 178 * the receipt of the next beacon i.e. when the TSF itself 179 * gets resynchronized to the AP's TSF - power save is 180 * needed to be temporarily disabled until that time 181 * 182 * Need to save the sequence number to restore it after 183 * the reset! 184 */ 185 saveFrameSeqCount = OS_REG_READ(ah, AR_D_SEQNUM); 186 } else 187 saveFrameSeqCount = 0; /* NB: silence compiler */ 188#if 0 189 /* 190 * XXX disable for now; this appears to sometimes cause OFDM 191 * XXX timing error floods when ani is enabled and bg scanning 192 * XXX kicks in 193 */ 194 /* If the channel change is across the same mode - perform a fast channel change */ 195 if (IS_2413(ah) || IS_5413(ah)) { 196 /* 197 * Fast channel change can only be used when: 198 * -channel change requested - so it's not the initial reset. 199 * -it's not a change to the current channel - 200 * often called when switching modes on a channel 201 * -the modes of the previous and requested channel are the 202 * same 203 * XXX opmode shouldn't change either? 204 */ 205 if (bChannelChange && 206 (AH_PRIVATE(ah)->ah_curchan != AH_NULL) && 207 (chan->ic_freq != AH_PRIVATE(ah)->ah_curchan->ic_freq) && 208 ((chan->ic_flags & IEEE80211_CHAN_ALLTURBO) == 209 (AH_PRIVATE(ah)->ah_curchan->ic_flags & IEEE80211_CHAN_ALLTURBO))) { 210 if (ar5212ChannelChange(ah, chan)) { 211 /* If ChannelChange completed - skip the rest of reset */ 212 /* XXX ani? */ 213 goto done; 214 } 215 } 216 } 217#endif 218 /* 219 * Preserve the antenna on a channel change 220 */ 221 saveDefAntenna = OS_REG_READ(ah, AR_DEF_ANTENNA); 222 if (saveDefAntenna == 0) /* XXX magic constants */ 223 saveDefAntenna = 1; 224 225 /* Save hardware flag before chip reset clears the register */ 226 macStaId1 = OS_REG_READ(ah, AR_STA_ID1) & 227 (AR_STA_ID1_BASE_RATE_11B | AR_STA_ID1_USE_DEFANT); 228 229 /* Save led state from pci config register */ 230 saveLedState = OS_REG_READ(ah, AR_PCICFG) & 231 (AR_PCICFG_LEDCTL | AR_PCICFG_LEDMODE | AR_PCICFG_LEDBLINK | 232 AR_PCICFG_LEDSLOW); 233 softLedCfg = OS_REG_READ(ah, AR_GPIOCR); 234 softLedState = OS_REG_READ(ah, AR_GPIODO); 235 236 ar5212RestoreClock(ah, opmode); /* move to refclk operation */ 237 238 /* 239 * Adjust gain parameters before reset if 240 * there's an outstanding gain updated. 241 */ 242 (void) ar5212GetRfgain(ah); 243 244 if (!ar5212ChipReset(ah, chan)) { 245 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__); 246 FAIL(HAL_EIO); 247 } 248 249 /* Setup the indices for the next set of register array writes */ 250 if (IEEE80211_IS_CHAN_2GHZ(chan)) { 251 freqIndex = 2; 252 if (IEEE80211_IS_CHAN_108G(chan)) 253 modesIndex = 5; 254 else if (IEEE80211_IS_CHAN_G(chan)) 255 modesIndex = 4; 256 else if (IEEE80211_IS_CHAN_B(chan)) 257 modesIndex = 3; 258 else { 259 HALDEBUG(ah, HAL_DEBUG_ANY, 260 "%s: invalid channel %u/0x%x\n", 261 __func__, chan->ic_freq, chan->ic_flags); 262 FAIL(HAL_EINVAL); 263 } 264 } else { 265 freqIndex = 1; 266 if (IEEE80211_IS_CHAN_TURBO(chan)) 267 modesIndex = 2; 268 else if (IEEE80211_IS_CHAN_A(chan)) 269 modesIndex = 1; 270 else { 271 HALDEBUG(ah, HAL_DEBUG_ANY, 272 "%s: invalid channel %u/0x%x\n", 273 __func__, chan->ic_freq, chan->ic_flags); 274 FAIL(HAL_EINVAL); 275 } 276 } 277 278 OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__); 279 280 /* Set correct Baseband to analog shift setting to access analog chips. */ 281 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 282 283 regWrites = ath_hal_ini_write(ah, &ahp->ah_ini_modes, modesIndex, 0); 284 regWrites = write_common(ah, &ahp->ah_ini_common, bChannelChange, 285 regWrites); 286 ahp->ah_rfHal->writeRegs(ah, modesIndex, freqIndex, regWrites); 287 288 OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__); 289 290 if (IEEE80211_IS_CHAN_HALF(chan) || IEEE80211_IS_CHAN_QUARTER(chan)) { 291 ar5212SetIFSTiming(ah, chan); 292 if (IS_5413(ah)) { 293 /* 294 * Force window_length for 1/2 and 1/4 rate channels, 295 * the ini file sets this to zero otherwise. 296 */ 297 OS_REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL, 298 AR_PHY_FRAME_CTL_WINLEN, 3); 299 } 300 } 301 302 /* Overwrite INI values for revised chipsets */ 303 if (AH_PRIVATE(ah)->ah_phyRev >= AR_PHY_CHIP_ID_REV_2) { 304 /* ADC_CTL */ 305 OS_REG_WRITE(ah, AR_PHY_ADC_CTL, 306 SM(2, AR_PHY_ADC_CTL_OFF_INBUFGAIN) | 307 SM(2, AR_PHY_ADC_CTL_ON_INBUFGAIN) | 308 AR_PHY_ADC_CTL_OFF_PWDDAC | 309 AR_PHY_ADC_CTL_OFF_PWDADC); 310 311 /* TX_PWR_ADJ */ 312 if (ichan->channel == 2484) { 313 cckOfdmPwrDelta = SCALE_OC_DELTA( 314 ee->ee_cckOfdmPwrDelta - 315 ee->ee_scaledCh14FilterCckDelta); 316 } else { 317 cckOfdmPwrDelta = SCALE_OC_DELTA( 318 ee->ee_cckOfdmPwrDelta); 319 } 320 321 if (IEEE80211_IS_CHAN_G(chan)) { 322 OS_REG_WRITE(ah, AR_PHY_TXPWRADJ, 323 SM((ee->ee_cckOfdmPwrDelta*-1), 324 AR_PHY_TXPWRADJ_CCK_GAIN_DELTA) | 325 SM((cckOfdmPwrDelta*-1), 326 AR_PHY_TXPWRADJ_CCK_PCDAC_INDEX)); 327 } else { 328 OS_REG_WRITE(ah, AR_PHY_TXPWRADJ, 0); 329 } 330 331 /* Add barker RSSI thresh enable as disabled */ 332 OS_REG_CLR_BIT(ah, AR_PHY_DAG_CTRLCCK, 333 AR_PHY_DAG_CTRLCCK_EN_RSSI_THR); 334 OS_REG_RMW_FIELD(ah, AR_PHY_DAG_CTRLCCK, 335 AR_PHY_DAG_CTRLCCK_RSSI_THR, 2); 336 337 /* Set the mute mask to the correct default */ 338 OS_REG_WRITE(ah, AR_SEQ_MASK, 0x0000000F); 339 } 340 341 if (AH_PRIVATE(ah)->ah_phyRev >= AR_PHY_CHIP_ID_REV_3) { 342 /* Clear reg to alllow RX_CLEAR line debug */ 343 OS_REG_WRITE(ah, AR_PHY_BLUETOOTH, 0); 344 } 345 if (AH_PRIVATE(ah)->ah_phyRev >= AR_PHY_CHIP_ID_REV_4) { 346#ifdef notyet 347 /* Enable burst prefetch for the data queues */ 348 OS_REG_RMW_FIELD(ah, AR_D_FPCTL, ... ); 349 /* Enable double-buffering */ 350 OS_REG_CLR_BIT(ah, AR_TXCFG, AR_TXCFG_DBL_BUF_DIS); 351#endif 352 } 353 354 /* Set ADC/DAC select values */ 355 OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0e); 356 357 if (IS_5413(ah) || IS_2417(ah)) { 358 uint32_t newReg = 1; 359 if (IS_DISABLE_FAST_ADC_CHAN(ichan->channel)) 360 newReg = 0; 361 /* As it's a clock changing register, only write when the value needs to be changed */ 362 if (OS_REG_READ(ah, AR_PHY_FAST_ADC) != newReg) 363 OS_REG_WRITE(ah, AR_PHY_FAST_ADC, newReg); 364 } 365 366 /* Setup the transmit power values. */ 367 if (!ar5212SetTransmitPower(ah, chan, rfXpdGain)) { 368 HALDEBUG(ah, HAL_DEBUG_ANY, 369 "%s: error init'ing transmit power\n", __func__); 370 FAIL(HAL_EIO); 371 } 372 373 /* Write the analog registers */ 374 if (!ahp->ah_rfHal->setRfRegs(ah, chan, modesIndex, rfXpdGain)) { 375 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: ar5212SetRfRegs failed\n", 376 __func__); 377 FAIL(HAL_EIO); 378 } 379 380 /* Write delta slope for OFDM enabled modes (A, G, Turbo) */ 381 if (IEEE80211_IS_CHAN_OFDM(chan)) { 382 if (IS_5413(ah) || 383 AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER5_3) 384 ar5212SetSpurMitigation(ah, chan); 385 ar5212SetDeltaSlope(ah, chan); 386 } 387 388 /* Setup board specific options for EEPROM version 3 */ 389 if (!ar5212SetBoardValues(ah, chan)) { 390 HALDEBUG(ah, HAL_DEBUG_ANY, 391 "%s: error setting board options\n", __func__); 392 FAIL(HAL_EIO); 393 } 394 395 /* Restore certain DMA hardware registers on a channel change */ 396 if (bChannelChange) 397 OS_REG_WRITE(ah, AR_D_SEQNUM, saveFrameSeqCount); 398 399 OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__); 400 401 OS_REG_WRITE(ah, AR_STA_ID0, LE_READ_4(ahp->ah_macaddr)); 402 OS_REG_WRITE(ah, AR_STA_ID1, LE_READ_2(ahp->ah_macaddr + 4) 403 | macStaId1 404 | AR_STA_ID1_RTS_USE_DEF 405 | ahp->ah_staId1Defaults 406 ); 407 ar5212SetOperatingMode(ah, opmode); 408 409 /* Set Venice BSSID mask according to current state */ 410 OS_REG_WRITE(ah, AR_BSSMSKL, LE_READ_4(ahp->ah_bssidmask)); 411 OS_REG_WRITE(ah, AR_BSSMSKU, LE_READ_2(ahp->ah_bssidmask + 4)); 412 413 /* Restore previous led state */ 414 OS_REG_WRITE(ah, AR_PCICFG, OS_REG_READ(ah, AR_PCICFG) | saveLedState); 415 416 /* Restore soft Led state to GPIO */ 417 OS_REG_WRITE(ah, AR_GPIOCR, softLedCfg); 418 OS_REG_WRITE(ah, AR_GPIODO, softLedState); 419 420 /* Restore previous antenna */ 421 OS_REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna); 422 423 /* then our BSSID */ 424 OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid)); 425 OS_REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid + 4)); 426 427 /* Restore bmiss rssi & count thresholds */ 428 OS_REG_WRITE(ah, AR_RSSI_THR, ahp->ah_rssiThr); 429 430 OS_REG_WRITE(ah, AR_ISR, ~0); /* cleared on write */ 431 432 if (!ar5212SetChannel(ah, chan)) 433 FAIL(HAL_EIO); 434 435 OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__); 436 437 ar5212SetCoverageClass(ah, AH_PRIVATE(ah)->ah_coverageClass, 1); 438 439 ar5212SetRateDurationTable(ah, chan); 440 441 /* Set Tx frame start to tx data start delay */ 442 if (IS_RAD5112_ANY(ah) && 443 (IEEE80211_IS_CHAN_HALF(chan) || IEEE80211_IS_CHAN_QUARTER(chan))) { 444 txFrm2TxDStart = 445 IEEE80211_IS_CHAN_HALF(chan) ? 446 TX_FRAME_D_START_HALF_RATE: 447 TX_FRAME_D_START_QUARTER_RATE; 448 OS_REG_RMW_FIELD(ah, AR_PHY_TX_CTL, 449 AR_PHY_TX_FRAME_TO_TX_DATA_START, txFrm2TxDStart); 450 } 451 452 /* 453 * Setup fast diversity. 454 * Fast diversity can be enabled or disabled via regadd.txt. 455 * Default is enabled. 456 * For reference, 457 * Disable: reg val 458 * 0x00009860 0x00009d18 (if 11a / 11g, else no change) 459 * 0x00009970 0x192bb514 460 * 0x0000a208 0xd03e4648 461 * 462 * Enable: 0x00009860 0x00009d10 (if 11a / 11g, else no change) 463 * 0x00009970 0x192fb514 464 * 0x0000a208 0xd03e6788 465 */ 466 467 /* XXX Setup pre PHY ENABLE EAR additions */ 468 /* 469 * Wait for the frequency synth to settle (synth goes on 470 * via AR_PHY_ACTIVE_EN). Read the phy active delay register. 471 * Value is in 100ns increments. 472 */ 473 synthDelay = OS_REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; 474 if (IEEE80211_IS_CHAN_B(chan)) { 475 synthDelay = (4 * synthDelay) / 22; 476 } else { 477 synthDelay /= 10; 478 } 479 480 /* Activate the PHY (includes baseband activate and synthesizer on) */ 481 OS_REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); 482 483 /* 484 * There is an issue if the AP starts the calibration before 485 * the base band timeout completes. This could result in the 486 * rx_clear false triggering. As a workaround we add delay an 487 * extra BASE_ACTIVATE_DELAY usecs to ensure this condition 488 * does not happen. 489 */ 490 if (IEEE80211_IS_CHAN_HALF(chan)) { 491 OS_DELAY((synthDelay << 1) + BASE_ACTIVATE_DELAY); 492 } else if (IEEE80211_IS_CHAN_QUARTER(chan)) { 493 OS_DELAY((synthDelay << 2) + BASE_ACTIVATE_DELAY); 494 } else { 495 OS_DELAY(synthDelay + BASE_ACTIVATE_DELAY); 496 } 497 498 /* 499 * The udelay method is not reliable with notebooks. 500 * Need to check to see if the baseband is ready 501 */ 502 testReg = OS_REG_READ(ah, AR_PHY_TESTCTRL); 503 /* Selects the Tx hold */ 504 OS_REG_WRITE(ah, AR_PHY_TESTCTRL, AR_PHY_TESTCTRL_TXHOLD); 505 i = 0; 506 while ((i++ < 20) && 507 (OS_REG_READ(ah, 0x9c24) & 0x10)) /* test if baseband not ready */ OS_DELAY(200); 508 OS_REG_WRITE(ah, AR_PHY_TESTCTRL, testReg); 509 510 /* Calibrate the AGC and start a NF calculation */ 511 OS_REG_WRITE(ah, AR_PHY_AGC_CONTROL, 512 OS_REG_READ(ah, AR_PHY_AGC_CONTROL) 513 | AR_PHY_AGC_CONTROL_CAL 514 | AR_PHY_AGC_CONTROL_NF); 515 516 if (!IEEE80211_IS_CHAN_B(chan) && ahp->ah_bIQCalibration != IQ_CAL_DONE) { 517 /* Start IQ calibration w/ 2^(INIT_IQCAL_LOG_COUNT_MAX+1) samples */ 518 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4, 519 AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX, 520 INIT_IQCAL_LOG_COUNT_MAX); 521 OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4, 522 AR_PHY_TIMING_CTRL4_DO_IQCAL); 523 ahp->ah_bIQCalibration = IQ_CAL_RUNNING; 524 } else 525 ahp->ah_bIQCalibration = IQ_CAL_INACTIVE; 526 527 /* Setup compression registers */ 528 ar5212SetCompRegs(ah); 529 530 /* Set 1:1 QCU to DCU mapping for all queues */ 531 for (i = 0; i < AR_NUM_DCU; i++) 532 OS_REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); 533 534 ahp->ah_intrTxqs = 0; 535 for (i = 0; i < AH_PRIVATE(ah)->ah_caps.halTotalQueues; i++) 536 ar5212ResetTxQueue(ah, i); 537 538 /* 539 * Setup interrupt handling. Note that ar5212ResetTxQueue 540 * manipulates the secondary IMR's as queues are enabled 541 * and disabled. This is done with RMW ops to insure the 542 * settings we make here are preserved. 543 */ 544 ahp->ah_maskReg = AR_IMR_TXOK | AR_IMR_TXERR | AR_IMR_TXURN 545 | AR_IMR_RXOK | AR_IMR_RXERR | AR_IMR_RXORN 546 | AR_IMR_HIUERR 547 ; 548 if (opmode == HAL_M_HOSTAP) 549 ahp->ah_maskReg |= AR_IMR_MIB; 550 OS_REG_WRITE(ah, AR_IMR, ahp->ah_maskReg); 551 /* Enable bus errors that are OR'd to set the HIUERR bit */ 552 OS_REG_WRITE(ah, AR_IMR_S2, 553 OS_REG_READ(ah, AR_IMR_S2) 554 | AR_IMR_S2_MCABT | AR_IMR_S2_SSERR | AR_IMR_S2_DPERR); 555 556 if (AH_PRIVATE(ah)->ah_rfkillEnabled) 557 ar5212EnableRfKill(ah); 558 559 if (!ath_hal_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 0)) { 560 HALDEBUG(ah, HAL_DEBUG_ANY, 561 "%s: offset calibration failed to complete in 1ms;" 562 " noisy environment?\n", __func__); 563 } 564 565 /* 566 * Set clocks back to 32kHz if they had been using refClk, then 567 * use an external 32kHz crystal when sleeping, if one exists. 568 */ 569 ar5212SetupClock(ah, opmode); 570 571 /* 572 * Writing to AR_BEACON will start timers. Hence it should 573 * be the last register to be written. Do not reset tsf, do 574 * not enable beacons at this point, but preserve other values 575 * like beaconInterval. 576 */ 577 OS_REG_WRITE(ah, AR_BEACON, 578 (OS_REG_READ(ah, AR_BEACON) &~ (AR_BEACON_EN | AR_BEACON_RESET_TSF))); 579 580 /* XXX Setup post reset EAR additions */ 581 582 /* QoS support */ 583 if (AH_PRIVATE(ah)->ah_macVersion > AR_SREV_VERSION_VENICE || 584 (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE && 585 AH_PRIVATE(ah)->ah_macRev >= AR_SREV_GRIFFIN_LITE)) { 586 OS_REG_WRITE(ah, AR_QOS_CONTROL, 0x100aa); /* XXX magic */ 587 OS_REG_WRITE(ah, AR_QOS_SELECT, 0x3210); /* XXX magic */ 588 } 589 590 /* Turn on NOACK Support for QoS packets */ 591 OS_REG_WRITE(ah, AR_NOACK, 592 SM(2, AR_NOACK_2BIT_VALUE) | 593 SM(5, AR_NOACK_BIT_OFFSET) | 594 SM(0, AR_NOACK_BYTE_OFFSET)); 595 596 /* Get Antenna Gain reduction */ 597 if (IEEE80211_IS_CHAN_5GHZ(chan)) { 598 ath_hal_eepromGet(ah, AR_EEP_ANTGAINMAX_5, &twiceAntennaGain); 599 } else { 600 ath_hal_eepromGet(ah, AR_EEP_ANTGAINMAX_2, &twiceAntennaGain); 601 } 602 twiceAntennaReduction = 603 ath_hal_getantennareduction(ah, chan, twiceAntennaGain); 604 605 /* TPC for self-generated frames */ 606 607 ackTpcPow = MS(ahp->ah_macTPC, AR_TPC_ACK); 608 if ((ackTpcPow-ahp->ah_txPowerIndexOffset) > chan->ic_maxpower) 609 ackTpcPow = chan->ic_maxpower+ahp->ah_txPowerIndexOffset; 610 611 if (ackTpcPow > (2*chan->ic_maxregpower - twiceAntennaReduction)) 612 ackTpcPow = (2*chan->ic_maxregpower - twiceAntennaReduction) 613 + ahp->ah_txPowerIndexOffset; 614 615 ctsTpcPow = MS(ahp->ah_macTPC, AR_TPC_CTS); 616 if ((ctsTpcPow-ahp->ah_txPowerIndexOffset) > chan->ic_maxpower) 617 ctsTpcPow = chan->ic_maxpower+ahp->ah_txPowerIndexOffset; 618 619 if (ctsTpcPow > (2*chan->ic_maxregpower - twiceAntennaReduction)) 620 ctsTpcPow = (2*chan->ic_maxregpower - twiceAntennaReduction) 621 + ahp->ah_txPowerIndexOffset; 622 623 chirpTpcPow = MS(ahp->ah_macTPC, AR_TPC_CHIRP); 624 if ((chirpTpcPow-ahp->ah_txPowerIndexOffset) > chan->ic_maxpower) 625 chirpTpcPow = chan->ic_maxpower+ahp->ah_txPowerIndexOffset; 626 627 if (chirpTpcPow > (2*chan->ic_maxregpower - twiceAntennaReduction)) 628 chirpTpcPow = (2*chan->ic_maxregpower - twiceAntennaReduction) 629 + ahp->ah_txPowerIndexOffset; 630 631 if (ackTpcPow > 63) 632 ackTpcPow = 63; 633 if (ctsTpcPow > 63) 634 ctsTpcPow = 63; 635 if (chirpTpcPow > 63) 636 chirpTpcPow = 63; 637 638 powerVal = SM(ackTpcPow, AR_TPC_ACK) | 639 SM(ctsTpcPow, AR_TPC_CTS) | 640 SM(chirpTpcPow, AR_TPC_CHIRP); 641 642 OS_REG_WRITE(ah, AR_TPC, powerVal); 643 644 /* Restore user-specified settings */ 645 if (ahp->ah_miscMode != 0) 646 OS_REG_WRITE(ah, AR_MISC_MODE, ahp->ah_miscMode); 647 if (ahp->ah_sifstime != (u_int) -1) 648 ar5212SetSifsTime(ah, ahp->ah_sifstime); 649 if (ahp->ah_slottime != (u_int) -1) 650 ar5212SetSlotTime(ah, ahp->ah_slottime); 651 if (ahp->ah_acktimeout != (u_int) -1) 652 ar5212SetAckTimeout(ah, ahp->ah_acktimeout); 653 if (ahp->ah_ctstimeout != (u_int) -1) 654 ar5212SetCTSTimeout(ah, ahp->ah_ctstimeout); 655 if (AH_PRIVATE(ah)->ah_diagreg != 0) 656 OS_REG_WRITE(ah, AR_DIAG_SW, AH_PRIVATE(ah)->ah_diagreg); 657 658 AH_PRIVATE(ah)->ah_opmode = opmode; /* record operating mode */ 659#if 0 660done: 661#endif 662 if (bChannelChange && !IEEE80211_IS_CHAN_DFS(chan)) 663 chan->ic_state &= ~IEEE80211_CHANSTATE_CWINT; 664 665 HALDEBUG(ah, HAL_DEBUG_RESET, "%s: done\n", __func__); 666 667 RESTORE_CCK(ah, chan, isBmode); 668 669 OS_MARK(ah, AH_MARK_RESET_DONE, 0); 670 671 return AH_TRUE; 672bad: 673 RESTORE_CCK(ah, chan, isBmode); 674 675 OS_MARK(ah, AH_MARK_RESET_DONE, ecode); 676 if (status != AH_NULL) 677 *status = ecode; 678 return AH_FALSE; 679#undef FAIL 680#undef N 681} 682 683/* 684 * Call the rf backend to change the channel. 685 */ 686HAL_BOOL 687ar5212SetChannel(struct ath_hal *ah, const struct ieee80211_channel *chan) 688{ 689 struct ath_hal_5212 *ahp = AH5212(ah); 690 691 /* Change the synth */ 692 if (!ahp->ah_rfHal->setChannel(ah, chan)) 693 return AH_FALSE; 694 return AH_TRUE; 695} 696 697/* 698 * This channel change evaluates whether the selected hardware can 699 * perform a synthesizer-only channel change (no reset). If the 700 * TX is not stopped, or the RFBus cannot be granted in the given 701 * time, the function returns false as a reset is necessary 702 */ 703HAL_BOOL 704ar5212ChannelChange(struct ath_hal *ah, const struct ieee80211_channel *chan) 705{ 706 uint32_t ulCount; 707 uint32_t data, synthDelay, qnum; 708 uint16_t rfXpdGain[MAX_NUM_PDGAINS_PER_CHANNEL]; 709 HAL_BOOL txStopped = AH_TRUE; 710 HAL_CHANNEL_INTERNAL *ichan; 711 712 /* 713 * Map public channel to private. 714 */ 715 ichan = ath_hal_checkchannel(ah, chan); 716 717 /* TX must be stopped or RF Bus grant will not work */ 718 for (qnum = 0; qnum < AH_PRIVATE(ah)->ah_caps.halTotalQueues; qnum++) { 719 if (ar5212NumTxPending(ah, qnum)) { 720 txStopped = AH_FALSE; 721 break; 722 } 723 } 724 if (!txStopped) 725 return AH_FALSE; 726 727 /* Kill last Baseband Rx Frame */ 728 OS_REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_REQUEST); /* Request analog bus grant */ 729 for (ulCount = 0; ulCount < 100; ulCount++) { 730 if (OS_REG_READ(ah, AR_PHY_RFBUS_GNT)) 731 break; 732 OS_DELAY(5); 733 } 734 if (ulCount >= 100) 735 return AH_FALSE; 736 737 /* Change the synth */ 738 if (!ar5212SetChannel(ah, chan)) 739 return AH_FALSE; 740 741 /* 742 * Wait for the frequency synth to settle (synth goes on via PHY_ACTIVE_EN). 743 * Read the phy active delay register. Value is in 100ns increments. 744 */ 745 data = OS_REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; 746 if (IEEE80211_IS_CHAN_B(chan)) { 747 synthDelay = (4 * data) / 22; 748 } else { 749 synthDelay = data / 10; 750 } 751 OS_DELAY(synthDelay + BASE_ACTIVATE_DELAY); 752 753 /* Setup the transmit power values. */ 754 if (!ar5212SetTransmitPower(ah, chan, rfXpdGain)) { 755 HALDEBUG(ah, HAL_DEBUG_ANY, 756 "%s: error init'ing transmit power\n", __func__); 757 return AH_FALSE; 758 } 759 760 /* Write delta slope for OFDM enabled modes (A, G, Turbo) */ 761 if (IEEE80211_IS_CHAN_OFDM(chan)) { 762 if (IS_5413(ah) || 763 AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER5_3) 764 ar5212SetSpurMitigation(ah, chan); 765 ar5212SetDeltaSlope(ah, chan); 766 } 767 768 /* Release the RFBus Grant */ 769 OS_REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0); 770 771 /* Start Noise Floor Cal */ 772 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); 773 return AH_TRUE; 774} 775 776void 777ar5212SetOperatingMode(struct ath_hal *ah, int opmode) 778{ 779 uint32_t val; 780 781 val = OS_REG_READ(ah, AR_STA_ID1); 782 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC); 783 switch (opmode) { 784 case HAL_M_HOSTAP: 785 OS_REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP 786 | AR_STA_ID1_KSRCH_MODE); 787 OS_REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 788 break; 789 case HAL_M_IBSS: 790 OS_REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC 791 | AR_STA_ID1_KSRCH_MODE); 792 OS_REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 793 break; 794 case HAL_M_STA: 795 case HAL_M_MONITOR: 796 OS_REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE); 797 break; 798 } 799} 800 801/* 802 * Places the PHY and Radio chips into reset. A full reset 803 * must be called to leave this state. The PCI/MAC/PCU are 804 * not placed into reset as we must receive interrupt to 805 * re-enable the hardware. 806 */ 807HAL_BOOL 808ar5212PhyDisable(struct ath_hal *ah) 809{ 810 return ar5212SetResetReg(ah, AR_RC_BB); 811} 812 813/* 814 * Places all of hardware into reset 815 */ 816HAL_BOOL 817ar5212Disable(struct ath_hal *ah) 818{ 819 if (!ar5212SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) 820 return AH_FALSE; 821 /* 822 * Reset the HW - PCI must be reset after the rest of the 823 * device has been reset. 824 */ 825 return ar5212SetResetReg(ah, AR_RC_MAC | AR_RC_BB | AR_RC_PCI); 826} 827 828/* 829 * Places the hardware into reset and then pulls it out of reset 830 * 831 * TODO: Only write the PLL if we're changing to or from CCK mode 832 * 833 * WARNING: The order of the PLL and mode registers must be correct. 834 */ 835HAL_BOOL 836ar5212ChipReset(struct ath_hal *ah, const struct ieee80211_channel *chan) 837{ 838 839 OS_MARK(ah, AH_MARK_CHIPRESET, chan ? chan->ic_freq : 0); 840 841 /* 842 * Reset the HW - PCI must be reset after the rest of the 843 * device has been reset 844 */ 845 if (!ar5212SetResetReg(ah, AR_RC_MAC | AR_RC_BB | AR_RC_PCI)) 846 return AH_FALSE; 847 848 /* Bring out of sleep mode (AGAIN) */ 849 if (!ar5212SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) 850 return AH_FALSE; 851 852 /* Clear warm reset register */ 853 if (!ar5212SetResetReg(ah, 0)) 854 return AH_FALSE; 855 856 /* 857 * Perform warm reset before the mode/PLL/turbo registers 858 * are changed in order to deactivate the radio. Mode changes 859 * with an active radio can result in corrupted shifts to the 860 * radio device. 861 */ 862 863 /* 864 * Set CCK and Turbo modes correctly. 865 */ 866 if (chan != AH_NULL) { /* NB: can be null during attach */ 867 uint32_t rfMode, phyPLL = 0, curPhyPLL, turbo; 868 869 if (IS_5413(ah)) { /* NB: =>'s 5424 also */ 870 rfMode = AR_PHY_MODE_AR5112; 871 if (IEEE80211_IS_CHAN_HALF(chan)) 872 rfMode |= AR_PHY_MODE_HALF; 873 else if (IEEE80211_IS_CHAN_QUARTER(chan)) 874 rfMode |= AR_PHY_MODE_QUARTER; 875 876 if (IEEE80211_IS_CHAN_CCK(chan)) 877 phyPLL = AR_PHY_PLL_CTL_44_5112; 878 else 879 phyPLL = AR_PHY_PLL_CTL_40_5413; 880 } else if (IS_RAD5111(ah)) { 881 rfMode = AR_PHY_MODE_AR5111; 882 if (IEEE80211_IS_CHAN_CCK(chan)) 883 phyPLL = AR_PHY_PLL_CTL_44; 884 else 885 phyPLL = AR_PHY_PLL_CTL_40; 886 if (IEEE80211_IS_CHAN_HALF(chan)) 887 phyPLL = AR_PHY_PLL_CTL_HALF; 888 else if (IEEE80211_IS_CHAN_QUARTER(chan)) 889 phyPLL = AR_PHY_PLL_CTL_QUARTER; 890 } else { /* 5112, 2413, 2316, 2317 */ 891 rfMode = AR_PHY_MODE_AR5112; 892 if (IEEE80211_IS_CHAN_CCK(chan)) 893 phyPLL = AR_PHY_PLL_CTL_44_5112; 894 else 895 phyPLL = AR_PHY_PLL_CTL_40_5112; 896 if (IEEE80211_IS_CHAN_HALF(chan)) 897 phyPLL |= AR_PHY_PLL_CTL_HALF; 898 else if (IEEE80211_IS_CHAN_QUARTER(chan)) 899 phyPLL |= AR_PHY_PLL_CTL_QUARTER; 900 } 901 if (IEEE80211_IS_CHAN_G(chan)) 902 rfMode |= AR_PHY_MODE_DYNAMIC; 903 else if (IEEE80211_IS_CHAN_OFDM(chan)) 904 rfMode |= AR_PHY_MODE_OFDM; 905 else 906 rfMode |= AR_PHY_MODE_CCK; 907 if (IEEE80211_IS_CHAN_5GHZ(chan)) 908 rfMode |= AR_PHY_MODE_RF5GHZ; 909 else 910 rfMode |= AR_PHY_MODE_RF2GHZ; 911 turbo = IEEE80211_IS_CHAN_TURBO(chan) ? 912 (AR_PHY_FC_TURBO_MODE | AR_PHY_FC_TURBO_SHORT) : 0; 913 curPhyPLL = OS_REG_READ(ah, AR_PHY_PLL_CTL); 914 /* 915 * PLL, Mode, and Turbo values must be written in the correct 916 * order to ensure: 917 * - The PLL cannot be set to 44 unless the CCK or DYNAMIC 918 * mode bit is set 919 * - Turbo cannot be set at the same time as CCK or DYNAMIC 920 */ 921 if (IEEE80211_IS_CHAN_CCK(chan)) { 922 OS_REG_WRITE(ah, AR_PHY_TURBO, turbo); 923 OS_REG_WRITE(ah, AR_PHY_MODE, rfMode); 924 if (curPhyPLL != phyPLL) { 925 OS_REG_WRITE(ah, AR_PHY_PLL_CTL, phyPLL); 926 /* Wait for the PLL to settle */ 927 OS_DELAY(PLL_SETTLE_DELAY); 928 } 929 } else { 930 if (curPhyPLL != phyPLL) { 931 OS_REG_WRITE(ah, AR_PHY_PLL_CTL, phyPLL); 932 /* Wait for the PLL to settle */ 933 OS_DELAY(PLL_SETTLE_DELAY); 934 } 935 OS_REG_WRITE(ah, AR_PHY_TURBO, turbo); 936 OS_REG_WRITE(ah, AR_PHY_MODE, rfMode); 937 } 938 } 939 return AH_TRUE; 940} 941 942/* 943 * Recalibrate the lower PHY chips to account for temperature/environment 944 * changes. 945 */ 946HAL_BOOL 947ar5212PerCalibrationN(struct ath_hal *ah, 948 struct ieee80211_channel *chan, 949 u_int chainMask, HAL_BOOL longCal, HAL_BOOL *isCalDone) 950{ 951#define IQ_CAL_TRIES 10 952 struct ath_hal_5212 *ahp = AH5212(ah); 953 HAL_CHANNEL_INTERNAL *ichan; 954 int32_t qCoff, qCoffDenom; 955 int32_t iqCorrMeas, iCoff, iCoffDenom; 956 uint32_t powerMeasQ, powerMeasI; 957 HAL_BOOL isBmode; 958 959 OS_MARK(ah, AH_MARK_PERCAL, chan->ic_freq); 960 *isCalDone = AH_FALSE; 961 ichan = ath_hal_checkchannel(ah, chan); 962 if (ichan == AH_NULL) { 963 HALDEBUG(ah, HAL_DEBUG_ANY, 964 "%s: invalid channel %u/0x%x; no mapping\n", 965 __func__, chan->ic_freq, chan->ic_flags); 966 return AH_FALSE; 967 } 968 SAVE_CCK(ah, chan, isBmode); 969 970 if (ahp->ah_bIQCalibration == IQ_CAL_DONE || 971 ahp->ah_bIQCalibration == IQ_CAL_INACTIVE) 972 *isCalDone = AH_TRUE; 973 974 /* IQ calibration in progress. Check to see if it has finished. */ 975 if (ahp->ah_bIQCalibration == IQ_CAL_RUNNING && 976 !(OS_REG_READ(ah, AR_PHY_TIMING_CTRL4) & AR_PHY_TIMING_CTRL4_DO_IQCAL)) { 977 int i; 978 979 /* IQ Calibration has finished. */ 980 ahp->ah_bIQCalibration = IQ_CAL_INACTIVE; 981 *isCalDone = AH_TRUE; 982 983 /* workaround for misgated IQ Cal results */ 984 i = 0; 985 do { 986 /* Read calibration results. */ 987 powerMeasI = OS_REG_READ(ah, AR_PHY_IQCAL_RES_PWR_MEAS_I); 988 powerMeasQ = OS_REG_READ(ah, AR_PHY_IQCAL_RES_PWR_MEAS_Q); 989 iqCorrMeas = OS_REG_READ(ah, AR_PHY_IQCAL_RES_IQ_CORR_MEAS); 990 if (powerMeasI && powerMeasQ) 991 break; 992 /* Do we really need this??? */ 993 OS_REG_WRITE (ah, AR_PHY_TIMING_CTRL4, 994 OS_REG_READ(ah, AR_PHY_TIMING_CTRL4) | 995 AR_PHY_TIMING_CTRL4_DO_IQCAL); 996 } while (++i < IQ_CAL_TRIES); 997 998 /* 999 * Prescale these values to remove 64-bit operation 1000 * requirement at the loss of a little precision. 1001 */ 1002 iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 128; 1003 qCoffDenom = powerMeasQ / 128; 1004 1005 /* Protect against divide-by-0 and loss of sign bits. */ 1006 if (iCoffDenom != 0 && qCoffDenom >= 2) { 1007 iCoff = (int8_t)(-iqCorrMeas) / iCoffDenom; 1008 /* IQCORR_Q_I_COFF is a signed 6 bit number */ 1009 if (iCoff < -32) { 1010 iCoff = -32; 1011 } else if (iCoff > 31) { 1012 iCoff = 31; 1013 } 1014 1015 /* IQCORR_Q_Q_COFF is a signed 5 bit number */ 1016 qCoff = (powerMeasI / qCoffDenom) - 128; 1017 if (qCoff < -16) { 1018 qCoff = -16; 1019 } else if (qCoff > 15) { 1020 qCoff = 15; 1021 } 1022 1023 HALDEBUG(ah, HAL_DEBUG_PERCAL, 1024 "****************** MISGATED IQ CAL! *******************\n"); 1025 HALDEBUG(ah, HAL_DEBUG_PERCAL, 1026 "time = %d, i = %d, \n", OS_GETUPTIME(ah), i); 1027 HALDEBUG(ah, HAL_DEBUG_PERCAL, 1028 "powerMeasI = 0x%08x\n", powerMeasI); 1029 HALDEBUG(ah, HAL_DEBUG_PERCAL, 1030 "powerMeasQ = 0x%08x\n", powerMeasQ); 1031 HALDEBUG(ah, HAL_DEBUG_PERCAL, 1032 "iqCorrMeas = 0x%08x\n", iqCorrMeas); 1033 HALDEBUG(ah, HAL_DEBUG_PERCAL, 1034 "iCoff = %d\n", iCoff); 1035 HALDEBUG(ah, HAL_DEBUG_PERCAL, 1036 "qCoff = %d\n", qCoff); 1037 1038 /* Write values and enable correction */ 1039 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4, 1040 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF, iCoff); 1041 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4, 1042 AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, qCoff); 1043 OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4, 1044 AR_PHY_TIMING_CTRL4_IQCORR_ENABLE); 1045 1046 ahp->ah_bIQCalibration = IQ_CAL_DONE; 1047 ichan->privFlags |= CHANNEL_IQVALID; 1048 ichan->iCoff = iCoff; 1049 ichan->qCoff = qCoff; 1050 } 1051 } else if (!IEEE80211_IS_CHAN_B(chan) && ahp->ah_bIQCalibration == IQ_CAL_DONE && 1052 (ichan->privFlags & CHANNEL_IQVALID) == 0) { 1053 /* 1054 * Start IQ calibration if configured channel has changed. 1055 * Use a magic number of 15 based on default value. 1056 */ 1057 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4, 1058 AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX, 1059 INIT_IQCAL_LOG_COUNT_MAX); 1060 OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4, 1061 AR_PHY_TIMING_CTRL4_DO_IQCAL); 1062 ahp->ah_bIQCalibration = IQ_CAL_RUNNING; 1063 } 1064 /* XXX EAR */ 1065 1066 if (longCal) { 1067 /* Check noise floor results */ 1068 ar5212GetNf(ah, chan); 1069 if (!IEEE80211_IS_CHAN_CWINT(chan)) { 1070 /* Perform cal for 5Ghz channels and any OFDM on 5112 */ 1071 if (IEEE80211_IS_CHAN_5GHZ(chan) || 1072 (IS_RAD5112(ah) && IEEE80211_IS_CHAN_OFDM(chan))) 1073 ar5212RequestRfgain(ah); 1074 } 1075 } 1076 RESTORE_CCK(ah, chan, isBmode); 1077 1078 return AH_TRUE; 1079#undef IQ_CAL_TRIES 1080} 1081 1082HAL_BOOL 1083ar5212PerCalibration(struct ath_hal *ah, struct ieee80211_channel *chan, 1084 HAL_BOOL *isIQdone) 1085{ 1086 return ar5212PerCalibrationN(ah, chan, 0x1, AH_TRUE, isIQdone); 1087} 1088 1089HAL_BOOL 1090ar5212ResetCalValid(struct ath_hal *ah, const struct ieee80211_channel *chan) 1091{ 1092 /* XXX */ 1093 return AH_TRUE; 1094} 1095 1096/* 1097 * Write the given reset bit mask into the reset register 1098 */ 1099static HAL_BOOL 1100ar5212SetResetReg(struct ath_hal *ah, uint32_t resetMask) 1101{ 1102 uint32_t mask = resetMask ? resetMask : ~0; 1103 HAL_BOOL rt; 1104 1105 /* XXX ar5212MacStop & co. */ 1106 1107 if (IS_PCIE(ah)) { 1108 resetMask &= ~AR_RC_PCI; 1109 } 1110 1111 (void) OS_REG_READ(ah, AR_RXDP);/* flush any pending MMR writes */ 1112 OS_REG_WRITE(ah, AR_RC, resetMask); 1113 OS_DELAY(15); /* need to wait at least 128 clocks 1114 when reseting PCI before read */ 1115 mask &= (AR_RC_MAC | AR_RC_BB); 1116 resetMask &= (AR_RC_MAC | AR_RC_BB); 1117 rt = ath_hal_wait(ah, AR_RC, mask, resetMask); 1118 if ((resetMask & AR_RC_MAC) == 0) { 1119 if (isBigEndian()) { 1120 /* 1121 * Set CFG, little-endian for register 1122 * and descriptor accesses. 1123 */ 1124 mask = INIT_CONFIG_STATUS | AR_CFG_SWRD | AR_CFG_SWRG; 1125#ifndef AH_NEED_DESC_SWAP 1126 mask |= AR_CFG_SWTD; 1127#endif 1128 OS_REG_WRITE(ah, AR_CFG, LE_READ_4(&mask)); 1129 } else 1130 OS_REG_WRITE(ah, AR_CFG, INIT_CONFIG_STATUS); 1131 if (ar5212SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) 1132 (void) OS_REG_READ(ah, AR_ISR_RAC); 1133 } 1134 1135 /* track PHY power state so we don't try to r/w BB registers */ 1136 AH5212(ah)->ah_phyPowerOn = ((resetMask & AR_RC_BB) == 0); 1137 return rt; 1138} 1139 1140int16_t 1141ar5212GetNoiseFloor(struct ath_hal *ah) 1142{ 1143 int16_t nf = (OS_REG_READ(ah, AR_PHY(25)) >> 19) & 0x1ff; 1144 if (nf & 0x100) 1145 nf = 0 - ((nf ^ 0x1ff) + 1); 1146 return nf; 1147} 1148 1149static HAL_BOOL 1150getNoiseFloorThresh(struct ath_hal *ah, const struct ieee80211_channel *chan, 1151 int16_t *nft) 1152{ 1153 const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom; 1154 1155 HALASSERT(ah->ah_magic == AR5212_MAGIC); 1156 1157 switch (chan->ic_flags & IEEE80211_CHAN_ALLFULL) { 1158 case IEEE80211_CHAN_A: 1159 *nft = ee->ee_noiseFloorThresh[headerInfo11A]; 1160 break; 1161 case IEEE80211_CHAN_B: 1162 *nft = ee->ee_noiseFloorThresh[headerInfo11B]; 1163 break; 1164 case IEEE80211_CHAN_G: 1165 case IEEE80211_CHAN_PUREG: /* NB: really 108G */ 1166 *nft = ee->ee_noiseFloorThresh[headerInfo11G]; 1167 break; 1168 default: 1169 HALDEBUG(ah, HAL_DEBUG_ANY, 1170 "%s: invalid channel flags %u/0x%x\n", 1171 __func__, chan->ic_freq, chan->ic_flags); 1172 return AH_FALSE; 1173 } 1174 return AH_TRUE; 1175} 1176 1177/* 1178 * Setup the noise floor cal history buffer. 1179 */ 1180void 1181ar5212InitNfCalHistBuffer(struct ath_hal *ah) 1182{ 1183 struct ath_hal_5212 *ahp = AH5212(ah); 1184 int i; 1185 1186 ahp->ah_nfCalHist.first_run = 1; 1187 ahp->ah_nfCalHist.currIndex = 0; 1188 ahp->ah_nfCalHist.privNF = AR5212_CCA_MAX_GOOD_VALUE; 1189 ahp->ah_nfCalHist.invalidNFcount = AR512_NF_CAL_HIST_MAX; 1190 for (i = 0; i < AR512_NF_CAL_HIST_MAX; i ++) 1191 ahp->ah_nfCalHist.nfCalBuffer[i] = AR5212_CCA_MAX_GOOD_VALUE; 1192} 1193 1194/* 1195 * Add a noise floor value to the ring buffer. 1196 */ 1197static __inline void 1198updateNFHistBuff(struct ar5212NfCalHist *h, int16_t nf) 1199{ 1200 h->nfCalBuffer[h->currIndex] = nf; 1201 if (++h->currIndex >= AR512_NF_CAL_HIST_MAX) 1202 h->currIndex = 0; 1203} 1204 1205/* 1206 * Return the median noise floor value in the ring buffer. 1207 */ 1208int16_t 1209ar5212GetNfHistMid(const int16_t calData[AR512_NF_CAL_HIST_MAX]) 1210{ 1211 int16_t sort[AR512_NF_CAL_HIST_MAX]; 1212 int i, j; 1213 1214 OS_MEMCPY(sort, calData, AR512_NF_CAL_HIST_MAX*sizeof(int16_t)); 1215 for (i = 0; i < AR512_NF_CAL_HIST_MAX-1; i ++) { 1216 for (j = 1; j < AR512_NF_CAL_HIST_MAX-i; j ++) { 1217 if (sort[j] > sort[j-1]) { 1218 int16_t nf = sort[j]; 1219 sort[j] = sort[j-1]; 1220 sort[j-1] = nf; 1221 } 1222 } 1223 } 1224 return sort[(AR512_NF_CAL_HIST_MAX-1)>>1]; 1225} 1226 1227/* 1228 * Read the NF and check it against the noise floor threshhold 1229 */ 1230int16_t 1231ar5212GetNf(struct ath_hal *ah, struct ieee80211_channel *chan) 1232{ 1233 struct ath_hal_5212 *ahp = AH5212(ah); 1234 struct ar5212NfCalHist *h = &ahp->ah_nfCalHist; 1235 HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan); 1236 int16_t nf, nfThresh; 1237 int32_t val; 1238 1239 if (OS_REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) { 1240 HALDEBUG(ah, HAL_DEBUG_ANY, 1241 "%s: NF did not complete in calibration window\n", __func__); 1242 ichan->rawNoiseFloor = h->privNF; /* most recent value */ 1243 return ichan->rawNoiseFloor; 1244 } 1245 1246 /* 1247 * Finished NF cal, check against threshold. 1248 */ 1249 nf = ar5212GetNoiseFloor(ah); 1250 if (getNoiseFloorThresh(ah, chan, &nfThresh)) { 1251 if (nf > nfThresh) { 1252 HALDEBUG(ah, HAL_DEBUG_ANY, 1253 "%s: noise floor failed detected; detected %u, " 1254 "threshold %u\n", __func__, nf, nfThresh); 1255 /* 1256 * NB: Don't discriminate 2.4 vs 5Ghz, if this 1257 * happens it indicates a problem regardless 1258 * of the band. 1259 */ 1260 chan->ic_state |= IEEE80211_CHANSTATE_CWINT; 1261 nf = 0; 1262 } 1263 } else 1264 nf = 0; 1265 1266 /* 1267 * Pass through histogram and write median value as 1268 * calculated from the accrued window. We require a 1269 * full window of in-range values to be seen before we 1270 * start using the history. 1271 */ 1272 updateNFHistBuff(h, nf); 1273 if (h->first_run) { 1274 if (nf < AR5212_CCA_MIN_BAD_VALUE || 1275 nf > AR5212_CCA_MAX_HIGH_VALUE) { 1276 nf = AR5212_CCA_MAX_GOOD_VALUE; 1277 h->invalidNFcount = AR512_NF_CAL_HIST_MAX; 1278 } else if (--(h->invalidNFcount) == 0) { 1279 h->first_run = 0; 1280 h->privNF = nf = ar5212GetNfHistMid(h->nfCalBuffer); 1281 } else { 1282 nf = AR5212_CCA_MAX_GOOD_VALUE; 1283 } 1284 } else { 1285 h->privNF = nf = ar5212GetNfHistMid(h->nfCalBuffer); 1286 } 1287 1288 val = OS_REG_READ(ah, AR_PHY(25)); 1289 val &= 0xFFFFFE00; 1290 val |= (((uint32_t)nf << 1) & 0x1FF); 1291 OS_REG_WRITE(ah, AR_PHY(25), val); 1292 OS_REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_ENABLE_NF); 1293 OS_REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NO_UPDATE_NF); 1294 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); 1295 1296 if (!ath_hal_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF, 0)) { 1297#ifdef AH_DEBUG 1298 ath_hal_printf(ah, "%s: AGC not ready AGC_CONTROL 0x%x\n", 1299 __func__, OS_REG_READ(ah, AR_PHY_AGC_CONTROL)); 1300#endif 1301 } 1302 1303 /* 1304 * Now load a high maxCCAPower value again so that we're 1305 * not capped by the median we just loaded 1306 */ 1307 val &= 0xFFFFFE00; 1308 val |= (((uint32_t)(-50) << 1) & 0x1FF); 1309 OS_REG_WRITE(ah, AR_PHY(25), val); 1310 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_ENABLE_NF); 1311 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NO_UPDATE_NF); 1312 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); 1313 1314 return (ichan->rawNoiseFloor = nf); 1315} 1316 1317/* 1318 * Set up compression configuration registers 1319 */ 1320void 1321ar5212SetCompRegs(struct ath_hal *ah) 1322{ 1323 struct ath_hal_5212 *ahp = AH5212(ah); 1324 int i; 1325 1326 /* Check if h/w supports compression */ 1327 if (!AH_PRIVATE(ah)->ah_caps.halCompressSupport) 1328 return; 1329 1330 OS_REG_WRITE(ah, AR_DCCFG, 1); 1331 1332 OS_REG_WRITE(ah, AR_CCFG, 1333 (AR_COMPRESSION_WINDOW_SIZE >> 8) & AR_CCFG_WIN_M); 1334 1335 OS_REG_WRITE(ah, AR_CCFG, 1336 OS_REG_READ(ah, AR_CCFG) | AR_CCFG_MIB_INT_EN); 1337 OS_REG_WRITE(ah, AR_CCUCFG, 1338 AR_CCUCFG_RESET_VAL | AR_CCUCFG_CATCHUP_EN); 1339 1340 OS_REG_WRITE(ah, AR_CPCOVF, 0); 1341 1342 /* reset decompression mask */ 1343 for (i = 0; i < HAL_DECOMP_MASK_SIZE; i++) { 1344 OS_REG_WRITE(ah, AR_DCM_A, i); 1345 OS_REG_WRITE(ah, AR_DCM_D, ahp->ah_decompMask[i]); 1346 } 1347} 1348 1349HAL_BOOL 1350ar5212SetAntennaSwitchInternal(struct ath_hal *ah, HAL_ANT_SETTING settings, 1351 const struct ieee80211_channel *chan) 1352{ 1353#define ANT_SWITCH_TABLE1 AR_PHY(88) 1354#define ANT_SWITCH_TABLE2 AR_PHY(89) 1355 struct ath_hal_5212 *ahp = AH5212(ah); 1356 const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom; 1357 uint32_t antSwitchA, antSwitchB; 1358 int ix; 1359 1360 HALASSERT(ah->ah_magic == AR5212_MAGIC); 1361 HALASSERT(ahp->ah_phyPowerOn); 1362 1363 switch (chan->ic_flags & IEEE80211_CHAN_ALLFULL) { 1364 case IEEE80211_CHAN_A: 1365 ix = 0; 1366 break; 1367 case IEEE80211_CHAN_G: 1368 case IEEE80211_CHAN_PUREG: /* NB: 108G */ 1369 ix = 2; 1370 break; 1371 case IEEE80211_CHAN_B: 1372 if (IS_2425(ah) || IS_2417(ah)) { 1373 /* NB: Nala/Swan: 11b is handled using 11g */ 1374 ix = 2; 1375 } else 1376 ix = 1; 1377 break; 1378 default: 1379 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n", 1380 __func__, chan->ic_flags); 1381 return AH_FALSE; 1382 } 1383 1384 antSwitchA = ee->ee_antennaControl[1][ix] 1385 | (ee->ee_antennaControl[2][ix] << 6) 1386 | (ee->ee_antennaControl[3][ix] << 12) 1387 | (ee->ee_antennaControl[4][ix] << 18) 1388 | (ee->ee_antennaControl[5][ix] << 24) 1389 ; 1390 antSwitchB = ee->ee_antennaControl[6][ix] 1391 | (ee->ee_antennaControl[7][ix] << 6) 1392 | (ee->ee_antennaControl[8][ix] << 12) 1393 | (ee->ee_antennaControl[9][ix] << 18) 1394 | (ee->ee_antennaControl[10][ix] << 24) 1395 ; 1396 /* 1397 * For fixed antenna, give the same setting for both switch banks 1398 */ 1399 switch (settings) { 1400 case HAL_ANT_FIXED_A: 1401 antSwitchB = antSwitchA; 1402 break; 1403 case HAL_ANT_FIXED_B: 1404 antSwitchA = antSwitchB; 1405 break; 1406 case HAL_ANT_VARIABLE: 1407 break; 1408 default: 1409 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad antenna setting %u\n", 1410 __func__, settings); 1411 return AH_FALSE; 1412 } 1413 if (antSwitchB == antSwitchA) { 1414 HALDEBUG(ah, HAL_DEBUG_RFPARAM, 1415 "%s: Setting fast diversity off.\n", __func__); 1416 OS_REG_CLR_BIT(ah,AR_PHY_CCK_DETECT, 1417 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV); 1418 ahp->ah_diversity = AH_FALSE; 1419 } else { 1420 HALDEBUG(ah, HAL_DEBUG_RFPARAM, 1421 "%s: Setting fast diversity on.\n", __func__); 1422 OS_REG_SET_BIT(ah,AR_PHY_CCK_DETECT, 1423 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV); 1424 ahp->ah_diversity = AH_TRUE; 1425 } 1426 ahp->ah_antControl = settings; 1427 1428 OS_REG_WRITE(ah, ANT_SWITCH_TABLE1, antSwitchA); 1429 OS_REG_WRITE(ah, ANT_SWITCH_TABLE2, antSwitchB); 1430 1431 return AH_TRUE; 1432#undef ANT_SWITCH_TABLE2 1433#undef ANT_SWITCH_TABLE1 1434} 1435 1436HAL_BOOL 1437ar5212IsSpurChannel(struct ath_hal *ah, const struct ieee80211_channel *chan) 1438{ 1439 uint16_t freq = ath_hal_gethwchannel(ah, chan); 1440 uint32_t clockFreq = 1441 ((IS_5413(ah) || IS_RAD5112_ANY(ah) || IS_2417(ah)) ? 40 : 32); 1442 return ( ((freq % clockFreq) != 0) 1443 && (((freq % clockFreq) < 10) 1444 || (((freq) % clockFreq) > 22)) ); 1445} 1446 1447/* 1448 * Read EEPROM header info and program the device for correct operation 1449 * given the channel value. 1450 */ 1451HAL_BOOL 1452ar5212SetBoardValues(struct ath_hal *ah, const struct ieee80211_channel *chan) 1453{ 1454#define NO_FALSE_DETECT_BACKOFF 2 1455#define CB22_FALSE_DETECT_BACKOFF 6 1456#define AR_PHY_BIS(_ah, _reg, _mask, _val) \ 1457 OS_REG_WRITE(_ah, AR_PHY(_reg), \ 1458 (OS_REG_READ(_ah, AR_PHY(_reg)) & _mask) | (_val)); 1459 struct ath_hal_5212 *ahp = AH5212(ah); 1460 const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom; 1461 int arrayMode, falseDectectBackoff; 1462 int is2GHz = IEEE80211_IS_CHAN_2GHZ(chan); 1463 HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan); 1464 int8_t adcDesiredSize, pgaDesiredSize; 1465 uint16_t switchSettling, txrxAtten, rxtxMargin; 1466 int iCoff, qCoff; 1467 1468 HALASSERT(ah->ah_magic == AR5212_MAGIC); 1469 1470 switch (chan->ic_flags & IEEE80211_CHAN_ALLTURBOFULL) { 1471 case IEEE80211_CHAN_A: 1472 case IEEE80211_CHAN_ST: 1473 arrayMode = headerInfo11A; 1474 if (!IS_RAD5112_ANY(ah) && !IS_2413(ah) && !IS_5413(ah)) 1475 OS_REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL, 1476 AR_PHY_FRAME_CTL_TX_CLIP, 1477 ahp->ah_gainValues.currStep->paramVal[GP_TXCLIP]); 1478 break; 1479 case IEEE80211_CHAN_B: 1480 arrayMode = headerInfo11B; 1481 break; 1482 case IEEE80211_CHAN_G: 1483 case IEEE80211_CHAN_108G: 1484 arrayMode = headerInfo11G; 1485 break; 1486 default: 1487 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n", 1488 __func__, chan->ic_flags); 1489 return AH_FALSE; 1490 } 1491 1492 /* Set the antenna register(s) correctly for the chip revision */ 1493 AR_PHY_BIS(ah, 68, 0xFFFFFC06, 1494 (ee->ee_antennaControl[0][arrayMode] << 4) | 0x1); 1495 1496 ar5212SetAntennaSwitchInternal(ah, ahp->ah_antControl, chan); 1497 1498 /* Set the Noise Floor Thresh on ar5211 devices */ 1499 OS_REG_WRITE(ah, AR_PHY(90), 1500 (ee->ee_noiseFloorThresh[arrayMode] & 0x1FF) 1501 | (1 << 9)); 1502 1503 if (ee->ee_version >= AR_EEPROM_VER5_0 && IEEE80211_IS_CHAN_TURBO(chan)) { 1504 switchSettling = ee->ee_switchSettlingTurbo[is2GHz]; 1505 adcDesiredSize = ee->ee_adcDesiredSizeTurbo[is2GHz]; 1506 pgaDesiredSize = ee->ee_pgaDesiredSizeTurbo[is2GHz]; 1507 txrxAtten = ee->ee_txrxAttenTurbo[is2GHz]; 1508 rxtxMargin = ee->ee_rxtxMarginTurbo[is2GHz]; 1509 } else { 1510 switchSettling = ee->ee_switchSettling[arrayMode]; 1511 adcDesiredSize = ee->ee_adcDesiredSize[arrayMode]; 1512 pgaDesiredSize = ee->ee_pgaDesiredSize[is2GHz]; 1513 txrxAtten = ee->ee_txrxAtten[is2GHz]; 1514 rxtxMargin = ee->ee_rxtxMargin[is2GHz]; 1515 } 1516 1517 OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, 1518 AR_PHY_SETTLING_SWITCH, switchSettling); 1519 OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, 1520 AR_PHY_DESIRED_SZ_ADC, adcDesiredSize); 1521 OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, 1522 AR_PHY_DESIRED_SZ_PGA, pgaDesiredSize); 1523 OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN, 1524 AR_PHY_RXGAIN_TXRX_ATTEN, txrxAtten); 1525 OS_REG_WRITE(ah, AR_PHY(13), 1526 (ee->ee_txEndToXPAOff[arrayMode] << 24) 1527 | (ee->ee_txEndToXPAOff[arrayMode] << 16) 1528 | (ee->ee_txFrameToXPAOn[arrayMode] << 8) 1529 | ee->ee_txFrameToXPAOn[arrayMode]); 1530 AR_PHY_BIS(ah, 10, 0xFFFF00FF, 1531 ee->ee_txEndToXLNAOn[arrayMode] << 8); 1532 AR_PHY_BIS(ah, 25, 0xFFF80FFF, 1533 (ee->ee_thresh62[arrayMode] << 12) & 0x7F000); 1534 1535 /* 1536 * False detect backoff - suspected 32 MHz spur causes false 1537 * detects in OFDM, causing Tx Hangs. Decrease weak signal 1538 * sensitivity for this card. 1539 */ 1540 falseDectectBackoff = NO_FALSE_DETECT_BACKOFF; 1541 if (ee->ee_version < AR_EEPROM_VER3_3) { 1542 /* XXX magic number */ 1543 if (AH_PRIVATE(ah)->ah_subvendorid == 0x1022 && 1544 IEEE80211_IS_CHAN_OFDM(chan)) 1545 falseDectectBackoff += CB22_FALSE_DETECT_BACKOFF; 1546 } else { 1547 if (ar5212IsSpurChannel(ah, chan)) 1548 falseDectectBackoff += ee->ee_falseDetectBackoff[arrayMode]; 1549 } 1550 AR_PHY_BIS(ah, 73, 0xFFFFFF01, (falseDectectBackoff << 1) & 0xFE); 1551 1552 if (ichan->privFlags & CHANNEL_IQVALID) { 1553 iCoff = ichan->iCoff; 1554 qCoff = ichan->qCoff; 1555 } else { 1556 iCoff = ee->ee_iqCalI[is2GHz]; 1557 qCoff = ee->ee_iqCalQ[is2GHz]; 1558 } 1559 1560 /* write previous IQ results */ 1561 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4, 1562 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF, iCoff); 1563 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4, 1564 AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, qCoff); 1565 OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4, 1566 AR_PHY_TIMING_CTRL4_IQCORR_ENABLE); 1567 1568 if (ee->ee_version >= AR_EEPROM_VER4_1) { 1569 if (!IEEE80211_IS_CHAN_108G(chan) || ee->ee_version >= AR_EEPROM_VER5_0) 1570 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, 1571 AR_PHY_GAIN_2GHZ_RXTX_MARGIN, rxtxMargin); 1572 } 1573 if (ee->ee_version >= AR_EEPROM_VER5_1) { 1574 /* for now always disabled */ 1575 OS_REG_WRITE(ah, AR_PHY_HEAVY_CLIP_ENABLE, 0); 1576 } 1577 1578 return AH_TRUE; 1579#undef AR_PHY_BIS 1580#undef NO_FALSE_DETECT_BACKOFF 1581#undef CB22_FALSE_DETECT_BACKOFF 1582} 1583 1584/* 1585 * Apply Spur Immunity to Boards that require it. 1586 * Applies only to OFDM RX operation. 1587 */ 1588 1589void 1590ar5212SetSpurMitigation(struct ath_hal *ah, 1591 const struct ieee80211_channel *chan) 1592{ 1593 uint32_t pilotMask[2] = {0, 0}, binMagMask[4] = {0, 0, 0 , 0}; 1594 uint16_t i, finalSpur, curChanAsSpur, binWidth = 0, spurDetectWidth, spurChan; 1595 int32_t spurDeltaPhase = 0, spurFreqSd = 0, spurOffset, binOffsetNumT16, curBinOffset; 1596 int16_t numBinOffsets; 1597 static const uint16_t magMapFor4[4] = {1, 2, 2, 1}; 1598 static const uint16_t magMapFor3[3] = {1, 2, 1}; 1599 const uint16_t *pMagMap; 1600 HAL_BOOL is2GHz = IEEE80211_IS_CHAN_2GHZ(chan); 1601 HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan); 1602 uint32_t val; 1603 1604#define CHAN_TO_SPUR(_f, _freq) ( ((_freq) - ((_f) ? 2300 : 4900)) * 10 ) 1605 if (IS_2417(ah)) { 1606 HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s: no spur mitigation\n", 1607 __func__); 1608 return; 1609 } 1610 1611 curChanAsSpur = CHAN_TO_SPUR(is2GHz, ichan->channel); 1612 1613 if (ichan->mainSpur) { 1614 /* Pull out the saved spur value */ 1615 finalSpur = ichan->mainSpur; 1616 } else { 1617 /* 1618 * Check if spur immunity should be performed for this channel 1619 * Should only be performed once per channel and then saved 1620 */ 1621 finalSpur = AR_NO_SPUR; 1622 spurDetectWidth = HAL_SPUR_CHAN_WIDTH; 1623 if (IEEE80211_IS_CHAN_TURBO(chan)) 1624 spurDetectWidth *= 2; 1625 1626 /* Decide if any spur affects the current channel */ 1627 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { 1628 spurChan = ath_hal_getSpurChan(ah, i, is2GHz); 1629 if (spurChan == AR_NO_SPUR) { 1630 break; 1631 } 1632 if ((curChanAsSpur - spurDetectWidth <= (spurChan & HAL_SPUR_VAL_MASK)) && 1633 (curChanAsSpur + spurDetectWidth >= (spurChan & HAL_SPUR_VAL_MASK))) { 1634 finalSpur = spurChan & HAL_SPUR_VAL_MASK; 1635 break; 1636 } 1637 } 1638 /* Save detected spur (or no spur) for this channel */ 1639 ichan->mainSpur = finalSpur; 1640 } 1641 1642 /* Write spur immunity data */ 1643 if (finalSpur == AR_NO_SPUR) { 1644 /* Disable Spur Immunity Regs if they appear set */ 1645 if (OS_REG_READ(ah, AR_PHY_TIMING_CTRL4) & AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER) { 1646 /* Clear Spur Delta Phase, Spur Freq, and enable bits */ 1647 OS_REG_RMW_FIELD(ah, AR_PHY_MASK_CTL, AR_PHY_MASK_CTL_RATE, 0); 1648 val = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4); 1649 val &= ~(AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER | 1650 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK | 1651 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK); 1652 OS_REG_WRITE(ah, AR_PHY_MASK_CTL, val); 1653 OS_REG_WRITE(ah, AR_PHY_TIMING11, 0); 1654 1655 /* Clear pilot masks */ 1656 OS_REG_WRITE(ah, AR_PHY_TIMING7, 0); 1657 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING8, AR_PHY_TIMING8_PILOT_MASK_2, 0); 1658 OS_REG_WRITE(ah, AR_PHY_TIMING9, 0); 1659 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING10, AR_PHY_TIMING10_PILOT_MASK_2, 0); 1660 1661 /* Clear magnitude masks */ 1662 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_1, 0); 1663 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_2, 0); 1664 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_3, 0); 1665 OS_REG_RMW_FIELD(ah, AR_PHY_MASK_CTL, AR_PHY_MASK_CTL_MASK_4, 0); 1666 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_1, 0); 1667 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_2, 0); 1668 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_3, 0); 1669 OS_REG_RMW_FIELD(ah, AR_PHY_BIN_MASK2_4, AR_PHY_BIN_MASK2_4_MASK_4, 0); 1670 } 1671 } else { 1672 spurOffset = finalSpur - curChanAsSpur; 1673 /* 1674 * Spur calculations: 1675 * spurDeltaPhase is (spurOffsetIn100KHz / chipFrequencyIn100KHz) << 21 1676 * spurFreqSd is (spurOffsetIn100KHz / sampleFrequencyIn100KHz) << 11 1677 */ 1678 if (IEEE80211_IS_CHAN_TURBO(chan)) { 1679 /* Chip Frequency & sampleFrequency are 80 MHz */ 1680 spurDeltaPhase = (spurOffset << 16) / 25; 1681 spurFreqSd = spurDeltaPhase >> 10; 1682 binWidth = HAL_BIN_WIDTH_TURBO_100HZ; 1683 } else if (IEEE80211_IS_CHAN_G(chan)) { 1684 /* Chip Frequency is 44MHz, sampleFrequency is 40 MHz */ 1685 spurFreqSd = (spurOffset << 8) / 55; 1686 spurDeltaPhase = (spurOffset << 17) / 25; 1687 binWidth = HAL_BIN_WIDTH_BASE_100HZ; 1688 } else { 1689 HALASSERT(!IEEE80211_IS_CHAN_B(chan)); 1690 /* Chip Frequency & sampleFrequency are 40 MHz */ 1691 spurDeltaPhase = (spurOffset << 17) / 25; 1692 spurFreqSd = spurDeltaPhase >> 10; 1693 binWidth = HAL_BIN_WIDTH_BASE_100HZ; 1694 } 1695 1696 /* Compute Pilot Mask */ 1697 binOffsetNumT16 = ((spurOffset * 1000) << 4) / binWidth; 1698 /* The spur is on a bin if it's remainder at times 16 is 0 */ 1699 if (binOffsetNumT16 & 0xF) { 1700 numBinOffsets = 4; 1701 pMagMap = magMapFor4; 1702 } else { 1703 numBinOffsets = 3; 1704 pMagMap = magMapFor3; 1705 } 1706 for (i = 0; i < numBinOffsets; i++) { 1707 if ((binOffsetNumT16 >> 4) > HAL_MAX_BINS_ALLOWED) { 1708 HALDEBUG(ah, HAL_DEBUG_ANY, 1709 "Too man bins in spur mitigation\n"); 1710 return; 1711 } 1712 1713 /* Get Pilot Mask values */ 1714 curBinOffset = (binOffsetNumT16 >> 4) + i + 25; 1715 if ((curBinOffset >= 0) && (curBinOffset <= 32)) { 1716 if (curBinOffset <= 25) 1717 pilotMask[0] |= 1 << curBinOffset; 1718 else if (curBinOffset >= 27) 1719 pilotMask[0] |= 1 << (curBinOffset - 1); 1720 } else if ((curBinOffset >= 33) && (curBinOffset <= 52)) 1721 pilotMask[1] |= 1 << (curBinOffset - 33); 1722 1723 /* Get viterbi values */ 1724 if ((curBinOffset >= -1) && (curBinOffset <= 14)) 1725 binMagMask[0] |= pMagMap[i] << (curBinOffset + 1) * 2; 1726 else if ((curBinOffset >= 15) && (curBinOffset <= 30)) 1727 binMagMask[1] |= pMagMap[i] << (curBinOffset - 15) * 2; 1728 else if ((curBinOffset >= 31) && (curBinOffset <= 46)) 1729 binMagMask[2] |= pMagMap[i] << (curBinOffset -31) * 2; 1730 else if((curBinOffset >= 47) && (curBinOffset <= 53)) 1731 binMagMask[3] |= pMagMap[i] << (curBinOffset -47) * 2; 1732 } 1733 1734 /* Write Spur Delta Phase, Spur Freq, and enable bits */ 1735 OS_REG_RMW_FIELD(ah, AR_PHY_MASK_CTL, AR_PHY_MASK_CTL_RATE, 0xFF); 1736 val = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4); 1737 val |= (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER | 1738 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK | 1739 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK); 1740 OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4, val); 1741 OS_REG_WRITE(ah, AR_PHY_TIMING11, AR_PHY_TIMING11_USE_SPUR_IN_AGC | 1742 SM(spurFreqSd, AR_PHY_TIMING11_SPUR_FREQ_SD) | 1743 SM(spurDeltaPhase, AR_PHY_TIMING11_SPUR_DELTA_PHASE)); 1744 1745 /* Write pilot masks */ 1746 OS_REG_WRITE(ah, AR_PHY_TIMING7, pilotMask[0]); 1747 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING8, AR_PHY_TIMING8_PILOT_MASK_2, pilotMask[1]); 1748 OS_REG_WRITE(ah, AR_PHY_TIMING9, pilotMask[0]); 1749 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING10, AR_PHY_TIMING10_PILOT_MASK_2, pilotMask[1]); 1750 1751 /* Write magnitude masks */ 1752 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_1, binMagMask[0]); 1753 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_2, binMagMask[1]); 1754 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_3, binMagMask[2]); 1755 OS_REG_RMW_FIELD(ah, AR_PHY_MASK_CTL, AR_PHY_MASK_CTL_MASK_4, binMagMask[3]); 1756 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_1, binMagMask[0]); 1757 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_2, binMagMask[1]); 1758 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_3, binMagMask[2]); 1759 OS_REG_RMW_FIELD(ah, AR_PHY_BIN_MASK2_4, AR_PHY_BIN_MASK2_4_MASK_4, binMagMask[3]); 1760 } 1761#undef CHAN_TO_SPUR 1762} 1763 1764 1765/* 1766 * Delta slope coefficient computation. 1767 * Required for OFDM operation. 1768 */ 1769void 1770ar5212SetDeltaSlope(struct ath_hal *ah, const struct ieee80211_channel *chan) 1771{ 1772#define COEF_SCALE_S 24 1773#define INIT_CLOCKMHZSCALED 0x64000000 1774 uint16_t freq = ath_hal_gethwchannel(ah, chan); 1775 unsigned long coef_scaled, coef_exp, coef_man, ds_coef_exp, ds_coef_man; 1776 unsigned long clockMhzScaled = INIT_CLOCKMHZSCALED; 1777 1778 if (IEEE80211_IS_CHAN_TURBO(chan)) 1779 clockMhzScaled *= 2; 1780 /* half and quarter rate can divide the scaled clock by 2 or 4 respectively */ 1781 /* scale for selected channel bandwidth */ 1782 if (IEEE80211_IS_CHAN_HALF(chan)) { 1783 clockMhzScaled = clockMhzScaled >> 1; 1784 } else if (IEEE80211_IS_CHAN_QUARTER(chan)) { 1785 clockMhzScaled = clockMhzScaled >> 2; 1786 } 1787 1788 /* 1789 * ALGO -> coef = 1e8/fcarrier*fclock/40; 1790 * scaled coef to provide precision for this floating calculation 1791 */ 1792 coef_scaled = clockMhzScaled / freq; 1793 1794 /* 1795 * ALGO -> coef_exp = 14-floor(log2(coef)); 1796 * floor(log2(x)) is the highest set bit position 1797 */ 1798 for (coef_exp = 31; coef_exp > 0; coef_exp--) 1799 if ((coef_scaled >> coef_exp) & 0x1) 1800 break; 1801 /* A coef_exp of 0 is a legal bit position but an unexpected coef_exp */ 1802 HALASSERT(coef_exp); 1803 coef_exp = 14 - (coef_exp - COEF_SCALE_S); 1804 1805 /* 1806 * ALGO -> coef_man = floor(coef* 2^coef_exp+0.5); 1807 * The coefficient is already shifted up for scaling 1808 */ 1809 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1)); 1810 ds_coef_man = coef_man >> (COEF_SCALE_S - coef_exp); 1811 ds_coef_exp = coef_exp - 16; 1812 1813 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING3, 1814 AR_PHY_TIMING3_DSC_MAN, ds_coef_man); 1815 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING3, 1816 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp); 1817#undef INIT_CLOCKMHZSCALED 1818#undef COEF_SCALE_S 1819} 1820 1821/* 1822 * Set a limit on the overall output power. Used for dynamic 1823 * transmit power control and the like. 1824 * 1825 * NB: limit is in units of 0.5 dbM. 1826 */ 1827HAL_BOOL 1828ar5212SetTxPowerLimit(struct ath_hal *ah, uint32_t limit) 1829{ 1830 /* XXX blech, construct local writable copy */ 1831 struct ieee80211_channel dummy = *AH_PRIVATE(ah)->ah_curchan; 1832 uint16_t dummyXpdGains[2]; 1833 HAL_BOOL isBmode; 1834 1835 SAVE_CCK(ah, &dummy, isBmode); 1836 AH_PRIVATE(ah)->ah_powerLimit = AH_MIN(limit, MAX_RATE_POWER); 1837 return ar5212SetTransmitPower(ah, &dummy, dummyXpdGains); 1838} 1839 1840/* 1841 * Set the transmit power in the baseband for the given 1842 * operating channel and mode. 1843 */ 1844HAL_BOOL 1845ar5212SetTransmitPower(struct ath_hal *ah, 1846 const struct ieee80211_channel *chan, uint16_t *rfXpdGain) 1847{ 1848#define POW_OFDM(_r, _s) (((0 & 1)<< ((_s)+6)) | (((_r) & 0x3f) << (_s))) 1849#define POW_CCK(_r, _s) (((_r) & 0x3f) << (_s)) 1850#define N(a) (sizeof (a) / sizeof (a[0])) 1851 static const uint16_t tpcScaleReductionTable[5] = 1852 { 0, 3, 6, 9, MAX_RATE_POWER }; 1853 struct ath_hal_5212 *ahp = AH5212(ah); 1854 uint16_t freq = ath_hal_gethwchannel(ah, chan); 1855 const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom; 1856 int16_t minPower, maxPower, tpcInDb, powerLimit; 1857 int i; 1858 1859 HALASSERT(ah->ah_magic == AR5212_MAGIC); 1860 1861 OS_MEMZERO(ahp->ah_pcdacTable, ahp->ah_pcdacTableSize); 1862 OS_MEMZERO(ahp->ah_ratesArray, sizeof(ahp->ah_ratesArray)); 1863 1864 powerLimit = AH_MIN(MAX_RATE_POWER, AH_PRIVATE(ah)->ah_powerLimit); 1865 if (powerLimit >= MAX_RATE_POWER || powerLimit == 0) 1866 tpcInDb = tpcScaleReductionTable[AH_PRIVATE(ah)->ah_tpScale]; 1867 else 1868 tpcInDb = 0; 1869 if (!ar5212SetRateTable(ah, chan, tpcInDb, powerLimit, 1870 AH_TRUE, &minPower, &maxPower)) { 1871 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unable to set rate table\n", 1872 __func__); 1873 return AH_FALSE; 1874 } 1875 if (!ahp->ah_rfHal->setPowerTable(ah, 1876 &minPower, &maxPower, chan, rfXpdGain)) { 1877 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unable to set power table\n", 1878 __func__); 1879 return AH_FALSE; 1880 } 1881 1882 /* 1883 * Adjust XR power/rate up by 2 dB to account for greater peak 1884 * to avg ratio - except in newer avg power designs 1885 */ 1886 if (!IS_2413(ah) && !IS_5413(ah)) 1887 ahp->ah_ratesArray[15] += 4; 1888 /* 1889 * txPowerIndexOffset is set by the SetPowerTable() call - 1890 * adjust the rate table 1891 */ 1892 for (i = 0; i < N(ahp->ah_ratesArray); i++) { 1893 ahp->ah_ratesArray[i] += ahp->ah_txPowerIndexOffset; 1894 if (ahp->ah_ratesArray[i] > 63) 1895 ahp->ah_ratesArray[i] = 63; 1896 } 1897 1898 if (ee->ee_eepMap < 2) { 1899 /* 1900 * Correct gain deltas for 5212 G operation - 1901 * Removed with revised chipset 1902 */ 1903 if (AH_PRIVATE(ah)->ah_phyRev < AR_PHY_CHIP_ID_REV_2 && 1904 IEEE80211_IS_CHAN_G(chan)) { 1905 uint16_t cckOfdmPwrDelta; 1906 1907 if (freq == 2484) 1908 cckOfdmPwrDelta = SCALE_OC_DELTA( 1909 ee->ee_cckOfdmPwrDelta - 1910 ee->ee_scaledCh14FilterCckDelta); 1911 else 1912 cckOfdmPwrDelta = SCALE_OC_DELTA( 1913 ee->ee_cckOfdmPwrDelta); 1914 ar5212CorrectGainDelta(ah, cckOfdmPwrDelta); 1915 } 1916 /* 1917 * Finally, write the power values into the 1918 * baseband power table 1919 */ 1920 for (i = 0; i < (PWR_TABLE_SIZE/2); i++) { 1921 OS_REG_WRITE(ah, AR_PHY_PCDAC_TX_POWER(i), 1922 ((((ahp->ah_pcdacTable[2*i + 1] << 8) | 0xff) & 0xffff) << 16) 1923 | (((ahp->ah_pcdacTable[2*i] << 8) | 0xff) & 0xffff) 1924 ); 1925 } 1926 } 1927 1928 /* Write the OFDM power per rate set */ 1929 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE1, 1930 POW_OFDM(ahp->ah_ratesArray[3], 24) 1931 | POW_OFDM(ahp->ah_ratesArray[2], 16) 1932 | POW_OFDM(ahp->ah_ratesArray[1], 8) 1933 | POW_OFDM(ahp->ah_ratesArray[0], 0) 1934 ); 1935 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE2, 1936 POW_OFDM(ahp->ah_ratesArray[7], 24) 1937 | POW_OFDM(ahp->ah_ratesArray[6], 16) 1938 | POW_OFDM(ahp->ah_ratesArray[5], 8) 1939 | POW_OFDM(ahp->ah_ratesArray[4], 0) 1940 ); 1941 1942 /* Write the CCK power per rate set */ 1943 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE3, 1944 POW_CCK(ahp->ah_ratesArray[10], 24) 1945 | POW_CCK(ahp->ah_ratesArray[9], 16) 1946 | POW_CCK(ahp->ah_ratesArray[15], 8) /* XR target power */ 1947 | POW_CCK(ahp->ah_ratesArray[8], 0) 1948 ); 1949 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE4, 1950 POW_CCK(ahp->ah_ratesArray[14], 24) 1951 | POW_CCK(ahp->ah_ratesArray[13], 16) 1952 | POW_CCK(ahp->ah_ratesArray[12], 8) 1953 | POW_CCK(ahp->ah_ratesArray[11], 0) 1954 ); 1955 1956 /* 1957 * Set max power to 30 dBm and, optionally, 1958 * enable TPC in tx descriptors. 1959 */ 1960 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE_MAX, MAX_RATE_POWER | 1961 (ahp->ah_tpcEnabled ? AR_PHY_POWER_TX_RATE_MAX_TPC_ENABLE : 0)); 1962 1963 return AH_TRUE; 1964#undef N 1965#undef POW_CCK 1966#undef POW_OFDM 1967} 1968 1969/* 1970 * Sets the transmit power in the baseband for the given 1971 * operating channel and mode. 1972 */ 1973static HAL_BOOL 1974ar5212SetRateTable(struct ath_hal *ah, const struct ieee80211_channel *chan, 1975 int16_t tpcScaleReduction, int16_t powerLimit, HAL_BOOL commit, 1976 int16_t *pMinPower, int16_t *pMaxPower) 1977{ 1978 struct ath_hal_5212 *ahp = AH5212(ah); 1979 uint16_t freq = ath_hal_gethwchannel(ah, chan); 1980 const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom; 1981 uint16_t *rpow = ahp->ah_ratesArray; 1982 uint16_t twiceMaxEdgePower = MAX_RATE_POWER; 1983 uint16_t twiceMaxEdgePowerCck = MAX_RATE_POWER; 1984 uint16_t twiceMaxRDPower = MAX_RATE_POWER; 1985 int i; 1986 uint8_t cfgCtl; 1987 int8_t twiceAntennaGain, twiceAntennaReduction; 1988 const RD_EDGES_POWER *rep; 1989 TRGT_POWER_INFO targetPowerOfdm, targetPowerCck; 1990 int16_t scaledPower, maxAvailPower = 0; 1991 int16_t r13, r9, r7, r0; 1992 1993 HALASSERT(ah->ah_magic == AR5212_MAGIC); 1994 1995 twiceMaxRDPower = chan->ic_maxregpower * 2; 1996 *pMaxPower = -MAX_RATE_POWER; 1997 *pMinPower = MAX_RATE_POWER; 1998 1999 /* Get conformance test limit maximum for this channel */ 2000 cfgCtl = ath_hal_getctl(ah, chan); 2001 for (i = 0; i < ee->ee_numCtls; i++) { 2002 uint16_t twiceMinEdgePower; 2003 2004 if (ee->ee_ctl[i] == 0) 2005 continue; 2006 if (ee->ee_ctl[i] == cfgCtl || 2007 cfgCtl == ((ee->ee_ctl[i] & CTL_MODE_M) | SD_NO_CTL)) { 2008 rep = &ee->ee_rdEdgesPower[i * NUM_EDGES]; 2009 twiceMinEdgePower = ar5212GetMaxEdgePower(freq, rep); 2010 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) { 2011 /* Find the minimum of all CTL edge powers that apply to this channel */ 2012 twiceMaxEdgePower = AH_MIN(twiceMaxEdgePower, twiceMinEdgePower); 2013 } else { 2014 twiceMaxEdgePower = twiceMinEdgePower; 2015 break; 2016 } 2017 } 2018 } 2019 2020 if (IEEE80211_IS_CHAN_G(chan)) { 2021 /* Check for a CCK CTL for 11G CCK powers */ 2022 cfgCtl = (cfgCtl & ~CTL_MODE_M) | CTL_11B; 2023 for (i = 0; i < ee->ee_numCtls; i++) { 2024 uint16_t twiceMinEdgePowerCck; 2025 2026 if (ee->ee_ctl[i] == 0) 2027 continue; 2028 if (ee->ee_ctl[i] == cfgCtl || 2029 cfgCtl == ((ee->ee_ctl[i] & CTL_MODE_M) | SD_NO_CTL)) { 2030 rep = &ee->ee_rdEdgesPower[i * NUM_EDGES]; 2031 twiceMinEdgePowerCck = ar5212GetMaxEdgePower(freq, rep); 2032 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) { 2033 /* Find the minimum of all CTL edge powers that apply to this channel */ 2034 twiceMaxEdgePowerCck = AH_MIN(twiceMaxEdgePowerCck, twiceMinEdgePowerCck); 2035 } else { 2036 twiceMaxEdgePowerCck = twiceMinEdgePowerCck; 2037 break; 2038 } 2039 } 2040 } 2041 } else { 2042 /* Set the 11B cck edge power to the one found before */ 2043 twiceMaxEdgePowerCck = twiceMaxEdgePower; 2044 } 2045 2046 /* Get Antenna Gain reduction */ 2047 if (IEEE80211_IS_CHAN_5GHZ(chan)) { 2048 ath_hal_eepromGet(ah, AR_EEP_ANTGAINMAX_5, &twiceAntennaGain); 2049 } else { 2050 ath_hal_eepromGet(ah, AR_EEP_ANTGAINMAX_2, &twiceAntennaGain); 2051 } 2052 twiceAntennaReduction = 2053 ath_hal_getantennareduction(ah, chan, twiceAntennaGain); 2054 2055 if (IEEE80211_IS_CHAN_OFDM(chan)) { 2056 /* Get final OFDM target powers */ 2057 if (IEEE80211_IS_CHAN_2GHZ(chan)) { 2058 ar5212GetTargetPowers(ah, chan, ee->ee_trgtPwr_11g, 2059 ee->ee_numTargetPwr_11g, &targetPowerOfdm); 2060 } else { 2061 ar5212GetTargetPowers(ah, chan, ee->ee_trgtPwr_11a, 2062 ee->ee_numTargetPwr_11a, &targetPowerOfdm); 2063 } 2064 2065 /* Get Maximum OFDM power */ 2066 /* Minimum of target and edge powers */ 2067 scaledPower = AH_MIN(twiceMaxEdgePower, 2068 twiceMaxRDPower - twiceAntennaReduction); 2069 2070 /* 2071 * If turbo is set, reduce power to keep power 2072 * consumption under 2 Watts. Note that we always do 2073 * this unless specially configured. Then we limit 2074 * power only for non-AP operation. 2075 */ 2076 if (IEEE80211_IS_CHAN_TURBO(chan) 2077#ifdef AH_ENABLE_AP_SUPPORT 2078 && AH_PRIVATE(ah)->ah_opmode != HAL_M_HOSTAP 2079#endif 2080 ) { 2081 /* 2082 * If turbo is set, reduce power to keep power 2083 * consumption under 2 Watts 2084 */ 2085 if (ee->ee_version >= AR_EEPROM_VER3_1) 2086 scaledPower = AH_MIN(scaledPower, 2087 ee->ee_turbo2WMaxPower5); 2088 /* 2089 * EEPROM version 4.0 added an additional 2090 * constraint on 2.4GHz channels. 2091 */ 2092 if (ee->ee_version >= AR_EEPROM_VER4_0 && 2093 IEEE80211_IS_CHAN_2GHZ(chan)) 2094 scaledPower = AH_MIN(scaledPower, 2095 ee->ee_turbo2WMaxPower2); 2096 } 2097 2098 maxAvailPower = AH_MIN(scaledPower, 2099 targetPowerOfdm.twicePwr6_24); 2100 2101 /* Reduce power by max regulatory domain allowed restrictions */ 2102 scaledPower = maxAvailPower - (tpcScaleReduction * 2); 2103 scaledPower = (scaledPower < 0) ? 0 : scaledPower; 2104 scaledPower = AH_MIN(scaledPower, powerLimit); 2105 2106 if (commit) { 2107 /* Set OFDM rates 9, 12, 18, 24 */ 2108 r0 = rpow[0] = rpow[1] = rpow[2] = rpow[3] = rpow[4] = scaledPower; 2109 2110 /* Set OFDM rates 36, 48, 54, XR */ 2111 rpow[5] = AH_MIN(rpow[0], targetPowerOfdm.twicePwr36); 2112 rpow[6] = AH_MIN(rpow[0], targetPowerOfdm.twicePwr48); 2113 r7 = rpow[7] = AH_MIN(rpow[0], targetPowerOfdm.twicePwr54); 2114 2115 if (ee->ee_version >= AR_EEPROM_VER4_0) { 2116 /* Setup XR target power from EEPROM */ 2117 rpow[15] = AH_MIN(scaledPower, IEEE80211_IS_CHAN_2GHZ(chan) ? 2118 ee->ee_xrTargetPower2 : ee->ee_xrTargetPower5); 2119 } else { 2120 /* XR uses 6mb power */ 2121 rpow[15] = rpow[0]; 2122 } 2123 ahp->ah_ofdmTxPower = *pMaxPower; 2124 2125 } else { 2126 r0 = scaledPower; 2127 r7 = AH_MIN(r0, targetPowerOfdm.twicePwr54); 2128 } 2129 *pMinPower = r7; 2130 *pMaxPower = r0; 2131 2132 HALDEBUG(ah, HAL_DEBUG_RFPARAM, 2133 "%s: MaxRD: %d TurboMax: %d MaxCTL: %d " 2134 "TPC_Reduction %d chan=%d (0x%x) maxAvailPower=%d pwr6_24=%d, maxPower=%d\n", 2135 __func__, twiceMaxRDPower, ee->ee_turbo2WMaxPower5, 2136 twiceMaxEdgePower, tpcScaleReduction * 2, 2137 chan->ic_freq, chan->ic_flags, 2138 maxAvailPower, targetPowerOfdm.twicePwr6_24, *pMaxPower); 2139 } 2140 2141 if (IEEE80211_IS_CHAN_CCK(chan)) { 2142 /* Get final CCK target powers */ 2143 ar5212GetTargetPowers(ah, chan, ee->ee_trgtPwr_11b, 2144 ee->ee_numTargetPwr_11b, &targetPowerCck); 2145 2146 /* Reduce power by max regulatory domain allowed restrictions */ 2147 scaledPower = AH_MIN(twiceMaxEdgePowerCck, 2148 twiceMaxRDPower - twiceAntennaReduction); 2149 if (maxAvailPower < AH_MIN(scaledPower, targetPowerCck.twicePwr6_24)) 2150 maxAvailPower = AH_MIN(scaledPower, targetPowerCck.twicePwr6_24); 2151 2152 /* Reduce power by user selection */ 2153 scaledPower = AH_MIN(scaledPower, targetPowerCck.twicePwr6_24) - (tpcScaleReduction * 2); 2154 scaledPower = (scaledPower < 0) ? 0 : scaledPower; 2155 scaledPower = AH_MIN(scaledPower, powerLimit); 2156 2157 if (commit) { 2158 /* Set CCK rates 2L, 2S, 5.5L, 5.5S, 11L, 11S */ 2159 rpow[8] = AH_MIN(scaledPower, targetPowerCck.twicePwr6_24); 2160 r9 = rpow[9] = AH_MIN(scaledPower, targetPowerCck.twicePwr36); 2161 rpow[10] = rpow[9]; 2162 rpow[11] = AH_MIN(scaledPower, targetPowerCck.twicePwr48); 2163 rpow[12] = rpow[11]; 2164 r13 = rpow[13] = AH_MIN(scaledPower, targetPowerCck.twicePwr54); 2165 rpow[14] = rpow[13]; 2166 } else { 2167 r9 = AH_MIN(scaledPower, targetPowerCck.twicePwr36); 2168 r13 = AH_MIN(scaledPower, targetPowerCck.twicePwr54); 2169 } 2170 2171 /* Set min/max power based off OFDM values or initialization */ 2172 if (r13 < *pMinPower) 2173 *pMinPower = r13; 2174 if (r9 > *pMaxPower) 2175 *pMaxPower = r9; 2176 2177 HALDEBUG(ah, HAL_DEBUG_RFPARAM, 2178 "%s: cck: MaxRD: %d MaxCTL: %d " 2179 "TPC_Reduction %d chan=%d (0x%x) maxAvailPower=%d pwr6_24=%d, maxPower=%d\n", 2180 __func__, twiceMaxRDPower, twiceMaxEdgePowerCck, 2181 tpcScaleReduction * 2, chan->ic_freq, chan->ic_flags, 2182 maxAvailPower, targetPowerCck.twicePwr6_24, *pMaxPower); 2183 } 2184 if (commit) { 2185 ahp->ah_tx6PowerInHalfDbm = *pMaxPower; 2186 AH_PRIVATE(ah)->ah_maxPowerLevel = ahp->ah_tx6PowerInHalfDbm; 2187 } 2188 return AH_TRUE; 2189} 2190 2191HAL_BOOL 2192ar5212GetChipPowerLimits(struct ath_hal *ah, struct ieee80211_channel *chan) 2193{ 2194 struct ath_hal_5212 *ahp = AH5212(ah); 2195#if 0 2196 static const uint16_t tpcScaleReductionTable[5] = 2197 { 0, 3, 6, 9, MAX_RATE_POWER }; 2198 int16_t tpcInDb, powerLimit; 2199#endif 2200 int16_t minPower, maxPower; 2201 2202 /* 2203 * Get Pier table max and min powers. 2204 */ 2205 if (ahp->ah_rfHal->getChannelMaxMinPower(ah, chan, &maxPower, &minPower)) { 2206 /* NB: rf code returns 1/4 dBm units, convert */ 2207 chan->ic_maxpower = maxPower / 2; 2208 chan->ic_minpower = minPower / 2; 2209 } else { 2210 HALDEBUG(ah, HAL_DEBUG_ANY, 2211 "%s: no min/max power for %u/0x%x\n", 2212 __func__, chan->ic_freq, chan->ic_flags); 2213 chan->ic_maxpower = MAX_RATE_POWER; 2214 chan->ic_minpower = 0; 2215 } 2216#if 0 2217 /* 2218 * Now adjust to reflect any global scale and/or CTL's. 2219 * (XXX is that correct?) 2220 */ 2221 powerLimit = AH_MIN(MAX_RATE_POWER, AH_PRIVATE(ah)->ah_powerLimit); 2222 if (powerLimit >= MAX_RATE_POWER || powerLimit == 0) 2223 tpcInDb = tpcScaleReductionTable[AH_PRIVATE(ah)->ah_tpScale]; 2224 else 2225 tpcInDb = 0; 2226 if (!ar5212SetRateTable(ah, chan, tpcInDb, powerLimit, 2227 AH_FALSE, &minPower, &maxPower)) { 2228 HALDEBUG(ah, HAL_DEBUG_ANY, 2229 "%s: unable to find max/min power\n",__func__); 2230 return AH_FALSE; 2231 } 2232 if (maxPower < chan->ic_maxpower) 2233 chan->ic_maxpower = maxPower; 2234 if (minPower < chan->ic_minpower) 2235 chan->ic_minpower = minPower; 2236 HALDEBUG(ah, HAL_DEBUG_RESET, 2237 "Chan %d: MaxPow = %d MinPow = %d\n", 2238 chan->ic_freq, chan->ic_maxpower, chans->ic_minpower); 2239#endif 2240 return AH_TRUE; 2241} 2242 2243/* 2244 * Correct for the gain-delta between ofdm and cck mode target 2245 * powers. Write the results to the rate table and the power table. 2246 * 2247 * Conventions : 2248 * 1. rpow[ii] is the integer value of 2*(desired power 2249 * for the rate ii in dBm) to provide 0.5dB resolution. rate 2250 * mapping is as following : 2251 * [0..7] --> ofdm 6, 9, .. 48, 54 2252 * [8..14] --> cck 1L, 2L, 2S, .. 11L, 11S 2253 * [15] --> XR (all rates get the same power) 2254 * 2. powv[ii] is the pcdac corresponding to ii/2 dBm. 2255 */ 2256static void 2257ar5212CorrectGainDelta(struct ath_hal *ah, int twiceOfdmCckDelta) 2258{ 2259#define N(_a) (sizeof(_a) / sizeof(_a[0])) 2260 struct ath_hal_5212 *ahp = AH5212(ah); 2261 const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom; 2262 int16_t ratesIndex[N(ahp->ah_ratesArray)]; 2263 uint16_t ii, jj, iter; 2264 int32_t cckIndex; 2265 int16_t gainDeltaAdjust; 2266 2267 HALASSERT(ah->ah_magic == AR5212_MAGIC); 2268 2269 gainDeltaAdjust = ee->ee_cckOfdmGainDelta; 2270 2271 /* make a local copy of desired powers as initial indices */ 2272 OS_MEMCPY(ratesIndex, ahp->ah_ratesArray, sizeof(ratesIndex)); 2273 2274 /* fix only the CCK indices */ 2275 for (ii = 8; ii < 15; ii++) { 2276 /* apply a gain_delta correction of -15 for CCK */ 2277 ratesIndex[ii] -= gainDeltaAdjust; 2278 2279 /* Now check for contention with all ofdm target powers */ 2280 jj = 0; 2281 iter = 0; 2282 /* indicates not all ofdm rates checked forcontention yet */ 2283 while (jj < 16) { 2284 if (ratesIndex[ii] < 0) 2285 ratesIndex[ii] = 0; 2286 if (jj == 8) { /* skip CCK rates */ 2287 jj = 15; 2288 continue; 2289 } 2290 if (ratesIndex[ii] == ahp->ah_ratesArray[jj]) { 2291 if (ahp->ah_ratesArray[jj] == 0) 2292 ratesIndex[ii]++; 2293 else if (iter > 50) { 2294 /* 2295 * To avoid pathological case of of 2296 * dm target powers 0 and 0.5dBm 2297 */ 2298 ratesIndex[ii]++; 2299 } else 2300 ratesIndex[ii]--; 2301 /* check with all rates again */ 2302 jj = 0; 2303 iter++; 2304 } else 2305 jj++; 2306 } 2307 if (ratesIndex[ii] >= PWR_TABLE_SIZE) 2308 ratesIndex[ii] = PWR_TABLE_SIZE -1; 2309 cckIndex = ahp->ah_ratesArray[ii] - twiceOfdmCckDelta; 2310 if (cckIndex < 0) 2311 cckIndex = 0; 2312 2313 /* 2314 * Validate that the indexes for the powv are not 2315 * out of bounds. 2316 */ 2317 HALASSERT(cckIndex < PWR_TABLE_SIZE); 2318 HALASSERT(ratesIndex[ii] < PWR_TABLE_SIZE); 2319 ahp->ah_pcdacTable[ratesIndex[ii]] = 2320 ahp->ah_pcdacTable[cckIndex]; 2321 } 2322 /* Override rate per power table with new values */ 2323 for (ii = 8; ii < 15; ii++) 2324 ahp->ah_ratesArray[ii] = ratesIndex[ii]; 2325#undef N 2326} 2327 2328/* 2329 * Find the maximum conformance test limit for the given channel and CTL info 2330 */ 2331static uint16_t 2332ar5212GetMaxEdgePower(uint16_t channel, const RD_EDGES_POWER *pRdEdgesPower) 2333{ 2334 /* temp array for holding edge channels */ 2335 uint16_t tempChannelList[NUM_EDGES]; 2336 uint16_t clo, chi, twiceMaxEdgePower; 2337 int i, numEdges; 2338 2339 /* Get the edge power */ 2340 for (i = 0; i < NUM_EDGES; i++) { 2341 if (pRdEdgesPower[i].rdEdge == 0) 2342 break; 2343 tempChannelList[i] = pRdEdgesPower[i].rdEdge; 2344 } 2345 numEdges = i; 2346 2347 ar5212GetLowerUpperValues(channel, tempChannelList, 2348 numEdges, &clo, &chi); 2349 /* Get the index for the lower channel */ 2350 for (i = 0; i < numEdges && clo != tempChannelList[i]; i++) 2351 ; 2352 /* Is lower channel ever outside the rdEdge? */ 2353 HALASSERT(i != numEdges); 2354 2355 if ((clo == chi && clo == channel) || (pRdEdgesPower[i].flag)) { 2356 /* 2357 * If there's an exact channel match or an inband flag set 2358 * on the lower channel use the given rdEdgePower 2359 */ 2360 twiceMaxEdgePower = pRdEdgesPower[i].twice_rdEdgePower; 2361 HALASSERT(twiceMaxEdgePower > 0); 2362 } else 2363 twiceMaxEdgePower = MAX_RATE_POWER; 2364 return twiceMaxEdgePower; 2365} 2366 2367/* 2368 * Returns interpolated or the scaled up interpolated value 2369 */ 2370static uint16_t 2371interpolate(uint16_t target, uint16_t srcLeft, uint16_t srcRight, 2372 uint16_t targetLeft, uint16_t targetRight) 2373{ 2374 uint16_t rv; 2375 int16_t lRatio; 2376 2377 /* to get an accurate ratio, always scale, if want to scale, then don't scale back down */ 2378 if ((targetLeft * targetRight) == 0) 2379 return 0; 2380 2381 if (srcRight != srcLeft) { 2382 /* 2383 * Note the ratio always need to be scaled, 2384 * since it will be a fraction. 2385 */ 2386 lRatio = (target - srcLeft) * EEP_SCALE / (srcRight - srcLeft); 2387 if (lRatio < 0) { 2388 /* Return as Left target if value would be negative */ 2389 rv = targetLeft; 2390 } else if (lRatio > EEP_SCALE) { 2391 /* Return as Right target if Ratio is greater than 100% (SCALE) */ 2392 rv = targetRight; 2393 } else { 2394 rv = (lRatio * targetRight + (EEP_SCALE - lRatio) * 2395 targetLeft) / EEP_SCALE; 2396 } 2397 } else { 2398 rv = targetLeft; 2399 } 2400 return rv; 2401} 2402 2403/* 2404 * Return the four rates of target power for the given target power table 2405 * channel, and number of channels 2406 */ 2407static void 2408ar5212GetTargetPowers(struct ath_hal *ah, const struct ieee80211_channel *chan, 2409 const TRGT_POWER_INFO *powInfo, 2410 uint16_t numChannels, TRGT_POWER_INFO *pNewPower) 2411{ 2412 uint16_t freq = ath_hal_gethwchannel(ah, chan); 2413 /* temp array for holding target power channels */ 2414 uint16_t tempChannelList[NUM_TEST_FREQUENCIES]; 2415 uint16_t clo, chi, ixlo, ixhi; 2416 int i; 2417 2418 /* Copy the target powers into the temp channel list */ 2419 for (i = 0; i < numChannels; i++) 2420 tempChannelList[i] = powInfo[i].testChannel; 2421 2422 ar5212GetLowerUpperValues(freq, tempChannelList, 2423 numChannels, &clo, &chi); 2424 2425 /* Get the indices for the channel */ 2426 ixlo = ixhi = 0; 2427 for (i = 0; i < numChannels; i++) { 2428 if (clo == tempChannelList[i]) { 2429 ixlo = i; 2430 } 2431 if (chi == tempChannelList[i]) { 2432 ixhi = i; 2433 break; 2434 } 2435 } 2436 2437 /* 2438 * Get the lower and upper channels, target powers, 2439 * and interpolate between them. 2440 */ 2441 pNewPower->twicePwr6_24 = interpolate(freq, clo, chi, 2442 powInfo[ixlo].twicePwr6_24, powInfo[ixhi].twicePwr6_24); 2443 pNewPower->twicePwr36 = interpolate(freq, clo, chi, 2444 powInfo[ixlo].twicePwr36, powInfo[ixhi].twicePwr36); 2445 pNewPower->twicePwr48 = interpolate(freq, clo, chi, 2446 powInfo[ixlo].twicePwr48, powInfo[ixhi].twicePwr48); 2447 pNewPower->twicePwr54 = interpolate(freq, clo, chi, 2448 powInfo[ixlo].twicePwr54, powInfo[ixhi].twicePwr54); 2449} 2450 2451/* 2452 * Search a list for a specified value v that is within 2453 * EEP_DELTA of the search values. Return the closest 2454 * values in the list above and below the desired value. 2455 * EEP_DELTA is a factional value; everything is scaled 2456 * so only integer arithmetic is used. 2457 * 2458 * NB: the input list is assumed to be sorted in ascending order 2459 */ 2460void 2461ar5212GetLowerUpperValues(uint16_t v, uint16_t *lp, uint16_t listSize, 2462 uint16_t *vlo, uint16_t *vhi) 2463{ 2464 uint32_t target = v * EEP_SCALE; 2465 uint16_t *ep = lp+listSize; 2466 2467 /* 2468 * Check first and last elements for out-of-bounds conditions. 2469 */ 2470 if (target < (uint32_t)(lp[0] * EEP_SCALE - EEP_DELTA)) { 2471 *vlo = *vhi = lp[0]; 2472 return; 2473 } 2474 if (target > (uint32_t)(ep[-1] * EEP_SCALE + EEP_DELTA)) { 2475 *vlo = *vhi = ep[-1]; 2476 return; 2477 } 2478 2479 /* look for value being near or between 2 values in list */ 2480 for (; lp < ep; lp++) { 2481 /* 2482 * If value is close to the current value of the list 2483 * then target is not between values, it is one of the values 2484 */ 2485 if (abs(lp[0] * EEP_SCALE - target) < EEP_DELTA) { 2486 *vlo = *vhi = lp[0]; 2487 return; 2488 } 2489 /* 2490 * Look for value being between current value and next value 2491 * if so return these 2 values 2492 */ 2493 if (target < (uint32_t)(lp[1] * EEP_SCALE - EEP_DELTA)) { 2494 *vlo = lp[0]; 2495 *vhi = lp[1]; 2496 return; 2497 } 2498 } 2499 HALASSERT(AH_FALSE); /* should not reach here */ 2500} 2501 2502/* 2503 * Perform analog "swizzling" of parameters into their location 2504 * 2505 * NB: used by RF backends 2506 */ 2507void 2508ar5212ModifyRfBuffer(uint32_t *rfBuf, uint32_t reg32, uint32_t numBits, 2509 uint32_t firstBit, uint32_t column) 2510{ 2511#define MAX_ANALOG_START 319 /* XXX */ 2512 uint32_t tmp32, mask, arrayEntry, lastBit; 2513 int32_t bitPosition, bitsLeft; 2514 2515 HALASSERT(column <= 3); 2516 HALASSERT(numBits <= 32); 2517 HALASSERT(firstBit + numBits <= MAX_ANALOG_START); 2518 2519 tmp32 = ath_hal_reverseBits(reg32, numBits); 2520 arrayEntry = (firstBit - 1) / 8; 2521 bitPosition = (firstBit - 1) % 8; 2522 bitsLeft = numBits; 2523 while (bitsLeft > 0) { 2524 lastBit = (bitPosition + bitsLeft > 8) ? 2525 8 : bitPosition + bitsLeft; 2526 mask = (((1 << lastBit) - 1) ^ ((1 << bitPosition) - 1)) << 2527 (column * 8); 2528 rfBuf[arrayEntry] &= ~mask; 2529 rfBuf[arrayEntry] |= ((tmp32 << bitPosition) << 2530 (column * 8)) & mask; 2531 bitsLeft -= 8 - bitPosition; 2532 tmp32 = tmp32 >> (8 - bitPosition); 2533 bitPosition = 0; 2534 arrayEntry++; 2535 } 2536#undef MAX_ANALOG_START 2537} 2538 2539/* 2540 * Sets the rate to duration values in MAC - used for multi- 2541 * rate retry. 2542 * The rate duration table needs to cover all valid rate codes; 2543 * the 11g table covers all ofdm rates, while the 11b table 2544 * covers all cck rates => all valid rates get covered between 2545 * these two mode's ratetables! 2546 * But if we're turbo, the ofdm phy is replaced by the turbo phy 2547 * and cck is not valid with turbo => all rates get covered 2548 * by the turbo ratetable only 2549 */ 2550void 2551ar5212SetRateDurationTable(struct ath_hal *ah, 2552 const struct ieee80211_channel *chan) 2553{ 2554 const HAL_RATE_TABLE *rt; 2555 int i; 2556 2557 /* NB: band doesn't matter for 1/2 and 1/4 rate */ 2558 if (IEEE80211_IS_CHAN_HALF(chan)) { 2559 rt = ar5212GetRateTable(ah, HAL_MODE_11A_HALF_RATE); 2560 } else if (IEEE80211_IS_CHAN_QUARTER(chan)) { 2561 rt = ar5212GetRateTable(ah, HAL_MODE_11A_QUARTER_RATE); 2562 } else { 2563 rt = ar5212GetRateTable(ah, 2564 IEEE80211_IS_CHAN_TURBO(chan) ? HAL_MODE_TURBO : HAL_MODE_11G); 2565 } 2566 2567 for (i = 0; i < rt->rateCount; ++i) 2568 OS_REG_WRITE(ah, 2569 AR_RATE_DURATION(rt->info[i].rateCode), 2570 ath_hal_computetxtime(ah, rt, 2571 WLAN_CTRL_FRAME_SIZE, 2572 rt->info[i].controlRate, AH_FALSE)); 2573 if (!IEEE80211_IS_CHAN_TURBO(chan)) { 2574 /* 11g Table is used to cover the CCK rates. */ 2575 rt = ar5212GetRateTable(ah, HAL_MODE_11G); 2576 for (i = 0; i < rt->rateCount; ++i) { 2577 uint32_t reg = AR_RATE_DURATION(rt->info[i].rateCode); 2578 2579 if (rt->info[i].phy != IEEE80211_T_CCK) 2580 continue; 2581 2582 OS_REG_WRITE(ah, reg, 2583 ath_hal_computetxtime(ah, rt, 2584 WLAN_CTRL_FRAME_SIZE, 2585 rt->info[i].controlRate, AH_FALSE)); 2586 /* cck rates have short preamble option also */ 2587 if (rt->info[i].shortPreamble) { 2588 reg += rt->info[i].shortPreamble << 2; 2589 OS_REG_WRITE(ah, reg, 2590 ath_hal_computetxtime(ah, rt, 2591 WLAN_CTRL_FRAME_SIZE, 2592 rt->info[i].controlRate, 2593 AH_TRUE)); 2594 } 2595 } 2596 } 2597} 2598 2599/* Adjust various register settings based on half/quarter rate clock setting. 2600 * This includes: +USEC, TX/RX latency, 2601 * + IFS params: slot, eifs, misc etc. 2602 */ 2603void 2604ar5212SetIFSTiming(struct ath_hal *ah, const struct ieee80211_channel *chan) 2605{ 2606 uint32_t txLat, rxLat, usec, slot, refClock, eifs, init_usec; 2607 2608 HALASSERT(IEEE80211_IS_CHAN_HALF(chan) || 2609 IEEE80211_IS_CHAN_QUARTER(chan)); 2610 2611 refClock = OS_REG_READ(ah, AR_USEC) & AR_USEC_USEC32; 2612 if (IEEE80211_IS_CHAN_HALF(chan)) { 2613 slot = IFS_SLOT_HALF_RATE; 2614 rxLat = RX_NON_FULL_RATE_LATENCY << AR5212_USEC_RX_LAT_S; 2615 txLat = TX_HALF_RATE_LATENCY << AR5212_USEC_TX_LAT_S; 2616 usec = HALF_RATE_USEC; 2617 eifs = IFS_EIFS_HALF_RATE; 2618 init_usec = INIT_USEC >> 1; 2619 } else { /* quarter rate */ 2620 slot = IFS_SLOT_QUARTER_RATE; 2621 rxLat = RX_NON_FULL_RATE_LATENCY << AR5212_USEC_RX_LAT_S; 2622 txLat = TX_QUARTER_RATE_LATENCY << AR5212_USEC_TX_LAT_S; 2623 usec = QUARTER_RATE_USEC; 2624 eifs = IFS_EIFS_QUARTER_RATE; 2625 init_usec = INIT_USEC >> 2; 2626 } 2627 2628 OS_REG_WRITE(ah, AR_USEC, (usec | refClock | txLat | rxLat)); 2629 OS_REG_WRITE(ah, AR_D_GBL_IFS_SLOT, slot); 2630 OS_REG_WRITE(ah, AR_D_GBL_IFS_EIFS, eifs); 2631 OS_REG_RMW_FIELD(ah, AR_D_GBL_IFS_MISC, 2632 AR_D_GBL_IFS_MISC_USEC_DURATION, init_usec); 2633} 2634