ar5212_recv.c revision 185377
1/* 2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $Id: ar5212_recv.c,v 1.4 2008/11/10 04:08:03 sam Exp $ 18 */ 19#include "opt_ah.h" 20 21#ifdef AH_SUPPORT_AR5212 22 23#include "ah.h" 24#include "ah_internal.h" 25 26#include "ar5212/ar5212.h" 27#include "ar5212/ar5212reg.h" 28#include "ar5212/ar5212desc.h" 29 30/* 31 * Get the RXDP. 32 */ 33uint32_t 34ar5212GetRxDP(struct ath_hal *ath) 35{ 36 return OS_REG_READ(ath, AR_RXDP); 37} 38 39/* 40 * Set the RxDP. 41 */ 42void 43ar5212SetRxDP(struct ath_hal *ah, uint32_t rxdp) 44{ 45 OS_REG_WRITE(ah, AR_RXDP, rxdp); 46 HALASSERT(OS_REG_READ(ah, AR_RXDP) == rxdp); 47} 48 49/* 50 * Set Receive Enable bits. 51 */ 52void 53ar5212EnableReceive(struct ath_hal *ah) 54{ 55 OS_REG_WRITE(ah, AR_CR, AR_CR_RXE); 56} 57 58/* 59 * Stop Receive at the DMA engine 60 */ 61HAL_BOOL 62ar5212StopDmaReceive(struct ath_hal *ah) 63{ 64 OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* Set receive disable bit */ 65 if (!ath_hal_wait(ah, AR_CR, AR_CR_RXE, 0)) { 66#ifdef AH_DEBUG 67 ath_hal_printf(ah, "%s: dma failed to stop in 10ms\n" 68 "AR_CR=0x%08x\nAR_DIAG_SW=0x%08x\n", 69 __func__, 70 OS_REG_READ(ah, AR_CR), 71 OS_REG_READ(ah, AR_DIAG_SW)); 72#endif 73 return AH_FALSE; 74 } else { 75 return AH_TRUE; 76 } 77} 78 79/* 80 * Start Transmit at the PCU engine (unpause receive) 81 */ 82void 83ar5212StartPcuReceive(struct ath_hal *ah) 84{ 85 struct ath_hal_private *ahp = AH_PRIVATE(ah); 86 87 OS_REG_WRITE(ah, AR_DIAG_SW, 88 OS_REG_READ(ah, AR_DIAG_SW) &~ AR_DIAG_RX_DIS); 89 ar5212EnableMibCounters(ah); 90 /* NB: restore current settings */ 91 ar5212AniReset(ah, ahp->ah_curchan, ahp->ah_opmode, AH_TRUE); 92} 93 94/* 95 * Stop Transmit at the PCU engine (pause receive) 96 */ 97void 98ar5212StopPcuReceive(struct ath_hal *ah) 99{ 100 OS_REG_WRITE(ah, AR_DIAG_SW, 101 OS_REG_READ(ah, AR_DIAG_SW) | AR_DIAG_RX_DIS); 102 ar5212DisableMibCounters(ah); 103} 104 105/* 106 * Set multicast filter 0 (lower 32-bits) 107 * filter 1 (upper 32-bits) 108 */ 109void 110ar5212SetMulticastFilter(struct ath_hal *ah, uint32_t filter0, uint32_t filter1) 111{ 112 OS_REG_WRITE(ah, AR_MCAST_FIL0, filter0); 113 OS_REG_WRITE(ah, AR_MCAST_FIL1, filter1); 114} 115 116/* 117 * Clear multicast filter by index 118 */ 119HAL_BOOL 120ar5212ClrMulticastFilterIndex(struct ath_hal *ah, uint32_t ix) 121{ 122 uint32_t val; 123 124 if (ix >= 64) 125 return AH_FALSE; 126 if (ix >= 32) { 127 val = OS_REG_READ(ah, AR_MCAST_FIL1); 128 OS_REG_WRITE(ah, AR_MCAST_FIL1, (val &~ (1<<(ix-32)))); 129 } else { 130 val = OS_REG_READ(ah, AR_MCAST_FIL0); 131 OS_REG_WRITE(ah, AR_MCAST_FIL0, (val &~ (1<<ix))); 132 } 133 return AH_TRUE; 134} 135 136/* 137 * Set multicast filter by index 138 */ 139HAL_BOOL 140ar5212SetMulticastFilterIndex(struct ath_hal *ah, uint32_t ix) 141{ 142 uint32_t val; 143 144 if (ix >= 64) 145 return AH_FALSE; 146 if (ix >= 32) { 147 val = OS_REG_READ(ah, AR_MCAST_FIL1); 148 OS_REG_WRITE(ah, AR_MCAST_FIL1, (val | (1<<(ix-32)))); 149 } else { 150 val = OS_REG_READ(ah, AR_MCAST_FIL0); 151 OS_REG_WRITE(ah, AR_MCAST_FIL0, (val | (1<<ix))); 152 } 153 return AH_TRUE; 154} 155 156/* 157 * Get the receive filter. 158 */ 159uint32_t 160ar5212GetRxFilter(struct ath_hal *ah) 161{ 162 uint32_t bits = OS_REG_READ(ah, AR_RX_FILTER); 163 uint32_t phybits = OS_REG_READ(ah, AR_PHY_ERR); 164 if (phybits & AR_PHY_ERR_RADAR) 165 bits |= HAL_RX_FILTER_PHYRADAR; 166 if (phybits & (AR_PHY_ERR_OFDM_TIMING|AR_PHY_ERR_CCK_TIMING)) 167 bits |= HAL_RX_FILTER_PHYERR; 168 return bits; 169} 170 171/* 172 * Set the receive filter. 173 */ 174void 175ar5212SetRxFilter(struct ath_hal *ah, uint32_t bits) 176{ 177 uint32_t phybits; 178 179 OS_REG_WRITE(ah, AR_RX_FILTER, 180 bits &~ (HAL_RX_FILTER_PHYRADAR|HAL_RX_FILTER_PHYERR)); 181 phybits = 0; 182 if (bits & HAL_RX_FILTER_PHYRADAR) 183 phybits |= AR_PHY_ERR_RADAR; 184 if (bits & HAL_RX_FILTER_PHYERR) 185 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING; 186 OS_REG_WRITE(ah, AR_PHY_ERR, phybits); 187 if (phybits) { 188 OS_REG_WRITE(ah, AR_RXCFG, 189 OS_REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA); 190 } else { 191 OS_REG_WRITE(ah, AR_RXCFG, 192 OS_REG_READ(ah, AR_RXCFG) &~ AR_RXCFG_ZLFDMA); 193 } 194} 195 196/* 197 * Initialize RX descriptor, by clearing the status and setting 198 * the size (and any other flags). 199 */ 200HAL_BOOL 201ar5212SetupRxDesc(struct ath_hal *ah, struct ath_desc *ds, 202 uint32_t size, u_int flags) 203{ 204 struct ar5212_desc *ads = AR5212DESC(ds); 205 206 HALASSERT((size &~ AR_BufLen) == 0); 207 208 ads->ds_ctl0 = 0; 209 ads->ds_ctl1 = size & AR_BufLen; 210 211 if (flags & HAL_RXDESC_INTREQ) 212 ads->ds_ctl1 |= AR_RxInterReq; 213 ads->ds_rxstatus0 = ads->ds_rxstatus1 = 0; 214 215 return AH_TRUE; 216} 217 218/* 219 * Process an RX descriptor, and return the status to the caller. 220 * Copy some hardware specific items into the software portion 221 * of the descriptor. 222 * 223 * NB: the caller is responsible for validating the memory contents 224 * of the descriptor (e.g. flushing any cached copy). 225 */ 226HAL_STATUS 227ar5212ProcRxDesc(struct ath_hal *ah, struct ath_desc *ds, 228 uint32_t pa, struct ath_desc *nds, uint64_t tsf, 229 struct ath_rx_status *rs) 230{ 231 struct ar5212_desc *ads = AR5212DESC(ds); 232 struct ar5212_desc *ands = AR5212DESC(nds); 233 234 if ((ads->ds_rxstatus1 & AR_Done) == 0) 235 return HAL_EINPROGRESS; 236 /* 237 * Given the use of a self-linked tail be very sure that the hw is 238 * done with this descriptor; the hw may have done this descriptor 239 * once and picked it up again...make sure the hw has moved on. 240 */ 241 if ((ands->ds_rxstatus1&AR_Done) == 0 && OS_REG_READ(ah, AR_RXDP) == pa) 242 return HAL_EINPROGRESS; 243 244 rs->rs_datalen = ads->ds_rxstatus0 & AR_DataLen; 245 rs->rs_tstamp = MS(ads->ds_rxstatus1, AR_RcvTimestamp); 246 rs->rs_status = 0; 247 /* XXX what about KeyCacheMiss? */ 248 rs->rs_rssi = MS(ads->ds_rxstatus0, AR_RcvSigStrength); 249 /* discard invalid h/w rssi data */ 250 if (rs->rs_rssi == -128) 251 rs->rs_rssi = 0; 252 if (ads->ds_rxstatus1 & AR_KeyIdxValid) 253 rs->rs_keyix = MS(ads->ds_rxstatus1, AR_KeyIdx); 254 else 255 rs->rs_keyix = HAL_RXKEYIX_INVALID; 256 /* NB: caller expected to do rate table mapping */ 257 rs->rs_rate = MS(ads->ds_rxstatus0, AR_RcvRate); 258 rs->rs_antenna = MS(ads->ds_rxstatus0, AR_RcvAntenna); 259 rs->rs_more = (ads->ds_rxstatus0 & AR_More) ? 1 : 0; 260 261 if ((ads->ds_rxstatus1 & AR_FrmRcvOK) == 0) { 262 /* 263 * These four bits should not be set together. The 264 * 5212 spec states a Michael error can only occur if 265 * DecryptCRCErr not set (and TKIP is used). Experience 266 * indicates however that you can also get Michael errors 267 * when a CRC error is detected, but these are specious. 268 * Consequently we filter them out here so we don't 269 * confuse and/or complicate drivers. 270 */ 271 if (ads->ds_rxstatus1 & AR_CRCErr) 272 rs->rs_status |= HAL_RXERR_CRC; 273 else if (ads->ds_rxstatus1 & AR_PHYErr) { 274 u_int phyerr; 275 276 rs->rs_status |= HAL_RXERR_PHY; 277 phyerr = MS(ads->ds_rxstatus1, AR_PHYErrCode); 278 rs->rs_phyerr = phyerr; 279 if (!AH5212(ah)->ah_hasHwPhyCounters && 280 phyerr != HAL_PHYERR_RADAR) 281 ar5212AniPhyErrReport(ah, rs); 282 } else if (ads->ds_rxstatus1 & AR_DecryptCRCErr) 283 rs->rs_status |= HAL_RXERR_DECRYPT; 284 else if (ads->ds_rxstatus1 & AR_MichaelErr) 285 rs->rs_status |= HAL_RXERR_MIC; 286 } 287 return HAL_OK; 288} 289#endif /* AH_SUPPORT_AR5212 */ 290