1185377Ssam/* 2185377Ssam * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3185377Ssam * Copyright (c) 2002-2006 Atheros Communications, Inc. 4185377Ssam * 5185377Ssam * Permission to use, copy, modify, and/or distribute this software for any 6185377Ssam * purpose with or without fee is hereby granted, provided that the above 7185377Ssam * copyright notice and this permission notice appear in all copies. 8185377Ssam * 9185377Ssam * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10185377Ssam * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11185377Ssam * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12185377Ssam * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13185377Ssam * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14185377Ssam * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15185377Ssam * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16185377Ssam * 17204644Srpaulo * $FreeBSD$ 18185377Ssam */ 19185377Ssam#ifndef _DEV_ATH_AR5211DESC_H 20185377Ssam#define _DEV_ATH_AR5211DESC_H 21185377Ssam 22185377Ssam/* 23185377Ssam * Defintions for the DMA descriptors used by the Atheros 24185377Ssam * AR5211 and AR5110 Wireless Lan controller parts. 25185377Ssam */ 26185377Ssam 27185377Ssam/* DMA descriptors */ 28185377Ssamstruct ar5211_desc { 29185377Ssam uint32_t ds_link; /* link pointer */ 30185377Ssam uint32_t ds_data; /* data buffer pointer */ 31185377Ssam uint32_t ds_ctl0; /* DMA control 0 */ 32185377Ssam uint32_t ds_ctl1; /* DMA control 1 */ 33185377Ssam uint32_t ds_status0; /* DMA status 0 */ 34185377Ssam uint32_t ds_status1; /* DMA status 1 */ 35185377Ssam} __packed; 36185377Ssam#define AR5211DESC(_ds) ((struct ar5211_desc *)(_ds)) 37185377Ssam#define AR5211DESC_CONST(_ds) ((const struct ar5211_desc *)(_ds)) 38185377Ssam 39185377Ssam/* TX ds_ctl0 */ 40185377Ssam#define AR_FrameLen 0x00000fff /* frame length */ 41185377Ssam/* bits 12-17 are reserved */ 42185377Ssam#define AR_XmitRate 0x003c0000 /* txrate */ 43185377Ssam#define AR_XmitRate_S 18 44185377Ssam#define AR_RTSCTSEnable 0x00400000 /* RTS/CTS enable */ 45185377Ssam#define AR_VEOL 0x00800000 /* virtual end-of-list */ 46185377Ssam#define AR_ClearDestMask 0x01000000 /* Clear destination mask bit */ 47185377Ssam#define AR_AntModeXmit 0x1e000000 /* TX antenna seslection */ 48185377Ssam#define AR_AntModeXmit_S 25 49185377Ssam#define AR_TxInterReq 0x20000000 /* TX interrupt request */ 50185377Ssam#define AR_EncryptKeyValid 0x40000000 /* EncryptKeyIdx is valid */ 51185377Ssam/* bit 31 is reserved */ 52185377Ssam 53185377Ssam/* TX ds_ctl1 */ 54185377Ssam#define AR_BufLen 0x00000fff /* data buffer length */ 55185377Ssam#define AR_More 0x00001000 /* more desc in this frame */ 56185377Ssam#define AR_EncryptKeyIdx 0x000fe000 /* ecnrypt key table index */ 57185377Ssam#define AR_EncryptKeyIdx_S 13 58185377Ssam#define AR_FrmType 0x00700000 /* frame type indication */ 59185377Ssam#define AR_FrmType_S 20 60185377Ssam#define AR_Frm_Normal 0x00000000 /* normal frame */ 61185377Ssam#define AR_Frm_ATIM 0x00100000 /* ATIM frame */ 62185377Ssam#define AR_Frm_PSPOLL 0x00200000 /* PS poll frame */ 63185377Ssam#define AR_Frm_Beacon 0x00300000 /* Beacon frame */ 64185377Ssam#define AR_Frm_ProbeResp 0x00400000 /* no delay data */ 65185377Ssam#define AR_NoAck 0x00800000 /* No ACK flag */ 66185377Ssam/* bits 24-31 are reserved */ 67185377Ssam 68185377Ssam/* RX ds_ctl1 */ 69185377Ssam/* AR_BufLen 0x00000fff data buffer length */ 70185377Ssam/* bit 12 is reserved */ 71185377Ssam#define AR_RxInterReq 0x00002000 /* RX interrupt request */ 72185377Ssam/* bits 14-31 are reserved */ 73185377Ssam 74185377Ssam/* TX ds_status0 */ 75185377Ssam#define AR_FrmXmitOK 0x00000001 /* TX success */ 76185377Ssam#define AR_ExcessiveRetries 0x00000002 /* excessive retries */ 77185377Ssam#define AR_FIFOUnderrun 0x00000004 /* TX FIFO underrun */ 78185377Ssam#define AR_Filtered 0x00000008 /* TX filter indication */ 79185377Ssam/* NB: the spec has the Short+Long retry counts reversed */ 80185377Ssam#define AR_LongRetryCnt 0x000000f0 /* long retry count */ 81185377Ssam#define AR_LongRetryCnt_S 4 82185377Ssam#define AR_ShortRetryCnt 0x00000f00 /* short retry count */ 83185377Ssam#define AR_ShortRetryCnt_S 8 84185377Ssam#define AR_VirtCollCnt 0x0000f000 /* virtual collision count */ 85185377Ssam#define AR_VirtCollCnt_S 12 86185377Ssam#define AR_SendTimestamp 0xffff0000 /* TX timestamp */ 87185377Ssam#define AR_SendTimestamp_S 16 88185377Ssam 89185377Ssam/* RX ds_status0 */ 90185377Ssam#define AR_DataLen 0x00000fff /* RX data length */ 91185377Ssam/* AR_More 0x00001000 more desc in this frame */ 92185377Ssam/* bits 13-14 are reserved */ 93185377Ssam#define AR_RcvRate 0x00078000 /* reception rate */ 94185377Ssam#define AR_RcvRate_S 15 95185377Ssam#define AR_RcvSigStrength 0x07f80000 /* receive signal strength */ 96185377Ssam#define AR_RcvSigStrength_S 19 97185377Ssam#define AR_RcvAntenna 0x38000000 /* receive antenaa */ 98185377Ssam#define AR_RcvAntenna_S 27 99185377Ssam/* bits 30-31 are reserved */ 100185377Ssam 101185377Ssam/* TX ds_status1 */ 102185377Ssam#define AR_Done 0x00000001 /* descripter complete */ 103185377Ssam#define AR_SeqNum 0x00001ffe /* TX sequence number */ 104185377Ssam#define AR_SeqNum_S 1 105185377Ssam#define AR_AckSigStrength 0x001fe000 /* strength of ACK */ 106185377Ssam#define AR_AckSigStrength_S 13 107185377Ssam/* bits 21-31 are reserved */ 108185377Ssam 109185377Ssam/* RX ds_status1 */ 110185377Ssam/* AR_Done 0x00000001 descripter complete */ 111185377Ssam#define AR_FrmRcvOK 0x00000002 /* frame reception success */ 112185377Ssam#define AR_CRCErr 0x00000004 /* CRC error */ 113185377Ssam/* bit 3 reserved */ 114185377Ssam#define AR_DecryptCRCErr 0x00000010 /* Decryption CRC fiailure */ 115185377Ssam#define AR_PHYErr 0x000000e0 /* PHY error */ 116185377Ssam#define AR_PHYErr_S 5 117185377Ssam#define AR_PHYErr_Underrun 0x00000000 /* Transmit underrun */ 118185377Ssam#define AR_PHYErr_Tim 0x00000020 /* Timing error */ 119185377Ssam#define AR_PHYErr_Par 0x00000040 /* Parity error */ 120185377Ssam#define AR_PHYErr_Rate 0x00000060 /* Illegal rate */ 121185377Ssam#define AR_PHYErr_Len 0x00000080 /* Illegal length */ 122185377Ssam#define AR_PHYErr_Radar 0x000000a0 /* Radar detect */ 123185377Ssam#define AR_PHYErr_Srv 0x000000c0 /* Illegal service */ 124185377Ssam#define AR_PHYErr_TOR 0x000000e0 /* Transmit override receive */ 125185377Ssam#define AR_KeyIdxValid 0x00000100 /* decryption key index valid */ 126185377Ssam#define AR_KeyIdx 0x00007e00 /* Decryption key index */ 127185377Ssam#define AR_KeyIdx_S 9 128185377Ssam#define AR_RcvTimestamp 0x0fff8000 /* timestamp */ 129185377Ssam#define AR_RcvTimestamp_S 15 130185377Ssam#define AR_KeyCacheMiss 0x10000000 /* key cache miss indication */ 131185377Ssam 132185377Ssam#endif /* _DEV_ATH_AR5211DESC_H_ */ 133