ar5210desc.h revision 185377
1185377Ssam/* 2185377Ssam * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3185377Ssam * Copyright (c) 2002-2004 Atheros Communications, Inc. 4185377Ssam * 5185377Ssam * Permission to use, copy, modify, and/or distribute this software for any 6185377Ssam * purpose with or without fee is hereby granted, provided that the above 7185377Ssam * copyright notice and this permission notice appear in all copies. 8185377Ssam * 9185377Ssam * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10185377Ssam * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11185377Ssam * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12185377Ssam * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13185377Ssam * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14185377Ssam * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15185377Ssam * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16185377Ssam * 17185377Ssam * $Id: ar5210desc.h,v 1.5 2008/11/10 04:08:02 sam Exp $ 18185377Ssam */ 19185377Ssam#ifndef _DEV_ATH_AR5210DESC_H 20185377Ssam#define _DEV_ATH_AR5210DESC_H 21185377Ssam 22185377Ssam#include "ah_desc.h" 23185377Ssam 24185377Ssam/* 25185377Ssam * Defintions for the DMA descriptors used by the Atheros 26185377Ssam * AR5210/AR5211 and AR5110 Wireless Lan controller parts. 27185377Ssam */ 28185377Ssam 29185377Ssam/* DMA descriptors */ 30185377Ssamstruct ar5210_desc { 31185377Ssam uint32_t ds_link; /* link pointer */ 32185377Ssam uint32_t ds_data; /* data buffer pointer */ 33185377Ssam uint32_t ds_ctl0; /* DMA control 0 */ 34185377Ssam uint32_t ds_ctl1; /* DMA control 1 */ 35185377Ssam uint32_t ds_status0; /* DMA status 0 */ 36185377Ssam uint32_t ds_status1; /* DMA status 1 */ 37185377Ssam} __packed; 38185377Ssam#define AR5210DESC(_ds) ((struct ar5210_desc *)(_ds)) 39185377Ssam#define AR5210DESC_CONST(_ds) ((const struct ar5210_desc *)(_ds)) 40185377Ssam 41185377Ssam/* TX ds_ctl0 */ 42185377Ssam#define AR_FrameLen 0x00000fff /* frame length */ 43185377Ssam#define AR_HdrLen 0x0003f000 /* header length */ 44185377Ssam#define AR_HdrLen_S 12 45185377Ssam#define AR_XmitRate 0x003c0000 /* txrate */ 46185377Ssam#define AR_XmitRate_S 18 47185377Ssam#define AR_Rate_6M 0xb 48185377Ssam#define AR_Rate_9M 0xf 49185377Ssam#define AR_Rate_12M 0xa 50185377Ssam#define AR_Rate_18M 0xe 51185377Ssam#define AR_Rate_24M 0x9 52185377Ssam#define AR_Rate_36M 0xd 53185377Ssam#define AR_Rate_48M 0x8 54185377Ssam#define AR_Rate_54M 0xc 55185377Ssam#define AR_RTSCTSEnable 0x00400000 /* RTS/CTS enable */ 56185377Ssam#define AR_LongPkt 0x00800000 /* long packet indication */ 57185377Ssam#define AR_ClearDestMask 0x01000000 /* Clear destination mask bit */ 58185377Ssam#define AR_AntModeXmit 0x02000000 /* TX antenna seslection */ 59185377Ssam#define AR_FrmType 0x1c000000 /* frame type indication */ 60185377Ssam#define AR_Frm_Normal 0x00000000 /* normal frame */ 61185377Ssam#define AR_Frm_ATIM 0x04000000 /* ATIM frame */ 62185377Ssam#define AR_Frm_PSPOLL 0x08000000 /* PS poll frame */ 63185377Ssam#define AR_Frm_NoDelay 0x0c000000 /* no delay data */ 64185377Ssam#define AR_Frm_PIFS 0x10000000 /* PIFS data */ 65185377Ssam#define AR_TxInterReq 0x20000000 /* TX interrupt request */ 66185377Ssam#define AR_EncryptKeyValid 0x40000000 /* EncryptKeyIdx is valid */ 67185377Ssam 68185377Ssam/* TX ds_ctl1 */ 69185377Ssam#define AR_BufLen 0x00000fff /* data buffer length */ 70185377Ssam#define AR_More 0x00001000 /* more desc in this frame */ 71185377Ssam#define AR_EncryptKeyIdx 0x0007e000 /* encrypt key table index */ 72185377Ssam#define AR_EncryptKeyIdx_S 13 73185377Ssam#define AR_RTSDuration 0xfff80000 /* lower 13bit of duration */ 74185377Ssam 75185377Ssam/* RX ds_ctl1 */ 76185377Ssam/* AR_BufLen 0x00000fff data buffer length */ 77185377Ssam#define AR_RxInterReq 0x00002000 /* RX interrupt request */ 78185377Ssam 79185377Ssam/* TX ds_status0 */ 80185377Ssam#define AR_FrmXmitOK 0x00000001 /* TX success */ 81185377Ssam#define AR_ExcessiveRetries 0x00000002 /* excessive retries */ 82185377Ssam#define AR_FIFOUnderrun 0x00000004 /* TX FIFO underrun */ 83185377Ssam#define AR_Filtered 0x00000008 /* TX filter indication */ 84185377Ssam/* NB: the spec has the Short+Long retry counts reversed */ 85185377Ssam#define AR_LongRetryCnt 0x000000f0 /* long retry count */ 86185377Ssam#define AR_LongRetryCnt_S 4 87185377Ssam#define AR_ShortRetryCnt 0x00000f00 /* short retry count */ 88185377Ssam#define AR_ShortRetryCnt_S 8 89185377Ssam#define AR_SendTimestamp 0xffff0000 /* TX timestamp */ 90185377Ssam#define AR_SendTimestamp_S 16 91185377Ssam 92185377Ssam/* RX ds_status0 */ 93185377Ssam#define AR_DataLen 0x00000fff /* RX data length */ 94185377Ssam/* AR_More 0x00001000 more desc in this frame */ 95185377Ssam#define AR_RcvAntenna 0x00004000 /* received on ant 1 */ 96185377Ssam#define AR_RcvRate 0x00078000 /* reception rate */ 97185377Ssam#define AR_RcvRate_S 15 98185377Ssam#define AR_RcvSigStrength 0x07f80000 /* receive signal strength */ 99185377Ssam#define AR_RcvSigStrength_S 19 100185377Ssam 101185377Ssam/* TX ds_status1 */ 102185377Ssam#define AR_Done 0x00000001 /* descripter complete */ 103185377Ssam#define AR_SeqNum 0x00001ffe /* TX sequence number */ 104185377Ssam#define AR_AckSigStrength 0x001fe000 /* strength of ACK */ 105185377Ssam#define AR_AckSigStrength_S 13 106185377Ssam 107185377Ssam/* RX ds_status1 */ 108185377Ssam/* AR_Done 0x00000001 descripter complete */ 109185377Ssam#define AR_FrmRcvOK 0x00000002 /* frame reception success */ 110185377Ssam#define AR_CRCErr 0x00000004 /* CRC error */ 111185377Ssam#define AR_FIFOOverrun 0x00000008 /* RX FIFO overrun */ 112185377Ssam#define AR_DecryptCRCErr 0x00000010 /* Decryption CRC fiailure */ 113185377Ssam#define AR_PHYErr 0x000000e0 /* PHY error */ 114185377Ssam#define AR_PHYErr_S 5 115185377Ssam#define AR_PHYErr_NoErr 0x00000000 /* No error */ 116185377Ssam#define AR_PHYErr_Tim 0x00000020 /* Timing error */ 117185377Ssam#define AR_PHYErr_Par 0x00000040 /* Parity error */ 118185377Ssam#define AR_PHYErr_Rate 0x00000060 /* Illegal rate */ 119185377Ssam#define AR_PHYErr_Len 0x00000080 /* Illegal length */ 120185377Ssam#define AR_PHYErr_QAM 0x000000a0 /* 64 QAM rate */ 121185377Ssam#define AR_PHYErr_Srv 0x000000c0 /* Service bit error */ 122185377Ssam#define AR_PHYErr_TOR 0x000000e0 /* Transmit override receive */ 123185377Ssam#define AR_KeyIdxValid 0x00000100 /* decryption key index valid */ 124185377Ssam#define AR_KeyIdx 0x00007e00 /* Decryption key index */ 125185377Ssam#define AR_KeyIdx_S 9 126185377Ssam#define AR_RcvTimestamp 0x0fff8000 /* timestamp */ 127185377Ssam#define AR_RcvTimestamp_S 15 128185377Ssam#define AR_KeyCacheMiss 0x10000000 /* key cache miss indication */ 129185377Ssam 130185377Ssam#endif /* _DEV_ATH_AR5210DESC_H_ */ 131