ata-siliconimage.c revision 201758
1/*- 2 * Copyright (c) 1998 - 2008 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: head/sys/dev/ata/chipsets/ata-siliconimage.c 201758 2010-01-07 21:01:37Z mbr $"); 29 30#include "opt_ata.h" 31#include <sys/param.h> 32#include <sys/module.h> 33#include <sys/systm.h> 34#include <sys/kernel.h> 35#include <sys/ata.h> 36#include <sys/bus.h> 37#include <sys/endian.h> 38#include <sys/malloc.h> 39#include <sys/lock.h> 40#include <sys/mutex.h> 41#include <sys/sema.h> 42#include <sys/taskqueue.h> 43#include <vm/uma.h> 44#include <machine/stdarg.h> 45#include <machine/resource.h> 46#include <machine/bus.h> 47#include <sys/rman.h> 48#include <dev/pci/pcivar.h> 49#include <dev/pci/pcireg.h> 50#include <dev/ata/ata-all.h> 51#include <dev/ata/ata-pci.h> 52#include <ata_if.h> 53 54/* local prototypes */ 55static int ata_cmd_ch_attach(device_t dev); 56static int ata_cmd_status(device_t dev); 57static int ata_cmd_setmode(device_t dev, int target, int mode); 58static int ata_sii_ch_attach(device_t dev); 59static int ata_sii_ch_detach(device_t dev); 60static int ata_sii_status(device_t dev); 61static void ata_sii_reset(device_t dev); 62static int ata_sii_setmode(device_t dev, int target, int mode); 63static int ata_siiprb_ch_attach(device_t dev); 64static int ata_siiprb_ch_detach(device_t dev); 65static int ata_siiprb_status(device_t dev); 66static int ata_siiprb_begin_transaction(struct ata_request *request); 67static int ata_siiprb_end_transaction(struct ata_request *request); 68static int ata_siiprb_pm_read(device_t dev, int port, int reg, u_int32_t *result); 69static int ata_siiprb_pm_write(device_t dev, int port, int reg, u_int32_t result); 70static u_int32_t ata_siiprb_softreset(device_t dev, int port); 71static void ata_siiprb_reset(device_t dev); 72static void ata_siiprb_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 73static void ata_siiprb_dmainit(device_t dev); 74 75/* misc defines */ 76#define SII_MEMIO 1 77#define SII_PRBIO 2 78#define SII_INTR 0x01 79#define SII_SETCLK 0x02 80#define SII_BUG 0x04 81#define SII_4CH 0x08 82 83 84/* 85 * Silicon Image Inc. (SiI) (former CMD) chipset support functions 86 */ 87static int 88ata_sii_probe(device_t dev) 89{ 90 struct ata_pci_controller *ctlr = device_get_softc(dev); 91 static struct ata_chip_id ids[] = 92 {{ ATA_SII3114, 0x00, SII_MEMIO, SII_4CH, ATA_SA150, "3114" }, 93 { ATA_SII3512, 0x02, SII_MEMIO, 0, ATA_SA150, "3512" }, 94 { ATA_SII3112, 0x02, SII_MEMIO, 0, ATA_SA150, "3112" }, 95 { ATA_SII3112_1, 0x02, SII_MEMIO, 0, ATA_SA150, "3112" }, 96 { ATA_SII3512, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "3512" }, 97 { ATA_SII3112, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "3112" }, 98 { ATA_SII3112_1, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "3112" }, 99 { ATA_SII3124, 0x00, SII_PRBIO, SII_4CH, ATA_SA300, "3124" }, 100 { ATA_SII3132, 0x00, SII_PRBIO, 0, ATA_SA300, "3132" }, 101 { ATA_SII3132_1, 0x00, SII_PRBIO, 0, ATA_SA300, "3132" }, 102 { ATA_SII3132_2, 0x00, SII_PRBIO, 0, ATA_SA300, "3132" }, 103 { ATA_SII0680, 0x00, SII_MEMIO, SII_SETCLK, ATA_UDMA6, "680" }, 104 { ATA_CMD649, 0x00, 0, SII_INTR, ATA_UDMA5, "(CMD) 649" }, 105 { ATA_CMD648, 0x00, 0, SII_INTR, ATA_UDMA4, "(CMD) 648" }, 106 { ATA_CMD646, 0x07, 0, 0, ATA_UDMA2, "(CMD) 646U2" }, 107 { ATA_CMD646, 0x00, 0, 0, ATA_WDMA2, "(CMD) 646" }, 108 { 0, 0, 0, 0, 0, 0}}; 109 110 if (pci_get_vendor(dev) != ATA_SILICON_IMAGE_ID) 111 return ENXIO; 112 113 if (!(ctlr->chip = ata_match_chip(dev, ids))) 114 return ENXIO; 115 116 ata_set_desc(dev); 117 ctlr->chipinit = ata_sii_chipinit; 118 return (BUS_PROBE_DEFAULT); 119} 120 121int 122ata_sii_chipinit(device_t dev) 123{ 124 struct ata_pci_controller *ctlr = device_get_softc(dev); 125 126 if (ata_setup_interrupt(dev, ata_generic_intr)) 127 return ENXIO; 128 129 switch (ctlr->chip->cfg1) { 130 case SII_PRBIO: 131 ctlr->r_type1 = SYS_RES_MEMORY; 132 ctlr->r_rid1 = PCIR_BAR(0); 133 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1, 134 &ctlr->r_rid1, RF_ACTIVE))) 135 return ENXIO; 136 137 ctlr->r_rid2 = PCIR_BAR(2); 138 ctlr->r_type2 = SYS_RES_MEMORY; 139 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 140 &ctlr->r_rid2, RF_ACTIVE))){ 141 bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1,ctlr->r_res1); 142 return ENXIO; 143 } 144 ctlr->ch_attach = ata_siiprb_ch_attach; 145 ctlr->ch_detach = ata_siiprb_ch_detach; 146 ctlr->reset = ata_siiprb_reset; 147 ctlr->setmode = ata_sata_setmode; 148 ctlr->getrev = ata_sata_getrev; 149 ctlr->channels = (ctlr->chip->cfg2 == SII_4CH) ? 4 : 2; 150 151 /* reset controller */ 152 ATA_OUTL(ctlr->r_res1, 0x0040, 0x80000000); 153 DELAY(10000); 154 ATA_OUTL(ctlr->r_res1, 0x0040, 0x0000000f); 155 break; 156 157 case SII_MEMIO: 158 ctlr->r_type2 = SYS_RES_MEMORY; 159 ctlr->r_rid2 = PCIR_BAR(5); 160 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 161 &ctlr->r_rid2, RF_ACTIVE))){ 162 if (ctlr->chip->chipid != ATA_SII0680 || 163 (pci_read_config(dev, 0x8a, 1) & 1)) 164 return ENXIO; 165 } 166 167 if (ctlr->chip->cfg2 & SII_SETCLK) { 168 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10) 169 pci_write_config(dev, 0x8a, 170 (pci_read_config(dev, 0x8a, 1) & 0xcf)|0x10,1); 171 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10) 172 device_printf(dev, "%s could not set ATA133 clock\n", 173 ctlr->chip->text); 174 } 175 176 /* if we have 4 channels enable the second set */ 177 if (ctlr->chip->cfg2 & SII_4CH) { 178 ATA_OUTL(ctlr->r_res2, 0x0200, 0x00000002); 179 ctlr->channels = 4; 180 } 181 182 /* dont block interrupts from any channel */ 183 pci_write_config(dev, 0x48, 184 (pci_read_config(dev, 0x48, 4) & ~0x03c00000), 4); 185 186 /* enable PCI interrupt as BIOS might not */ 187 pci_write_config(dev, 0x8a, (pci_read_config(dev, 0x8a, 1) & 0x3f), 1); 188 189 if (ctlr->r_res2) { 190 ctlr->ch_attach = ata_sii_ch_attach; 191 ctlr->ch_detach = ata_sii_ch_detach; 192 } 193 194 if (ctlr->chip->max_dma >= ATA_SA150) { 195 ctlr->reset = ata_sii_reset; 196 ctlr->setmode = ata_sata_setmode; 197 ctlr->getrev = ata_sata_getrev; 198 } 199 else 200 ctlr->setmode = ata_sii_setmode; 201 break; 202 203 default: 204 if ((pci_read_config(dev, 0x51, 1) & 0x08) != 0x08) { 205 device_printf(dev, "HW has secondary channel disabled\n"); 206 ctlr->channels = 1; 207 } 208 209 /* enable interrupt as BIOS might not */ 210 pci_write_config(dev, 0x71, 0x01, 1); 211 212 ctlr->ch_attach = ata_cmd_ch_attach; 213 ctlr->ch_detach = ata_pci_ch_detach; 214 ctlr->setmode = ata_cmd_setmode; 215 break; 216 } 217 return 0; 218} 219 220static int 221ata_cmd_ch_attach(device_t dev) 222{ 223 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 224 struct ata_channel *ch = device_get_softc(dev); 225 226 /* setup the usual register normal pci style */ 227 if (ata_pci_ch_attach(dev)) 228 return ENXIO; 229 230 if (ctlr->chip->cfg2 & SII_INTR) 231 ch->hw.status = ata_cmd_status; 232 233 return 0; 234} 235 236static int 237ata_cmd_status(device_t dev) 238{ 239 struct ata_channel *ch = device_get_softc(dev); 240 u_int8_t reg71; 241 242 if (((reg71 = pci_read_config(device_get_parent(dev), 0x71, 1)) & 243 (ch->unit ? 0x08 : 0x04))) { 244 pci_write_config(device_get_parent(dev), 0x71, 245 reg71 & ~(ch->unit ? 0x04 : 0x08), 1); 246 return ata_pci_status(dev); 247 } 248 return 0; 249} 250 251static int 252ata_cmd_setmode(device_t dev, int target, int mode) 253{ 254 device_t parent = device_get_parent(dev); 255 struct ata_pci_controller *ctlr = device_get_softc(parent); 256 struct ata_channel *ch = device_get_softc(dev); 257 int devno = (ch->unit << 1) + target; 258 int treg = 0x54 + ((devno < 3) ? (devno << 1) : 7); 259 int ureg = ch->unit ? 0x7b : 0x73; 260 int piomode; 261 uint8_t piotimings[] = { 0xa9, 0x57, 0x44, 0x32, 0x3f, 0x87, 0x32, 0x3f }; 262 uint8_t udmatimings[][2] = { { 0x31, 0xc2 }, { 0x21, 0x82 }, 263 { 0x11, 0x42 }, { 0x25, 0x8a }, 264 { 0x15, 0x4a }, { 0x05, 0x0a } }; 265 266 mode = min(mode, ctlr->chip->max_dma); 267 if (mode >= ATA_UDMA0) { 268 u_int8_t umode = pci_read_config(parent, ureg, 1); 269 270 umode &= ~(target == 0 ? 0x35 : 0xca); 271 umode |= udmatimings[mode & ATA_MODE_MASK][target]; 272 pci_write_config(parent, ureg, umode, 1); 273 piomode = ATA_PIO4; 274 } else { 275 pci_write_config(parent, ureg, 276 pci_read_config(parent, ureg, 1) & 277 ~(target == 0 ? 0x35 : 0xca), 1); 278 piomode = mode; 279 } 280 pci_write_config(parent, treg, piotimings[ata_mode2idx(piomode)], 1); 281 return (mode); 282} 283 284static int 285ata_sii_ch_attach(device_t dev) 286{ 287 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 288 struct ata_channel *ch = device_get_softc(dev); 289 int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2); 290 int i; 291 292 ata_pci_dmainit(dev); 293 294 for (i = ATA_DATA; i <= ATA_COMMAND; i++) { 295 ch->r_io[i].res = ctlr->r_res2; 296 ch->r_io[i].offset = 0x80 + i + (unit01 << 6) + (unit10 << 8); 297 } 298 ch->r_io[ATA_CONTROL].res = ctlr->r_res2; 299 ch->r_io[ATA_CONTROL].offset = 0x8a + (unit01 << 6) + (unit10 << 8); 300 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2; 301 ata_default_registers(dev); 302 303 ch->r_io[ATA_BMCMD_PORT].res = ctlr->r_res2; 304 ch->r_io[ATA_BMCMD_PORT].offset = 0x00 + (unit01 << 3) + (unit10 << 8); 305 ch->r_io[ATA_BMSTAT_PORT].res = ctlr->r_res2; 306 ch->r_io[ATA_BMSTAT_PORT].offset = 0x02 + (unit01 << 3) + (unit10 << 8); 307 ch->r_io[ATA_BMDTP_PORT].res = ctlr->r_res2; 308 ch->r_io[ATA_BMDTP_PORT].offset = 0x04 + (unit01 << 3) + (unit10 << 8); 309 310 if (ctlr->chip->max_dma >= ATA_SA150) { 311 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 312 ch->r_io[ATA_SSTATUS].offset = 0x104 + (unit01 << 7) + (unit10 << 8); 313 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 314 ch->r_io[ATA_SERROR].offset = 0x108 + (unit01 << 7) + (unit10 << 8); 315 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 316 ch->r_io[ATA_SCONTROL].offset = 0x100 + (unit01 << 7) + (unit10 << 8); 317 ch->flags |= ATA_NO_SLAVE; 318 ch->flags |= ATA_SATA; 319 320 /* enable PHY state change interrupt */ 321 ATA_OUTL(ctlr->r_res2, 0x148 + (unit01 << 7) + (unit10 << 8),(1 << 16)); 322 } 323 324 if (ctlr->chip->cfg2 & SII_BUG) { 325 /* work around errata in early chips */ 326 ch->dma.boundary = 8192; 327 ch->dma.segsize = 15 * DEV_BSIZE; 328 } 329 330 ata_pci_hw(dev); 331 ch->hw.status = ata_sii_status; 332 if (ctlr->chip->cfg2 & SII_SETCLK) 333 ch->flags |= ATA_CHECKS_CABLE; 334 return 0; 335} 336 337static int 338ata_sii_ch_detach(device_t dev) 339{ 340 341 ata_pci_dmafini(dev); 342 return (0); 343} 344 345static int 346ata_sii_status(device_t dev) 347{ 348 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 349 struct ata_channel *ch = device_get_softc(dev); 350 int offset0 = ((ch->unit & 1) << 3) + ((ch->unit & 2) << 8); 351 int offset1 = ((ch->unit & 1) << 6) + ((ch->unit & 2) << 8); 352 353 /* do we have any PHY events ? */ 354 if (ctlr->chip->max_dma >= ATA_SA150 && 355 (ATA_INL(ctlr->r_res2, 0x10 + offset0) & 0x00000010)) 356 ata_sata_phy_check_events(dev); 357 358 if (ATA_INL(ctlr->r_res2, 0xa0 + offset1) & 0x00000800) 359 return ata_pci_status(dev); 360 else 361 return 0; 362} 363 364static void 365ata_sii_reset(device_t dev) 366{ 367 if (ata_sata_phy_reset(dev, -1, 1)) 368 ata_generic_reset(dev); 369} 370 371static int 372ata_sii_setmode(device_t dev, int target, int mode) 373{ 374 device_t parent = device_get_parent(dev); 375 struct ata_pci_controller *ctlr = device_get_softc(parent); 376 struct ata_channel *ch = device_get_softc(dev); 377 int rego = (ch->unit << 4) + (target << 1); 378 int mreg = ch->unit ? 0x84 : 0x80; 379 int mask = 0x03 << (target << 2); 380 int mval = pci_read_config(parent, mreg, 1) & ~mask; 381 int piomode; 382 u_int8_t preg = 0xa4 + rego; 383 u_int8_t dreg = 0xa8 + rego; 384 u_int8_t ureg = 0xac + rego; 385 u_int16_t piotimings[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 }; 386 u_int16_t dmatimings[] = { 0x2208, 0x10c2, 0x10c1 }; 387 u_int8_t udmatimings[] = { 0xf, 0xb, 0x7, 0x5, 0x3, 0x2, 0x1 }; 388 389 mode = min(mode, ctlr->chip->max_dma); 390 391 if (ctlr->chip->cfg2 & SII_SETCLK) { 392 if (mode > ATA_UDMA2 && (pci_read_config(parent, 0x79, 1) & 393 (ch->unit ? 0x02 : 0x01))) { 394 ata_print_cable(dev, "controller"); 395 mode = ATA_UDMA2; 396 } 397 } 398 if (mode >= ATA_UDMA0) { 399 pci_write_config(parent, mreg, 400 mval | (0x03 << (target << 2)), 1); 401 pci_write_config(parent, ureg, 402 (pci_read_config(parent, ureg, 1) & ~0x3f) | 403 udmatimings[mode & ATA_MODE_MASK], 1); 404 piomode = ATA_PIO4; 405 } else if (mode >= ATA_WDMA0) { 406 pci_write_config(parent, mreg, 407 mval | (0x02 << (target << 2)), 1); 408 pci_write_config(parent, dreg, dmatimings[mode & ATA_MODE_MASK], 2); 409 piomode = (mode == ATA_WDMA0) ? ATA_PIO0 : 410 (mode == ATA_WDMA1) ? ATA_PIO3 : ATA_PIO4; 411 } else { 412 pci_write_config(parent, mreg, 413 mval | (0x01 << (target << 2)), 1); 414 piomode = mode; 415 } 416 pci_write_config(parent, preg, piotimings[ata_mode2idx(piomode)], 2); 417 return (mode); 418} 419 420 421struct ata_siiprb_dma_prdentry { 422 u_int64_t addr; 423 u_int32_t count; 424 u_int32_t control; 425} __packed; 426 427#define ATA_SIIPRB_DMA_ENTRIES 129 428struct ata_siiprb_ata_command { 429 struct ata_siiprb_dma_prdentry prd[ATA_SIIPRB_DMA_ENTRIES]; 430} __packed; 431 432struct ata_siiprb_atapi_command { 433 u_int8_t ccb[16]; 434 struct ata_siiprb_dma_prdentry prd[ATA_SIIPRB_DMA_ENTRIES]; 435} __packed; 436 437struct ata_siiprb_command { 438 u_int16_t control; 439 u_int16_t protocol_override; 440 u_int32_t transfer_count; 441 u_int8_t fis[24]; 442 union { 443 struct ata_siiprb_ata_command ata; 444 struct ata_siiprb_atapi_command atapi; 445 } u; 446} __packed; 447 448static int 449ata_siiprb_ch_attach(device_t dev) 450{ 451 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 452 struct ata_channel *ch = device_get_softc(dev); 453 int offset = ch->unit * 0x2000; 454 455 ata_siiprb_dmainit(dev); 456 457 /* set the SATA resources */ 458 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 459 ch->r_io[ATA_SSTATUS].offset = 0x1f04 + offset; 460 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 461 ch->r_io[ATA_SERROR].offset = 0x1f08 + offset; 462 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 463 ch->r_io[ATA_SCONTROL].offset = 0x1f00 + offset; 464 ch->r_io[ATA_SACTIVE].res = ctlr->r_res2; 465 ch->r_io[ATA_SACTIVE].offset = 0x1f0c + offset; 466 467 ch->hw.status = ata_siiprb_status; 468 ch->hw.begin_transaction = ata_siiprb_begin_transaction; 469 ch->hw.end_transaction = ata_siiprb_end_transaction; 470 ch->hw.command = NULL; /* not used here */ 471 ch->hw.softreset = ata_siiprb_softreset; 472 ch->hw.pm_read = ata_siiprb_pm_read; 473 ch->hw.pm_write = ata_siiprb_pm_write; 474 475 return 0; 476} 477 478static int 479ata_siiprb_ch_detach(device_t dev) 480{ 481 482 ata_dmafini(dev); 483 return 0; 484} 485 486static int 487ata_siiprb_status(device_t dev) 488{ 489 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 490 struct ata_channel *ch = device_get_softc(dev); 491 u_int32_t action = ATA_INL(ctlr->r_res1, 0x0044); 492 int offset = ch->unit * 0x2000; 493 494 if (action & (1 << ch->unit)) { 495 u_int32_t istatus = ATA_INL(ctlr->r_res2, 0x1008 + offset); 496 497 /* do we have any PHY events ? */ 498 ata_sata_phy_check_events(dev); 499 500 /* clear interrupt(s) */ 501 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, istatus); 502 503 /* do we have any device action ? */ 504 return (istatus & 0x00000003); 505 } 506 return 0; 507} 508 509static int 510ata_siiprb_begin_transaction(struct ata_request *request) 511{ 512 struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent)); 513 struct ata_channel *ch = device_get_softc(request->parent); 514 struct ata_siiprb_command *prb; 515 struct ata_siiprb_dma_prdentry *prd; 516 int offset = ch->unit * 0x2000; 517 u_int64_t prb_bus; 518 519 /* SOS XXX */ 520 if (request->u.ata.command == ATA_DEVICE_RESET) { 521 request->result = 0; 522 return ATA_OP_FINISHED; 523 } 524 525 /* get a piece of the workspace for this request */ 526 prb = (struct ata_siiprb_command *)ch->dma.work; 527 528 /* clear the prb structure */ 529 bzero(prb, sizeof(struct ata_siiprb_command)); 530 531 /* setup the FIS for this request */ 532 if (!ata_request2fis_h2d(request, &prb->fis[0])) { 533 device_printf(request->parent, "setting up SATA FIS failed\n"); 534 request->result = EIO; 535 return ATA_OP_FINISHED; 536 } 537 538 /* setup transfer type */ 539 if (request->flags & ATA_R_ATAPI) { 540 bcopy(request->u.atapi.ccb, prb->u.atapi.ccb, 16); 541 if (request->flags & ATA_R_ATAPI16) 542 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000020); 543 else 544 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000020); 545 if (request->flags & ATA_R_READ) 546 prb->control = htole16(0x0010); 547 if (request->flags & ATA_R_WRITE) 548 prb->control = htole16(0x0020); 549 prd = &prb->u.atapi.prd[0]; 550 } 551 else 552 prd = &prb->u.ata.prd[0]; 553 554 /* if request moves data setup and load SG list */ 555 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) { 556 if (ch->dma.load(request, prd, NULL)) { 557 device_printf(request->parent, "setting up DMA failed\n"); 558 request->result = EIO; 559 return ATA_OP_FINISHED; 560 } 561 } 562 563 /* activate the prb */ 564 prb_bus = ch->dma.work_bus; 565 ATA_OUTL(ctlr->r_res2, 0x1c00 + offset, prb_bus); 566 ATA_OUTL(ctlr->r_res2, 0x1c04 + offset, prb_bus>>32); 567 568 /* start the timeout */ 569 callout_reset(&request->callout, request->timeout * hz, 570 (timeout_t*)ata_timeout, request); 571 return ATA_OP_CONTINUES; 572} 573 574static int 575ata_siiprb_end_transaction(struct ata_request *request) 576{ 577 struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent)); 578 struct ata_channel *ch = device_get_softc(request->parent); 579 struct ata_siiprb_command *prb; 580 int offset = ch->unit * 0x2000; 581 int error, timeout; 582 583 /* kill the timeout */ 584 callout_stop(&request->callout); 585 586 prb = (struct ata_siiprb_command *) 587 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset); 588 589 /* any controller errors flagged ? */ 590 if ((error = ATA_INL(ctlr->r_res2, 0x1024 + offset))) { 591 if (bootverbose) 592 printf("ata_siiprb_end_transaction %s error=%08x\n", 593 ata_cmd2str(request), error); 594 595 /* if device error status get details */ 596 if (error == 1 || error == 2) { 597 request->status = prb->fis[2]; 598 if (request->status & ATA_S_ERROR) 599 request->error = prb->fis[3]; 600 } 601 602 /* SOS XXX handle other controller errors here */ 603 604 /* initialize port */ 605 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000004); 606 607 /* poll for port ready */ 608 for (timeout = 0; timeout < 1000; timeout++) { 609 DELAY(1000); 610 if (ATA_INL(ctlr->r_res2, 0x1008 + offset) & 0x00040000) 611 break; 612 } 613 if (bootverbose) { 614 if (timeout >= 1000) 615 device_printf(ch->dev, "port initialize timeout\n"); 616 else 617 device_printf(ch->dev, "port initialize time=%dms\n", timeout); 618 } 619 } 620 621 /* on control commands read back registers to the request struct */ 622 if (request->flags & ATA_R_CONTROL) { 623 request->u.ata.count = prb->fis[12] | ((u_int16_t)prb->fis[13] << 8); 624 request->u.ata.lba = prb->fis[4] | ((u_int64_t)prb->fis[5] << 8) | 625 ((u_int64_t)prb->fis[6] << 16); 626 if (request->flags & ATA_R_48BIT) 627 request->u.ata.lba |= ((u_int64_t)prb->fis[8] << 24) | 628 ((u_int64_t)prb->fis[9] << 32) | 629 ((u_int64_t)prb->fis[10] << 40); 630 else 631 request->u.ata.lba |= ((u_int64_t)(prb->fis[7] & 0x0f) << 24); 632 } 633 634 /* update progress */ 635 if (!(request->status & ATA_S_ERROR) && !(request->flags & ATA_R_TIMEOUT)) { 636 if (request->flags & ATA_R_READ) 637 request->donecount = prb->transfer_count; 638 else 639 request->donecount = request->bytecount; 640 } 641 642 /* release SG list etc */ 643 ch->dma.unload(request); 644 645 return ATA_OP_FINISHED; 646} 647 648static int 649ata_siiprb_issue_cmd(device_t dev) 650{ 651 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 652 struct ata_channel *ch = device_get_softc(dev); 653 u_int64_t prb_bus = ch->dma.work_bus; 654 u_int32_t status; 655 int offset = ch->unit * 0x2000; 656 int timeout; 657 658 /* issue command to chip */ 659 ATA_OUTL(ctlr->r_res2, 0x1c00 + offset, prb_bus); 660 ATA_OUTL(ctlr->r_res2, 0x1c04 + offset, prb_bus >> 32); 661 662 /* poll for command finished */ 663 for (timeout = 0; timeout < 10000; timeout++) { 664 DELAY(1000); 665 if ((status = ATA_INL(ctlr->r_res2, 0x1008 + offset)) & 0x00010000) 666 break; 667 } 668 // SOS XXX ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x00010000); 669 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x08ff08ff); 670 671 if (timeout >= 1000) 672 return EIO; 673 674 if (bootverbose) 675 device_printf(dev, "siiprb_issue_cmd time=%dms status=%08x\n", 676 timeout, status); 677 return 0; 678} 679 680static int 681ata_siiprb_pm_read(device_t dev, int port, int reg, u_int32_t *result) 682{ 683 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 684 struct ata_channel *ch = device_get_softc(dev); 685 struct ata_siiprb_command *prb = (struct ata_siiprb_command *)ch->dma.work; 686 int offset = ch->unit * 0x2000; 687 688 bzero(prb, sizeof(struct ata_siiprb_command)); 689 prb->fis[0] = 0x27; /* host to device */ 690 prb->fis[1] = 0x8f; /* command FIS to PM port */ 691 prb->fis[2] = ATA_READ_PM; 692 prb->fis[3] = reg; 693 prb->fis[7] = port; 694 if (ata_siiprb_issue_cmd(dev)) { 695 device_printf(dev, "error reading PM port\n"); 696 return EIO; 697 } 698 prb = (struct ata_siiprb_command *) 699 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset); 700 *result = prb->fis[12]|(prb->fis[4]<<8)|(prb->fis[5]<<16)|(prb->fis[6]<<24); 701 return 0; 702} 703 704static int 705ata_siiprb_pm_write(device_t dev, int port, int reg, u_int32_t value) 706{ 707 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 708 struct ata_channel *ch = device_get_softc(dev); 709 struct ata_siiprb_command *prb = (struct ata_siiprb_command *)ch->dma.work; 710 int offset = ch->unit * 0x2000; 711 712 bzero(prb, sizeof(struct ata_siiprb_command)); 713 prb->fis[0] = 0x27; /* host to device */ 714 prb->fis[1] = 0x8f; /* command FIS to PM port */ 715 prb->fis[2] = ATA_WRITE_PM; 716 prb->fis[3] = reg; 717 prb->fis[7] = port; 718 prb->fis[12] = value & 0xff; 719 prb->fis[4] = (value >> 8) & 0xff; 720 prb->fis[5] = (value >> 16) & 0xff; 721 prb->fis[6] = (value >> 24) & 0xff; 722 if (ata_siiprb_issue_cmd(dev)) { 723 device_printf(dev, "error writing PM port\n"); 724 return ATA_E_ABORT; 725 } 726 prb = (struct ata_siiprb_command *) 727 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset); 728 return prb->fis[3]; 729} 730 731static u_int32_t 732ata_siiprb_softreset(device_t dev, int port) 733{ 734 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 735 struct ata_channel *ch = device_get_softc(dev); 736 struct ata_siiprb_command *prb = (struct ata_siiprb_command *)ch->dma.work; 737 u_int32_t signature; 738 int offset = ch->unit * 0x2000; 739 740 /* setup the workspace for a soft reset command */ 741 bzero(prb, sizeof(struct ata_siiprb_command)); 742 prb->control = htole16(0x0080); 743 prb->fis[1] = port & 0x0f; 744 745 /* issue soft reset */ 746 if (ata_siiprb_issue_cmd(dev)) 747 return -1; 748 749 ata_udelay(150000); 750 751 /* get possible signature */ 752 prb = (struct ata_siiprb_command *) 753 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset); 754 signature=prb->fis[12]|(prb->fis[4]<<8)|(prb->fis[5]<<16)|(prb->fis[6]<<24); 755 756 /* clear error bits/interrupt */ 757 ATA_IDX_OUTL(ch, ATA_SERROR, 0xffffffff); 758 759 return signature; 760} 761 762static void 763ata_siiprb_reset(device_t dev) 764{ 765 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 766 struct ata_channel *ch = device_get_softc(dev); 767 int offset = ch->unit * 0x2000; 768 u_int32_t status, signature; 769 int timeout; 770 771 /* disable interrupts */ 772 ATA_OUTL(ctlr->r_res2, 0x1014 + offset, 0x000000ff); 773 774 /* reset channel HW */ 775 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000001); 776 DELAY(1000); 777 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000001); 778 DELAY(10000); 779 780 /* poll for channel ready */ 781 for (timeout = 0; timeout < 1000; timeout++) { 782 if ((status = ATA_INL(ctlr->r_res2, 0x1008 + offset)) & 0x00040000) 783 break; 784 DELAY(1000); 785 } 786 787 if (bootverbose) { 788 if (timeout >= 1000) 789 device_printf(dev, "channel HW reset timeout\n"); 790 else 791 device_printf(dev, "channel HW reset time=%dms\n", timeout); 792 } 793 794 /* reset phy */ 795 if (!ata_sata_phy_reset(dev, -1, 1)) { 796 if (bootverbose) 797 device_printf(dev, "phy reset found no device\n"); 798 ch->devices = 0; 799 goto finish; 800 } 801 802 /* issue soft reset */ 803 signature = ata_siiprb_softreset(dev, ATA_PM); 804 if (bootverbose) 805 device_printf(dev, "SIGNATURE=%08x\n", signature); 806 807 /* figure out whats there */ 808 switch (signature >> 16) { 809 case 0x0000: 810 ch->devices = ATA_ATA_MASTER; 811 break; 812 case 0x9669: 813 ch->devices = ATA_PORTMULTIPLIER; 814 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x2000); /* enable PM support */ 815 //SOS XXX need to clear all PM status and interrupts!!!! 816 ata_pm_identify(dev); 817 break; 818 case 0xeb14: 819 ch->devices = ATA_ATAPI_MASTER; 820 break; 821 default: 822 ch->devices = 0; 823 } 824 if (bootverbose) 825 device_printf(dev, "siiprb_reset devices=%08x\n", ch->devices); 826 827finish: 828 /* clear interrupt(s) */ 829 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x000008ff); 830 831 /* require explicit interrupt ack */ 832 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000008); 833 834 /* 64bit mode */ 835 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000400); 836 837 /* enable interrupts wanted */ 838 ATA_OUTL(ctlr->r_res2, 0x1010 + offset, 0x000000ff); 839} 840 841static void 842ata_siiprb_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 843{ 844 struct ata_dmasetprd_args *args = xsc; 845 struct ata_siiprb_dma_prdentry *prd = args->dmatab; 846 int i; 847 848 if ((args->error = error)) 849 return; 850 851 for (i = 0; i < nsegs; i++) { 852 prd[i].addr = htole64(segs[i].ds_addr); 853 prd[i].count = htole32(segs[i].ds_len); 854 } 855 prd[i - 1].control = htole32(ATA_DMA_EOT); 856 KASSERT(nsegs <= ATA_SIIPRB_DMA_ENTRIES,("too many DMA segment entries\n")); 857 args->nsegs = nsegs; 858} 859 860static void 861ata_siiprb_dmainit(device_t dev) 862{ 863 struct ata_channel *ch = device_get_softc(dev); 864 865 ata_dmainit(dev); 866 /* note start and stop are not used here */ 867 ch->dma.setprd = ata_siiprb_dmasetprd; 868 ch->dma.max_address = BUS_SPACE_MAXADDR; 869 ch->dma.max_iosize = (ATA_SIIPRB_DMA_ENTRIES - 1) * PAGE_SIZE; 870} 871 872ATA_DECLARE_DRIVER(ata_sii); 873