ata-siliconimage.c revision 188769
1/*- 2 * Copyright (c) 1998 - 2008 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: head/sys/dev/ata/chipsets/ata-siliconimage.c 188769 2009-02-19 00:32:55Z mav $"); 29 30#include "opt_ata.h" 31#include <sys/param.h> 32#include <sys/module.h> 33#include <sys/systm.h> 34#include <sys/kernel.h> 35#include <sys/ata.h> 36#include <sys/bus.h> 37#include <sys/endian.h> 38#include <sys/malloc.h> 39#include <sys/lock.h> 40#include <sys/mutex.h> 41#include <sys/sema.h> 42#include <sys/taskqueue.h> 43#include <vm/uma.h> 44#include <machine/stdarg.h> 45#include <machine/resource.h> 46#include <machine/bus.h> 47#include <sys/rman.h> 48#include <dev/pci/pcivar.h> 49#include <dev/pci/pcireg.h> 50#include <dev/ata/ata-all.h> 51#include <dev/ata/ata-pci.h> 52#include <ata_if.h> 53 54/* local prototypes */ 55static int ata_cmd_ch_attach(device_t dev); 56static int ata_cmd_status(device_t dev); 57static void ata_cmd_setmode(device_t dev, int mode); 58static int ata_sii_ch_attach(device_t dev); 59static int ata_sii_ch_detach(device_t dev); 60static int ata_sii_status(device_t dev); 61static void ata_sii_reset(device_t dev); 62static void ata_sii_setmode(device_t dev, int mode); 63static int ata_siiprb_ch_attach(device_t dev); 64static int ata_siiprb_ch_detach(device_t dev); 65static int ata_siiprb_status(device_t dev); 66static int ata_siiprb_begin_transaction(struct ata_request *request); 67static int ata_siiprb_end_transaction(struct ata_request *request); 68static int ata_siiprb_pm_read(device_t dev, int port, int reg, u_int32_t *result); 69static int ata_siiprb_pm_write(device_t dev, int port, int reg, u_int32_t result); 70static u_int32_t ata_siiprb_softreset(device_t dev, int port); 71static void ata_siiprb_reset(device_t dev); 72static void ata_siiprb_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 73static void ata_siiprb_dmainit(device_t dev); 74 75/* misc defines */ 76#define SII_MEMIO 1 77#define SII_PRBIO 2 78#define SII_INTR 0x01 79#define SII_SETCLK 0x02 80#define SII_BUG 0x04 81#define SII_4CH 0x08 82 83 84/* 85 * Silicon Image Inc. (SiI) (former CMD) chipset support functions 86 */ 87static int 88ata_sii_probe(device_t dev) 89{ 90 struct ata_pci_controller *ctlr = device_get_softc(dev); 91 static struct ata_chip_id ids[] = 92 {{ ATA_SII3114, 0x00, SII_MEMIO, SII_4CH, ATA_SA150, "3114" }, 93 { ATA_SII3512, 0x02, SII_MEMIO, 0, ATA_SA150, "3512" }, 94 { ATA_SII3112, 0x02, SII_MEMIO, 0, ATA_SA150, "3112" }, 95 { ATA_SII3112_1, 0x02, SII_MEMIO, 0, ATA_SA150, "3112" }, 96 { ATA_SII3512, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "3512" }, 97 { ATA_SII3112, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "3112" }, 98 { ATA_SII3112_1, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "3112" }, 99 { ATA_SII3124, 0x00, SII_PRBIO, SII_4CH, ATA_SA300, "3124" }, 100 { ATA_SII3132, 0x00, SII_PRBIO, 0, ATA_SA300, "3132" }, 101 { ATA_SII3132_1, 0x00, SII_PRBIO, 0, ATA_SA300, "3132" }, 102 { ATA_SII0680, 0x00, SII_MEMIO, SII_SETCLK, ATA_UDMA6, "680" }, 103 { ATA_CMD649, 0x00, 0, SII_INTR, ATA_UDMA5, "(CMD) 649" }, 104 { ATA_CMD648, 0x00, 0, SII_INTR, ATA_UDMA4, "(CMD) 648" }, 105 { ATA_CMD646, 0x07, 0, 0, ATA_UDMA2, "(CMD) 646U2" }, 106 { ATA_CMD646, 0x00, 0, 0, ATA_WDMA2, "(CMD) 646" }, 107 { 0, 0, 0, 0, 0, 0}}; 108 109 if (pci_get_vendor(dev) != ATA_SILICON_IMAGE_ID) 110 return ENXIO; 111 112 if (!(ctlr->chip = ata_match_chip(dev, ids))) 113 return ENXIO; 114 115 ata_set_desc(dev); 116 ctlr->chipinit = ata_sii_chipinit; 117 return 0; 118} 119 120int 121ata_sii_chipinit(device_t dev) 122{ 123 struct ata_pci_controller *ctlr = device_get_softc(dev); 124 125 if (ata_setup_interrupt(dev, ata_generic_intr)) 126 return ENXIO; 127 128 switch (ctlr->chip->cfg1) { 129 case SII_PRBIO: 130 ctlr->r_type1 = SYS_RES_MEMORY; 131 ctlr->r_rid1 = PCIR_BAR(0); 132 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1, 133 &ctlr->r_rid1, RF_ACTIVE))) 134 return ENXIO; 135 136 ctlr->r_rid2 = PCIR_BAR(2); 137 ctlr->r_type2 = SYS_RES_MEMORY; 138 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 139 &ctlr->r_rid2, RF_ACTIVE))){ 140 bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1,ctlr->r_res1); 141 return ENXIO; 142 } 143 ctlr->ch_attach = ata_siiprb_ch_attach; 144 ctlr->ch_detach = ata_siiprb_ch_detach; 145 ctlr->reset = ata_siiprb_reset; 146 ctlr->setmode = ata_sata_setmode; 147 ctlr->channels = (ctlr->chip->cfg2 == SII_4CH) ? 4 : 2; 148 149 /* reset controller */ 150 ATA_OUTL(ctlr->r_res1, 0x0040, 0x80000000); 151 DELAY(10000); 152 ATA_OUTL(ctlr->r_res1, 0x0040, 0x0000000f); 153 154 /* enable PCI interrupt */ 155 pci_write_config(dev, PCIR_COMMAND, 156 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2); 157 break; 158 159 case SII_MEMIO: 160 ctlr->r_type2 = SYS_RES_MEMORY; 161 ctlr->r_rid2 = PCIR_BAR(5); 162 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 163 &ctlr->r_rid2, RF_ACTIVE))){ 164 if (ctlr->chip->chipid != ATA_SII0680 || 165 (pci_read_config(dev, 0x8a, 1) & 1)) 166 return ENXIO; 167 } 168 169 if (ctlr->chip->cfg2 & SII_SETCLK) { 170 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10) 171 pci_write_config(dev, 0x8a, 172 (pci_read_config(dev, 0x8a, 1) & 0xcf)|0x10,1); 173 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10) 174 device_printf(dev, "%s could not set ATA133 clock\n", 175 ctlr->chip->text); 176 } 177 178 /* if we have 4 channels enable the second set */ 179 if (ctlr->chip->cfg2 & SII_4CH) { 180 ATA_OUTL(ctlr->r_res2, 0x0200, 0x00000002); 181 ctlr->channels = 4; 182 } 183 184 /* dont block interrupts from any channel */ 185 pci_write_config(dev, 0x48, 186 (pci_read_config(dev, 0x48, 4) & ~0x03c00000), 4); 187 188 /* enable PCI interrupt as BIOS might not */ 189 pci_write_config(dev, 0x8a, (pci_read_config(dev, 0x8a, 1) & 0x3f), 1); 190 191 if (ctlr->r_res2) { 192 ctlr->ch_attach = ata_sii_ch_attach; 193 ctlr->ch_detach = ata_sii_ch_detach; 194 } 195 196 if (ctlr->chip->max_dma >= ATA_SA150) { 197 ctlr->reset = ata_sii_reset; 198 ctlr->setmode = ata_sata_setmode; 199 } 200 else 201 ctlr->setmode = ata_sii_setmode; 202 break; 203 204 default: 205 if ((pci_read_config(dev, 0x51, 1) & 0x08) != 0x08) { 206 device_printf(dev, "HW has secondary channel disabled\n"); 207 ctlr->channels = 1; 208 } 209 210 /* enable interrupt as BIOS might not */ 211 pci_write_config(dev, 0x71, 0x01, 1); 212 213 ctlr->ch_attach = ata_cmd_ch_attach; 214 ctlr->ch_detach = ata_pci_ch_detach; 215 ctlr->setmode = ata_cmd_setmode; 216 break; 217 } 218 return 0; 219} 220 221static int 222ata_cmd_ch_attach(device_t dev) 223{ 224 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 225 struct ata_channel *ch = device_get_softc(dev); 226 227 /* setup the usual register normal pci style */ 228 if (ata_pci_ch_attach(dev)) 229 return ENXIO; 230 231 if (ctlr->chip->cfg2 & SII_INTR) 232 ch->hw.status = ata_cmd_status; 233 234 return 0; 235} 236 237static int 238ata_cmd_status(device_t dev) 239{ 240 struct ata_channel *ch = device_get_softc(dev); 241 u_int8_t reg71; 242 243 if (((reg71 = pci_read_config(device_get_parent(dev), 0x71, 1)) & 244 (ch->unit ? 0x08 : 0x04))) { 245 pci_write_config(device_get_parent(dev), 0x71, 246 reg71 & ~(ch->unit ? 0x04 : 0x08), 1); 247 return ata_pci_status(dev); 248 } 249 return 0; 250} 251 252static void 253ata_cmd_setmode(device_t dev, int mode) 254{ 255 device_t gparent = GRANDPARENT(dev); 256 struct ata_pci_controller *ctlr = device_get_softc(gparent); 257 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 258 struct ata_device *atadev = device_get_softc(dev); 259 int devno = (ch->unit << 1) + atadev->unit; 260 int error; 261 262 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 263 264 mode = ata_check_80pin(dev, mode); 265 266 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 267 268 if (bootverbose) 269 device_printf(dev, "%ssetting %s on %s chip\n", 270 (error) ? "FAILURE " : "", 271 ata_mode2str(mode), ctlr->chip->text); 272 if (!error) { 273 int treg = 0x54 + ((devno < 3) ? (devno << 1) : 7); 274 int ureg = ch->unit ? 0x7b : 0x73; 275 276 if (mode >= ATA_UDMA0) { 277 int udmatimings[][2] = { { 0x31, 0xc2 }, { 0x21, 0x82 }, 278 { 0x11, 0x42 }, { 0x25, 0x8a }, 279 { 0x15, 0x4a }, { 0x05, 0x0a } }; 280 281 u_int8_t umode = pci_read_config(gparent, ureg, 1); 282 283 umode &= ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca); 284 umode |= udmatimings[mode & ATA_MODE_MASK][atadev->unit]; 285 pci_write_config(gparent, ureg, umode, 1); 286 } 287 else if (mode >= ATA_WDMA0) { 288 int dmatimings[] = { 0x87, 0x32, 0x3f }; 289 290 pci_write_config(gparent, treg, dmatimings[mode & ATA_MODE_MASK],1); 291 pci_write_config(gparent, ureg, 292 pci_read_config(gparent, ureg, 1) & 293 ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca), 1); 294 } 295 else { 296 int piotimings[] = { 0xa9, 0x57, 0x44, 0x32, 0x3f }; 297 pci_write_config(gparent, treg, 298 piotimings[(mode & ATA_MODE_MASK) - ATA_PIO0], 1); 299 pci_write_config(gparent, ureg, 300 pci_read_config(gparent, ureg, 1) & 301 ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca), 1); 302 } 303 atadev->mode = mode; 304 } 305} 306 307static int 308ata_sii_ch_attach(device_t dev) 309{ 310 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 311 struct ata_channel *ch = device_get_softc(dev); 312 int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2); 313 int i; 314 315 ata_pci_dmainit(dev); 316 317 for (i = ATA_DATA; i <= ATA_COMMAND; i++) { 318 ch->r_io[i].res = ctlr->r_res2; 319 ch->r_io[i].offset = 0x80 + i + (unit01 << 6) + (unit10 << 8); 320 } 321 ch->r_io[ATA_CONTROL].res = ctlr->r_res2; 322 ch->r_io[ATA_CONTROL].offset = 0x8a + (unit01 << 6) + (unit10 << 8); 323 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2; 324 ata_default_registers(dev); 325 326 ch->r_io[ATA_BMCMD_PORT].res = ctlr->r_res2; 327 ch->r_io[ATA_BMCMD_PORT].offset = 0x00 + (unit01 << 3) + (unit10 << 8); 328 ch->r_io[ATA_BMSTAT_PORT].res = ctlr->r_res2; 329 ch->r_io[ATA_BMSTAT_PORT].offset = 0x02 + (unit01 << 3) + (unit10 << 8); 330 ch->r_io[ATA_BMDTP_PORT].res = ctlr->r_res2; 331 ch->r_io[ATA_BMDTP_PORT].offset = 0x04 + (unit01 << 3) + (unit10 << 8); 332 333 if (ctlr->chip->max_dma >= ATA_SA150) { 334 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 335 ch->r_io[ATA_SSTATUS].offset = 0x104 + (unit01 << 7) + (unit10 << 8); 336 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 337 ch->r_io[ATA_SERROR].offset = 0x108 + (unit01 << 7) + (unit10 << 8); 338 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 339 ch->r_io[ATA_SCONTROL].offset = 0x100 + (unit01 << 7) + (unit10 << 8); 340 ch->flags |= ATA_NO_SLAVE; 341 342 /* enable PHY state change interrupt */ 343 ATA_OUTL(ctlr->r_res2, 0x148 + (unit01 << 7) + (unit10 << 8),(1 << 16)); 344 } 345 346 if (ctlr->chip->cfg2 & SII_BUG) { 347 /* work around errata in early chips */ 348 ch->dma.boundary = 8192; 349 ch->dma.segsize = 15 * DEV_BSIZE; 350 } 351 352 ata_pci_hw(dev); 353 ch->hw.status = ata_sii_status; 354 return 0; 355} 356 357static int 358ata_sii_ch_detach(device_t dev) 359{ 360 361 ata_pci_dmafini(dev); 362 return (0); 363} 364 365static int 366ata_sii_status(device_t dev) 367{ 368 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 369 struct ata_channel *ch = device_get_softc(dev); 370 int offset0 = ((ch->unit & 1) << 3) + ((ch->unit & 2) << 8); 371 int offset1 = ((ch->unit & 1) << 6) + ((ch->unit & 2) << 8); 372 373 /* do we have any PHY events ? */ 374 if (ctlr->chip->max_dma >= ATA_SA150 && 375 (ATA_INL(ctlr->r_res2, 0x10 + offset0) & 0x00000010)) 376 ata_sata_phy_check_events(dev); 377 378 if (ATA_INL(ctlr->r_res2, 0xa0 + offset1) & 0x00000800) 379 return ata_pci_status(dev); 380 else 381 return 0; 382} 383 384static void 385ata_sii_reset(device_t dev) 386{ 387 if (ata_sata_phy_reset(dev)) 388 ata_generic_reset(dev); 389} 390 391static void 392ata_sii_setmode(device_t dev, int mode) 393{ 394 device_t gparent = GRANDPARENT(dev); 395 struct ata_pci_controller *ctlr = device_get_softc(gparent); 396 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 397 struct ata_device *atadev = device_get_softc(dev); 398 int rego = (ch->unit << 4) + (atadev->unit << 1); 399 int mreg = ch->unit ? 0x84 : 0x80; 400 int mask = 0x03 << (atadev->unit << 2); 401 int mval = pci_read_config(gparent, mreg, 1) & ~mask; 402 int error; 403 404 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 405 406 if (ctlr->chip->cfg2 & SII_SETCLK) { 407 if (mode > ATA_UDMA2 && (pci_read_config(gparent, 0x79, 1) & 408 (ch->unit ? 0x02 : 0x01))) { 409 ata_print_cable(dev, "controller"); 410 mode = ATA_UDMA2; 411 } 412 } 413 else 414 mode = ata_check_80pin(dev, mode); 415 416 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 417 418 if (bootverbose) 419 device_printf(dev, "%ssetting %s on %s chip\n", 420 (error) ? "FAILURE " : "", 421 ata_mode2str(mode), ctlr->chip->text); 422 if (error) 423 return; 424 425 if (mode >= ATA_UDMA0) { 426 u_int8_t udmatimings[] = { 0xf, 0xb, 0x7, 0x5, 0x3, 0x2, 0x1 }; 427 u_int8_t ureg = 0xac + rego; 428 429 pci_write_config(gparent, mreg, 430 mval | (0x03 << (atadev->unit << 2)), 1); 431 pci_write_config(gparent, ureg, 432 (pci_read_config(gparent, ureg, 1) & ~0x3f) | 433 udmatimings[mode & ATA_MODE_MASK], 1); 434 435 } 436 else if (mode >= ATA_WDMA0) { 437 u_int8_t dreg = 0xa8 + rego; 438 u_int16_t dmatimings[] = { 0x2208, 0x10c2, 0x10c1 }; 439 440 pci_write_config(gparent, mreg, 441 mval | (0x02 << (atadev->unit << 2)), 1); 442 pci_write_config(gparent, dreg, dmatimings[mode & ATA_MODE_MASK], 2); 443 444 } 445 else { 446 u_int8_t preg = 0xa4 + rego; 447 u_int16_t piotimings[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 }; 448 449 pci_write_config(gparent, mreg, 450 mval | (0x01 << (atadev->unit << 2)), 1); 451 pci_write_config(gparent, preg, piotimings[mode & ATA_MODE_MASK], 2); 452 } 453 atadev->mode = mode; 454} 455 456 457struct ata_siiprb_dma_prdentry { 458 u_int64_t addr; 459 u_int32_t count; 460 u_int32_t control; 461} __packed; 462 463#define ATA_SIIPRB_DMA_ENTRIES 125 464struct ata_siiprb_ata_command { 465 struct ata_siiprb_dma_prdentry prd[ATA_SIIPRB_DMA_ENTRIES]; 466} __packed; 467 468struct ata_siiprb_atapi_command { 469 u_int8_t ccb[16]; 470 struct ata_siiprb_dma_prdentry prd[ATA_SIIPRB_DMA_ENTRIES]; 471} __packed; 472 473struct ata_siiprb_command { 474 u_int16_t control; 475 u_int16_t protocol_override; 476 u_int32_t transfer_count; 477 u_int8_t fis[24]; 478 union { 479 struct ata_siiprb_ata_command ata; 480 struct ata_siiprb_atapi_command atapi; 481 } u; 482} __packed; 483 484static int 485ata_siiprb_ch_attach(device_t dev) 486{ 487 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 488 struct ata_channel *ch = device_get_softc(dev); 489 int offset = ch->unit * 0x2000; 490 491 ata_siiprb_dmainit(dev); 492 493 /* set the SATA resources */ 494 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 495 ch->r_io[ATA_SSTATUS].offset = 0x1f04 + offset; 496 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 497 ch->r_io[ATA_SERROR].offset = 0x1f08 + offset; 498 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 499 ch->r_io[ATA_SCONTROL].offset = 0x1f00 + offset; 500 ch->r_io[ATA_SACTIVE].res = ctlr->r_res2; 501 ch->r_io[ATA_SACTIVE].offset = 0x1f0c + offset; 502 503 ch->hw.status = ata_siiprb_status; 504 ch->hw.begin_transaction = ata_siiprb_begin_transaction; 505 ch->hw.end_transaction = ata_siiprb_end_transaction; 506 ch->hw.command = NULL; /* not used here */ 507 ch->hw.softreset = ata_siiprb_softreset; 508 ch->hw.pm_read = ata_siiprb_pm_read; 509 ch->hw.pm_write = ata_siiprb_pm_write; 510 511 return 0; 512} 513 514static int 515ata_siiprb_ch_detach(device_t dev) 516{ 517 518 ata_dmafini(dev); 519 return 0; 520} 521 522static int 523ata_siiprb_status(device_t dev) 524{ 525 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 526 struct ata_channel *ch = device_get_softc(dev); 527 u_int32_t action = ATA_INL(ctlr->r_res1, 0x0044); 528 int offset = ch->unit * 0x2000; 529 530 if (action & (1 << ch->unit)) { 531 u_int32_t istatus = ATA_INL(ctlr->r_res2, 0x1008 + offset); 532 533 /* do we have any PHY events ? */ 534 ata_sata_phy_check_events(dev); 535 536 /* clear interrupt(s) */ 537 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, istatus); 538 539 /* do we have any device action ? */ 540 return (istatus & 0x00000003); 541 } 542 return 0; 543} 544 545static int 546ata_siiprb_begin_transaction(struct ata_request *request) 547{ 548 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev)); 549 struct ata_channel *ch = device_get_softc(request->parent); 550 struct ata_siiprb_command *prb; 551 struct ata_siiprb_dma_prdentry *prd; 552 int offset = ch->unit * 0x2000; 553 u_int64_t prb_bus; 554 555 /* SOS XXX */ 556 if (request->u.ata.command == ATA_DEVICE_RESET) { 557 request->result = 0; 558 return ATA_OP_FINISHED; 559 } 560 561 /* get a piece of the workspace for this request */ 562 prb = (struct ata_siiprb_command *) 563 (ch->dma.work + (sizeof(struct ata_siiprb_command) * request->tag)); 564 565 /* clear the prb structure */ 566 bzero(prb, sizeof(struct ata_siiprb_command)); 567 568 /* setup the FIS for this request */ 569 if (!ata_request2fis_h2d(request, &prb->fis[0])) { 570 device_printf(request->dev, "setting up SATA FIS failed\n"); 571 request->result = EIO; 572 return ATA_OP_FINISHED; 573 } 574 575 /* setup transfer type */ 576 if (request->flags & ATA_R_ATAPI) { 577 struct ata_device *atadev = device_get_softc(request->dev); 578 579 bcopy(request->u.atapi.ccb, prb->u.atapi.ccb, 16); 580 if ((atadev->param.config & ATA_PROTO_MASK) == ATA_PROTO_ATAPI_12) 581 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000020); 582 else 583 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000020); 584 if (request->flags & ATA_R_READ) 585 prb->control = htole16(0x0010); 586 if (request->flags & ATA_R_WRITE) 587 prb->control = htole16(0x0020); 588 prd = &prb->u.atapi.prd[0]; 589 } 590 else 591 prd = &prb->u.ata.prd[0]; 592 593 /* if request moves data setup and load SG list */ 594 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) { 595 if (ch->dma.load(request, prd, NULL)) { 596 device_printf(request->dev, "setting up DMA failed\n"); 597 request->result = EIO; 598 return ATA_OP_FINISHED; 599 } 600 } 601 602 /* activate the prb */ 603 prb_bus = ch->dma.work_bus + 604 (sizeof(struct ata_siiprb_command) * request->tag); 605 ATA_OUTL(ctlr->r_res2, 606 0x1c00 + offset + (request->tag * sizeof(u_int64_t)), prb_bus); 607 ATA_OUTL(ctlr->r_res2, 608 0x1c04 + offset + (request->tag * sizeof(u_int64_t)), prb_bus>>32); 609 610 /* start the timeout */ 611 callout_reset(&request->callout, request->timeout * hz, 612 (timeout_t*)ata_timeout, request); 613 return ATA_OP_CONTINUES; 614} 615 616static int 617ata_siiprb_end_transaction(struct ata_request *request) 618{ 619 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev)); 620 struct ata_channel *ch = device_get_softc(request->parent); 621 struct ata_siiprb_command *prb; 622 int offset = ch->unit * 0x2000; 623 int error, timeout; 624 625 /* kill the timeout */ 626 callout_stop(&request->callout); 627 628 prb = (struct ata_siiprb_command *) 629 ((u_int8_t *)rman_get_virtual(ctlr->r_res2)+(request->tag << 7)+offset); 630 631 /* any controller errors flagged ? */ 632 if ((error = ATA_INL(ctlr->r_res2, 0x1024 + offset))) { 633 if (bootverbose) 634 printf("ata_siiprb_end_transaction %s error=%08x\n", 635 ata_cmd2str(request), error); 636 637 /* if device error status get details */ 638 if (error == 1 || error == 2) { 639 request->status = prb->fis[2]; 640 if (request->status & ATA_S_ERROR) 641 request->error = prb->fis[3]; 642 } 643 644 /* SOS XXX handle other controller errors here */ 645 646 /* initialize port */ 647 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000004); 648 649 /* poll for port ready */ 650 for (timeout = 0; timeout < 1000; timeout++) { 651 DELAY(1000); 652 if (ATA_INL(ctlr->r_res2, 0x1008 + offset) & 0x00040000) 653 break; 654 } 655 if (bootverbose) { 656 if (timeout >= 1000) 657 device_printf(ch->dev, "port initialize timeout\n"); 658 else 659 device_printf(ch->dev, "port initialize time=%dms\n", timeout); 660 } 661 } 662 663 /* on control commands read back registers to the request struct */ 664 if (request->flags & ATA_R_CONTROL) { 665 struct ata_device *atadev = device_get_softc(request->dev); 666 667 request->u.ata.count = prb->fis[12] | ((u_int16_t)prb->fis[13] << 8); 668 request->u.ata.lba = prb->fis[4] | ((u_int64_t)prb->fis[5] << 8) | 669 ((u_int64_t)prb->fis[6] << 16); 670 if (atadev->flags & ATA_D_48BIT_ACTIVE) 671 request->u.ata.lba |= ((u_int64_t)prb->fis[8] << 24) | 672 ((u_int64_t)prb->fis[9] << 32) | 673 ((u_int64_t)prb->fis[10] << 40); 674 else 675 request->u.ata.lba |= ((u_int64_t)(prb->fis[7] & 0x0f) << 24); 676 } 677 678 /* update progress */ 679 if (!(request->status & ATA_S_ERROR) && !(request->flags & ATA_R_TIMEOUT)) { 680 if (request->flags & ATA_R_READ) 681 request->donecount = prb->transfer_count; 682 else 683 request->donecount = request->bytecount; 684 } 685 686 /* release SG list etc */ 687 ch->dma.unload(request); 688 689 return ATA_OP_FINISHED; 690} 691 692static int 693ata_siiprb_issue_cmd(device_t dev) 694{ 695 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 696 struct ata_channel *ch = device_get_softc(dev); 697 u_int64_t prb_bus = ch->dma.work_bus; 698 u_int32_t status; 699 int offset = ch->unit * 0x2000; 700 int timeout; 701 702 /* issue command to chip */ 703 ATA_OUTL(ctlr->r_res2, 0x1c00 + offset, prb_bus); 704 ATA_OUTL(ctlr->r_res2, 0x1c04 + offset, prb_bus >> 32); 705 706 /* poll for command finished */ 707 for (timeout = 0; timeout < 10000; timeout++) { 708 DELAY(1000); 709 if ((status = ATA_INL(ctlr->r_res2, 0x1008 + offset)) & 0x00010000) 710 break; 711 } 712 // SOS XXX ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x00010000); 713 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x08ff08ff); 714 715 if (timeout >= 1000) 716 return EIO; 717 718 if (bootverbose) 719 device_printf(dev, "siiprb_issue_cmd time=%dms status=%08x\n", 720 timeout, status); 721 return 0; 722} 723 724static int 725ata_siiprb_pm_read(device_t dev, int port, int reg, u_int32_t *result) 726{ 727 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 728 struct ata_channel *ch = device_get_softc(dev); 729 struct ata_siiprb_command *prb = (struct ata_siiprb_command *)ch->dma.work; 730 int offset = ch->unit * 0x2000; 731 732 bzero(prb, sizeof(struct ata_siiprb_command)); 733 prb->fis[0] = 0x27; /* host to device */ 734 prb->fis[1] = 0x8f; /* command FIS to PM port */ 735 prb->fis[2] = ATA_READ_PM; 736 prb->fis[3] = reg; 737 prb->fis[7] = port; 738 if (ata_siiprb_issue_cmd(dev)) { 739 device_printf(dev, "error reading PM port\n"); 740 return EIO; 741 } 742 prb = (struct ata_siiprb_command *) 743 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset); 744 *result = prb->fis[12]|(prb->fis[4]<<8)|(prb->fis[5]<<16)|(prb->fis[6]<<24); 745 return 0; 746} 747 748static int 749ata_siiprb_pm_write(device_t dev, int port, int reg, u_int32_t value) 750{ 751 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 752 struct ata_channel *ch = device_get_softc(dev); 753 struct ata_siiprb_command *prb = (struct ata_siiprb_command *)ch->dma.work; 754 int offset = ch->unit * 0x2000; 755 756 bzero(prb, sizeof(struct ata_siiprb_command)); 757 prb->fis[0] = 0x27; /* host to device */ 758 prb->fis[1] = 0x8f; /* command FIS to PM port */ 759 prb->fis[2] = ATA_WRITE_PM; 760 prb->fis[3] = reg; 761 prb->fis[7] = port; 762 prb->fis[12] = value & 0xff; 763 prb->fis[4] = (value >> 8) & 0xff;; 764 prb->fis[5] = (value >> 16) & 0xff;; 765 prb->fis[6] = (value >> 24) & 0xff;; 766 if (ata_siiprb_issue_cmd(dev)) { 767 device_printf(dev, "error writing PM port\n"); 768 return ATA_E_ABORT; 769 } 770 prb = (struct ata_siiprb_command *) 771 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset); 772 return prb->fis[3]; 773} 774 775static u_int32_t 776ata_siiprb_softreset(device_t dev, int port) 777{ 778 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 779 struct ata_channel *ch = device_get_softc(dev); 780 struct ata_siiprb_command *prb = (struct ata_siiprb_command *)ch->dma.work; 781 u_int32_t signature; 782 int offset = ch->unit * 0x2000; 783 784 /* setup the workspace for a soft reset command */ 785 bzero(prb, sizeof(struct ata_siiprb_command)); 786 prb->control = htole16(0x0080); 787 prb->fis[1] = port & 0x0f; 788 789 /* issue soft reset */ 790 if (ata_siiprb_issue_cmd(dev)) 791 return -1; 792 793 ata_udelay(150000); 794 795 /* get possible signature */ 796 prb = (struct ata_siiprb_command *) 797 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset); 798 signature=prb->fis[12]|(prb->fis[4]<<8)|(prb->fis[5]<<16)|(prb->fis[6]<<24); 799 800 /* clear error bits/interrupt */ 801 ATA_IDX_OUTL(ch, ATA_SERROR, 0xffffffff); 802 803 return signature; 804} 805 806static void 807ata_siiprb_reset(device_t dev) 808{ 809 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 810 struct ata_channel *ch = device_get_softc(dev); 811 int offset = ch->unit * 0x2000; 812 u_int32_t status, signature; 813 int timeout; 814 815 /* disable interrupts */ 816 ATA_OUTL(ctlr->r_res2, 0x1014 + offset, 0x000000ff); 817 818 /* reset channel HW */ 819 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000001); 820 DELAY(1000); 821 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000001); 822 DELAY(10000); 823 824 /* poll for channel ready */ 825 for (timeout = 0; timeout < 1000; timeout++) { 826 if ((status = ATA_INL(ctlr->r_res2, 0x1008 + offset)) & 0x00040000) 827 break; 828 DELAY(1000); 829 } 830 831 if (bootverbose) { 832 if (timeout >= 1000) 833 device_printf(dev, "channel HW reset timeout\n"); 834 else 835 device_printf(dev, "channel HW reset time=%dms\n", timeout); 836 } 837 838 /* reset phy */ 839 if (!ata_sata_phy_reset(dev)) { 840 if (bootverbose) 841 device_printf(dev, "phy reset found no device\n"); 842 ch->devices = 0; 843 goto finish; 844 } 845 846 /* issue soft reset */ 847 signature = ata_siiprb_softreset(dev, ATA_PM); 848 if (bootverbose) 849 device_printf(dev, "SIGNATURE=%08x\n", signature); 850 851 /* figure out whats there */ 852 switch (signature) { 853 case 0x00000101: 854 ch->devices = ATA_ATA_MASTER; 855 break; 856 case 0x96690101: 857 ch->devices = ATA_PORTMULTIPLIER; 858 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x2000); /* enable PM support */ 859 //SOS XXX need to clear all PM status and interrupts!!!! 860 ata_pm_identify(dev); 861 break; 862 case 0xeb140101: 863 ch->devices = ATA_ATAPI_MASTER; 864 break; 865 default: 866 ch->devices = 0; 867 } 868 if (bootverbose) 869 device_printf(dev, "siiprb_reset devices=%08x\n", ch->devices); 870 871finish: 872 /* clear interrupt(s) */ 873 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x000008ff); 874 875 /* require explicit interrupt ack */ 876 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000008); 877 878 /* 64bit mode */ 879 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000400); 880 881 /* enable interrupts wanted */ 882 ATA_OUTL(ctlr->r_res2, 0x1010 + offset, 0x000000ff); 883} 884 885static void 886ata_siiprb_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 887{ 888 struct ata_dmasetprd_args *args = xsc; 889 struct ata_siiprb_dma_prdentry *prd = args->dmatab; 890 int i; 891 892 if ((args->error = error)) 893 return; 894 895 for (i = 0; i < nsegs; i++) { 896 prd[i].addr = htole64(segs[i].ds_addr); 897 prd[i].count = htole32(segs[i].ds_len); 898 } 899 prd[i - 1].control = htole32(ATA_DMA_EOT); 900 KASSERT(nsegs <= ATA_SIIPRB_DMA_ENTRIES,("too many DMA segment entries\n")); 901 args->nsegs = nsegs; 902} 903 904static void 905ata_siiprb_dmainit(device_t dev) 906{ 907 struct ata_channel *ch = device_get_softc(dev); 908 909 ata_dmainit(dev); 910 /* note start and stop are not used here */ 911 ch->dma.setprd = ata_siiprb_dmasetprd; 912 ch->dma.max_address = BUS_SPACE_MAXADDR; 913} 914 915ATA_DECLARE_DRIVER(ata_sii); 916