ata-siliconimage.c revision 242156
1183724Ssos/*- 2230132Suqs * Copyright (c) 1998 - 2008 S��ren Schmidt <sos@FreeBSD.org> 3183724Ssos * All rights reserved. 4183724Ssos * 5183724Ssos * Redistribution and use in source and binary forms, with or without 6183724Ssos * modification, are permitted provided that the following conditions 7183724Ssos * are met: 8183724Ssos * 1. Redistributions of source code must retain the above copyright 9183724Ssos * notice, this list of conditions and the following disclaimer, 10183724Ssos * without modification, immediately at the beginning of the file. 11183724Ssos * 2. Redistributions in binary form must reproduce the above copyright 12183724Ssos * notice, this list of conditions and the following disclaimer in the 13183724Ssos * documentation and/or other materials provided with the distribution. 14183724Ssos * 15183724Ssos * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16183724Ssos * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17183724Ssos * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18183724Ssos * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19183724Ssos * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20183724Ssos * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21183724Ssos * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22183724Ssos * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23183724Ssos * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24183724Ssos * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25183724Ssos */ 26183724Ssos 27183724Ssos#include <sys/cdefs.h> 28183724Ssos__FBSDID("$FreeBSD: head/sys/dev/ata/chipsets/ata-siliconimage.c 242156 2012-10-26 20:03:08Z mav $"); 29183724Ssos 30183724Ssos#include "opt_ata.h" 31183724Ssos#include <sys/param.h> 32183724Ssos#include <sys/module.h> 33183724Ssos#include <sys/systm.h> 34183724Ssos#include <sys/kernel.h> 35183724Ssos#include <sys/ata.h> 36183724Ssos#include <sys/bus.h> 37183724Ssos#include <sys/endian.h> 38183724Ssos#include <sys/malloc.h> 39183724Ssos#include <sys/lock.h> 40183724Ssos#include <sys/mutex.h> 41183724Ssos#include <sys/sema.h> 42183724Ssos#include <sys/taskqueue.h> 43183724Ssos#include <vm/uma.h> 44183724Ssos#include <machine/stdarg.h> 45183724Ssos#include <machine/resource.h> 46183724Ssos#include <machine/bus.h> 47183724Ssos#include <sys/rman.h> 48183724Ssos#include <dev/pci/pcivar.h> 49183724Ssos#include <dev/pci/pcireg.h> 50183724Ssos#include <dev/ata/ata-all.h> 51183724Ssos#include <dev/ata/ata-pci.h> 52183724Ssos#include <ata_if.h> 53183724Ssos 54183724Ssos/* local prototypes */ 55188765Smavstatic int ata_cmd_ch_attach(device_t dev); 56183724Ssosstatic int ata_cmd_status(device_t dev); 57200171Smavstatic int ata_cmd_setmode(device_t dev, int target, int mode); 58188765Smavstatic int ata_sii_ch_attach(device_t dev); 59188769Smavstatic int ata_sii_ch_detach(device_t dev); 60183724Ssosstatic int ata_sii_status(device_t dev); 61183724Ssosstatic void ata_sii_reset(device_t dev); 62200171Smavstatic int ata_sii_setmode(device_t dev, int target, int mode); 63188765Smavstatic int ata_siiprb_ch_attach(device_t dev); 64188769Smavstatic int ata_siiprb_ch_detach(device_t dev); 65183724Ssosstatic int ata_siiprb_status(device_t dev); 66183724Ssosstatic int ata_siiprb_begin_transaction(struct ata_request *request); 67183724Ssosstatic int ata_siiprb_end_transaction(struct ata_request *request); 68183724Ssosstatic int ata_siiprb_pm_read(device_t dev, int port, int reg, u_int32_t *result); 69183724Ssosstatic int ata_siiprb_pm_write(device_t dev, int port, int reg, u_int32_t result); 70183724Ssosstatic u_int32_t ata_siiprb_softreset(device_t dev, int port); 71183724Ssosstatic void ata_siiprb_reset(device_t dev); 72183724Ssosstatic void ata_siiprb_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 73183724Ssosstatic void ata_siiprb_dmainit(device_t dev); 74183724Ssos 75183724Ssos/* misc defines */ 76183724Ssos#define SII_MEMIO 1 77183724Ssos#define SII_PRBIO 2 78183724Ssos#define SII_INTR 0x01 79183724Ssos#define SII_SETCLK 0x02 80183724Ssos#define SII_BUG 0x04 81183724Ssos#define SII_4CH 0x08 82183724Ssos 83183724Ssos/* 84183724Ssos * Silicon Image Inc. (SiI) (former CMD) chipset support functions 85183724Ssos */ 86183724Ssosstatic int 87183724Ssosata_sii_probe(device_t dev) 88183724Ssos{ 89183724Ssos struct ata_pci_controller *ctlr = device_get_softc(dev); 90233282Smarius static const struct ata_chip_id const ids[] = 91183724Ssos {{ ATA_SII3114, 0x00, SII_MEMIO, SII_4CH, ATA_SA150, "3114" }, 92183724Ssos { ATA_SII3512, 0x02, SII_MEMIO, 0, ATA_SA150, "3512" }, 93183724Ssos { ATA_SII3112, 0x02, SII_MEMIO, 0, ATA_SA150, "3112" }, 94183724Ssos { ATA_SII3112_1, 0x02, SII_MEMIO, 0, ATA_SA150, "3112" }, 95183724Ssos { ATA_SII3512, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "3512" }, 96183724Ssos { ATA_SII3112, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "3112" }, 97183724Ssos { ATA_SII3112_1, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "3112" }, 98183724Ssos { ATA_SII3124, 0x00, SII_PRBIO, SII_4CH, ATA_SA300, "3124" }, 99183724Ssos { ATA_SII3132, 0x00, SII_PRBIO, 0, ATA_SA300, "3132" }, 100183724Ssos { ATA_SII3132_1, 0x00, SII_PRBIO, 0, ATA_SA300, "3132" }, 101191897Smav { ATA_SII3132_2, 0x00, SII_PRBIO, 0, ATA_SA300, "3132" }, 102183724Ssos { ATA_SII0680, 0x00, SII_MEMIO, SII_SETCLK, ATA_UDMA6, "680" }, 103183724Ssos { ATA_CMD649, 0x00, 0, SII_INTR, ATA_UDMA5, "(CMD) 649" }, 104183724Ssos { ATA_CMD648, 0x00, 0, SII_INTR, ATA_UDMA4, "(CMD) 648" }, 105183724Ssos { ATA_CMD646, 0x07, 0, 0, ATA_UDMA2, "(CMD) 646U2" }, 106183724Ssos { ATA_CMD646, 0x00, 0, 0, ATA_WDMA2, "(CMD) 646" }, 107183724Ssos { 0, 0, 0, 0, 0, 0}}; 108183724Ssos 109183724Ssos if (pci_get_vendor(dev) != ATA_SILICON_IMAGE_ID) 110183724Ssos return ENXIO; 111183724Ssos 112183724Ssos if (!(ctlr->chip = ata_match_chip(dev, ids))) 113183724Ssos return ENXIO; 114183724Ssos 115183724Ssos ata_set_desc(dev); 116183724Ssos ctlr->chipinit = ata_sii_chipinit; 117194893Smav return (BUS_PROBE_DEFAULT); 118183724Ssos} 119183724Ssos 120183724Ssosint 121183724Ssosata_sii_chipinit(device_t dev) 122183724Ssos{ 123183724Ssos struct ata_pci_controller *ctlr = device_get_softc(dev); 124183724Ssos 125183724Ssos if (ata_setup_interrupt(dev, ata_generic_intr)) 126183724Ssos return ENXIO; 127183724Ssos 128183724Ssos switch (ctlr->chip->cfg1) { 129183724Ssos case SII_PRBIO: 130183724Ssos ctlr->r_type1 = SYS_RES_MEMORY; 131183724Ssos ctlr->r_rid1 = PCIR_BAR(0); 132183724Ssos if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1, 133183724Ssos &ctlr->r_rid1, RF_ACTIVE))) 134183724Ssos return ENXIO; 135183724Ssos 136183724Ssos ctlr->r_rid2 = PCIR_BAR(2); 137183724Ssos ctlr->r_type2 = SYS_RES_MEMORY; 138183724Ssos if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 139183724Ssos &ctlr->r_rid2, RF_ACTIVE))){ 140183724Ssos bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1,ctlr->r_res1); 141183724Ssos return ENXIO; 142183724Ssos } 143227000Smarius#ifdef __sparc64__ 144227000Smarius if (!bus_space_map(rman_get_bustag(ctlr->r_res2), 145227000Smarius rman_get_bushandle(ctlr->r_res2), rman_get_size(ctlr->r_res2), 146227000Smarius BUS_SPACE_MAP_LINEAR, NULL)) { 147227000Smarius bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1, 148227000Smarius ctlr->r_res1); 149227000Smarius bus_release_resource(dev, ctlr->r_type2, ctlr->r_rid2, 150227000Smarius ctlr->r_res2); 151227000Smarius return (ENXIO); 152227000Smarius } 153227000Smarius#endif 154188765Smav ctlr->ch_attach = ata_siiprb_ch_attach; 155188769Smav ctlr->ch_detach = ata_siiprb_ch_detach; 156183724Ssos ctlr->reset = ata_siiprb_reset; 157183724Ssos ctlr->setmode = ata_sata_setmode; 158200171Smav ctlr->getrev = ata_sata_getrev; 159183724Ssos ctlr->channels = (ctlr->chip->cfg2 == SII_4CH) ? 4 : 2; 160183724Ssos 161183724Ssos /* reset controller */ 162183724Ssos ATA_OUTL(ctlr->r_res1, 0x0040, 0x80000000); 163183724Ssos DELAY(10000); 164183724Ssos ATA_OUTL(ctlr->r_res1, 0x0040, 0x0000000f); 165183724Ssos break; 166183724Ssos 167183724Ssos case SII_MEMIO: 168183724Ssos ctlr->r_type2 = SYS_RES_MEMORY; 169183724Ssos ctlr->r_rid2 = PCIR_BAR(5); 170183724Ssos if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 171183724Ssos &ctlr->r_rid2, RF_ACTIVE))){ 172183724Ssos if (ctlr->chip->chipid != ATA_SII0680 || 173183724Ssos (pci_read_config(dev, 0x8a, 1) & 1)) 174183724Ssos return ENXIO; 175183724Ssos } 176183724Ssos 177183724Ssos if (ctlr->chip->cfg2 & SII_SETCLK) { 178183724Ssos if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10) 179183724Ssos pci_write_config(dev, 0x8a, 180183724Ssos (pci_read_config(dev, 0x8a, 1) & 0xcf)|0x10,1); 181183724Ssos if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10) 182183724Ssos device_printf(dev, "%s could not set ATA133 clock\n", 183183724Ssos ctlr->chip->text); 184183724Ssos } 185183724Ssos 186183724Ssos /* if we have 4 channels enable the second set */ 187183724Ssos if (ctlr->chip->cfg2 & SII_4CH) { 188183724Ssos ATA_OUTL(ctlr->r_res2, 0x0200, 0x00000002); 189183724Ssos ctlr->channels = 4; 190183724Ssos } 191183724Ssos 192183724Ssos /* dont block interrupts from any channel */ 193183724Ssos pci_write_config(dev, 0x48, 194183724Ssos (pci_read_config(dev, 0x48, 4) & ~0x03c00000), 4); 195183724Ssos 196183724Ssos /* enable PCI interrupt as BIOS might not */ 197183724Ssos pci_write_config(dev, 0x8a, (pci_read_config(dev, 0x8a, 1) & 0x3f), 1); 198183724Ssos 199188769Smav if (ctlr->r_res2) { 200188765Smav ctlr->ch_attach = ata_sii_ch_attach; 201188769Smav ctlr->ch_detach = ata_sii_ch_detach; 202188769Smav } 203183724Ssos 204183724Ssos if (ctlr->chip->max_dma >= ATA_SA150) { 205183724Ssos ctlr->reset = ata_sii_reset; 206183724Ssos ctlr->setmode = ata_sata_setmode; 207200171Smav ctlr->getrev = ata_sata_getrev; 208183724Ssos } 209183724Ssos else 210183724Ssos ctlr->setmode = ata_sii_setmode; 211183724Ssos break; 212183724Ssos 213183724Ssos default: 214183724Ssos if ((pci_read_config(dev, 0x51, 1) & 0x08) != 0x08) { 215183724Ssos device_printf(dev, "HW has secondary channel disabled\n"); 216183724Ssos ctlr->channels = 1; 217183724Ssos } 218183724Ssos 219183724Ssos /* enable interrupt as BIOS might not */ 220183724Ssos pci_write_config(dev, 0x71, 0x01, 1); 221183724Ssos 222188765Smav ctlr->ch_attach = ata_cmd_ch_attach; 223188769Smav ctlr->ch_detach = ata_pci_ch_detach; 224183724Ssos ctlr->setmode = ata_cmd_setmode; 225183724Ssos break; 226183724Ssos } 227183724Ssos return 0; 228183724Ssos} 229183724Ssos 230183724Ssosstatic int 231188765Smavata_cmd_ch_attach(device_t dev) 232183724Ssos{ 233183724Ssos struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 234183724Ssos struct ata_channel *ch = device_get_softc(dev); 235183724Ssos 236183724Ssos /* setup the usual register normal pci style */ 237188765Smav if (ata_pci_ch_attach(dev)) 238183724Ssos return ENXIO; 239183724Ssos 240183724Ssos if (ctlr->chip->cfg2 & SII_INTR) 241183724Ssos ch->hw.status = ata_cmd_status; 242183724Ssos 243230627Smarius#ifdef ATA_CAM 244230627Smarius ch->flags |= ATA_NO_ATAPI_DMA; 245230627Smarius#endif 246230627Smarius 247183724Ssos return 0; 248183724Ssos} 249183724Ssos 250183724Ssosstatic int 251183724Ssosata_cmd_status(device_t dev) 252183724Ssos{ 253183724Ssos struct ata_channel *ch = device_get_softc(dev); 254183724Ssos u_int8_t reg71; 255183724Ssos 256183724Ssos if (((reg71 = pci_read_config(device_get_parent(dev), 0x71, 1)) & 257183724Ssos (ch->unit ? 0x08 : 0x04))) { 258183724Ssos pci_write_config(device_get_parent(dev), 0x71, 259183724Ssos reg71 & ~(ch->unit ? 0x04 : 0x08), 1); 260183724Ssos return ata_pci_status(dev); 261183724Ssos } 262183724Ssos return 0; 263183724Ssos} 264183724Ssos 265200171Smavstatic int 266200171Smavata_cmd_setmode(device_t dev, int target, int mode) 267183724Ssos{ 268200171Smav device_t parent = device_get_parent(dev); 269200171Smav struct ata_pci_controller *ctlr = device_get_softc(parent); 270200171Smav struct ata_channel *ch = device_get_softc(dev); 271200171Smav int devno = (ch->unit << 1) + target; 272183724Ssos int treg = 0x54 + ((devno < 3) ? (devno << 1) : 7); 273183724Ssos int ureg = ch->unit ? 0x7b : 0x73; 274200171Smav int piomode; 275233282Smarius static const uint8_t piotimings[] = 276233282Smarius { 0xa9, 0x57, 0x44, 0x32, 0x3f, 0x87, 0x32, 0x3f }; 277233282Smarius static const uint8_t udmatimings[][2] = 278233282Smarius { { 0x31, 0xc2 }, { 0x21, 0x82 }, { 0x11, 0x42 }, 279233282Smarius { 0x25, 0x8a }, { 0x15, 0x4a }, { 0x05, 0x0a } }; 280183724Ssos 281200171Smav mode = min(mode, ctlr->chip->max_dma); 282200171Smav if (mode >= ATA_UDMA0) { 283200171Smav u_int8_t umode = pci_read_config(parent, ureg, 1); 284183724Ssos 285200171Smav umode &= ~(target == 0 ? 0x35 : 0xca); 286200171Smav umode |= udmatimings[mode & ATA_MODE_MASK][target]; 287200171Smav pci_write_config(parent, ureg, umode, 1); 288200171Smav piomode = ATA_PIO4; 289200171Smav } else { 290200171Smav pci_write_config(parent, ureg, 291200171Smav pci_read_config(parent, ureg, 1) & 292200171Smav ~(target == 0 ? 0x35 : 0xca), 1); 293200171Smav piomode = mode; 294183724Ssos } 295200171Smav pci_write_config(parent, treg, piotimings[ata_mode2idx(piomode)], 1); 296200171Smav return (mode); 297183724Ssos} 298183724Ssos 299183724Ssosstatic int 300188765Smavata_sii_ch_attach(device_t dev) 301183724Ssos{ 302183724Ssos struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 303183724Ssos struct ata_channel *ch = device_get_softc(dev); 304183724Ssos int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2); 305183724Ssos int i; 306183724Ssos 307183724Ssos for (i = ATA_DATA; i <= ATA_COMMAND; i++) { 308183724Ssos ch->r_io[i].res = ctlr->r_res2; 309183724Ssos ch->r_io[i].offset = 0x80 + i + (unit01 << 6) + (unit10 << 8); 310183724Ssos } 311183724Ssos ch->r_io[ATA_CONTROL].res = ctlr->r_res2; 312183724Ssos ch->r_io[ATA_CONTROL].offset = 0x8a + (unit01 << 6) + (unit10 << 8); 313183724Ssos ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2; 314183724Ssos ata_default_registers(dev); 315183724Ssos 316183724Ssos ch->r_io[ATA_BMCMD_PORT].res = ctlr->r_res2; 317183724Ssos ch->r_io[ATA_BMCMD_PORT].offset = 0x00 + (unit01 << 3) + (unit10 << 8); 318183724Ssos ch->r_io[ATA_BMSTAT_PORT].res = ctlr->r_res2; 319183724Ssos ch->r_io[ATA_BMSTAT_PORT].offset = 0x02 + (unit01 << 3) + (unit10 << 8); 320183724Ssos ch->r_io[ATA_BMDTP_PORT].res = ctlr->r_res2; 321183724Ssos ch->r_io[ATA_BMDTP_PORT].offset = 0x04 + (unit01 << 3) + (unit10 << 8); 322183724Ssos 323183724Ssos if (ctlr->chip->max_dma >= ATA_SA150) { 324183724Ssos ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 325183724Ssos ch->r_io[ATA_SSTATUS].offset = 0x104 + (unit01 << 7) + (unit10 << 8); 326183724Ssos ch->r_io[ATA_SERROR].res = ctlr->r_res2; 327183724Ssos ch->r_io[ATA_SERROR].offset = 0x108 + (unit01 << 7) + (unit10 << 8); 328183724Ssos ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 329183724Ssos ch->r_io[ATA_SCONTROL].offset = 0x100 + (unit01 << 7) + (unit10 << 8); 330183724Ssos ch->flags |= ATA_NO_SLAVE; 331200171Smav ch->flags |= ATA_SATA; 332212145Smav ch->flags |= ATA_KNOWN_PRESENCE; 333183724Ssos 334183724Ssos /* enable PHY state change interrupt */ 335183724Ssos ATA_OUTL(ctlr->r_res2, 0x148 + (unit01 << 7) + (unit10 << 8),(1 << 16)); 336183724Ssos } 337183724Ssos 338183724Ssos if (ctlr->chip->cfg2 & SII_BUG) { 339183724Ssos /* work around errata in early chips */ 340183724Ssos ch->dma.boundary = 8192; 341183724Ssos ch->dma.segsize = 15 * DEV_BSIZE; 342183724Ssos } 343183724Ssos 344183724Ssos ata_pci_hw(dev); 345183724Ssos ch->hw.status = ata_sii_status; 346200171Smav if (ctlr->chip->cfg2 & SII_SETCLK) 347200171Smav ch->flags |= ATA_CHECKS_CABLE; 348216013Smarius 349216013Smarius ata_pci_dmainit(dev); 350216013Smarius 351183724Ssos return 0; 352183724Ssos} 353183724Ssos 354183724Ssosstatic int 355188769Smavata_sii_ch_detach(device_t dev) 356188769Smav{ 357188769Smav 358188769Smav ata_pci_dmafini(dev); 359188769Smav return (0); 360188769Smav} 361188769Smav 362188769Smavstatic int 363183724Ssosata_sii_status(device_t dev) 364183724Ssos{ 365183724Ssos struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 366183724Ssos struct ata_channel *ch = device_get_softc(dev); 367183724Ssos int offset0 = ((ch->unit & 1) << 3) + ((ch->unit & 2) << 8); 368183724Ssos int offset1 = ((ch->unit & 1) << 6) + ((ch->unit & 2) << 8); 369183724Ssos 370183724Ssos /* do we have any PHY events ? */ 371183724Ssos if (ctlr->chip->max_dma >= ATA_SA150 && 372183724Ssos (ATA_INL(ctlr->r_res2, 0x10 + offset0) & 0x00000010)) 373214016Smav ata_sata_phy_check_events(dev, -1); 374183724Ssos 375183724Ssos if (ATA_INL(ctlr->r_res2, 0xa0 + offset1) & 0x00000800) 376183724Ssos return ata_pci_status(dev); 377183724Ssos else 378183724Ssos return 0; 379183724Ssos} 380183724Ssos 381183724Ssosstatic void 382183724Ssosata_sii_reset(device_t dev) 383183724Ssos{ 384212146Smav struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 385209884Smav struct ata_channel *ch = device_get_softc(dev); 386212146Smav int offset = ((ch->unit & 1) << 7) + ((ch->unit & 2) << 8); 387212146Smav uint32_t val; 388209884Smav 389212146Smav /* Apply R_ERR on DMA activate FIS errata workaround. */ 390212146Smav val = ATA_INL(ctlr->r_res2, 0x14c + offset); 391212146Smav if ((val & 0x3) == 0x1) 392212146Smav ATA_OUTL(ctlr->r_res2, 0x14c + offset, val & ~0x3); 393212146Smav 394190581Smav if (ata_sata_phy_reset(dev, -1, 1)) 395183724Ssos ata_generic_reset(dev); 396209884Smav else 397209884Smav ch->devices = 0; 398183724Ssos} 399183724Ssos 400200171Smavstatic int 401200171Smavata_sii_setmode(device_t dev, int target, int mode) 402183724Ssos{ 403200171Smav device_t parent = device_get_parent(dev); 404200171Smav struct ata_pci_controller *ctlr = device_get_softc(parent); 405200171Smav struct ata_channel *ch = device_get_softc(dev); 406200171Smav int rego = (ch->unit << 4) + (target << 1); 407200171Smav int mreg = ch->unit ? 0x84 : 0x80; 408200171Smav int mask = 0x03 << (target << 2); 409200171Smav int mval = pci_read_config(parent, mreg, 1) & ~mask; 410200171Smav int piomode; 411200171Smav u_int8_t preg = 0xa4 + rego; 412200171Smav u_int8_t dreg = 0xa8 + rego; 413200171Smav u_int8_t ureg = 0xac + rego; 414233282Smarius static const uint16_t piotimings[] = 415233282Smarius { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 }; 416233282Smarius static const uint16_t dmatimings[] = { 0x2208, 0x10c2, 0x10c1 }; 417233282Smarius static const uint8_t udmatimings[] = 418233282Smarius { 0xf, 0xb, 0x7, 0x5, 0x3, 0x2, 0x1 }; 419183724Ssos 420200171Smav mode = min(mode, ctlr->chip->max_dma); 421183724Ssos 422200171Smav if (ctlr->chip->cfg2 & SII_SETCLK) { 423209872Smav if (ata_dma_check_80pin && mode > ATA_UDMA2 && 424209872Smav (pci_read_config(parent, 0x79, 1) & 425183724Ssos (ch->unit ? 0x02 : 0x01))) { 426200171Smav ata_print_cable(dev, "controller"); 427200171Smav mode = ATA_UDMA2; 428200171Smav } 429183724Ssos } 430200171Smav if (mode >= ATA_UDMA0) { 431200171Smav pci_write_config(parent, mreg, 432200171Smav mval | (0x03 << (target << 2)), 1); 433200171Smav pci_write_config(parent, ureg, 434200171Smav (pci_read_config(parent, ureg, 1) & ~0x3f) | 435183724Ssos udmatimings[mode & ATA_MODE_MASK], 1); 436200171Smav piomode = ATA_PIO4; 437200171Smav } else if (mode >= ATA_WDMA0) { 438200171Smav pci_write_config(parent, mreg, 439200171Smav mval | (0x02 << (target << 2)), 1); 440200171Smav pci_write_config(parent, dreg, dmatimings[mode & ATA_MODE_MASK], 2); 441200171Smav piomode = (mode == ATA_WDMA0) ? ATA_PIO0 : 442200171Smav (mode == ATA_WDMA1) ? ATA_PIO3 : ATA_PIO4; 443200171Smav } else { 444200171Smav pci_write_config(parent, mreg, 445200171Smav mval | (0x01 << (target << 2)), 1); 446200171Smav piomode = mode; 447200171Smav } 448200171Smav pci_write_config(parent, preg, piotimings[ata_mode2idx(piomode)], 2); 449200171Smav return (mode); 450183724Ssos} 451183724Ssos 452183724Ssosstruct ata_siiprb_dma_prdentry { 453183724Ssos u_int64_t addr; 454183724Ssos u_int32_t count; 455183724Ssos u_int32_t control; 456183724Ssos} __packed; 457183724Ssos 458198717Smav#define ATA_SIIPRB_DMA_ENTRIES 129 459183724Ssosstruct ata_siiprb_ata_command { 460183724Ssos struct ata_siiprb_dma_prdentry prd[ATA_SIIPRB_DMA_ENTRIES]; 461183724Ssos} __packed; 462183724Ssos 463183724Ssosstruct ata_siiprb_atapi_command { 464183724Ssos u_int8_t ccb[16]; 465183724Ssos struct ata_siiprb_dma_prdentry prd[ATA_SIIPRB_DMA_ENTRIES]; 466183724Ssos} __packed; 467183724Ssos 468183724Ssosstruct ata_siiprb_command { 469183724Ssos u_int16_t control; 470183724Ssos u_int16_t protocol_override; 471183724Ssos u_int32_t transfer_count; 472183724Ssos u_int8_t fis[24]; 473183724Ssos union { 474183724Ssos struct ata_siiprb_ata_command ata; 475183724Ssos struct ata_siiprb_atapi_command atapi; 476183724Ssos } u; 477183724Ssos} __packed; 478183724Ssos 479183724Ssosstatic int 480188765Smavata_siiprb_ch_attach(device_t dev) 481183724Ssos{ 482183724Ssos struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 483183724Ssos struct ata_channel *ch = device_get_softc(dev); 484183724Ssos int offset = ch->unit * 0x2000; 485183724Ssos 486188765Smav ata_siiprb_dmainit(dev); 487188765Smav 488183724Ssos /* set the SATA resources */ 489183724Ssos ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 490183724Ssos ch->r_io[ATA_SSTATUS].offset = 0x1f04 + offset; 491183724Ssos ch->r_io[ATA_SERROR].res = ctlr->r_res2; 492183724Ssos ch->r_io[ATA_SERROR].offset = 0x1f08 + offset; 493183724Ssos ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 494183724Ssos ch->r_io[ATA_SCONTROL].offset = 0x1f00 + offset; 495183724Ssos ch->r_io[ATA_SACTIVE].res = ctlr->r_res2; 496183724Ssos ch->r_io[ATA_SACTIVE].offset = 0x1f0c + offset; 497183724Ssos 498183724Ssos ch->hw.status = ata_siiprb_status; 499183724Ssos ch->hw.begin_transaction = ata_siiprb_begin_transaction; 500183724Ssos ch->hw.end_transaction = ata_siiprb_end_transaction; 501183724Ssos ch->hw.command = NULL; /* not used here */ 502183724Ssos ch->hw.softreset = ata_siiprb_softreset; 503183724Ssos ch->hw.pm_read = ata_siiprb_pm_read; 504183724Ssos ch->hw.pm_write = ata_siiprb_pm_write; 505203525Smav ch->flags |= ATA_NO_SLAVE; 506203525Smav ch->flags |= ATA_SATA; 507183724Ssos return 0; 508183724Ssos} 509183724Ssos 510183724Ssosstatic int 511188769Smavata_siiprb_ch_detach(device_t dev) 512188769Smav{ 513219338Smarius struct ata_channel *ch = device_get_softc(dev); 514188769Smav 515219338Smarius if (ch->dma.work_tag && ch->dma.work_map) 516219338Smarius bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, 517219338Smarius BUS_DMASYNC_POSTWRITE); 518188769Smav ata_dmafini(dev); 519188769Smav return 0; 520188769Smav} 521188769Smav 522188769Smavstatic int 523183724Ssosata_siiprb_status(device_t dev) 524183724Ssos{ 525183724Ssos struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 526183724Ssos struct ata_channel *ch = device_get_softc(dev); 527183724Ssos u_int32_t action = ATA_INL(ctlr->r_res1, 0x0044); 528183724Ssos int offset = ch->unit * 0x2000; 529183724Ssos 530183724Ssos if (action & (1 << ch->unit)) { 531183724Ssos u_int32_t istatus = ATA_INL(ctlr->r_res2, 0x1008 + offset); 532183724Ssos 533183724Ssos /* do we have any PHY events ? */ 534214016Smav ata_sata_phy_check_events(dev, -1); 535183724Ssos 536183724Ssos /* clear interrupt(s) */ 537183724Ssos ATA_OUTL(ctlr->r_res2, 0x1008 + offset, istatus); 538183724Ssos 539183724Ssos /* do we have any device action ? */ 540183724Ssos return (istatus & 0x00000003); 541183724Ssos } 542183724Ssos return 0; 543183724Ssos} 544183724Ssos 545183724Ssosstatic int 546183724Ssosata_siiprb_begin_transaction(struct ata_request *request) 547183724Ssos{ 548198717Smav struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent)); 549183724Ssos struct ata_channel *ch = device_get_softc(request->parent); 550183724Ssos struct ata_siiprb_command *prb; 551183724Ssos struct ata_siiprb_dma_prdentry *prd; 552183724Ssos int offset = ch->unit * 0x2000; 553183724Ssos u_int64_t prb_bus; 554183724Ssos 555183724Ssos /* SOS XXX */ 556183724Ssos if (request->u.ata.command == ATA_DEVICE_RESET) { 557183724Ssos request->result = 0; 558183724Ssos return ATA_OP_FINISHED; 559183724Ssos } 560183724Ssos 561183724Ssos /* get a piece of the workspace for this request */ 562198717Smav prb = (struct ata_siiprb_command *)ch->dma.work; 563183724Ssos 564183724Ssos /* clear the prb structure */ 565183724Ssos bzero(prb, sizeof(struct ata_siiprb_command)); 566183724Ssos 567183724Ssos /* setup the FIS for this request */ 568183724Ssos if (!ata_request2fis_h2d(request, &prb->fis[0])) { 569198717Smav device_printf(request->parent, "setting up SATA FIS failed\n"); 570183724Ssos request->result = EIO; 571183724Ssos return ATA_OP_FINISHED; 572183724Ssos } 573183724Ssos 574183724Ssos /* setup transfer type */ 575183724Ssos if (request->flags & ATA_R_ATAPI) { 576183724Ssos bcopy(request->u.atapi.ccb, prb->u.atapi.ccb, 16); 577198717Smav if (request->flags & ATA_R_ATAPI16) 578198717Smav ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000020); 579198717Smav else 580183724Ssos ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000020); 581183724Ssos if (request->flags & ATA_R_READ) 582183724Ssos prb->control = htole16(0x0010); 583183724Ssos if (request->flags & ATA_R_WRITE) 584183724Ssos prb->control = htole16(0x0020); 585183724Ssos prd = &prb->u.atapi.prd[0]; 586183724Ssos } 587183724Ssos else 588183724Ssos prd = &prb->u.ata.prd[0]; 589183724Ssos 590183724Ssos /* if request moves data setup and load SG list */ 591183724Ssos if (request->flags & (ATA_R_READ | ATA_R_WRITE)) { 592183724Ssos if (ch->dma.load(request, prd, NULL)) { 593198717Smav device_printf(request->parent, "setting up DMA failed\n"); 594183724Ssos request->result = EIO; 595183724Ssos return ATA_OP_FINISHED; 596183724Ssos } 597183724Ssos } 598183724Ssos 599219338Smarius bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, BUS_DMASYNC_PREWRITE); 600219338Smarius 601183724Ssos /* activate the prb */ 602198717Smav prb_bus = ch->dma.work_bus; 603198717Smav ATA_OUTL(ctlr->r_res2, 0x1c00 + offset, prb_bus); 604198717Smav ATA_OUTL(ctlr->r_res2, 0x1c04 + offset, prb_bus>>32); 605183724Ssos 606183724Ssos /* start the timeout */ 607183724Ssos callout_reset(&request->callout, request->timeout * hz, 608183724Ssos (timeout_t*)ata_timeout, request); 609183724Ssos return ATA_OP_CONTINUES; 610183724Ssos} 611183724Ssos 612183724Ssosstatic int 613183724Ssosata_siiprb_end_transaction(struct ata_request *request) 614183724Ssos{ 615198717Smav struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent)); 616183724Ssos struct ata_channel *ch = device_get_softc(request->parent); 617183724Ssos struct ata_siiprb_command *prb; 618183724Ssos int offset = ch->unit * 0x2000; 619183724Ssos int error, timeout; 620183724Ssos 621183724Ssos /* kill the timeout */ 622183724Ssos callout_stop(&request->callout); 623219338Smarius 624219338Smarius bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, BUS_DMASYNC_POSTWRITE); 625219338Smarius 626183724Ssos prb = (struct ata_siiprb_command *) 627198717Smav ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset); 628183724Ssos 629183724Ssos /* any controller errors flagged ? */ 630183724Ssos if ((error = ATA_INL(ctlr->r_res2, 0x1024 + offset))) { 631183724Ssos if (bootverbose) 632183724Ssos printf("ata_siiprb_end_transaction %s error=%08x\n", 633183724Ssos ata_cmd2str(request), error); 634183724Ssos 635183724Ssos /* if device error status get details */ 636183724Ssos if (error == 1 || error == 2) { 637183724Ssos request->status = prb->fis[2]; 638183724Ssos if (request->status & ATA_S_ERROR) 639183724Ssos request->error = prb->fis[3]; 640183724Ssos } 641183724Ssos 642183724Ssos /* SOS XXX handle other controller errors here */ 643183724Ssos 644183724Ssos /* initialize port */ 645183724Ssos ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000004); 646183724Ssos 647183724Ssos /* poll for port ready */ 648183724Ssos for (timeout = 0; timeout < 1000; timeout++) { 649183724Ssos DELAY(1000); 650183724Ssos if (ATA_INL(ctlr->r_res2, 0x1008 + offset) & 0x00040000) 651183724Ssos break; 652183724Ssos } 653183724Ssos if (bootverbose) { 654183724Ssos if (timeout >= 1000) 655183724Ssos device_printf(ch->dev, "port initialize timeout\n"); 656183724Ssos else 657183724Ssos device_printf(ch->dev, "port initialize time=%dms\n", timeout); 658183724Ssos } 659183724Ssos } 660183724Ssos 661242156Smav /* Read back registers to the request struct. */ 662242156Smav if ((request->flags & ATA_R_ATAPI) == 0 && 663242156Smav ((request->status & ATA_S_ERROR) || 664242156Smav (request->flags & (ATA_R_CONTROL | ATA_R_NEEDRESULT)))) { 665183724Ssos request->u.ata.count = prb->fis[12] | ((u_int16_t)prb->fis[13] << 8); 666183724Ssos request->u.ata.lba = prb->fis[4] | ((u_int64_t)prb->fis[5] << 8) | 667183724Ssos ((u_int64_t)prb->fis[6] << 16); 668198717Smav if (request->flags & ATA_R_48BIT) 669183724Ssos request->u.ata.lba |= ((u_int64_t)prb->fis[8] << 24) | 670183724Ssos ((u_int64_t)prb->fis[9] << 32) | 671183724Ssos ((u_int64_t)prb->fis[10] << 40); 672183724Ssos else 673183724Ssos request->u.ata.lba |= ((u_int64_t)(prb->fis[7] & 0x0f) << 24); 674183724Ssos } 675183724Ssos 676183724Ssos /* update progress */ 677183724Ssos if (!(request->status & ATA_S_ERROR) && !(request->flags & ATA_R_TIMEOUT)) { 678183724Ssos if (request->flags & ATA_R_READ) 679213047Sjchandra request->donecount = le32toh(prb->transfer_count); 680183724Ssos else 681183724Ssos request->donecount = request->bytecount; 682183724Ssos } 683183724Ssos 684183724Ssos /* release SG list etc */ 685183724Ssos ch->dma.unload(request); 686183724Ssos 687183724Ssos return ATA_OP_FINISHED; 688183724Ssos} 689183724Ssos 690183724Ssosstatic int 691183724Ssosata_siiprb_issue_cmd(device_t dev) 692183724Ssos{ 693183724Ssos struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 694183724Ssos struct ata_channel *ch = device_get_softc(dev); 695183724Ssos u_int64_t prb_bus = ch->dma.work_bus; 696183724Ssos u_int32_t status; 697183724Ssos int offset = ch->unit * 0x2000; 698183724Ssos int timeout; 699183724Ssos 700219338Smarius bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, BUS_DMASYNC_PREWRITE); 701219338Smarius 702183724Ssos /* issue command to chip */ 703183724Ssos ATA_OUTL(ctlr->r_res2, 0x1c00 + offset, prb_bus); 704183724Ssos ATA_OUTL(ctlr->r_res2, 0x1c04 + offset, prb_bus >> 32); 705183724Ssos 706183724Ssos /* poll for command finished */ 707183724Ssos for (timeout = 0; timeout < 10000; timeout++) { 708183724Ssos DELAY(1000); 709183724Ssos if ((status = ATA_INL(ctlr->r_res2, 0x1008 + offset)) & 0x00010000) 710183724Ssos break; 711183724Ssos } 712219338Smarius 713219338Smarius bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, BUS_DMASYNC_POSTWRITE); 714219338Smarius 715183724Ssos // SOS XXX ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x00010000); 716183724Ssos ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x08ff08ff); 717183724Ssos 718183724Ssos if (timeout >= 1000) 719183724Ssos return EIO; 720183724Ssos 721183724Ssos if (bootverbose) 722183724Ssos device_printf(dev, "siiprb_issue_cmd time=%dms status=%08x\n", 723183724Ssos timeout, status); 724183724Ssos return 0; 725183724Ssos} 726183724Ssos 727183724Ssosstatic int 728183724Ssosata_siiprb_pm_read(device_t dev, int port, int reg, u_int32_t *result) 729183724Ssos{ 730183724Ssos struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 731183724Ssos struct ata_channel *ch = device_get_softc(dev); 732183724Ssos struct ata_siiprb_command *prb = (struct ata_siiprb_command *)ch->dma.work; 733183724Ssos int offset = ch->unit * 0x2000; 734183724Ssos 735214016Smav if (port < 0) { 736214016Smav *result = ATA_IDX_INL(ch, reg); 737214016Smav return (0); 738214016Smav } 739214016Smav if (port < ATA_PM) { 740214016Smav switch (reg) { 741214016Smav case ATA_SSTATUS: 742214016Smav reg = 0; 743214016Smav break; 744214016Smav case ATA_SERROR: 745214016Smav reg = 1; 746214016Smav break; 747214016Smav case ATA_SCONTROL: 748214016Smav reg = 2; 749214016Smav break; 750214016Smav default: 751214016Smav return (EINVAL); 752214016Smav } 753214016Smav } 754183724Ssos bzero(prb, sizeof(struct ata_siiprb_command)); 755183724Ssos prb->fis[0] = 0x27; /* host to device */ 756183724Ssos prb->fis[1] = 0x8f; /* command FIS to PM port */ 757183724Ssos prb->fis[2] = ATA_READ_PM; 758183724Ssos prb->fis[3] = reg; 759183724Ssos prb->fis[7] = port; 760183724Ssos if (ata_siiprb_issue_cmd(dev)) { 761183724Ssos device_printf(dev, "error reading PM port\n"); 762183724Ssos return EIO; 763183724Ssos } 764183724Ssos prb = (struct ata_siiprb_command *) 765183724Ssos ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset); 766183724Ssos *result = prb->fis[12]|(prb->fis[4]<<8)|(prb->fis[5]<<16)|(prb->fis[6]<<24); 767183724Ssos return 0; 768183724Ssos} 769183724Ssos 770183724Ssosstatic int 771183724Ssosata_siiprb_pm_write(device_t dev, int port, int reg, u_int32_t value) 772183724Ssos{ 773183724Ssos struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 774183724Ssos struct ata_channel *ch = device_get_softc(dev); 775183724Ssos struct ata_siiprb_command *prb = (struct ata_siiprb_command *)ch->dma.work; 776183724Ssos int offset = ch->unit * 0x2000; 777183724Ssos 778214016Smav if (port < 0) { 779214016Smav ATA_IDX_OUTL(ch, reg, value); 780214016Smav return (0); 781214016Smav } 782214016Smav if (port < ATA_PM) { 783214016Smav switch (reg) { 784214016Smav case ATA_SSTATUS: 785214016Smav reg = 0; 786214016Smav break; 787214016Smav case ATA_SERROR: 788214016Smav reg = 1; 789214016Smav break; 790214016Smav case ATA_SCONTROL: 791214016Smav reg = 2; 792214016Smav break; 793214016Smav default: 794214016Smav return (EINVAL); 795214016Smav } 796214016Smav } 797183724Ssos bzero(prb, sizeof(struct ata_siiprb_command)); 798183724Ssos prb->fis[0] = 0x27; /* host to device */ 799183724Ssos prb->fis[1] = 0x8f; /* command FIS to PM port */ 800183724Ssos prb->fis[2] = ATA_WRITE_PM; 801183724Ssos prb->fis[3] = reg; 802183724Ssos prb->fis[7] = port; 803183724Ssos prb->fis[12] = value & 0xff; 804201758Smbr prb->fis[4] = (value >> 8) & 0xff; 805201758Smbr prb->fis[5] = (value >> 16) & 0xff; 806201758Smbr prb->fis[6] = (value >> 24) & 0xff; 807183724Ssos if (ata_siiprb_issue_cmd(dev)) { 808183724Ssos device_printf(dev, "error writing PM port\n"); 809183724Ssos return ATA_E_ABORT; 810183724Ssos } 811183724Ssos prb = (struct ata_siiprb_command *) 812183724Ssos ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset); 813183724Ssos return prb->fis[3]; 814183724Ssos} 815183724Ssos 816183724Ssosstatic u_int32_t 817183724Ssosata_siiprb_softreset(device_t dev, int port) 818183724Ssos{ 819183724Ssos struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 820183724Ssos struct ata_channel *ch = device_get_softc(dev); 821183724Ssos struct ata_siiprb_command *prb = (struct ata_siiprb_command *)ch->dma.work; 822183724Ssos u_int32_t signature; 823183724Ssos int offset = ch->unit * 0x2000; 824183724Ssos 825183724Ssos /* setup the workspace for a soft reset command */ 826183724Ssos bzero(prb, sizeof(struct ata_siiprb_command)); 827183724Ssos prb->control = htole16(0x0080); 828183724Ssos prb->fis[1] = port & 0x0f; 829183724Ssos 830183724Ssos /* issue soft reset */ 831183724Ssos if (ata_siiprb_issue_cmd(dev)) 832183724Ssos return -1; 833183724Ssos 834183724Ssos ata_udelay(150000); 835183724Ssos 836183724Ssos /* get possible signature */ 837183724Ssos prb = (struct ata_siiprb_command *) 838183724Ssos ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset); 839183724Ssos signature=prb->fis[12]|(prb->fis[4]<<8)|(prb->fis[5]<<16)|(prb->fis[6]<<24); 840183724Ssos 841183724Ssos /* clear error bits/interrupt */ 842183724Ssos ATA_IDX_OUTL(ch, ATA_SERROR, 0xffffffff); 843183724Ssos 844183724Ssos return signature; 845183724Ssos} 846183724Ssos 847183724Ssosstatic void 848183724Ssosata_siiprb_reset(device_t dev) 849183724Ssos{ 850183724Ssos struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 851183724Ssos struct ata_channel *ch = device_get_softc(dev); 852183724Ssos int offset = ch->unit * 0x2000; 853183724Ssos u_int32_t status, signature; 854183724Ssos int timeout; 855183724Ssos 856183724Ssos /* disable interrupts */ 857183724Ssos ATA_OUTL(ctlr->r_res2, 0x1014 + offset, 0x000000ff); 858183724Ssos 859183724Ssos /* reset channel HW */ 860183724Ssos ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000001); 861183724Ssos DELAY(1000); 862183724Ssos ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000001); 863183724Ssos DELAY(10000); 864183724Ssos 865183724Ssos /* poll for channel ready */ 866183724Ssos for (timeout = 0; timeout < 1000; timeout++) { 867183724Ssos if ((status = ATA_INL(ctlr->r_res2, 0x1008 + offset)) & 0x00040000) 868183724Ssos break; 869183724Ssos DELAY(1000); 870183724Ssos } 871183724Ssos 872183724Ssos if (bootverbose) { 873183724Ssos if (timeout >= 1000) 874183724Ssos device_printf(dev, "channel HW reset timeout\n"); 875183724Ssos else 876183724Ssos device_printf(dev, "channel HW reset time=%dms\n", timeout); 877183724Ssos } 878183724Ssos 879183724Ssos /* reset phy */ 880190581Smav if (!ata_sata_phy_reset(dev, -1, 1)) { 881183724Ssos if (bootverbose) 882183724Ssos device_printf(dev, "phy reset found no device\n"); 883183724Ssos ch->devices = 0; 884183724Ssos goto finish; 885183724Ssos } 886183724Ssos 887183724Ssos /* issue soft reset */ 888183724Ssos signature = ata_siiprb_softreset(dev, ATA_PM); 889183724Ssos if (bootverbose) 890183724Ssos device_printf(dev, "SIGNATURE=%08x\n", signature); 891183724Ssos 892183724Ssos /* figure out whats there */ 893188906Smav switch (signature >> 16) { 894188906Smav case 0x0000: 895183724Ssos ch->devices = ATA_ATA_MASTER; 896183724Ssos break; 897188906Smav case 0x9669: 898183724Ssos ch->devices = ATA_PORTMULTIPLIER; 899183724Ssos ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x2000); /* enable PM support */ 900183724Ssos //SOS XXX need to clear all PM status and interrupts!!!! 901183724Ssos ata_pm_identify(dev); 902183724Ssos break; 903188906Smav case 0xeb14: 904183724Ssos ch->devices = ATA_ATAPI_MASTER; 905183724Ssos break; 906183724Ssos default: 907183724Ssos ch->devices = 0; 908183724Ssos } 909183724Ssos if (bootverbose) 910183724Ssos device_printf(dev, "siiprb_reset devices=%08x\n", ch->devices); 911183724Ssos 912183724Ssosfinish: 913183724Ssos /* clear interrupt(s) */ 914183724Ssos ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x000008ff); 915183724Ssos 916183724Ssos /* require explicit interrupt ack */ 917183724Ssos ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000008); 918183724Ssos 919183724Ssos /* 64bit mode */ 920183724Ssos ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000400); 921183724Ssos 922183724Ssos /* enable interrupts wanted */ 923183724Ssos ATA_OUTL(ctlr->r_res2, 0x1010 + offset, 0x000000ff); 924183724Ssos} 925183724Ssos 926183724Ssosstatic void 927183724Ssosata_siiprb_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 928183724Ssos{ 929183724Ssos struct ata_dmasetprd_args *args = xsc; 930183724Ssos struct ata_siiprb_dma_prdentry *prd = args->dmatab; 931183724Ssos int i; 932183724Ssos 933183724Ssos if ((args->error = error)) 934183724Ssos return; 935183724Ssos 936183724Ssos for (i = 0; i < nsegs; i++) { 937183724Ssos prd[i].addr = htole64(segs[i].ds_addr); 938183724Ssos prd[i].count = htole32(segs[i].ds_len); 939183724Ssos } 940183724Ssos prd[i - 1].control = htole32(ATA_DMA_EOT); 941183724Ssos KASSERT(nsegs <= ATA_SIIPRB_DMA_ENTRIES,("too many DMA segment entries\n")); 942183724Ssos args->nsegs = nsegs; 943183724Ssos} 944183724Ssos 945183724Ssosstatic void 946183724Ssosata_siiprb_dmainit(device_t dev) 947183724Ssos{ 948183724Ssos struct ata_channel *ch = device_get_softc(dev); 949183724Ssos 950183724Ssos /* note start and stop are not used here */ 951183724Ssos ch->dma.setprd = ata_siiprb_dmasetprd; 952183724Ssos ch->dma.max_address = BUS_SPACE_MAXADDR; 953198717Smav ch->dma.max_iosize = (ATA_SIIPRB_DMA_ENTRIES - 1) * PAGE_SIZE; 954216013Smarius ata_dmainit(dev); 955183724Ssos} 956183724Ssos 957183724SsosATA_DECLARE_DRIVER(ata_sii); 958