ata-siliconimage.c revision 212145
1183724Ssos/*- 2183724Ssos * Copyright (c) 1998 - 2008 S�ren Schmidt <sos@FreeBSD.org> 3183724Ssos * All rights reserved. 4183724Ssos * 5183724Ssos * Redistribution and use in source and binary forms, with or without 6183724Ssos * modification, are permitted provided that the following conditions 7183724Ssos * are met: 8183724Ssos * 1. Redistributions of source code must retain the above copyright 9183724Ssos * notice, this list of conditions and the following disclaimer, 10183724Ssos * without modification, immediately at the beginning of the file. 11183724Ssos * 2. Redistributions in binary form must reproduce the above copyright 12183724Ssos * notice, this list of conditions and the following disclaimer in the 13183724Ssos * documentation and/or other materials provided with the distribution. 14183724Ssos * 15183724Ssos * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16183724Ssos * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17183724Ssos * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18183724Ssos * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19183724Ssos * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20183724Ssos * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21183724Ssos * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22183724Ssos * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23183724Ssos * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24183724Ssos * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25183724Ssos */ 26183724Ssos 27183724Ssos#include <sys/cdefs.h> 28183724Ssos__FBSDID("$FreeBSD: head/sys/dev/ata/chipsets/ata-siliconimage.c 212145 2010-09-02 11:18:43Z mav $"); 29183724Ssos 30183724Ssos#include "opt_ata.h" 31183724Ssos#include <sys/param.h> 32183724Ssos#include <sys/module.h> 33183724Ssos#include <sys/systm.h> 34183724Ssos#include <sys/kernel.h> 35183724Ssos#include <sys/ata.h> 36183724Ssos#include <sys/bus.h> 37183724Ssos#include <sys/endian.h> 38183724Ssos#include <sys/malloc.h> 39183724Ssos#include <sys/lock.h> 40183724Ssos#include <sys/mutex.h> 41183724Ssos#include <sys/sema.h> 42183724Ssos#include <sys/taskqueue.h> 43183724Ssos#include <vm/uma.h> 44183724Ssos#include <machine/stdarg.h> 45183724Ssos#include <machine/resource.h> 46183724Ssos#include <machine/bus.h> 47183724Ssos#include <sys/rman.h> 48183724Ssos#include <dev/pci/pcivar.h> 49183724Ssos#include <dev/pci/pcireg.h> 50183724Ssos#include <dev/ata/ata-all.h> 51183724Ssos#include <dev/ata/ata-pci.h> 52183724Ssos#include <ata_if.h> 53183724Ssos 54183724Ssos/* local prototypes */ 55188765Smavstatic int ata_cmd_ch_attach(device_t dev); 56183724Ssosstatic int ata_cmd_status(device_t dev); 57200171Smavstatic int ata_cmd_setmode(device_t dev, int target, int mode); 58188765Smavstatic int ata_sii_ch_attach(device_t dev); 59188769Smavstatic int ata_sii_ch_detach(device_t dev); 60183724Ssosstatic int ata_sii_status(device_t dev); 61183724Ssosstatic void ata_sii_reset(device_t dev); 62200171Smavstatic int ata_sii_setmode(device_t dev, int target, int mode); 63188765Smavstatic int ata_siiprb_ch_attach(device_t dev); 64188769Smavstatic int ata_siiprb_ch_detach(device_t dev); 65183724Ssosstatic int ata_siiprb_status(device_t dev); 66183724Ssosstatic int ata_siiprb_begin_transaction(struct ata_request *request); 67183724Ssosstatic int ata_siiprb_end_transaction(struct ata_request *request); 68183724Ssosstatic int ata_siiprb_pm_read(device_t dev, int port, int reg, u_int32_t *result); 69183724Ssosstatic int ata_siiprb_pm_write(device_t dev, int port, int reg, u_int32_t result); 70183724Ssosstatic u_int32_t ata_siiprb_softreset(device_t dev, int port); 71183724Ssosstatic void ata_siiprb_reset(device_t dev); 72183724Ssosstatic void ata_siiprb_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 73183724Ssosstatic void ata_siiprb_dmainit(device_t dev); 74183724Ssos 75183724Ssos/* misc defines */ 76183724Ssos#define SII_MEMIO 1 77183724Ssos#define SII_PRBIO 2 78183724Ssos#define SII_INTR 0x01 79183724Ssos#define SII_SETCLK 0x02 80183724Ssos#define SII_BUG 0x04 81183724Ssos#define SII_4CH 0x08 82183724Ssos 83183724Ssos 84183724Ssos/* 85183724Ssos * Silicon Image Inc. (SiI) (former CMD) chipset support functions 86183724Ssos */ 87183724Ssosstatic int 88183724Ssosata_sii_probe(device_t dev) 89183724Ssos{ 90183724Ssos struct ata_pci_controller *ctlr = device_get_softc(dev); 91183724Ssos static struct ata_chip_id ids[] = 92183724Ssos {{ ATA_SII3114, 0x00, SII_MEMIO, SII_4CH, ATA_SA150, "3114" }, 93183724Ssos { ATA_SII3512, 0x02, SII_MEMIO, 0, ATA_SA150, "3512" }, 94183724Ssos { ATA_SII3112, 0x02, SII_MEMIO, 0, ATA_SA150, "3112" }, 95183724Ssos { ATA_SII3112_1, 0x02, SII_MEMIO, 0, ATA_SA150, "3112" }, 96183724Ssos { ATA_SII3512, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "3512" }, 97183724Ssos { ATA_SII3112, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "3112" }, 98183724Ssos { ATA_SII3112_1, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "3112" }, 99183724Ssos { ATA_SII3124, 0x00, SII_PRBIO, SII_4CH, ATA_SA300, "3124" }, 100183724Ssos { ATA_SII3132, 0x00, SII_PRBIO, 0, ATA_SA300, "3132" }, 101183724Ssos { ATA_SII3132_1, 0x00, SII_PRBIO, 0, ATA_SA300, "3132" }, 102191897Smav { ATA_SII3132_2, 0x00, SII_PRBIO, 0, ATA_SA300, "3132" }, 103183724Ssos { ATA_SII0680, 0x00, SII_MEMIO, SII_SETCLK, ATA_UDMA6, "680" }, 104183724Ssos { ATA_CMD649, 0x00, 0, SII_INTR, ATA_UDMA5, "(CMD) 649" }, 105183724Ssos { ATA_CMD648, 0x00, 0, SII_INTR, ATA_UDMA4, "(CMD) 648" }, 106183724Ssos { ATA_CMD646, 0x07, 0, 0, ATA_UDMA2, "(CMD) 646U2" }, 107183724Ssos { ATA_CMD646, 0x00, 0, 0, ATA_WDMA2, "(CMD) 646" }, 108183724Ssos { 0, 0, 0, 0, 0, 0}}; 109183724Ssos 110183724Ssos if (pci_get_vendor(dev) != ATA_SILICON_IMAGE_ID) 111183724Ssos return ENXIO; 112183724Ssos 113183724Ssos if (!(ctlr->chip = ata_match_chip(dev, ids))) 114183724Ssos return ENXIO; 115183724Ssos 116183724Ssos ata_set_desc(dev); 117183724Ssos ctlr->chipinit = ata_sii_chipinit; 118194893Smav return (BUS_PROBE_DEFAULT); 119183724Ssos} 120183724Ssos 121183724Ssosint 122183724Ssosata_sii_chipinit(device_t dev) 123183724Ssos{ 124183724Ssos struct ata_pci_controller *ctlr = device_get_softc(dev); 125183724Ssos 126183724Ssos if (ata_setup_interrupt(dev, ata_generic_intr)) 127183724Ssos return ENXIO; 128183724Ssos 129183724Ssos switch (ctlr->chip->cfg1) { 130183724Ssos case SII_PRBIO: 131183724Ssos ctlr->r_type1 = SYS_RES_MEMORY; 132183724Ssos ctlr->r_rid1 = PCIR_BAR(0); 133183724Ssos if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1, 134183724Ssos &ctlr->r_rid1, RF_ACTIVE))) 135183724Ssos return ENXIO; 136183724Ssos 137183724Ssos ctlr->r_rid2 = PCIR_BAR(2); 138183724Ssos ctlr->r_type2 = SYS_RES_MEMORY; 139183724Ssos if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 140183724Ssos &ctlr->r_rid2, RF_ACTIVE))){ 141183724Ssos bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1,ctlr->r_res1); 142183724Ssos return ENXIO; 143183724Ssos } 144188765Smav ctlr->ch_attach = ata_siiprb_ch_attach; 145188769Smav ctlr->ch_detach = ata_siiprb_ch_detach; 146183724Ssos ctlr->reset = ata_siiprb_reset; 147183724Ssos ctlr->setmode = ata_sata_setmode; 148200171Smav ctlr->getrev = ata_sata_getrev; 149183724Ssos ctlr->channels = (ctlr->chip->cfg2 == SII_4CH) ? 4 : 2; 150183724Ssos 151183724Ssos /* reset controller */ 152183724Ssos ATA_OUTL(ctlr->r_res1, 0x0040, 0x80000000); 153183724Ssos DELAY(10000); 154183724Ssos ATA_OUTL(ctlr->r_res1, 0x0040, 0x0000000f); 155183724Ssos break; 156183724Ssos 157183724Ssos case SII_MEMIO: 158183724Ssos ctlr->r_type2 = SYS_RES_MEMORY; 159183724Ssos ctlr->r_rid2 = PCIR_BAR(5); 160183724Ssos if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 161183724Ssos &ctlr->r_rid2, RF_ACTIVE))){ 162183724Ssos if (ctlr->chip->chipid != ATA_SII0680 || 163183724Ssos (pci_read_config(dev, 0x8a, 1) & 1)) 164183724Ssos return ENXIO; 165183724Ssos } 166183724Ssos 167183724Ssos if (ctlr->chip->cfg2 & SII_SETCLK) { 168183724Ssos if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10) 169183724Ssos pci_write_config(dev, 0x8a, 170183724Ssos (pci_read_config(dev, 0x8a, 1) & 0xcf)|0x10,1); 171183724Ssos if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10) 172183724Ssos device_printf(dev, "%s could not set ATA133 clock\n", 173183724Ssos ctlr->chip->text); 174183724Ssos } 175183724Ssos 176183724Ssos /* if we have 4 channels enable the second set */ 177183724Ssos if (ctlr->chip->cfg2 & SII_4CH) { 178183724Ssos ATA_OUTL(ctlr->r_res2, 0x0200, 0x00000002); 179183724Ssos ctlr->channels = 4; 180183724Ssos } 181183724Ssos 182183724Ssos /* dont block interrupts from any channel */ 183183724Ssos pci_write_config(dev, 0x48, 184183724Ssos (pci_read_config(dev, 0x48, 4) & ~0x03c00000), 4); 185183724Ssos 186183724Ssos /* enable PCI interrupt as BIOS might not */ 187183724Ssos pci_write_config(dev, 0x8a, (pci_read_config(dev, 0x8a, 1) & 0x3f), 1); 188183724Ssos 189188769Smav if (ctlr->r_res2) { 190188765Smav ctlr->ch_attach = ata_sii_ch_attach; 191188769Smav ctlr->ch_detach = ata_sii_ch_detach; 192188769Smav } 193183724Ssos 194183724Ssos if (ctlr->chip->max_dma >= ATA_SA150) { 195183724Ssos ctlr->reset = ata_sii_reset; 196183724Ssos ctlr->setmode = ata_sata_setmode; 197200171Smav ctlr->getrev = ata_sata_getrev; 198183724Ssos } 199183724Ssos else 200183724Ssos ctlr->setmode = ata_sii_setmode; 201183724Ssos break; 202183724Ssos 203183724Ssos default: 204183724Ssos if ((pci_read_config(dev, 0x51, 1) & 0x08) != 0x08) { 205183724Ssos device_printf(dev, "HW has secondary channel disabled\n"); 206183724Ssos ctlr->channels = 1; 207183724Ssos } 208183724Ssos 209183724Ssos /* enable interrupt as BIOS might not */ 210183724Ssos pci_write_config(dev, 0x71, 0x01, 1); 211183724Ssos 212188765Smav ctlr->ch_attach = ata_cmd_ch_attach; 213188769Smav ctlr->ch_detach = ata_pci_ch_detach; 214183724Ssos ctlr->setmode = ata_cmd_setmode; 215183724Ssos break; 216183724Ssos } 217183724Ssos return 0; 218183724Ssos} 219183724Ssos 220183724Ssosstatic int 221188765Smavata_cmd_ch_attach(device_t dev) 222183724Ssos{ 223183724Ssos struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 224183724Ssos struct ata_channel *ch = device_get_softc(dev); 225183724Ssos 226183724Ssos /* setup the usual register normal pci style */ 227188765Smav if (ata_pci_ch_attach(dev)) 228183724Ssos return ENXIO; 229183724Ssos 230183724Ssos if (ctlr->chip->cfg2 & SII_INTR) 231183724Ssos ch->hw.status = ata_cmd_status; 232183724Ssos 233183724Ssos return 0; 234183724Ssos} 235183724Ssos 236183724Ssosstatic int 237183724Ssosata_cmd_status(device_t dev) 238183724Ssos{ 239183724Ssos struct ata_channel *ch = device_get_softc(dev); 240183724Ssos u_int8_t reg71; 241183724Ssos 242183724Ssos if (((reg71 = pci_read_config(device_get_parent(dev), 0x71, 1)) & 243183724Ssos (ch->unit ? 0x08 : 0x04))) { 244183724Ssos pci_write_config(device_get_parent(dev), 0x71, 245183724Ssos reg71 & ~(ch->unit ? 0x04 : 0x08), 1); 246183724Ssos return ata_pci_status(dev); 247183724Ssos } 248183724Ssos return 0; 249183724Ssos} 250183724Ssos 251200171Smavstatic int 252200171Smavata_cmd_setmode(device_t dev, int target, int mode) 253183724Ssos{ 254200171Smav device_t parent = device_get_parent(dev); 255200171Smav struct ata_pci_controller *ctlr = device_get_softc(parent); 256200171Smav struct ata_channel *ch = device_get_softc(dev); 257200171Smav int devno = (ch->unit << 1) + target; 258183724Ssos int treg = 0x54 + ((devno < 3) ? (devno << 1) : 7); 259183724Ssos int ureg = ch->unit ? 0x7b : 0x73; 260200171Smav int piomode; 261200171Smav uint8_t piotimings[] = { 0xa9, 0x57, 0x44, 0x32, 0x3f, 0x87, 0x32, 0x3f }; 262200171Smav uint8_t udmatimings[][2] = { { 0x31, 0xc2 }, { 0x21, 0x82 }, 263183724Ssos { 0x11, 0x42 }, { 0x25, 0x8a }, 264183724Ssos { 0x15, 0x4a }, { 0x05, 0x0a } }; 265183724Ssos 266200171Smav mode = min(mode, ctlr->chip->max_dma); 267200171Smav if (mode >= ATA_UDMA0) { 268200171Smav u_int8_t umode = pci_read_config(parent, ureg, 1); 269183724Ssos 270200171Smav umode &= ~(target == 0 ? 0x35 : 0xca); 271200171Smav umode |= udmatimings[mode & ATA_MODE_MASK][target]; 272200171Smav pci_write_config(parent, ureg, umode, 1); 273200171Smav piomode = ATA_PIO4; 274200171Smav } else { 275200171Smav pci_write_config(parent, ureg, 276200171Smav pci_read_config(parent, ureg, 1) & 277200171Smav ~(target == 0 ? 0x35 : 0xca), 1); 278200171Smav piomode = mode; 279183724Ssos } 280200171Smav pci_write_config(parent, treg, piotimings[ata_mode2idx(piomode)], 1); 281200171Smav return (mode); 282183724Ssos} 283183724Ssos 284183724Ssosstatic int 285188765Smavata_sii_ch_attach(device_t dev) 286183724Ssos{ 287183724Ssos struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 288183724Ssos struct ata_channel *ch = device_get_softc(dev); 289183724Ssos int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2); 290183724Ssos int i; 291183724Ssos 292188769Smav ata_pci_dmainit(dev); 293188769Smav 294183724Ssos for (i = ATA_DATA; i <= ATA_COMMAND; i++) { 295183724Ssos ch->r_io[i].res = ctlr->r_res2; 296183724Ssos ch->r_io[i].offset = 0x80 + i + (unit01 << 6) + (unit10 << 8); 297183724Ssos } 298183724Ssos ch->r_io[ATA_CONTROL].res = ctlr->r_res2; 299183724Ssos ch->r_io[ATA_CONTROL].offset = 0x8a + (unit01 << 6) + (unit10 << 8); 300183724Ssos ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2; 301183724Ssos ata_default_registers(dev); 302183724Ssos 303183724Ssos ch->r_io[ATA_BMCMD_PORT].res = ctlr->r_res2; 304183724Ssos ch->r_io[ATA_BMCMD_PORT].offset = 0x00 + (unit01 << 3) + (unit10 << 8); 305183724Ssos ch->r_io[ATA_BMSTAT_PORT].res = ctlr->r_res2; 306183724Ssos ch->r_io[ATA_BMSTAT_PORT].offset = 0x02 + (unit01 << 3) + (unit10 << 8); 307183724Ssos ch->r_io[ATA_BMDTP_PORT].res = ctlr->r_res2; 308183724Ssos ch->r_io[ATA_BMDTP_PORT].offset = 0x04 + (unit01 << 3) + (unit10 << 8); 309183724Ssos 310183724Ssos if (ctlr->chip->max_dma >= ATA_SA150) { 311183724Ssos ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 312183724Ssos ch->r_io[ATA_SSTATUS].offset = 0x104 + (unit01 << 7) + (unit10 << 8); 313183724Ssos ch->r_io[ATA_SERROR].res = ctlr->r_res2; 314183724Ssos ch->r_io[ATA_SERROR].offset = 0x108 + (unit01 << 7) + (unit10 << 8); 315183724Ssos ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 316183724Ssos ch->r_io[ATA_SCONTROL].offset = 0x100 + (unit01 << 7) + (unit10 << 8); 317183724Ssos ch->flags |= ATA_NO_SLAVE; 318200171Smav ch->flags |= ATA_SATA; 319212145Smav ch->flags |= ATA_KNOWN_PRESENCE; 320183724Ssos 321183724Ssos /* enable PHY state change interrupt */ 322183724Ssos ATA_OUTL(ctlr->r_res2, 0x148 + (unit01 << 7) + (unit10 << 8),(1 << 16)); 323183724Ssos } 324183724Ssos 325183724Ssos if (ctlr->chip->cfg2 & SII_BUG) { 326183724Ssos /* work around errata in early chips */ 327183724Ssos ch->dma.boundary = 8192; 328183724Ssos ch->dma.segsize = 15 * DEV_BSIZE; 329183724Ssos } 330183724Ssos 331183724Ssos ata_pci_hw(dev); 332183724Ssos ch->hw.status = ata_sii_status; 333200171Smav if (ctlr->chip->cfg2 & SII_SETCLK) 334200171Smav ch->flags |= ATA_CHECKS_CABLE; 335183724Ssos return 0; 336183724Ssos} 337183724Ssos 338183724Ssosstatic int 339188769Smavata_sii_ch_detach(device_t dev) 340188769Smav{ 341188769Smav 342188769Smav ata_pci_dmafini(dev); 343188769Smav return (0); 344188769Smav} 345188769Smav 346188769Smavstatic int 347183724Ssosata_sii_status(device_t dev) 348183724Ssos{ 349183724Ssos struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 350183724Ssos struct ata_channel *ch = device_get_softc(dev); 351183724Ssos int offset0 = ((ch->unit & 1) << 3) + ((ch->unit & 2) << 8); 352183724Ssos int offset1 = ((ch->unit & 1) << 6) + ((ch->unit & 2) << 8); 353183724Ssos 354183724Ssos /* do we have any PHY events ? */ 355183724Ssos if (ctlr->chip->max_dma >= ATA_SA150 && 356183724Ssos (ATA_INL(ctlr->r_res2, 0x10 + offset0) & 0x00000010)) 357183724Ssos ata_sata_phy_check_events(dev); 358183724Ssos 359183724Ssos if (ATA_INL(ctlr->r_res2, 0xa0 + offset1) & 0x00000800) 360183724Ssos return ata_pci_status(dev); 361183724Ssos else 362183724Ssos return 0; 363183724Ssos} 364183724Ssos 365183724Ssosstatic void 366183724Ssosata_sii_reset(device_t dev) 367183724Ssos{ 368209884Smav struct ata_channel *ch = device_get_softc(dev); 369209884Smav 370190581Smav if (ata_sata_phy_reset(dev, -1, 1)) 371183724Ssos ata_generic_reset(dev); 372209884Smav else 373209884Smav ch->devices = 0; 374183724Ssos} 375183724Ssos 376200171Smavstatic int 377200171Smavata_sii_setmode(device_t dev, int target, int mode) 378183724Ssos{ 379200171Smav device_t parent = device_get_parent(dev); 380200171Smav struct ata_pci_controller *ctlr = device_get_softc(parent); 381200171Smav struct ata_channel *ch = device_get_softc(dev); 382200171Smav int rego = (ch->unit << 4) + (target << 1); 383200171Smav int mreg = ch->unit ? 0x84 : 0x80; 384200171Smav int mask = 0x03 << (target << 2); 385200171Smav int mval = pci_read_config(parent, mreg, 1) & ~mask; 386200171Smav int piomode; 387200171Smav u_int8_t preg = 0xa4 + rego; 388200171Smav u_int8_t dreg = 0xa8 + rego; 389200171Smav u_int8_t ureg = 0xac + rego; 390200171Smav u_int16_t piotimings[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 }; 391200171Smav u_int16_t dmatimings[] = { 0x2208, 0x10c2, 0x10c1 }; 392200171Smav u_int8_t udmatimings[] = { 0xf, 0xb, 0x7, 0x5, 0x3, 0x2, 0x1 }; 393183724Ssos 394200171Smav mode = min(mode, ctlr->chip->max_dma); 395183724Ssos 396200171Smav if (ctlr->chip->cfg2 & SII_SETCLK) { 397209872Smav if (ata_dma_check_80pin && mode > ATA_UDMA2 && 398209872Smav (pci_read_config(parent, 0x79, 1) & 399183724Ssos (ch->unit ? 0x02 : 0x01))) { 400200171Smav ata_print_cable(dev, "controller"); 401200171Smav mode = ATA_UDMA2; 402200171Smav } 403183724Ssos } 404200171Smav if (mode >= ATA_UDMA0) { 405200171Smav pci_write_config(parent, mreg, 406200171Smav mval | (0x03 << (target << 2)), 1); 407200171Smav pci_write_config(parent, ureg, 408200171Smav (pci_read_config(parent, ureg, 1) & ~0x3f) | 409183724Ssos udmatimings[mode & ATA_MODE_MASK], 1); 410200171Smav piomode = ATA_PIO4; 411200171Smav } else if (mode >= ATA_WDMA0) { 412200171Smav pci_write_config(parent, mreg, 413200171Smav mval | (0x02 << (target << 2)), 1); 414200171Smav pci_write_config(parent, dreg, dmatimings[mode & ATA_MODE_MASK], 2); 415200171Smav piomode = (mode == ATA_WDMA0) ? ATA_PIO0 : 416200171Smav (mode == ATA_WDMA1) ? ATA_PIO3 : ATA_PIO4; 417200171Smav } else { 418200171Smav pci_write_config(parent, mreg, 419200171Smav mval | (0x01 << (target << 2)), 1); 420200171Smav piomode = mode; 421200171Smav } 422200171Smav pci_write_config(parent, preg, piotimings[ata_mode2idx(piomode)], 2); 423200171Smav return (mode); 424183724Ssos} 425183724Ssos 426183724Ssos 427183724Ssosstruct ata_siiprb_dma_prdentry { 428183724Ssos u_int64_t addr; 429183724Ssos u_int32_t count; 430183724Ssos u_int32_t control; 431183724Ssos} __packed; 432183724Ssos 433198717Smav#define ATA_SIIPRB_DMA_ENTRIES 129 434183724Ssosstruct ata_siiprb_ata_command { 435183724Ssos struct ata_siiprb_dma_prdentry prd[ATA_SIIPRB_DMA_ENTRIES]; 436183724Ssos} __packed; 437183724Ssos 438183724Ssosstruct ata_siiprb_atapi_command { 439183724Ssos u_int8_t ccb[16]; 440183724Ssos struct ata_siiprb_dma_prdentry prd[ATA_SIIPRB_DMA_ENTRIES]; 441183724Ssos} __packed; 442183724Ssos 443183724Ssosstruct ata_siiprb_command { 444183724Ssos u_int16_t control; 445183724Ssos u_int16_t protocol_override; 446183724Ssos u_int32_t transfer_count; 447183724Ssos u_int8_t fis[24]; 448183724Ssos union { 449183724Ssos struct ata_siiprb_ata_command ata; 450183724Ssos struct ata_siiprb_atapi_command atapi; 451183724Ssos } u; 452183724Ssos} __packed; 453183724Ssos 454183724Ssosstatic int 455188765Smavata_siiprb_ch_attach(device_t dev) 456183724Ssos{ 457183724Ssos struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 458183724Ssos struct ata_channel *ch = device_get_softc(dev); 459183724Ssos int offset = ch->unit * 0x2000; 460183724Ssos 461188765Smav ata_siiprb_dmainit(dev); 462188765Smav 463183724Ssos /* set the SATA resources */ 464183724Ssos ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 465183724Ssos ch->r_io[ATA_SSTATUS].offset = 0x1f04 + offset; 466183724Ssos ch->r_io[ATA_SERROR].res = ctlr->r_res2; 467183724Ssos ch->r_io[ATA_SERROR].offset = 0x1f08 + offset; 468183724Ssos ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 469183724Ssos ch->r_io[ATA_SCONTROL].offset = 0x1f00 + offset; 470183724Ssos ch->r_io[ATA_SACTIVE].res = ctlr->r_res2; 471183724Ssos ch->r_io[ATA_SACTIVE].offset = 0x1f0c + offset; 472183724Ssos 473183724Ssos ch->hw.status = ata_siiprb_status; 474183724Ssos ch->hw.begin_transaction = ata_siiprb_begin_transaction; 475183724Ssos ch->hw.end_transaction = ata_siiprb_end_transaction; 476183724Ssos ch->hw.command = NULL; /* not used here */ 477183724Ssos ch->hw.softreset = ata_siiprb_softreset; 478183724Ssos ch->hw.pm_read = ata_siiprb_pm_read; 479183724Ssos ch->hw.pm_write = ata_siiprb_pm_write; 480203525Smav ch->flags |= ATA_NO_SLAVE; 481203525Smav ch->flags |= ATA_SATA; 482183724Ssos return 0; 483183724Ssos} 484183724Ssos 485183724Ssosstatic int 486188769Smavata_siiprb_ch_detach(device_t dev) 487188769Smav{ 488188769Smav 489188769Smav ata_dmafini(dev); 490188769Smav return 0; 491188769Smav} 492188769Smav 493188769Smavstatic int 494183724Ssosata_siiprb_status(device_t dev) 495183724Ssos{ 496183724Ssos struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 497183724Ssos struct ata_channel *ch = device_get_softc(dev); 498183724Ssos u_int32_t action = ATA_INL(ctlr->r_res1, 0x0044); 499183724Ssos int offset = ch->unit * 0x2000; 500183724Ssos 501183724Ssos if (action & (1 << ch->unit)) { 502183724Ssos u_int32_t istatus = ATA_INL(ctlr->r_res2, 0x1008 + offset); 503183724Ssos 504183724Ssos /* do we have any PHY events ? */ 505183724Ssos ata_sata_phy_check_events(dev); 506183724Ssos 507183724Ssos /* clear interrupt(s) */ 508183724Ssos ATA_OUTL(ctlr->r_res2, 0x1008 + offset, istatus); 509183724Ssos 510183724Ssos /* do we have any device action ? */ 511183724Ssos return (istatus & 0x00000003); 512183724Ssos } 513183724Ssos return 0; 514183724Ssos} 515183724Ssos 516183724Ssosstatic int 517183724Ssosata_siiprb_begin_transaction(struct ata_request *request) 518183724Ssos{ 519198717Smav struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent)); 520183724Ssos struct ata_channel *ch = device_get_softc(request->parent); 521183724Ssos struct ata_siiprb_command *prb; 522183724Ssos struct ata_siiprb_dma_prdentry *prd; 523183724Ssos int offset = ch->unit * 0x2000; 524183724Ssos u_int64_t prb_bus; 525183724Ssos 526183724Ssos /* SOS XXX */ 527183724Ssos if (request->u.ata.command == ATA_DEVICE_RESET) { 528183724Ssos request->result = 0; 529183724Ssos return ATA_OP_FINISHED; 530183724Ssos } 531183724Ssos 532183724Ssos /* get a piece of the workspace for this request */ 533198717Smav prb = (struct ata_siiprb_command *)ch->dma.work; 534183724Ssos 535183724Ssos /* clear the prb structure */ 536183724Ssos bzero(prb, sizeof(struct ata_siiprb_command)); 537183724Ssos 538183724Ssos /* setup the FIS for this request */ 539183724Ssos if (!ata_request2fis_h2d(request, &prb->fis[0])) { 540198717Smav device_printf(request->parent, "setting up SATA FIS failed\n"); 541183724Ssos request->result = EIO; 542183724Ssos return ATA_OP_FINISHED; 543183724Ssos } 544183724Ssos 545183724Ssos /* setup transfer type */ 546183724Ssos if (request->flags & ATA_R_ATAPI) { 547183724Ssos bcopy(request->u.atapi.ccb, prb->u.atapi.ccb, 16); 548198717Smav if (request->flags & ATA_R_ATAPI16) 549198717Smav ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000020); 550198717Smav else 551183724Ssos ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000020); 552183724Ssos if (request->flags & ATA_R_READ) 553183724Ssos prb->control = htole16(0x0010); 554183724Ssos if (request->flags & ATA_R_WRITE) 555183724Ssos prb->control = htole16(0x0020); 556183724Ssos prd = &prb->u.atapi.prd[0]; 557183724Ssos } 558183724Ssos else 559183724Ssos prd = &prb->u.ata.prd[0]; 560183724Ssos 561183724Ssos /* if request moves data setup and load SG list */ 562183724Ssos if (request->flags & (ATA_R_READ | ATA_R_WRITE)) { 563183724Ssos if (ch->dma.load(request, prd, NULL)) { 564198717Smav device_printf(request->parent, "setting up DMA failed\n"); 565183724Ssos request->result = EIO; 566183724Ssos return ATA_OP_FINISHED; 567183724Ssos } 568183724Ssos } 569183724Ssos 570183724Ssos /* activate the prb */ 571198717Smav prb_bus = ch->dma.work_bus; 572198717Smav ATA_OUTL(ctlr->r_res2, 0x1c00 + offset, prb_bus); 573198717Smav ATA_OUTL(ctlr->r_res2, 0x1c04 + offset, prb_bus>>32); 574183724Ssos 575183724Ssos /* start the timeout */ 576183724Ssos callout_reset(&request->callout, request->timeout * hz, 577183724Ssos (timeout_t*)ata_timeout, request); 578183724Ssos return ATA_OP_CONTINUES; 579183724Ssos} 580183724Ssos 581183724Ssosstatic int 582183724Ssosata_siiprb_end_transaction(struct ata_request *request) 583183724Ssos{ 584198717Smav struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent)); 585183724Ssos struct ata_channel *ch = device_get_softc(request->parent); 586183724Ssos struct ata_siiprb_command *prb; 587183724Ssos int offset = ch->unit * 0x2000; 588183724Ssos int error, timeout; 589183724Ssos 590183724Ssos /* kill the timeout */ 591183724Ssos callout_stop(&request->callout); 592183724Ssos 593183724Ssos prb = (struct ata_siiprb_command *) 594198717Smav ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset); 595183724Ssos 596183724Ssos /* any controller errors flagged ? */ 597183724Ssos if ((error = ATA_INL(ctlr->r_res2, 0x1024 + offset))) { 598183724Ssos if (bootverbose) 599183724Ssos printf("ata_siiprb_end_transaction %s error=%08x\n", 600183724Ssos ata_cmd2str(request), error); 601183724Ssos 602183724Ssos /* if device error status get details */ 603183724Ssos if (error == 1 || error == 2) { 604183724Ssos request->status = prb->fis[2]; 605183724Ssos if (request->status & ATA_S_ERROR) 606183724Ssos request->error = prb->fis[3]; 607183724Ssos } 608183724Ssos 609183724Ssos /* SOS XXX handle other controller errors here */ 610183724Ssos 611183724Ssos /* initialize port */ 612183724Ssos ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000004); 613183724Ssos 614183724Ssos /* poll for port ready */ 615183724Ssos for (timeout = 0; timeout < 1000; timeout++) { 616183724Ssos DELAY(1000); 617183724Ssos if (ATA_INL(ctlr->r_res2, 0x1008 + offset) & 0x00040000) 618183724Ssos break; 619183724Ssos } 620183724Ssos if (bootverbose) { 621183724Ssos if (timeout >= 1000) 622183724Ssos device_printf(ch->dev, "port initialize timeout\n"); 623183724Ssos else 624183724Ssos device_printf(ch->dev, "port initialize time=%dms\n", timeout); 625183724Ssos } 626183724Ssos } 627183724Ssos 628183724Ssos /* on control commands read back registers to the request struct */ 629183724Ssos if (request->flags & ATA_R_CONTROL) { 630183724Ssos request->u.ata.count = prb->fis[12] | ((u_int16_t)prb->fis[13] << 8); 631183724Ssos request->u.ata.lba = prb->fis[4] | ((u_int64_t)prb->fis[5] << 8) | 632183724Ssos ((u_int64_t)prb->fis[6] << 16); 633198717Smav if (request->flags & ATA_R_48BIT) 634183724Ssos request->u.ata.lba |= ((u_int64_t)prb->fis[8] << 24) | 635183724Ssos ((u_int64_t)prb->fis[9] << 32) | 636183724Ssos ((u_int64_t)prb->fis[10] << 40); 637183724Ssos else 638183724Ssos request->u.ata.lba |= ((u_int64_t)(prb->fis[7] & 0x0f) << 24); 639183724Ssos } 640183724Ssos 641183724Ssos /* update progress */ 642183724Ssos if (!(request->status & ATA_S_ERROR) && !(request->flags & ATA_R_TIMEOUT)) { 643183724Ssos if (request->flags & ATA_R_READ) 644183724Ssos request->donecount = prb->transfer_count; 645183724Ssos else 646183724Ssos request->donecount = request->bytecount; 647183724Ssos } 648183724Ssos 649183724Ssos /* release SG list etc */ 650183724Ssos ch->dma.unload(request); 651183724Ssos 652183724Ssos return ATA_OP_FINISHED; 653183724Ssos} 654183724Ssos 655183724Ssosstatic int 656183724Ssosata_siiprb_issue_cmd(device_t dev) 657183724Ssos{ 658183724Ssos struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 659183724Ssos struct ata_channel *ch = device_get_softc(dev); 660183724Ssos u_int64_t prb_bus = ch->dma.work_bus; 661183724Ssos u_int32_t status; 662183724Ssos int offset = ch->unit * 0x2000; 663183724Ssos int timeout; 664183724Ssos 665183724Ssos /* issue command to chip */ 666183724Ssos ATA_OUTL(ctlr->r_res2, 0x1c00 + offset, prb_bus); 667183724Ssos ATA_OUTL(ctlr->r_res2, 0x1c04 + offset, prb_bus >> 32); 668183724Ssos 669183724Ssos /* poll for command finished */ 670183724Ssos for (timeout = 0; timeout < 10000; timeout++) { 671183724Ssos DELAY(1000); 672183724Ssos if ((status = ATA_INL(ctlr->r_res2, 0x1008 + offset)) & 0x00010000) 673183724Ssos break; 674183724Ssos } 675183724Ssos // SOS XXX ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x00010000); 676183724Ssos ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x08ff08ff); 677183724Ssos 678183724Ssos if (timeout >= 1000) 679183724Ssos return EIO; 680183724Ssos 681183724Ssos if (bootverbose) 682183724Ssos device_printf(dev, "siiprb_issue_cmd time=%dms status=%08x\n", 683183724Ssos timeout, status); 684183724Ssos return 0; 685183724Ssos} 686183724Ssos 687183724Ssosstatic int 688183724Ssosata_siiprb_pm_read(device_t dev, int port, int reg, u_int32_t *result) 689183724Ssos{ 690183724Ssos struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 691183724Ssos struct ata_channel *ch = device_get_softc(dev); 692183724Ssos struct ata_siiprb_command *prb = (struct ata_siiprb_command *)ch->dma.work; 693183724Ssos int offset = ch->unit * 0x2000; 694183724Ssos 695183724Ssos bzero(prb, sizeof(struct ata_siiprb_command)); 696183724Ssos prb->fis[0] = 0x27; /* host to device */ 697183724Ssos prb->fis[1] = 0x8f; /* command FIS to PM port */ 698183724Ssos prb->fis[2] = ATA_READ_PM; 699183724Ssos prb->fis[3] = reg; 700183724Ssos prb->fis[7] = port; 701183724Ssos if (ata_siiprb_issue_cmd(dev)) { 702183724Ssos device_printf(dev, "error reading PM port\n"); 703183724Ssos return EIO; 704183724Ssos } 705183724Ssos prb = (struct ata_siiprb_command *) 706183724Ssos ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset); 707183724Ssos *result = prb->fis[12]|(prb->fis[4]<<8)|(prb->fis[5]<<16)|(prb->fis[6]<<24); 708183724Ssos return 0; 709183724Ssos} 710183724Ssos 711183724Ssosstatic int 712183724Ssosata_siiprb_pm_write(device_t dev, int port, int reg, u_int32_t value) 713183724Ssos{ 714183724Ssos struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 715183724Ssos struct ata_channel *ch = device_get_softc(dev); 716183724Ssos struct ata_siiprb_command *prb = (struct ata_siiprb_command *)ch->dma.work; 717183724Ssos int offset = ch->unit * 0x2000; 718183724Ssos 719183724Ssos bzero(prb, sizeof(struct ata_siiprb_command)); 720183724Ssos prb->fis[0] = 0x27; /* host to device */ 721183724Ssos prb->fis[1] = 0x8f; /* command FIS to PM port */ 722183724Ssos prb->fis[2] = ATA_WRITE_PM; 723183724Ssos prb->fis[3] = reg; 724183724Ssos prb->fis[7] = port; 725183724Ssos prb->fis[12] = value & 0xff; 726201758Smbr prb->fis[4] = (value >> 8) & 0xff; 727201758Smbr prb->fis[5] = (value >> 16) & 0xff; 728201758Smbr prb->fis[6] = (value >> 24) & 0xff; 729183724Ssos if (ata_siiprb_issue_cmd(dev)) { 730183724Ssos device_printf(dev, "error writing PM port\n"); 731183724Ssos return ATA_E_ABORT; 732183724Ssos } 733183724Ssos prb = (struct ata_siiprb_command *) 734183724Ssos ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset); 735183724Ssos return prb->fis[3]; 736183724Ssos} 737183724Ssos 738183724Ssosstatic u_int32_t 739183724Ssosata_siiprb_softreset(device_t dev, int port) 740183724Ssos{ 741183724Ssos struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 742183724Ssos struct ata_channel *ch = device_get_softc(dev); 743183724Ssos struct ata_siiprb_command *prb = (struct ata_siiprb_command *)ch->dma.work; 744183724Ssos u_int32_t signature; 745183724Ssos int offset = ch->unit * 0x2000; 746183724Ssos 747183724Ssos /* setup the workspace for a soft reset command */ 748183724Ssos bzero(prb, sizeof(struct ata_siiprb_command)); 749183724Ssos prb->control = htole16(0x0080); 750183724Ssos prb->fis[1] = port & 0x0f; 751183724Ssos 752183724Ssos /* issue soft reset */ 753183724Ssos if (ata_siiprb_issue_cmd(dev)) 754183724Ssos return -1; 755183724Ssos 756183724Ssos ata_udelay(150000); 757183724Ssos 758183724Ssos /* get possible signature */ 759183724Ssos prb = (struct ata_siiprb_command *) 760183724Ssos ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset); 761183724Ssos signature=prb->fis[12]|(prb->fis[4]<<8)|(prb->fis[5]<<16)|(prb->fis[6]<<24); 762183724Ssos 763183724Ssos /* clear error bits/interrupt */ 764183724Ssos ATA_IDX_OUTL(ch, ATA_SERROR, 0xffffffff); 765183724Ssos 766183724Ssos return signature; 767183724Ssos} 768183724Ssos 769183724Ssosstatic void 770183724Ssosata_siiprb_reset(device_t dev) 771183724Ssos{ 772183724Ssos struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 773183724Ssos struct ata_channel *ch = device_get_softc(dev); 774183724Ssos int offset = ch->unit * 0x2000; 775183724Ssos u_int32_t status, signature; 776183724Ssos int timeout; 777183724Ssos 778183724Ssos /* disable interrupts */ 779183724Ssos ATA_OUTL(ctlr->r_res2, 0x1014 + offset, 0x000000ff); 780183724Ssos 781183724Ssos /* reset channel HW */ 782183724Ssos ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000001); 783183724Ssos DELAY(1000); 784183724Ssos ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000001); 785183724Ssos DELAY(10000); 786183724Ssos 787183724Ssos /* poll for channel ready */ 788183724Ssos for (timeout = 0; timeout < 1000; timeout++) { 789183724Ssos if ((status = ATA_INL(ctlr->r_res2, 0x1008 + offset)) & 0x00040000) 790183724Ssos break; 791183724Ssos DELAY(1000); 792183724Ssos } 793183724Ssos 794183724Ssos if (bootverbose) { 795183724Ssos if (timeout >= 1000) 796183724Ssos device_printf(dev, "channel HW reset timeout\n"); 797183724Ssos else 798183724Ssos device_printf(dev, "channel HW reset time=%dms\n", timeout); 799183724Ssos } 800183724Ssos 801183724Ssos /* reset phy */ 802190581Smav if (!ata_sata_phy_reset(dev, -1, 1)) { 803183724Ssos if (bootverbose) 804183724Ssos device_printf(dev, "phy reset found no device\n"); 805183724Ssos ch->devices = 0; 806183724Ssos goto finish; 807183724Ssos } 808183724Ssos 809183724Ssos /* issue soft reset */ 810183724Ssos signature = ata_siiprb_softreset(dev, ATA_PM); 811183724Ssos if (bootverbose) 812183724Ssos device_printf(dev, "SIGNATURE=%08x\n", signature); 813183724Ssos 814183724Ssos /* figure out whats there */ 815188906Smav switch (signature >> 16) { 816188906Smav case 0x0000: 817183724Ssos ch->devices = ATA_ATA_MASTER; 818183724Ssos break; 819188906Smav case 0x9669: 820183724Ssos ch->devices = ATA_PORTMULTIPLIER; 821183724Ssos ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x2000); /* enable PM support */ 822183724Ssos //SOS XXX need to clear all PM status and interrupts!!!! 823183724Ssos ata_pm_identify(dev); 824183724Ssos break; 825188906Smav case 0xeb14: 826183724Ssos ch->devices = ATA_ATAPI_MASTER; 827183724Ssos break; 828183724Ssos default: 829183724Ssos ch->devices = 0; 830183724Ssos } 831183724Ssos if (bootverbose) 832183724Ssos device_printf(dev, "siiprb_reset devices=%08x\n", ch->devices); 833183724Ssos 834183724Ssosfinish: 835183724Ssos /* clear interrupt(s) */ 836183724Ssos ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x000008ff); 837183724Ssos 838183724Ssos /* require explicit interrupt ack */ 839183724Ssos ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000008); 840183724Ssos 841183724Ssos /* 64bit mode */ 842183724Ssos ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000400); 843183724Ssos 844183724Ssos /* enable interrupts wanted */ 845183724Ssos ATA_OUTL(ctlr->r_res2, 0x1010 + offset, 0x000000ff); 846183724Ssos} 847183724Ssos 848183724Ssosstatic void 849183724Ssosata_siiprb_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 850183724Ssos{ 851183724Ssos struct ata_dmasetprd_args *args = xsc; 852183724Ssos struct ata_siiprb_dma_prdentry *prd = args->dmatab; 853183724Ssos int i; 854183724Ssos 855183724Ssos if ((args->error = error)) 856183724Ssos return; 857183724Ssos 858183724Ssos for (i = 0; i < nsegs; i++) { 859183724Ssos prd[i].addr = htole64(segs[i].ds_addr); 860183724Ssos prd[i].count = htole32(segs[i].ds_len); 861183724Ssos } 862183724Ssos prd[i - 1].control = htole32(ATA_DMA_EOT); 863183724Ssos KASSERT(nsegs <= ATA_SIIPRB_DMA_ENTRIES,("too many DMA segment entries\n")); 864183724Ssos args->nsegs = nsegs; 865183724Ssos} 866183724Ssos 867183724Ssosstatic void 868183724Ssosata_siiprb_dmainit(device_t dev) 869183724Ssos{ 870183724Ssos struct ata_channel *ch = device_get_softc(dev); 871183724Ssos 872183724Ssos ata_dmainit(dev); 873183724Ssos /* note start and stop are not used here */ 874183724Ssos ch->dma.setprd = ata_siiprb_dmasetprd; 875183724Ssos ch->dma.max_address = BUS_SPACE_MAXADDR; 876198717Smav ch->dma.max_iosize = (ATA_SIIPRB_DMA_ENTRIES - 1) * PAGE_SIZE; 877183724Ssos} 878183724Ssos 879183724SsosATA_DECLARE_DRIVER(ata_sii); 880