ata-siliconimage.c revision 209872
1219974Smav/*- 2219974Smav * Copyright (c) 1998 - 2008 S�ren Schmidt <sos@FreeBSD.org> 3219974Smav * All rights reserved. 4219974Smav * 5219974Smav * Redistribution and use in source and binary forms, with or without 6219974Smav * modification, are permitted provided that the following conditions 7219974Smav * are met: 8219974Smav * 1. Redistributions of source code must retain the above copyright 9219974Smav * notice, this list of conditions and the following disclaimer, 10219974Smav * without modification, immediately at the beginning of the file. 11219974Smav * 2. Redistributions in binary form must reproduce the above copyright 12219974Smav * notice, this list of conditions and the following disclaimer in the 13219974Smav * documentation and/or other materials provided with the distribution. 14219974Smav * 15219974Smav * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16219974Smav * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17219974Smav * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18219974Smav * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19219974Smav * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20219974Smav * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21219974Smav * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22219974Smav * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23219974Smav * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24219974Smav * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25219974Smav */ 26219974Smav 27219974Smav#include <sys/cdefs.h> 28219974Smav__FBSDID("$FreeBSD: head/sys/dev/ata/chipsets/ata-siliconimage.c 209872 2010-07-10 13:46:14Z mav $"); 29219974Smav 30219974Smav#include "opt_ata.h" 31219974Smav#include <sys/param.h> 32219974Smav#include <sys/module.h> 33219974Smav#include <sys/systm.h> 34219974Smav#include <sys/kernel.h> 35219974Smav#include <sys/ata.h> 36219974Smav#include <sys/bus.h> 37219974Smav#include <sys/endian.h> 38219974Smav#include <sys/malloc.h> 39219974Smav#include <sys/lock.h> 40219974Smav#include <sys/mutex.h> 41219974Smav#include <sys/sema.h> 42219974Smav#include <sys/taskqueue.h> 43219974Smav#include <vm/uma.h> 44219974Smav#include <machine/stdarg.h> 45219974Smav#include <machine/resource.h> 46219974Smav#include <machine/bus.h> 47219974Smav#include <sys/rman.h> 48219974Smav#include <dev/pci/pcivar.h> 49219974Smav#include <dev/pci/pcireg.h> 50219974Smav#include <dev/ata/ata-all.h> 51219974Smav#include <dev/ata/ata-pci.h> 52219974Smav#include <ata_if.h> 53219974Smav 54242649Smav/* local prototypes */ 55242649Smavstatic int ata_cmd_ch_attach(device_t dev); 56219974Smavstatic int ata_cmd_status(device_t dev); 57242649Smavstatic int ata_cmd_setmode(device_t dev, int target, int mode); 58219974Smavstatic int ata_sii_ch_attach(device_t dev); 59219974Smavstatic int ata_sii_ch_detach(device_t dev); 60219974Smavstatic int ata_sii_status(device_t dev); 61219974Smavstatic void ata_sii_reset(device_t dev); 62219974Smavstatic int ata_sii_setmode(device_t dev, int target, int mode); 63219974Smavstatic int ata_siiprb_ch_attach(device_t dev); 64219974Smavstatic int ata_siiprb_ch_detach(device_t dev); 65219974Smavstatic int ata_siiprb_status(device_t dev); 66219974Smavstatic int ata_siiprb_begin_transaction(struct ata_request *request); 67242649Smavstatic int ata_siiprb_end_transaction(struct ata_request *request); 68242649Smavstatic int ata_siiprb_pm_read(device_t dev, int port, int reg, u_int32_t *result); 69242649Smavstatic int ata_siiprb_pm_write(device_t dev, int port, int reg, u_int32_t result); 70242649Smavstatic u_int32_t ata_siiprb_softreset(device_t dev, int port); 71242649Smavstatic void ata_siiprb_reset(device_t dev); 72242649Smavstatic void ata_siiprb_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 73242649Smavstatic void ata_siiprb_dmainit(device_t dev); 74242649Smav 75242649Smav/* misc defines */ 76242649Smav#define SII_MEMIO 1 77242649Smav#define SII_PRBIO 2 78242649Smav#define SII_INTR 0x01 79242649Smav#define SII_SETCLK 0x02 80242649Smav#define SII_BUG 0x04 81242649Smav#define SII_4CH 0x08 82242649Smav 83242649Smav 84242649Smav/* 85242649Smav * Silicon Image Inc. (SiI) (former CMD) chipset support functions 86242649Smav */ 87242649Smavstatic int 88242649Smavata_sii_probe(device_t dev) 89242649Smav{ 90242649Smav struct ata_pci_controller *ctlr = device_get_softc(dev); 91242649Smav static struct ata_chip_id ids[] = 92242649Smav {{ ATA_SII3114, 0x00, SII_MEMIO, SII_4CH, ATA_SA150, "3114" }, 93242649Smav { ATA_SII3512, 0x02, SII_MEMIO, 0, ATA_SA150, "3512" }, 94242649Smav { ATA_SII3112, 0x02, SII_MEMIO, 0, ATA_SA150, "3112" }, 95242649Smav { ATA_SII3112_1, 0x02, SII_MEMIO, 0, ATA_SA150, "3112" }, 96219974Smav { ATA_SII3512, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "3512" }, 97219974Smav { ATA_SII3112, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "3112" }, 98219974Smav { ATA_SII3112_1, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "3112" }, 99219974Smav { ATA_SII3124, 0x00, SII_PRBIO, SII_4CH, ATA_SA300, "3124" }, 100219974Smav { ATA_SII3132, 0x00, SII_PRBIO, 0, ATA_SA300, "3132" }, 101219974Smav { ATA_SII3132_1, 0x00, SII_PRBIO, 0, ATA_SA300, "3132" }, 102219974Smav { ATA_SII3132_2, 0x00, SII_PRBIO, 0, ATA_SA300, "3132" }, 103219974Smav { ATA_SII0680, 0x00, SII_MEMIO, SII_SETCLK, ATA_UDMA6, "680" }, 104219974Smav { ATA_CMD649, 0x00, 0, SII_INTR, ATA_UDMA5, "(CMD) 649" }, 105219974Smav { ATA_CMD648, 0x00, 0, SII_INTR, ATA_UDMA4, "(CMD) 648" }, 106219974Smav { ATA_CMD646, 0x07, 0, 0, ATA_UDMA2, "(CMD) 646U2" }, 107219974Smav { ATA_CMD646, 0x00, 0, 0, ATA_WDMA2, "(CMD) 646" }, 108219974Smav { 0, 0, 0, 0, 0, 0}}; 109219974Smav 110219974Smav if (pci_get_vendor(dev) != ATA_SILICON_IMAGE_ID) 111219974Smav return ENXIO; 112219974Smav 113219974Smav if (!(ctlr->chip = ata_match_chip(dev, ids))) 114219974Smav return ENXIO; 115219974Smav 116219974Smav ata_set_desc(dev); 117219974Smav ctlr->chipinit = ata_sii_chipinit; 118219974Smav return (BUS_PROBE_DEFAULT); 119219974Smav} 120219974Smav 121219974Smavint 122219974Smavata_sii_chipinit(device_t dev) 123235874Smav{ 124219974Smav struct ata_pci_controller *ctlr = device_get_softc(dev); 125219974Smav 126219974Smav if (ata_setup_interrupt(dev, ata_generic_intr)) 127219974Smav return ENXIO; 128219974Smav 129219974Smav switch (ctlr->chip->cfg1) { 130219974Smav case SII_PRBIO: 131219974Smav ctlr->r_type1 = SYS_RES_MEMORY; 132219974Smav ctlr->r_rid1 = PCIR_BAR(0); 133219974Smav if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1, 134219974Smav &ctlr->r_rid1, RF_ACTIVE))) 135219974Smav return ENXIO; 136219974Smav 137219974Smav ctlr->r_rid2 = PCIR_BAR(2); 138219974Smav ctlr->r_type2 = SYS_RES_MEMORY; 139219974Smav if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 140219974Smav &ctlr->r_rid2, RF_ACTIVE))){ 141219974Smav bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1,ctlr->r_res1); 142219974Smav return ENXIO; 143219974Smav } 144219974Smav ctlr->ch_attach = ata_siiprb_ch_attach; 145219974Smav ctlr->ch_detach = ata_siiprb_ch_detach; 146219974Smav ctlr->reset = ata_siiprb_reset; 147219974Smav ctlr->setmode = ata_sata_setmode; 148219974Smav ctlr->getrev = ata_sata_getrev; 149219974Smav ctlr->channels = (ctlr->chip->cfg2 == SII_4CH) ? 4 : 2; 150219974Smav 151219974Smav /* reset controller */ 152219974Smav ATA_OUTL(ctlr->r_res1, 0x0040, 0x80000000); 153219974Smav DELAY(10000); 154219974Smav ATA_OUTL(ctlr->r_res1, 0x0040, 0x0000000f); 155219974Smav break; 156219974Smav 157219974Smav case SII_MEMIO: 158219974Smav ctlr->r_type2 = SYS_RES_MEMORY; 159219974Smav ctlr->r_rid2 = PCIR_BAR(5); 160219974Smav if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 161219974Smav &ctlr->r_rid2, RF_ACTIVE))){ 162219974Smav if (ctlr->chip->chipid != ATA_SII0680 || 163219974Smav (pci_read_config(dev, 0x8a, 1) & 1)) 164219974Smav return ENXIO; 165219974Smav } 166219974Smav 167219974Smav if (ctlr->chip->cfg2 & SII_SETCLK) { 168219974Smav if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10) 169219974Smav pci_write_config(dev, 0x8a, 170219974Smav (pci_read_config(dev, 0x8a, 1) & 0xcf)|0x10,1); 171219974Smav if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10) 172219974Smav device_printf(dev, "%s could not set ATA133 clock\n", 173219974Smav ctlr->chip->text); 174219974Smav } 175219974Smav 176219974Smav /* if we have 4 channels enable the second set */ 177219974Smav if (ctlr->chip->cfg2 & SII_4CH) { 178219974Smav ATA_OUTL(ctlr->r_res2, 0x0200, 0x00000002); 179219974Smav ctlr->channels = 4; 180219974Smav } 181219974Smav 182219974Smav /* dont block interrupts from any channel */ 183219974Smav pci_write_config(dev, 0x48, 184255563Smav (pci_read_config(dev, 0x48, 4) & ~0x03c00000), 4); 185219974Smav 186219974Smav /* enable PCI interrupt as BIOS might not */ 187219974Smav pci_write_config(dev, 0x8a, (pci_read_config(dev, 0x8a, 1) & 0x3f), 1); 188219974Smav 189219974Smav if (ctlr->r_res2) { 190219974Smav ctlr->ch_attach = ata_sii_ch_attach; 191219974Smav ctlr->ch_detach = ata_sii_ch_detach; 192219974Smav } 193219974Smav 194219974Smav if (ctlr->chip->max_dma >= ATA_SA150) { 195219974Smav ctlr->reset = ata_sii_reset; 196219974Smav ctlr->setmode = ata_sata_setmode; 197219974Smav ctlr->getrev = ata_sata_getrev; 198219974Smav } 199219974Smav else 200219974Smav ctlr->setmode = ata_sii_setmode; 201219974Smav break; 202219974Smav 203219974Smav default: 204219974Smav if ((pci_read_config(dev, 0x51, 1) & 0x08) != 0x08) { 205219974Smav device_printf(dev, "HW has secondary channel disabled\n"); 206219974Smav ctlr->channels = 1; 207219974Smav } 208219974Smav 209219974Smav /* enable interrupt as BIOS might not */ 210219974Smav pci_write_config(dev, 0x71, 0x01, 1); 211219974Smav 212219974Smav ctlr->ch_attach = ata_cmd_ch_attach; 213219974Smav ctlr->ch_detach = ata_pci_ch_detach; 214219974Smav ctlr->setmode = ata_cmd_setmode; 215219974Smav break; 216219974Smav } 217219974Smav return 0; 218219974Smav} 219219974Smav 220219974Smavstatic int 221219974Smavata_cmd_ch_attach(device_t dev) 222219974Smav{ 223219974Smav struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 224219974Smav struct ata_channel *ch = device_get_softc(dev); 225219974Smav 226219974Smav /* setup the usual register normal pci style */ 227219974Smav if (ata_pci_ch_attach(dev)) 228219974Smav return ENXIO; 229219974Smav 230219974Smav if (ctlr->chip->cfg2 & SII_INTR) 231219974Smav ch->hw.status = ata_cmd_status; 232219974Smav 233219974Smav return 0; 234219974Smav} 235219974Smav 236219974Smavstatic int 237219974Smavata_cmd_status(device_t dev) 238219974Smav{ 239219974Smav struct ata_channel *ch = device_get_softc(dev); 240219974Smav u_int8_t reg71; 241219974Smav 242219974Smav if (((reg71 = pci_read_config(device_get_parent(dev), 0x71, 1)) & 243219974Smav (ch->unit ? 0x08 : 0x04))) { 244219974Smav pci_write_config(device_get_parent(dev), 0x71, 245219974Smav reg71 & ~(ch->unit ? 0x04 : 0x08), 1); 246219974Smav return ata_pci_status(dev); 247219974Smav } 248219974Smav return 0; 249219974Smav} 250 251static int 252ata_cmd_setmode(device_t dev, int target, int mode) 253{ 254 device_t parent = device_get_parent(dev); 255 struct ata_pci_controller *ctlr = device_get_softc(parent); 256 struct ata_channel *ch = device_get_softc(dev); 257 int devno = (ch->unit << 1) + target; 258 int treg = 0x54 + ((devno < 3) ? (devno << 1) : 7); 259 int ureg = ch->unit ? 0x7b : 0x73; 260 int piomode; 261 uint8_t piotimings[] = { 0xa9, 0x57, 0x44, 0x32, 0x3f, 0x87, 0x32, 0x3f }; 262 uint8_t udmatimings[][2] = { { 0x31, 0xc2 }, { 0x21, 0x82 }, 263 { 0x11, 0x42 }, { 0x25, 0x8a }, 264 { 0x15, 0x4a }, { 0x05, 0x0a } }; 265 266 mode = min(mode, ctlr->chip->max_dma); 267 if (mode >= ATA_UDMA0) { 268 u_int8_t umode = pci_read_config(parent, ureg, 1); 269 270 umode &= ~(target == 0 ? 0x35 : 0xca); 271 umode |= udmatimings[mode & ATA_MODE_MASK][target]; 272 pci_write_config(parent, ureg, umode, 1); 273 piomode = ATA_PIO4; 274 } else { 275 pci_write_config(parent, ureg, 276 pci_read_config(parent, ureg, 1) & 277 ~(target == 0 ? 0x35 : 0xca), 1); 278 piomode = mode; 279 } 280 pci_write_config(parent, treg, piotimings[ata_mode2idx(piomode)], 1); 281 return (mode); 282} 283 284static int 285ata_sii_ch_attach(device_t dev) 286{ 287 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 288 struct ata_channel *ch = device_get_softc(dev); 289 int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2); 290 int i; 291 292 ata_pci_dmainit(dev); 293 294 for (i = ATA_DATA; i <= ATA_COMMAND; i++) { 295 ch->r_io[i].res = ctlr->r_res2; 296 ch->r_io[i].offset = 0x80 + i + (unit01 << 6) + (unit10 << 8); 297 } 298 ch->r_io[ATA_CONTROL].res = ctlr->r_res2; 299 ch->r_io[ATA_CONTROL].offset = 0x8a + (unit01 << 6) + (unit10 << 8); 300 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2; 301 ata_default_registers(dev); 302 303 ch->r_io[ATA_BMCMD_PORT].res = ctlr->r_res2; 304 ch->r_io[ATA_BMCMD_PORT].offset = 0x00 + (unit01 << 3) + (unit10 << 8); 305 ch->r_io[ATA_BMSTAT_PORT].res = ctlr->r_res2; 306 ch->r_io[ATA_BMSTAT_PORT].offset = 0x02 + (unit01 << 3) + (unit10 << 8); 307 ch->r_io[ATA_BMDTP_PORT].res = ctlr->r_res2; 308 ch->r_io[ATA_BMDTP_PORT].offset = 0x04 + (unit01 << 3) + (unit10 << 8); 309 310 if (ctlr->chip->max_dma >= ATA_SA150) { 311 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 312 ch->r_io[ATA_SSTATUS].offset = 0x104 + (unit01 << 7) + (unit10 << 8); 313 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 314 ch->r_io[ATA_SERROR].offset = 0x108 + (unit01 << 7) + (unit10 << 8); 315 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 316 ch->r_io[ATA_SCONTROL].offset = 0x100 + (unit01 << 7) + (unit10 << 8); 317 ch->flags |= ATA_NO_SLAVE; 318 ch->flags |= ATA_SATA; 319 320 /* enable PHY state change interrupt */ 321 ATA_OUTL(ctlr->r_res2, 0x148 + (unit01 << 7) + (unit10 << 8),(1 << 16)); 322 } 323 324 if (ctlr->chip->cfg2 & SII_BUG) { 325 /* work around errata in early chips */ 326 ch->dma.boundary = 8192; 327 ch->dma.segsize = 15 * DEV_BSIZE; 328 } 329 330 ata_pci_hw(dev); 331 ch->hw.status = ata_sii_status; 332 if (ctlr->chip->cfg2 & SII_SETCLK) 333 ch->flags |= ATA_CHECKS_CABLE; 334 return 0; 335} 336 337static int 338ata_sii_ch_detach(device_t dev) 339{ 340 341 ata_pci_dmafini(dev); 342 return (0); 343} 344 345static int 346ata_sii_status(device_t dev) 347{ 348 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 349 struct ata_channel *ch = device_get_softc(dev); 350 int offset0 = ((ch->unit & 1) << 3) + ((ch->unit & 2) << 8); 351 int offset1 = ((ch->unit & 1) << 6) + ((ch->unit & 2) << 8); 352 353 /* do we have any PHY events ? */ 354 if (ctlr->chip->max_dma >= ATA_SA150 && 355 (ATA_INL(ctlr->r_res2, 0x10 + offset0) & 0x00000010)) 356 ata_sata_phy_check_events(dev); 357 358 if (ATA_INL(ctlr->r_res2, 0xa0 + offset1) & 0x00000800) 359 return ata_pci_status(dev); 360 else 361 return 0; 362} 363 364static void 365ata_sii_reset(device_t dev) 366{ 367 if (ata_sata_phy_reset(dev, -1, 1)) 368 ata_generic_reset(dev); 369} 370 371static int 372ata_sii_setmode(device_t dev, int target, int mode) 373{ 374 device_t parent = device_get_parent(dev); 375 struct ata_pci_controller *ctlr = device_get_softc(parent); 376 struct ata_channel *ch = device_get_softc(dev); 377 int rego = (ch->unit << 4) + (target << 1); 378 int mreg = ch->unit ? 0x84 : 0x80; 379 int mask = 0x03 << (target << 2); 380 int mval = pci_read_config(parent, mreg, 1) & ~mask; 381 int piomode; 382 u_int8_t preg = 0xa4 + rego; 383 u_int8_t dreg = 0xa8 + rego; 384 u_int8_t ureg = 0xac + rego; 385 u_int16_t piotimings[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 }; 386 u_int16_t dmatimings[] = { 0x2208, 0x10c2, 0x10c1 }; 387 u_int8_t udmatimings[] = { 0xf, 0xb, 0x7, 0x5, 0x3, 0x2, 0x1 }; 388 389 mode = min(mode, ctlr->chip->max_dma); 390 391 if (ctlr->chip->cfg2 & SII_SETCLK) { 392 if (ata_dma_check_80pin && mode > ATA_UDMA2 && 393 (pci_read_config(parent, 0x79, 1) & 394 (ch->unit ? 0x02 : 0x01))) { 395 ata_print_cable(dev, "controller"); 396 mode = ATA_UDMA2; 397 } 398 } 399 if (mode >= ATA_UDMA0) { 400 pci_write_config(parent, mreg, 401 mval | (0x03 << (target << 2)), 1); 402 pci_write_config(parent, ureg, 403 (pci_read_config(parent, ureg, 1) & ~0x3f) | 404 udmatimings[mode & ATA_MODE_MASK], 1); 405 piomode = ATA_PIO4; 406 } else if (mode >= ATA_WDMA0) { 407 pci_write_config(parent, mreg, 408 mval | (0x02 << (target << 2)), 1); 409 pci_write_config(parent, dreg, dmatimings[mode & ATA_MODE_MASK], 2); 410 piomode = (mode == ATA_WDMA0) ? ATA_PIO0 : 411 (mode == ATA_WDMA1) ? ATA_PIO3 : ATA_PIO4; 412 } else { 413 pci_write_config(parent, mreg, 414 mval | (0x01 << (target << 2)), 1); 415 piomode = mode; 416 } 417 pci_write_config(parent, preg, piotimings[ata_mode2idx(piomode)], 2); 418 return (mode); 419} 420 421 422struct ata_siiprb_dma_prdentry { 423 u_int64_t addr; 424 u_int32_t count; 425 u_int32_t control; 426} __packed; 427 428#define ATA_SIIPRB_DMA_ENTRIES 129 429struct ata_siiprb_ata_command { 430 struct ata_siiprb_dma_prdentry prd[ATA_SIIPRB_DMA_ENTRIES]; 431} __packed; 432 433struct ata_siiprb_atapi_command { 434 u_int8_t ccb[16]; 435 struct ata_siiprb_dma_prdentry prd[ATA_SIIPRB_DMA_ENTRIES]; 436} __packed; 437 438struct ata_siiprb_command { 439 u_int16_t control; 440 u_int16_t protocol_override; 441 u_int32_t transfer_count; 442 u_int8_t fis[24]; 443 union { 444 struct ata_siiprb_ata_command ata; 445 struct ata_siiprb_atapi_command atapi; 446 } u; 447} __packed; 448 449static int 450ata_siiprb_ch_attach(device_t dev) 451{ 452 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 453 struct ata_channel *ch = device_get_softc(dev); 454 int offset = ch->unit * 0x2000; 455 456 ata_siiprb_dmainit(dev); 457 458 /* set the SATA resources */ 459 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 460 ch->r_io[ATA_SSTATUS].offset = 0x1f04 + offset; 461 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 462 ch->r_io[ATA_SERROR].offset = 0x1f08 + offset; 463 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 464 ch->r_io[ATA_SCONTROL].offset = 0x1f00 + offset; 465 ch->r_io[ATA_SACTIVE].res = ctlr->r_res2; 466 ch->r_io[ATA_SACTIVE].offset = 0x1f0c + offset; 467 468 ch->hw.status = ata_siiprb_status; 469 ch->hw.begin_transaction = ata_siiprb_begin_transaction; 470 ch->hw.end_transaction = ata_siiprb_end_transaction; 471 ch->hw.command = NULL; /* not used here */ 472 ch->hw.softreset = ata_siiprb_softreset; 473 ch->hw.pm_read = ata_siiprb_pm_read; 474 ch->hw.pm_write = ata_siiprb_pm_write; 475 ch->flags |= ATA_NO_SLAVE; 476 ch->flags |= ATA_SATA; 477 return 0; 478} 479 480static int 481ata_siiprb_ch_detach(device_t dev) 482{ 483 484 ata_dmafini(dev); 485 return 0; 486} 487 488static int 489ata_siiprb_status(device_t dev) 490{ 491 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 492 struct ata_channel *ch = device_get_softc(dev); 493 u_int32_t action = ATA_INL(ctlr->r_res1, 0x0044); 494 int offset = ch->unit * 0x2000; 495 496 if (action & (1 << ch->unit)) { 497 u_int32_t istatus = ATA_INL(ctlr->r_res2, 0x1008 + offset); 498 499 /* do we have any PHY events ? */ 500 ata_sata_phy_check_events(dev); 501 502 /* clear interrupt(s) */ 503 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, istatus); 504 505 /* do we have any device action ? */ 506 return (istatus & 0x00000003); 507 } 508 return 0; 509} 510 511static int 512ata_siiprb_begin_transaction(struct ata_request *request) 513{ 514 struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent)); 515 struct ata_channel *ch = device_get_softc(request->parent); 516 struct ata_siiprb_command *prb; 517 struct ata_siiprb_dma_prdentry *prd; 518 int offset = ch->unit * 0x2000; 519 u_int64_t prb_bus; 520 521 /* SOS XXX */ 522 if (request->u.ata.command == ATA_DEVICE_RESET) { 523 request->result = 0; 524 return ATA_OP_FINISHED; 525 } 526 527 /* get a piece of the workspace for this request */ 528 prb = (struct ata_siiprb_command *)ch->dma.work; 529 530 /* clear the prb structure */ 531 bzero(prb, sizeof(struct ata_siiprb_command)); 532 533 /* setup the FIS for this request */ 534 if (!ata_request2fis_h2d(request, &prb->fis[0])) { 535 device_printf(request->parent, "setting up SATA FIS failed\n"); 536 request->result = EIO; 537 return ATA_OP_FINISHED; 538 } 539 540 /* setup transfer type */ 541 if (request->flags & ATA_R_ATAPI) { 542 bcopy(request->u.atapi.ccb, prb->u.atapi.ccb, 16); 543 if (request->flags & ATA_R_ATAPI16) 544 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000020); 545 else 546 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000020); 547 if (request->flags & ATA_R_READ) 548 prb->control = htole16(0x0010); 549 if (request->flags & ATA_R_WRITE) 550 prb->control = htole16(0x0020); 551 prd = &prb->u.atapi.prd[0]; 552 } 553 else 554 prd = &prb->u.ata.prd[0]; 555 556 /* if request moves data setup and load SG list */ 557 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) { 558 if (ch->dma.load(request, prd, NULL)) { 559 device_printf(request->parent, "setting up DMA failed\n"); 560 request->result = EIO; 561 return ATA_OP_FINISHED; 562 } 563 } 564 565 /* activate the prb */ 566 prb_bus = ch->dma.work_bus; 567 ATA_OUTL(ctlr->r_res2, 0x1c00 + offset, prb_bus); 568 ATA_OUTL(ctlr->r_res2, 0x1c04 + offset, prb_bus>>32); 569 570 /* start the timeout */ 571 callout_reset(&request->callout, request->timeout * hz, 572 (timeout_t*)ata_timeout, request); 573 return ATA_OP_CONTINUES; 574} 575 576static int 577ata_siiprb_end_transaction(struct ata_request *request) 578{ 579 struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent)); 580 struct ata_channel *ch = device_get_softc(request->parent); 581 struct ata_siiprb_command *prb; 582 int offset = ch->unit * 0x2000; 583 int error, timeout; 584 585 /* kill the timeout */ 586 callout_stop(&request->callout); 587 588 prb = (struct ata_siiprb_command *) 589 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset); 590 591 /* any controller errors flagged ? */ 592 if ((error = ATA_INL(ctlr->r_res2, 0x1024 + offset))) { 593 if (bootverbose) 594 printf("ata_siiprb_end_transaction %s error=%08x\n", 595 ata_cmd2str(request), error); 596 597 /* if device error status get details */ 598 if (error == 1 || error == 2) { 599 request->status = prb->fis[2]; 600 if (request->status & ATA_S_ERROR) 601 request->error = prb->fis[3]; 602 } 603 604 /* SOS XXX handle other controller errors here */ 605 606 /* initialize port */ 607 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000004); 608 609 /* poll for port ready */ 610 for (timeout = 0; timeout < 1000; timeout++) { 611 DELAY(1000); 612 if (ATA_INL(ctlr->r_res2, 0x1008 + offset) & 0x00040000) 613 break; 614 } 615 if (bootverbose) { 616 if (timeout >= 1000) 617 device_printf(ch->dev, "port initialize timeout\n"); 618 else 619 device_printf(ch->dev, "port initialize time=%dms\n", timeout); 620 } 621 } 622 623 /* on control commands read back registers to the request struct */ 624 if (request->flags & ATA_R_CONTROL) { 625 request->u.ata.count = prb->fis[12] | ((u_int16_t)prb->fis[13] << 8); 626 request->u.ata.lba = prb->fis[4] | ((u_int64_t)prb->fis[5] << 8) | 627 ((u_int64_t)prb->fis[6] << 16); 628 if (request->flags & ATA_R_48BIT) 629 request->u.ata.lba |= ((u_int64_t)prb->fis[8] << 24) | 630 ((u_int64_t)prb->fis[9] << 32) | 631 ((u_int64_t)prb->fis[10] << 40); 632 else 633 request->u.ata.lba |= ((u_int64_t)(prb->fis[7] & 0x0f) << 24); 634 } 635 636 /* update progress */ 637 if (!(request->status & ATA_S_ERROR) && !(request->flags & ATA_R_TIMEOUT)) { 638 if (request->flags & ATA_R_READ) 639 request->donecount = prb->transfer_count; 640 else 641 request->donecount = request->bytecount; 642 } 643 644 /* release SG list etc */ 645 ch->dma.unload(request); 646 647 return ATA_OP_FINISHED; 648} 649 650static int 651ata_siiprb_issue_cmd(device_t dev) 652{ 653 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 654 struct ata_channel *ch = device_get_softc(dev); 655 u_int64_t prb_bus = ch->dma.work_bus; 656 u_int32_t status; 657 int offset = ch->unit * 0x2000; 658 int timeout; 659 660 /* issue command to chip */ 661 ATA_OUTL(ctlr->r_res2, 0x1c00 + offset, prb_bus); 662 ATA_OUTL(ctlr->r_res2, 0x1c04 + offset, prb_bus >> 32); 663 664 /* poll for command finished */ 665 for (timeout = 0; timeout < 10000; timeout++) { 666 DELAY(1000); 667 if ((status = ATA_INL(ctlr->r_res2, 0x1008 + offset)) & 0x00010000) 668 break; 669 } 670 // SOS XXX ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x00010000); 671 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x08ff08ff); 672 673 if (timeout >= 1000) 674 return EIO; 675 676 if (bootverbose) 677 device_printf(dev, "siiprb_issue_cmd time=%dms status=%08x\n", 678 timeout, status); 679 return 0; 680} 681 682static int 683ata_siiprb_pm_read(device_t dev, int port, int reg, u_int32_t *result) 684{ 685 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 686 struct ata_channel *ch = device_get_softc(dev); 687 struct ata_siiprb_command *prb = (struct ata_siiprb_command *)ch->dma.work; 688 int offset = ch->unit * 0x2000; 689 690 bzero(prb, sizeof(struct ata_siiprb_command)); 691 prb->fis[0] = 0x27; /* host to device */ 692 prb->fis[1] = 0x8f; /* command FIS to PM port */ 693 prb->fis[2] = ATA_READ_PM; 694 prb->fis[3] = reg; 695 prb->fis[7] = port; 696 if (ata_siiprb_issue_cmd(dev)) { 697 device_printf(dev, "error reading PM port\n"); 698 return EIO; 699 } 700 prb = (struct ata_siiprb_command *) 701 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset); 702 *result = prb->fis[12]|(prb->fis[4]<<8)|(prb->fis[5]<<16)|(prb->fis[6]<<24); 703 return 0; 704} 705 706static int 707ata_siiprb_pm_write(device_t dev, int port, int reg, u_int32_t value) 708{ 709 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 710 struct ata_channel *ch = device_get_softc(dev); 711 struct ata_siiprb_command *prb = (struct ata_siiprb_command *)ch->dma.work; 712 int offset = ch->unit * 0x2000; 713 714 bzero(prb, sizeof(struct ata_siiprb_command)); 715 prb->fis[0] = 0x27; /* host to device */ 716 prb->fis[1] = 0x8f; /* command FIS to PM port */ 717 prb->fis[2] = ATA_WRITE_PM; 718 prb->fis[3] = reg; 719 prb->fis[7] = port; 720 prb->fis[12] = value & 0xff; 721 prb->fis[4] = (value >> 8) & 0xff; 722 prb->fis[5] = (value >> 16) & 0xff; 723 prb->fis[6] = (value >> 24) & 0xff; 724 if (ata_siiprb_issue_cmd(dev)) { 725 device_printf(dev, "error writing PM port\n"); 726 return ATA_E_ABORT; 727 } 728 prb = (struct ata_siiprb_command *) 729 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset); 730 return prb->fis[3]; 731} 732 733static u_int32_t 734ata_siiprb_softreset(device_t dev, int port) 735{ 736 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 737 struct ata_channel *ch = device_get_softc(dev); 738 struct ata_siiprb_command *prb = (struct ata_siiprb_command *)ch->dma.work; 739 u_int32_t signature; 740 int offset = ch->unit * 0x2000; 741 742 /* setup the workspace for a soft reset command */ 743 bzero(prb, sizeof(struct ata_siiprb_command)); 744 prb->control = htole16(0x0080); 745 prb->fis[1] = port & 0x0f; 746 747 /* issue soft reset */ 748 if (ata_siiprb_issue_cmd(dev)) 749 return -1; 750 751 ata_udelay(150000); 752 753 /* get possible signature */ 754 prb = (struct ata_siiprb_command *) 755 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset); 756 signature=prb->fis[12]|(prb->fis[4]<<8)|(prb->fis[5]<<16)|(prb->fis[6]<<24); 757 758 /* clear error bits/interrupt */ 759 ATA_IDX_OUTL(ch, ATA_SERROR, 0xffffffff); 760 761 return signature; 762} 763 764static void 765ata_siiprb_reset(device_t dev) 766{ 767 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 768 struct ata_channel *ch = device_get_softc(dev); 769 int offset = ch->unit * 0x2000; 770 u_int32_t status, signature; 771 int timeout; 772 773 /* disable interrupts */ 774 ATA_OUTL(ctlr->r_res2, 0x1014 + offset, 0x000000ff); 775 776 /* reset channel HW */ 777 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000001); 778 DELAY(1000); 779 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000001); 780 DELAY(10000); 781 782 /* poll for channel ready */ 783 for (timeout = 0; timeout < 1000; timeout++) { 784 if ((status = ATA_INL(ctlr->r_res2, 0x1008 + offset)) & 0x00040000) 785 break; 786 DELAY(1000); 787 } 788 789 if (bootverbose) { 790 if (timeout >= 1000) 791 device_printf(dev, "channel HW reset timeout\n"); 792 else 793 device_printf(dev, "channel HW reset time=%dms\n", timeout); 794 } 795 796 /* reset phy */ 797 if (!ata_sata_phy_reset(dev, -1, 1)) { 798 if (bootverbose) 799 device_printf(dev, "phy reset found no device\n"); 800 ch->devices = 0; 801 goto finish; 802 } 803 804 /* issue soft reset */ 805 signature = ata_siiprb_softreset(dev, ATA_PM); 806 if (bootverbose) 807 device_printf(dev, "SIGNATURE=%08x\n", signature); 808 809 /* figure out whats there */ 810 switch (signature >> 16) { 811 case 0x0000: 812 ch->devices = ATA_ATA_MASTER; 813 break; 814 case 0x9669: 815 ch->devices = ATA_PORTMULTIPLIER; 816 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x2000); /* enable PM support */ 817 //SOS XXX need to clear all PM status and interrupts!!!! 818 ata_pm_identify(dev); 819 break; 820 case 0xeb14: 821 ch->devices = ATA_ATAPI_MASTER; 822 break; 823 default: 824 ch->devices = 0; 825 } 826 if (bootverbose) 827 device_printf(dev, "siiprb_reset devices=%08x\n", ch->devices); 828 829finish: 830 /* clear interrupt(s) */ 831 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x000008ff); 832 833 /* require explicit interrupt ack */ 834 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000008); 835 836 /* 64bit mode */ 837 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000400); 838 839 /* enable interrupts wanted */ 840 ATA_OUTL(ctlr->r_res2, 0x1010 + offset, 0x000000ff); 841} 842 843static void 844ata_siiprb_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 845{ 846 struct ata_dmasetprd_args *args = xsc; 847 struct ata_siiprb_dma_prdentry *prd = args->dmatab; 848 int i; 849 850 if ((args->error = error)) 851 return; 852 853 for (i = 0; i < nsegs; i++) { 854 prd[i].addr = htole64(segs[i].ds_addr); 855 prd[i].count = htole32(segs[i].ds_len); 856 } 857 prd[i - 1].control = htole32(ATA_DMA_EOT); 858 KASSERT(nsegs <= ATA_SIIPRB_DMA_ENTRIES,("too many DMA segment entries\n")); 859 args->nsegs = nsegs; 860} 861 862static void 863ata_siiprb_dmainit(device_t dev) 864{ 865 struct ata_channel *ch = device_get_softc(dev); 866 867 ata_dmainit(dev); 868 /* note start and stop are not used here */ 869 ch->dma.setprd = ata_siiprb_dmasetprd; 870 ch->dma.max_address = BUS_SPACE_MAXADDR; 871 ch->dma.max_iosize = (ATA_SIIPRB_DMA_ENTRIES - 1) * PAGE_SIZE; 872} 873 874ATA_DECLARE_DRIVER(ata_sii); 875