ata-siliconimage.c revision 188765
1/*- 2 * Copyright (c) 1998 - 2008 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: head/sys/dev/ata/chipsets/ata-siliconimage.c 188765 2009-02-18 22:17:48Z mav $"); 29 30#include "opt_ata.h" 31#include <sys/param.h> 32#include <sys/module.h> 33#include <sys/systm.h> 34#include <sys/kernel.h> 35#include <sys/ata.h> 36#include <sys/bus.h> 37#include <sys/endian.h> 38#include <sys/malloc.h> 39#include <sys/lock.h> 40#include <sys/mutex.h> 41#include <sys/sema.h> 42#include <sys/taskqueue.h> 43#include <vm/uma.h> 44#include <machine/stdarg.h> 45#include <machine/resource.h> 46#include <machine/bus.h> 47#include <sys/rman.h> 48#include <dev/pci/pcivar.h> 49#include <dev/pci/pcireg.h> 50#include <dev/ata/ata-all.h> 51#include <dev/ata/ata-pci.h> 52#include <ata_if.h> 53 54/* local prototypes */ 55static int ata_cmd_ch_attach(device_t dev); 56static int ata_cmd_status(device_t dev); 57static void ata_cmd_setmode(device_t dev, int mode); 58static int ata_sii_ch_attach(device_t dev); 59static int ata_sii_status(device_t dev); 60static void ata_sii_reset(device_t dev); 61static void ata_sii_setmode(device_t dev, int mode); 62static int ata_siiprb_ch_attach(device_t dev); 63static int ata_siiprb_status(device_t dev); 64static int ata_siiprb_begin_transaction(struct ata_request *request); 65static int ata_siiprb_end_transaction(struct ata_request *request); 66static int ata_siiprb_pm_read(device_t dev, int port, int reg, u_int32_t *result); 67static int ata_siiprb_pm_write(device_t dev, int port, int reg, u_int32_t result); 68static u_int32_t ata_siiprb_softreset(device_t dev, int port); 69static void ata_siiprb_reset(device_t dev); 70static void ata_siiprb_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 71static void ata_siiprb_dmainit(device_t dev); 72 73/* misc defines */ 74#define SII_MEMIO 1 75#define SII_PRBIO 2 76#define SII_INTR 0x01 77#define SII_SETCLK 0x02 78#define SII_BUG 0x04 79#define SII_4CH 0x08 80 81 82/* 83 * Silicon Image Inc. (SiI) (former CMD) chipset support functions 84 */ 85static int 86ata_sii_probe(device_t dev) 87{ 88 struct ata_pci_controller *ctlr = device_get_softc(dev); 89 static struct ata_chip_id ids[] = 90 {{ ATA_SII3114, 0x00, SII_MEMIO, SII_4CH, ATA_SA150, "3114" }, 91 { ATA_SII3512, 0x02, SII_MEMIO, 0, ATA_SA150, "3512" }, 92 { ATA_SII3112, 0x02, SII_MEMIO, 0, ATA_SA150, "3112" }, 93 { ATA_SII3112_1, 0x02, SII_MEMIO, 0, ATA_SA150, "3112" }, 94 { ATA_SII3512, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "3512" }, 95 { ATA_SII3112, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "3112" }, 96 { ATA_SII3112_1, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "3112" }, 97 { ATA_SII3124, 0x00, SII_PRBIO, SII_4CH, ATA_SA300, "3124" }, 98 { ATA_SII3132, 0x00, SII_PRBIO, 0, ATA_SA300, "3132" }, 99 { ATA_SII3132_1, 0x00, SII_PRBIO, 0, ATA_SA300, "3132" }, 100 { ATA_SII0680, 0x00, SII_MEMIO, SII_SETCLK, ATA_UDMA6, "680" }, 101 { ATA_CMD649, 0x00, 0, SII_INTR, ATA_UDMA5, "(CMD) 649" }, 102 { ATA_CMD648, 0x00, 0, SII_INTR, ATA_UDMA4, "(CMD) 648" }, 103 { ATA_CMD646, 0x07, 0, 0, ATA_UDMA2, "(CMD) 646U2" }, 104 { ATA_CMD646, 0x00, 0, 0, ATA_WDMA2, "(CMD) 646" }, 105 { 0, 0, 0, 0, 0, 0}}; 106 107 if (pci_get_vendor(dev) != ATA_SILICON_IMAGE_ID) 108 return ENXIO; 109 110 if (!(ctlr->chip = ata_match_chip(dev, ids))) 111 return ENXIO; 112 113 ata_set_desc(dev); 114 ctlr->chipinit = ata_sii_chipinit; 115 return 0; 116} 117 118int 119ata_sii_chipinit(device_t dev) 120{ 121 struct ata_pci_controller *ctlr = device_get_softc(dev); 122 123 if (ata_setup_interrupt(dev, ata_generic_intr)) 124 return ENXIO; 125 126 switch (ctlr->chip->cfg1) { 127 case SII_PRBIO: 128 ctlr->r_type1 = SYS_RES_MEMORY; 129 ctlr->r_rid1 = PCIR_BAR(0); 130 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1, 131 &ctlr->r_rid1, RF_ACTIVE))) 132 return ENXIO; 133 134 ctlr->r_rid2 = PCIR_BAR(2); 135 ctlr->r_type2 = SYS_RES_MEMORY; 136 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 137 &ctlr->r_rid2, RF_ACTIVE))){ 138 bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1,ctlr->r_res1); 139 return ENXIO; 140 } 141 ctlr->ch_attach = ata_siiprb_ch_attach; 142 ctlr->reset = ata_siiprb_reset; 143 ctlr->setmode = ata_sata_setmode; 144 ctlr->channels = (ctlr->chip->cfg2 == SII_4CH) ? 4 : 2; 145 146 /* reset controller */ 147 ATA_OUTL(ctlr->r_res1, 0x0040, 0x80000000); 148 DELAY(10000); 149 ATA_OUTL(ctlr->r_res1, 0x0040, 0x0000000f); 150 151 /* enable PCI interrupt */ 152 pci_write_config(dev, PCIR_COMMAND, 153 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2); 154 break; 155 156 case SII_MEMIO: 157 ctlr->r_type2 = SYS_RES_MEMORY; 158 ctlr->r_rid2 = PCIR_BAR(5); 159 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 160 &ctlr->r_rid2, RF_ACTIVE))){ 161 if (ctlr->chip->chipid != ATA_SII0680 || 162 (pci_read_config(dev, 0x8a, 1) & 1)) 163 return ENXIO; 164 } 165 166 if (ctlr->chip->cfg2 & SII_SETCLK) { 167 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10) 168 pci_write_config(dev, 0x8a, 169 (pci_read_config(dev, 0x8a, 1) & 0xcf)|0x10,1); 170 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10) 171 device_printf(dev, "%s could not set ATA133 clock\n", 172 ctlr->chip->text); 173 } 174 175 /* if we have 4 channels enable the second set */ 176 if (ctlr->chip->cfg2 & SII_4CH) { 177 ATA_OUTL(ctlr->r_res2, 0x0200, 0x00000002); 178 ctlr->channels = 4; 179 } 180 181 /* dont block interrupts from any channel */ 182 pci_write_config(dev, 0x48, 183 (pci_read_config(dev, 0x48, 4) & ~0x03c00000), 4); 184 185 /* enable PCI interrupt as BIOS might not */ 186 pci_write_config(dev, 0x8a, (pci_read_config(dev, 0x8a, 1) & 0x3f), 1); 187 188 if (ctlr->r_res2) 189 ctlr->ch_attach = ata_sii_ch_attach; 190 191 if (ctlr->chip->max_dma >= ATA_SA150) { 192 ctlr->reset = ata_sii_reset; 193 ctlr->setmode = ata_sata_setmode; 194 } 195 else 196 ctlr->setmode = ata_sii_setmode; 197 break; 198 199 default: 200 if ((pci_read_config(dev, 0x51, 1) & 0x08) != 0x08) { 201 device_printf(dev, "HW has secondary channel disabled\n"); 202 ctlr->channels = 1; 203 } 204 205 /* enable interrupt as BIOS might not */ 206 pci_write_config(dev, 0x71, 0x01, 1); 207 208 ctlr->ch_attach = ata_cmd_ch_attach; 209 ctlr->setmode = ata_cmd_setmode; 210 break; 211 } 212 return 0; 213} 214 215static int 216ata_cmd_ch_attach(device_t dev) 217{ 218 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 219 struct ata_channel *ch = device_get_softc(dev); 220 221 /* setup the usual register normal pci style */ 222 if (ata_pci_ch_attach(dev)) 223 return ENXIO; 224 225 if (ctlr->chip->cfg2 & SII_INTR) 226 ch->hw.status = ata_cmd_status; 227 228 return 0; 229} 230 231static int 232ata_cmd_status(device_t dev) 233{ 234 struct ata_channel *ch = device_get_softc(dev); 235 u_int8_t reg71; 236 237 if (((reg71 = pci_read_config(device_get_parent(dev), 0x71, 1)) & 238 (ch->unit ? 0x08 : 0x04))) { 239 pci_write_config(device_get_parent(dev), 0x71, 240 reg71 & ~(ch->unit ? 0x04 : 0x08), 1); 241 return ata_pci_status(dev); 242 } 243 return 0; 244} 245 246static void 247ata_cmd_setmode(device_t dev, int mode) 248{ 249 device_t gparent = GRANDPARENT(dev); 250 struct ata_pci_controller *ctlr = device_get_softc(gparent); 251 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 252 struct ata_device *atadev = device_get_softc(dev); 253 int devno = (ch->unit << 1) + atadev->unit; 254 int error; 255 256 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 257 258 mode = ata_check_80pin(dev, mode); 259 260 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 261 262 if (bootverbose) 263 device_printf(dev, "%ssetting %s on %s chip\n", 264 (error) ? "FAILURE " : "", 265 ata_mode2str(mode), ctlr->chip->text); 266 if (!error) { 267 int treg = 0x54 + ((devno < 3) ? (devno << 1) : 7); 268 int ureg = ch->unit ? 0x7b : 0x73; 269 270 if (mode >= ATA_UDMA0) { 271 int udmatimings[][2] = { { 0x31, 0xc2 }, { 0x21, 0x82 }, 272 { 0x11, 0x42 }, { 0x25, 0x8a }, 273 { 0x15, 0x4a }, { 0x05, 0x0a } }; 274 275 u_int8_t umode = pci_read_config(gparent, ureg, 1); 276 277 umode &= ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca); 278 umode |= udmatimings[mode & ATA_MODE_MASK][atadev->unit]; 279 pci_write_config(gparent, ureg, umode, 1); 280 } 281 else if (mode >= ATA_WDMA0) { 282 int dmatimings[] = { 0x87, 0x32, 0x3f }; 283 284 pci_write_config(gparent, treg, dmatimings[mode & ATA_MODE_MASK],1); 285 pci_write_config(gparent, ureg, 286 pci_read_config(gparent, ureg, 1) & 287 ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca), 1); 288 } 289 else { 290 int piotimings[] = { 0xa9, 0x57, 0x44, 0x32, 0x3f }; 291 pci_write_config(gparent, treg, 292 piotimings[(mode & ATA_MODE_MASK) - ATA_PIO0], 1); 293 pci_write_config(gparent, ureg, 294 pci_read_config(gparent, ureg, 1) & 295 ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca), 1); 296 } 297 atadev->mode = mode; 298 } 299} 300 301static int 302ata_sii_ch_attach(device_t dev) 303{ 304 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 305 struct ata_channel *ch = device_get_softc(dev); 306 int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2); 307 int i; 308 309 for (i = ATA_DATA; i <= ATA_COMMAND; i++) { 310 ch->r_io[i].res = ctlr->r_res2; 311 ch->r_io[i].offset = 0x80 + i + (unit01 << 6) + (unit10 << 8); 312 } 313 ch->r_io[ATA_CONTROL].res = ctlr->r_res2; 314 ch->r_io[ATA_CONTROL].offset = 0x8a + (unit01 << 6) + (unit10 << 8); 315 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2; 316 ata_default_registers(dev); 317 318 ch->r_io[ATA_BMCMD_PORT].res = ctlr->r_res2; 319 ch->r_io[ATA_BMCMD_PORT].offset = 0x00 + (unit01 << 3) + (unit10 << 8); 320 ch->r_io[ATA_BMSTAT_PORT].res = ctlr->r_res2; 321 ch->r_io[ATA_BMSTAT_PORT].offset = 0x02 + (unit01 << 3) + (unit10 << 8); 322 ch->r_io[ATA_BMDTP_PORT].res = ctlr->r_res2; 323 ch->r_io[ATA_BMDTP_PORT].offset = 0x04 + (unit01 << 3) + (unit10 << 8); 324 325 if (ctlr->chip->max_dma >= ATA_SA150) { 326 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 327 ch->r_io[ATA_SSTATUS].offset = 0x104 + (unit01 << 7) + (unit10 << 8); 328 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 329 ch->r_io[ATA_SERROR].offset = 0x108 + (unit01 << 7) + (unit10 << 8); 330 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 331 ch->r_io[ATA_SCONTROL].offset = 0x100 + (unit01 << 7) + (unit10 << 8); 332 ch->flags |= ATA_NO_SLAVE; 333 334 /* enable PHY state change interrupt */ 335 ATA_OUTL(ctlr->r_res2, 0x148 + (unit01 << 7) + (unit10 << 8),(1 << 16)); 336 } 337 338 if (ctlr->chip->cfg2 & SII_BUG) { 339 /* work around errata in early chips */ 340 ch->dma.boundary = 8192; 341 ch->dma.segsize = 15 * DEV_BSIZE; 342 } 343 344 ata_pci_hw(dev); 345 ch->hw.status = ata_sii_status; 346 return 0; 347} 348 349static int 350ata_sii_status(device_t dev) 351{ 352 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 353 struct ata_channel *ch = device_get_softc(dev); 354 int offset0 = ((ch->unit & 1) << 3) + ((ch->unit & 2) << 8); 355 int offset1 = ((ch->unit & 1) << 6) + ((ch->unit & 2) << 8); 356 357 /* do we have any PHY events ? */ 358 if (ctlr->chip->max_dma >= ATA_SA150 && 359 (ATA_INL(ctlr->r_res2, 0x10 + offset0) & 0x00000010)) 360 ata_sata_phy_check_events(dev); 361 362 if (ATA_INL(ctlr->r_res2, 0xa0 + offset1) & 0x00000800) 363 return ata_pci_status(dev); 364 else 365 return 0; 366} 367 368static void 369ata_sii_reset(device_t dev) 370{ 371 if (ata_sata_phy_reset(dev)) 372 ata_generic_reset(dev); 373} 374 375static void 376ata_sii_setmode(device_t dev, int mode) 377{ 378 device_t gparent = GRANDPARENT(dev); 379 struct ata_pci_controller *ctlr = device_get_softc(gparent); 380 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 381 struct ata_device *atadev = device_get_softc(dev); 382 int rego = (ch->unit << 4) + (atadev->unit << 1); 383 int mreg = ch->unit ? 0x84 : 0x80; 384 int mask = 0x03 << (atadev->unit << 2); 385 int mval = pci_read_config(gparent, mreg, 1) & ~mask; 386 int error; 387 388 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 389 390 if (ctlr->chip->cfg2 & SII_SETCLK) { 391 if (mode > ATA_UDMA2 && (pci_read_config(gparent, 0x79, 1) & 392 (ch->unit ? 0x02 : 0x01))) { 393 ata_print_cable(dev, "controller"); 394 mode = ATA_UDMA2; 395 } 396 } 397 else 398 mode = ata_check_80pin(dev, mode); 399 400 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 401 402 if (bootverbose) 403 device_printf(dev, "%ssetting %s on %s chip\n", 404 (error) ? "FAILURE " : "", 405 ata_mode2str(mode), ctlr->chip->text); 406 if (error) 407 return; 408 409 if (mode >= ATA_UDMA0) { 410 u_int8_t udmatimings[] = { 0xf, 0xb, 0x7, 0x5, 0x3, 0x2, 0x1 }; 411 u_int8_t ureg = 0xac + rego; 412 413 pci_write_config(gparent, mreg, 414 mval | (0x03 << (atadev->unit << 2)), 1); 415 pci_write_config(gparent, ureg, 416 (pci_read_config(gparent, ureg, 1) & ~0x3f) | 417 udmatimings[mode & ATA_MODE_MASK], 1); 418 419 } 420 else if (mode >= ATA_WDMA0) { 421 u_int8_t dreg = 0xa8 + rego; 422 u_int16_t dmatimings[] = { 0x2208, 0x10c2, 0x10c1 }; 423 424 pci_write_config(gparent, mreg, 425 mval | (0x02 << (atadev->unit << 2)), 1); 426 pci_write_config(gparent, dreg, dmatimings[mode & ATA_MODE_MASK], 2); 427 428 } 429 else { 430 u_int8_t preg = 0xa4 + rego; 431 u_int16_t piotimings[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 }; 432 433 pci_write_config(gparent, mreg, 434 mval | (0x01 << (atadev->unit << 2)), 1); 435 pci_write_config(gparent, preg, piotimings[mode & ATA_MODE_MASK], 2); 436 } 437 atadev->mode = mode; 438} 439 440 441struct ata_siiprb_dma_prdentry { 442 u_int64_t addr; 443 u_int32_t count; 444 u_int32_t control; 445} __packed; 446 447#define ATA_SIIPRB_DMA_ENTRIES 125 448struct ata_siiprb_ata_command { 449 struct ata_siiprb_dma_prdentry prd[ATA_SIIPRB_DMA_ENTRIES]; 450} __packed; 451 452struct ata_siiprb_atapi_command { 453 u_int8_t ccb[16]; 454 struct ata_siiprb_dma_prdentry prd[ATA_SIIPRB_DMA_ENTRIES]; 455} __packed; 456 457struct ata_siiprb_command { 458 u_int16_t control; 459 u_int16_t protocol_override; 460 u_int32_t transfer_count; 461 u_int8_t fis[24]; 462 union { 463 struct ata_siiprb_ata_command ata; 464 struct ata_siiprb_atapi_command atapi; 465 } u; 466} __packed; 467 468static int 469ata_siiprb_ch_attach(device_t dev) 470{ 471 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 472 struct ata_channel *ch = device_get_softc(dev); 473 int offset = ch->unit * 0x2000; 474 475 ata_siiprb_dmainit(dev); 476 477 /* set the SATA resources */ 478 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 479 ch->r_io[ATA_SSTATUS].offset = 0x1f04 + offset; 480 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 481 ch->r_io[ATA_SERROR].offset = 0x1f08 + offset; 482 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 483 ch->r_io[ATA_SCONTROL].offset = 0x1f00 + offset; 484 ch->r_io[ATA_SACTIVE].res = ctlr->r_res2; 485 ch->r_io[ATA_SACTIVE].offset = 0x1f0c + offset; 486 487 ch->hw.status = ata_siiprb_status; 488 ch->hw.begin_transaction = ata_siiprb_begin_transaction; 489 ch->hw.end_transaction = ata_siiprb_end_transaction; 490 ch->hw.command = NULL; /* not used here */ 491 ch->hw.softreset = ata_siiprb_softreset; 492 ch->hw.pm_read = ata_siiprb_pm_read; 493 ch->hw.pm_write = ata_siiprb_pm_write; 494 495 return 0; 496} 497 498static int 499ata_siiprb_status(device_t dev) 500{ 501 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 502 struct ata_channel *ch = device_get_softc(dev); 503 u_int32_t action = ATA_INL(ctlr->r_res1, 0x0044); 504 int offset = ch->unit * 0x2000; 505 506 if (action & (1 << ch->unit)) { 507 u_int32_t istatus = ATA_INL(ctlr->r_res2, 0x1008 + offset); 508 509 /* do we have any PHY events ? */ 510 ata_sata_phy_check_events(dev); 511 512 /* clear interrupt(s) */ 513 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, istatus); 514 515 /* do we have any device action ? */ 516 return (istatus & 0x00000003); 517 } 518 return 0; 519} 520 521static int 522ata_siiprb_begin_transaction(struct ata_request *request) 523{ 524 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev)); 525 struct ata_channel *ch = device_get_softc(request->parent); 526 struct ata_siiprb_command *prb; 527 struct ata_siiprb_dma_prdentry *prd; 528 int offset = ch->unit * 0x2000; 529 u_int64_t prb_bus; 530 531 /* SOS XXX */ 532 if (request->u.ata.command == ATA_DEVICE_RESET) { 533 request->result = 0; 534 return ATA_OP_FINISHED; 535 } 536 537 /* get a piece of the workspace for this request */ 538 prb = (struct ata_siiprb_command *) 539 (ch->dma.work + (sizeof(struct ata_siiprb_command) * request->tag)); 540 541 /* clear the prb structure */ 542 bzero(prb, sizeof(struct ata_siiprb_command)); 543 544 /* setup the FIS for this request */ 545 if (!ata_request2fis_h2d(request, &prb->fis[0])) { 546 device_printf(request->dev, "setting up SATA FIS failed\n"); 547 request->result = EIO; 548 return ATA_OP_FINISHED; 549 } 550 551 /* setup transfer type */ 552 if (request->flags & ATA_R_ATAPI) { 553 struct ata_device *atadev = device_get_softc(request->dev); 554 555 bcopy(request->u.atapi.ccb, prb->u.atapi.ccb, 16); 556 if ((atadev->param.config & ATA_PROTO_MASK) == ATA_PROTO_ATAPI_12) 557 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000020); 558 else 559 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000020); 560 if (request->flags & ATA_R_READ) 561 prb->control = htole16(0x0010); 562 if (request->flags & ATA_R_WRITE) 563 prb->control = htole16(0x0020); 564 prd = &prb->u.atapi.prd[0]; 565 } 566 else 567 prd = &prb->u.ata.prd[0]; 568 569 /* if request moves data setup and load SG list */ 570 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) { 571 if (ch->dma.load(request, prd, NULL)) { 572 device_printf(request->dev, "setting up DMA failed\n"); 573 request->result = EIO; 574 return ATA_OP_FINISHED; 575 } 576 } 577 578 /* activate the prb */ 579 prb_bus = ch->dma.work_bus + 580 (sizeof(struct ata_siiprb_command) * request->tag); 581 ATA_OUTL(ctlr->r_res2, 582 0x1c00 + offset + (request->tag * sizeof(u_int64_t)), prb_bus); 583 ATA_OUTL(ctlr->r_res2, 584 0x1c04 + offset + (request->tag * sizeof(u_int64_t)), prb_bus>>32); 585 586 /* start the timeout */ 587 callout_reset(&request->callout, request->timeout * hz, 588 (timeout_t*)ata_timeout, request); 589 return ATA_OP_CONTINUES; 590} 591 592static int 593ata_siiprb_end_transaction(struct ata_request *request) 594{ 595 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev)); 596 struct ata_channel *ch = device_get_softc(request->parent); 597 struct ata_siiprb_command *prb; 598 int offset = ch->unit * 0x2000; 599 int error, timeout; 600 601 /* kill the timeout */ 602 callout_stop(&request->callout); 603 604 prb = (struct ata_siiprb_command *) 605 ((u_int8_t *)rman_get_virtual(ctlr->r_res2)+(request->tag << 7)+offset); 606 607 /* any controller errors flagged ? */ 608 if ((error = ATA_INL(ctlr->r_res2, 0x1024 + offset))) { 609 if (bootverbose) 610 printf("ata_siiprb_end_transaction %s error=%08x\n", 611 ata_cmd2str(request), error); 612 613 /* if device error status get details */ 614 if (error == 1 || error == 2) { 615 request->status = prb->fis[2]; 616 if (request->status & ATA_S_ERROR) 617 request->error = prb->fis[3]; 618 } 619 620 /* SOS XXX handle other controller errors here */ 621 622 /* initialize port */ 623 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000004); 624 625 /* poll for port ready */ 626 for (timeout = 0; timeout < 1000; timeout++) { 627 DELAY(1000); 628 if (ATA_INL(ctlr->r_res2, 0x1008 + offset) & 0x00040000) 629 break; 630 } 631 if (bootverbose) { 632 if (timeout >= 1000) 633 device_printf(ch->dev, "port initialize timeout\n"); 634 else 635 device_printf(ch->dev, "port initialize time=%dms\n", timeout); 636 } 637 } 638 639 /* on control commands read back registers to the request struct */ 640 if (request->flags & ATA_R_CONTROL) { 641 struct ata_device *atadev = device_get_softc(request->dev); 642 643 request->u.ata.count = prb->fis[12] | ((u_int16_t)prb->fis[13] << 8); 644 request->u.ata.lba = prb->fis[4] | ((u_int64_t)prb->fis[5] << 8) | 645 ((u_int64_t)prb->fis[6] << 16); 646 if (atadev->flags & ATA_D_48BIT_ACTIVE) 647 request->u.ata.lba |= ((u_int64_t)prb->fis[8] << 24) | 648 ((u_int64_t)prb->fis[9] << 32) | 649 ((u_int64_t)prb->fis[10] << 40); 650 else 651 request->u.ata.lba |= ((u_int64_t)(prb->fis[7] & 0x0f) << 24); 652 } 653 654 /* update progress */ 655 if (!(request->status & ATA_S_ERROR) && !(request->flags & ATA_R_TIMEOUT)) { 656 if (request->flags & ATA_R_READ) 657 request->donecount = prb->transfer_count; 658 else 659 request->donecount = request->bytecount; 660 } 661 662 /* release SG list etc */ 663 ch->dma.unload(request); 664 665 return ATA_OP_FINISHED; 666} 667 668static int 669ata_siiprb_issue_cmd(device_t dev) 670{ 671 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 672 struct ata_channel *ch = device_get_softc(dev); 673 u_int64_t prb_bus = ch->dma.work_bus; 674 u_int32_t status; 675 int offset = ch->unit * 0x2000; 676 int timeout; 677 678 /* issue command to chip */ 679 ATA_OUTL(ctlr->r_res2, 0x1c00 + offset, prb_bus); 680 ATA_OUTL(ctlr->r_res2, 0x1c04 + offset, prb_bus >> 32); 681 682 /* poll for command finished */ 683 for (timeout = 0; timeout < 10000; timeout++) { 684 DELAY(1000); 685 if ((status = ATA_INL(ctlr->r_res2, 0x1008 + offset)) & 0x00010000) 686 break; 687 } 688 // SOS XXX ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x00010000); 689 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x08ff08ff); 690 691 if (timeout >= 1000) 692 return EIO; 693 694 if (bootverbose) 695 device_printf(dev, "siiprb_issue_cmd time=%dms status=%08x\n", 696 timeout, status); 697 return 0; 698} 699 700static int 701ata_siiprb_pm_read(device_t dev, int port, int reg, u_int32_t *result) 702{ 703 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 704 struct ata_channel *ch = device_get_softc(dev); 705 struct ata_siiprb_command *prb = (struct ata_siiprb_command *)ch->dma.work; 706 int offset = ch->unit * 0x2000; 707 708 bzero(prb, sizeof(struct ata_siiprb_command)); 709 prb->fis[0] = 0x27; /* host to device */ 710 prb->fis[1] = 0x8f; /* command FIS to PM port */ 711 prb->fis[2] = ATA_READ_PM; 712 prb->fis[3] = reg; 713 prb->fis[7] = port; 714 if (ata_siiprb_issue_cmd(dev)) { 715 device_printf(dev, "error reading PM port\n"); 716 return EIO; 717 } 718 prb = (struct ata_siiprb_command *) 719 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset); 720 *result = prb->fis[12]|(prb->fis[4]<<8)|(prb->fis[5]<<16)|(prb->fis[6]<<24); 721 return 0; 722} 723 724static int 725ata_siiprb_pm_write(device_t dev, int port, int reg, u_int32_t value) 726{ 727 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 728 struct ata_channel *ch = device_get_softc(dev); 729 struct ata_siiprb_command *prb = (struct ata_siiprb_command *)ch->dma.work; 730 int offset = ch->unit * 0x2000; 731 732 bzero(prb, sizeof(struct ata_siiprb_command)); 733 prb->fis[0] = 0x27; /* host to device */ 734 prb->fis[1] = 0x8f; /* command FIS to PM port */ 735 prb->fis[2] = ATA_WRITE_PM; 736 prb->fis[3] = reg; 737 prb->fis[7] = port; 738 prb->fis[12] = value & 0xff; 739 prb->fis[4] = (value >> 8) & 0xff;; 740 prb->fis[5] = (value >> 16) & 0xff;; 741 prb->fis[6] = (value >> 24) & 0xff;; 742 if (ata_siiprb_issue_cmd(dev)) { 743 device_printf(dev, "error writing PM port\n"); 744 return ATA_E_ABORT; 745 } 746 prb = (struct ata_siiprb_command *) 747 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset); 748 return prb->fis[3]; 749} 750 751static u_int32_t 752ata_siiprb_softreset(device_t dev, int port) 753{ 754 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 755 struct ata_channel *ch = device_get_softc(dev); 756 struct ata_siiprb_command *prb = (struct ata_siiprb_command *)ch->dma.work; 757 u_int32_t signature; 758 int offset = ch->unit * 0x2000; 759 760 /* setup the workspace for a soft reset command */ 761 bzero(prb, sizeof(struct ata_siiprb_command)); 762 prb->control = htole16(0x0080); 763 prb->fis[1] = port & 0x0f; 764 765 /* issue soft reset */ 766 if (ata_siiprb_issue_cmd(dev)) 767 return -1; 768 769 ata_udelay(150000); 770 771 /* get possible signature */ 772 prb = (struct ata_siiprb_command *) 773 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset); 774 signature=prb->fis[12]|(prb->fis[4]<<8)|(prb->fis[5]<<16)|(prb->fis[6]<<24); 775 776 /* clear error bits/interrupt */ 777 ATA_IDX_OUTL(ch, ATA_SERROR, 0xffffffff); 778 779 return signature; 780} 781 782static void 783ata_siiprb_reset(device_t dev) 784{ 785 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 786 struct ata_channel *ch = device_get_softc(dev); 787 int offset = ch->unit * 0x2000; 788 u_int32_t status, signature; 789 int timeout; 790 791 /* disable interrupts */ 792 ATA_OUTL(ctlr->r_res2, 0x1014 + offset, 0x000000ff); 793 794 /* reset channel HW */ 795 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000001); 796 DELAY(1000); 797 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000001); 798 DELAY(10000); 799 800 /* poll for channel ready */ 801 for (timeout = 0; timeout < 1000; timeout++) { 802 if ((status = ATA_INL(ctlr->r_res2, 0x1008 + offset)) & 0x00040000) 803 break; 804 DELAY(1000); 805 } 806 807 if (bootverbose) { 808 if (timeout >= 1000) 809 device_printf(dev, "channel HW reset timeout\n"); 810 else 811 device_printf(dev, "channel HW reset time=%dms\n", timeout); 812 } 813 814 /* reset phy */ 815 if (!ata_sata_phy_reset(dev)) { 816 if (bootverbose) 817 device_printf(dev, "phy reset found no device\n"); 818 ch->devices = 0; 819 goto finish; 820 } 821 822 /* issue soft reset */ 823 signature = ata_siiprb_softreset(dev, ATA_PM); 824 if (bootverbose) 825 device_printf(dev, "SIGNATURE=%08x\n", signature); 826 827 /* figure out whats there */ 828 switch (signature) { 829 case 0x00000101: 830 ch->devices = ATA_ATA_MASTER; 831 break; 832 case 0x96690101: 833 ch->devices = ATA_PORTMULTIPLIER; 834 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x2000); /* enable PM support */ 835 //SOS XXX need to clear all PM status and interrupts!!!! 836 ata_pm_identify(dev); 837 break; 838 case 0xeb140101: 839 ch->devices = ATA_ATAPI_MASTER; 840 break; 841 default: 842 ch->devices = 0; 843 } 844 if (bootverbose) 845 device_printf(dev, "siiprb_reset devices=%08x\n", ch->devices); 846 847finish: 848 /* clear interrupt(s) */ 849 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x000008ff); 850 851 /* require explicit interrupt ack */ 852 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000008); 853 854 /* 64bit mode */ 855 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000400); 856 857 /* enable interrupts wanted */ 858 ATA_OUTL(ctlr->r_res2, 0x1010 + offset, 0x000000ff); 859} 860 861static void 862ata_siiprb_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 863{ 864 struct ata_dmasetprd_args *args = xsc; 865 struct ata_siiprb_dma_prdentry *prd = args->dmatab; 866 int i; 867 868 if ((args->error = error)) 869 return; 870 871 for (i = 0; i < nsegs; i++) { 872 prd[i].addr = htole64(segs[i].ds_addr); 873 prd[i].count = htole32(segs[i].ds_len); 874 } 875 prd[i - 1].control = htole32(ATA_DMA_EOT); 876 KASSERT(nsegs <= ATA_SIIPRB_DMA_ENTRIES,("too many DMA segment entries\n")); 877 args->nsegs = nsegs; 878} 879 880static void 881ata_siiprb_dmainit(device_t dev) 882{ 883 struct ata_channel *ch = device_get_softc(dev); 884 885 ata_dmainit(dev); 886 /* note start and stop are not used here */ 887 ch->dma.setprd = ata_siiprb_dmasetprd; 888 ch->dma.max_address = BUS_SPACE_MAXADDR; 889} 890 891ATA_DECLARE_DRIVER(ata_sii); 892