1183724Ssos/*- 2230132Suqs * Copyright (c) 1998 - 2008 S��ren Schmidt <sos@FreeBSD.org> 3183724Ssos * All rights reserved. 4183724Ssos * 5183724Ssos * Redistribution and use in source and binary forms, with or without 6183724Ssos * modification, are permitted provided that the following conditions 7183724Ssos * are met: 8183724Ssos * 1. Redistributions of source code must retain the above copyright 9183724Ssos * notice, this list of conditions and the following disclaimer, 10183724Ssos * without modification, immediately at the beginning of the file. 11183724Ssos * 2. Redistributions in binary form must reproduce the above copyright 12183724Ssos * notice, this list of conditions and the following disclaimer in the 13183724Ssos * documentation and/or other materials provided with the distribution. 14183724Ssos * 15183724Ssos * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16183724Ssos * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17183724Ssos * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18183724Ssos * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19183724Ssos * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20183724Ssos * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21183724Ssos * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22183724Ssos * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23183724Ssos * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24183724Ssos * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25183724Ssos */ 26183724Ssos 27183724Ssos#include <sys/cdefs.h> 28183724Ssos__FBSDID("$FreeBSD$"); 29183724Ssos 30183724Ssos#include <sys/param.h> 31183724Ssos#include <sys/module.h> 32183724Ssos#include <sys/systm.h> 33183724Ssos#include <sys/kernel.h> 34183724Ssos#include <sys/ata.h> 35183724Ssos#include <sys/bus.h> 36183724Ssos#include <sys/endian.h> 37183724Ssos#include <sys/malloc.h> 38183724Ssos#include <sys/lock.h> 39183724Ssos#include <sys/mutex.h> 40183724Ssos#include <sys/sema.h> 41183724Ssos#include <sys/taskqueue.h> 42183724Ssos#include <vm/uma.h> 43183724Ssos#include <machine/stdarg.h> 44183724Ssos#include <machine/resource.h> 45183724Ssos#include <machine/bus.h> 46183724Ssos#include <sys/rman.h> 47183724Ssos#include <dev/pci/pcivar.h> 48183724Ssos#include <dev/pci/pcireg.h> 49183724Ssos#include <dev/ata/ata-all.h> 50183724Ssos#include <dev/ata/ata-pci.h> 51183724Ssos#include <ata_if.h> 52183724Ssos 53183724Ssos/* local prototypes */ 54188765Smavstatic int ata_cmd_ch_attach(device_t dev); 55183724Ssosstatic int ata_cmd_status(device_t dev); 56200171Smavstatic int ata_cmd_setmode(device_t dev, int target, int mode); 57188765Smavstatic int ata_sii_ch_attach(device_t dev); 58188769Smavstatic int ata_sii_ch_detach(device_t dev); 59183724Ssosstatic int ata_sii_status(device_t dev); 60183724Ssosstatic void ata_sii_reset(device_t dev); 61200171Smavstatic int ata_sii_setmode(device_t dev, int target, int mode); 62188765Smavstatic int ata_siiprb_ch_attach(device_t dev); 63188769Smavstatic int ata_siiprb_ch_detach(device_t dev); 64183724Ssosstatic int ata_siiprb_status(device_t dev); 65183724Ssosstatic int ata_siiprb_begin_transaction(struct ata_request *request); 66183724Ssosstatic int ata_siiprb_end_transaction(struct ata_request *request); 67183724Ssosstatic int ata_siiprb_pm_read(device_t dev, int port, int reg, u_int32_t *result); 68183724Ssosstatic int ata_siiprb_pm_write(device_t dev, int port, int reg, u_int32_t result); 69183724Ssosstatic u_int32_t ata_siiprb_softreset(device_t dev, int port); 70183724Ssosstatic void ata_siiprb_reset(device_t dev); 71183724Ssosstatic void ata_siiprb_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 72183724Ssosstatic void ata_siiprb_dmainit(device_t dev); 73183724Ssos 74183724Ssos/* misc defines */ 75183724Ssos#define SII_MEMIO 1 76183724Ssos#define SII_PRBIO 2 77183724Ssos#define SII_INTR 0x01 78183724Ssos#define SII_SETCLK 0x02 79183724Ssos#define SII_BUG 0x04 80183724Ssos#define SII_4CH 0x08 81183724Ssos 82183724Ssos/* 83183724Ssos * Silicon Image Inc. (SiI) (former CMD) chipset support functions 84183724Ssos */ 85183724Ssosstatic int 86183724Ssosata_sii_probe(device_t dev) 87183724Ssos{ 88183724Ssos struct ata_pci_controller *ctlr = device_get_softc(dev); 89242625Sdim static const struct ata_chip_id ids[] = 90183724Ssos {{ ATA_SII3114, 0x00, SII_MEMIO, SII_4CH, ATA_SA150, "3114" }, 91183724Ssos { ATA_SII3512, 0x02, SII_MEMIO, 0, ATA_SA150, "3512" }, 92183724Ssos { ATA_SII3112, 0x02, SII_MEMIO, 0, ATA_SA150, "3112" }, 93183724Ssos { ATA_SII3112_1, 0x02, SII_MEMIO, 0, ATA_SA150, "3112" }, 94183724Ssos { ATA_SII3512, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "3512" }, 95183724Ssos { ATA_SII3112, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "3112" }, 96183724Ssos { ATA_SII3112_1, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "3112" }, 97183724Ssos { ATA_SII3124, 0x00, SII_PRBIO, SII_4CH, ATA_SA300, "3124" }, 98183724Ssos { ATA_SII3132, 0x00, SII_PRBIO, 0, ATA_SA300, "3132" }, 99183724Ssos { ATA_SII3132_1, 0x00, SII_PRBIO, 0, ATA_SA300, "3132" }, 100191897Smav { ATA_SII3132_2, 0x00, SII_PRBIO, 0, ATA_SA300, "3132" }, 101183724Ssos { ATA_SII0680, 0x00, SII_MEMIO, SII_SETCLK, ATA_UDMA6, "680" }, 102183724Ssos { ATA_CMD649, 0x00, 0, SII_INTR, ATA_UDMA5, "(CMD) 649" }, 103183724Ssos { ATA_CMD648, 0x00, 0, SII_INTR, ATA_UDMA4, "(CMD) 648" }, 104183724Ssos { ATA_CMD646, 0x07, 0, 0, ATA_UDMA2, "(CMD) 646U2" }, 105183724Ssos { ATA_CMD646, 0x00, 0, 0, ATA_WDMA2, "(CMD) 646" }, 106183724Ssos { 0, 0, 0, 0, 0, 0}}; 107183724Ssos 108183724Ssos if (pci_get_vendor(dev) != ATA_SILICON_IMAGE_ID) 109183724Ssos return ENXIO; 110183724Ssos 111183724Ssos if (!(ctlr->chip = ata_match_chip(dev, ids))) 112183724Ssos return ENXIO; 113183724Ssos 114183724Ssos ata_set_desc(dev); 115183724Ssos ctlr->chipinit = ata_sii_chipinit; 116194893Smav return (BUS_PROBE_DEFAULT); 117183724Ssos} 118183724Ssos 119183724Ssosint 120183724Ssosata_sii_chipinit(device_t dev) 121183724Ssos{ 122183724Ssos struct ata_pci_controller *ctlr = device_get_softc(dev); 123183724Ssos 124183724Ssos if (ata_setup_interrupt(dev, ata_generic_intr)) 125183724Ssos return ENXIO; 126183724Ssos 127183724Ssos switch (ctlr->chip->cfg1) { 128183724Ssos case SII_PRBIO: 129183724Ssos ctlr->r_type1 = SYS_RES_MEMORY; 130183724Ssos ctlr->r_rid1 = PCIR_BAR(0); 131183724Ssos if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1, 132183724Ssos &ctlr->r_rid1, RF_ACTIVE))) 133183724Ssos return ENXIO; 134183724Ssos 135183724Ssos ctlr->r_rid2 = PCIR_BAR(2); 136183724Ssos ctlr->r_type2 = SYS_RES_MEMORY; 137183724Ssos if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 138183724Ssos &ctlr->r_rid2, RF_ACTIVE))){ 139183724Ssos bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1,ctlr->r_res1); 140183724Ssos return ENXIO; 141183724Ssos } 142227000Smarius#ifdef __sparc64__ 143227000Smarius if (!bus_space_map(rman_get_bustag(ctlr->r_res2), 144227000Smarius rman_get_bushandle(ctlr->r_res2), rman_get_size(ctlr->r_res2), 145227000Smarius BUS_SPACE_MAP_LINEAR, NULL)) { 146227000Smarius bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1, 147227000Smarius ctlr->r_res1); 148227000Smarius bus_release_resource(dev, ctlr->r_type2, ctlr->r_rid2, 149227000Smarius ctlr->r_res2); 150227000Smarius return (ENXIO); 151227000Smarius } 152227000Smarius#endif 153188765Smav ctlr->ch_attach = ata_siiprb_ch_attach; 154188769Smav ctlr->ch_detach = ata_siiprb_ch_detach; 155183724Ssos ctlr->reset = ata_siiprb_reset; 156183724Ssos ctlr->setmode = ata_sata_setmode; 157200171Smav ctlr->getrev = ata_sata_getrev; 158183724Ssos ctlr->channels = (ctlr->chip->cfg2 == SII_4CH) ? 4 : 2; 159183724Ssos 160183724Ssos /* reset controller */ 161183724Ssos ATA_OUTL(ctlr->r_res1, 0x0040, 0x80000000); 162183724Ssos DELAY(10000); 163183724Ssos ATA_OUTL(ctlr->r_res1, 0x0040, 0x0000000f); 164183724Ssos break; 165183724Ssos 166183724Ssos case SII_MEMIO: 167183724Ssos ctlr->r_type2 = SYS_RES_MEMORY; 168183724Ssos ctlr->r_rid2 = PCIR_BAR(5); 169183724Ssos if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 170183724Ssos &ctlr->r_rid2, RF_ACTIVE))){ 171183724Ssos if (ctlr->chip->chipid != ATA_SII0680 || 172183724Ssos (pci_read_config(dev, 0x8a, 1) & 1)) 173183724Ssos return ENXIO; 174183724Ssos } 175183724Ssos 176183724Ssos if (ctlr->chip->cfg2 & SII_SETCLK) { 177183724Ssos if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10) 178183724Ssos pci_write_config(dev, 0x8a, 179183724Ssos (pci_read_config(dev, 0x8a, 1) & 0xcf)|0x10,1); 180183724Ssos if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10) 181183724Ssos device_printf(dev, "%s could not set ATA133 clock\n", 182183724Ssos ctlr->chip->text); 183183724Ssos } 184183724Ssos 185183724Ssos /* if we have 4 channels enable the second set */ 186183724Ssos if (ctlr->chip->cfg2 & SII_4CH) { 187183724Ssos ATA_OUTL(ctlr->r_res2, 0x0200, 0x00000002); 188183724Ssos ctlr->channels = 4; 189183724Ssos } 190183724Ssos 191183724Ssos /* dont block interrupts from any channel */ 192183724Ssos pci_write_config(dev, 0x48, 193183724Ssos (pci_read_config(dev, 0x48, 4) & ~0x03c00000), 4); 194183724Ssos 195183724Ssos /* enable PCI interrupt as BIOS might not */ 196183724Ssos pci_write_config(dev, 0x8a, (pci_read_config(dev, 0x8a, 1) & 0x3f), 1); 197183724Ssos 198188769Smav if (ctlr->r_res2) { 199188765Smav ctlr->ch_attach = ata_sii_ch_attach; 200188769Smav ctlr->ch_detach = ata_sii_ch_detach; 201188769Smav } 202183724Ssos 203183724Ssos if (ctlr->chip->max_dma >= ATA_SA150) { 204183724Ssos ctlr->reset = ata_sii_reset; 205183724Ssos ctlr->setmode = ata_sata_setmode; 206200171Smav ctlr->getrev = ata_sata_getrev; 207183724Ssos } 208183724Ssos else 209183724Ssos ctlr->setmode = ata_sii_setmode; 210183724Ssos break; 211183724Ssos 212183724Ssos default: 213183724Ssos if ((pci_read_config(dev, 0x51, 1) & 0x08) != 0x08) { 214183724Ssos device_printf(dev, "HW has secondary channel disabled\n"); 215183724Ssos ctlr->channels = 1; 216183724Ssos } 217183724Ssos 218183724Ssos /* enable interrupt as BIOS might not */ 219183724Ssos pci_write_config(dev, 0x71, 0x01, 1); 220183724Ssos 221188765Smav ctlr->ch_attach = ata_cmd_ch_attach; 222188769Smav ctlr->ch_detach = ata_pci_ch_detach; 223183724Ssos ctlr->setmode = ata_cmd_setmode; 224183724Ssos break; 225183724Ssos } 226183724Ssos return 0; 227183724Ssos} 228183724Ssos 229183724Ssosstatic int 230188765Smavata_cmd_ch_attach(device_t dev) 231183724Ssos{ 232183724Ssos struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 233183724Ssos struct ata_channel *ch = device_get_softc(dev); 234183724Ssos 235183724Ssos /* setup the usual register normal pci style */ 236188765Smav if (ata_pci_ch_attach(dev)) 237183724Ssos return ENXIO; 238183724Ssos 239183724Ssos if (ctlr->chip->cfg2 & SII_INTR) 240183724Ssos ch->hw.status = ata_cmd_status; 241183724Ssos 242230627Smarius ch->flags |= ATA_NO_ATAPI_DMA; 243230627Smarius 244183724Ssos return 0; 245183724Ssos} 246183724Ssos 247183724Ssosstatic int 248183724Ssosata_cmd_status(device_t dev) 249183724Ssos{ 250183724Ssos struct ata_channel *ch = device_get_softc(dev); 251183724Ssos u_int8_t reg71; 252183724Ssos 253183724Ssos if (((reg71 = pci_read_config(device_get_parent(dev), 0x71, 1)) & 254183724Ssos (ch->unit ? 0x08 : 0x04))) { 255183724Ssos pci_write_config(device_get_parent(dev), 0x71, 256183724Ssos reg71 & ~(ch->unit ? 0x04 : 0x08), 1); 257183724Ssos return ata_pci_status(dev); 258183724Ssos } 259183724Ssos return 0; 260183724Ssos} 261183724Ssos 262200171Smavstatic int 263200171Smavata_cmd_setmode(device_t dev, int target, int mode) 264183724Ssos{ 265200171Smav device_t parent = device_get_parent(dev); 266200171Smav struct ata_pci_controller *ctlr = device_get_softc(parent); 267200171Smav struct ata_channel *ch = device_get_softc(dev); 268200171Smav int devno = (ch->unit << 1) + target; 269183724Ssos int treg = 0x54 + ((devno < 3) ? (devno << 1) : 7); 270183724Ssos int ureg = ch->unit ? 0x7b : 0x73; 271200171Smav int piomode; 272233282Smarius static const uint8_t piotimings[] = 273233282Smarius { 0xa9, 0x57, 0x44, 0x32, 0x3f, 0x87, 0x32, 0x3f }; 274233282Smarius static const uint8_t udmatimings[][2] = 275233282Smarius { { 0x31, 0xc2 }, { 0x21, 0x82 }, { 0x11, 0x42 }, 276233282Smarius { 0x25, 0x8a }, { 0x15, 0x4a }, { 0x05, 0x0a } }; 277183724Ssos 278200171Smav mode = min(mode, ctlr->chip->max_dma); 279200171Smav if (mode >= ATA_UDMA0) { 280200171Smav u_int8_t umode = pci_read_config(parent, ureg, 1); 281183724Ssos 282200171Smav umode &= ~(target == 0 ? 0x35 : 0xca); 283200171Smav umode |= udmatimings[mode & ATA_MODE_MASK][target]; 284200171Smav pci_write_config(parent, ureg, umode, 1); 285200171Smav piomode = ATA_PIO4; 286200171Smav } else { 287200171Smav pci_write_config(parent, ureg, 288200171Smav pci_read_config(parent, ureg, 1) & 289200171Smav ~(target == 0 ? 0x35 : 0xca), 1); 290200171Smav piomode = mode; 291183724Ssos } 292200171Smav pci_write_config(parent, treg, piotimings[ata_mode2idx(piomode)], 1); 293200171Smav return (mode); 294183724Ssos} 295183724Ssos 296183724Ssosstatic int 297188765Smavata_sii_ch_attach(device_t dev) 298183724Ssos{ 299183724Ssos struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 300183724Ssos struct ata_channel *ch = device_get_softc(dev); 301183724Ssos int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2); 302183724Ssos int i; 303183724Ssos 304183724Ssos for (i = ATA_DATA; i <= ATA_COMMAND; i++) { 305183724Ssos ch->r_io[i].res = ctlr->r_res2; 306183724Ssos ch->r_io[i].offset = 0x80 + i + (unit01 << 6) + (unit10 << 8); 307183724Ssos } 308183724Ssos ch->r_io[ATA_CONTROL].res = ctlr->r_res2; 309183724Ssos ch->r_io[ATA_CONTROL].offset = 0x8a + (unit01 << 6) + (unit10 << 8); 310183724Ssos ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2; 311183724Ssos ata_default_registers(dev); 312183724Ssos 313183724Ssos ch->r_io[ATA_BMCMD_PORT].res = ctlr->r_res2; 314183724Ssos ch->r_io[ATA_BMCMD_PORT].offset = 0x00 + (unit01 << 3) + (unit10 << 8); 315183724Ssos ch->r_io[ATA_BMSTAT_PORT].res = ctlr->r_res2; 316183724Ssos ch->r_io[ATA_BMSTAT_PORT].offset = 0x02 + (unit01 << 3) + (unit10 << 8); 317183724Ssos ch->r_io[ATA_BMDTP_PORT].res = ctlr->r_res2; 318183724Ssos ch->r_io[ATA_BMDTP_PORT].offset = 0x04 + (unit01 << 3) + (unit10 << 8); 319183724Ssos 320183724Ssos if (ctlr->chip->max_dma >= ATA_SA150) { 321183724Ssos ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 322183724Ssos ch->r_io[ATA_SSTATUS].offset = 0x104 + (unit01 << 7) + (unit10 << 8); 323183724Ssos ch->r_io[ATA_SERROR].res = ctlr->r_res2; 324183724Ssos ch->r_io[ATA_SERROR].offset = 0x108 + (unit01 << 7) + (unit10 << 8); 325183724Ssos ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 326183724Ssos ch->r_io[ATA_SCONTROL].offset = 0x100 + (unit01 << 7) + (unit10 << 8); 327183724Ssos ch->flags |= ATA_NO_SLAVE; 328200171Smav ch->flags |= ATA_SATA; 329212145Smav ch->flags |= ATA_KNOWN_PRESENCE; 330183724Ssos 331183724Ssos /* enable PHY state change interrupt */ 332183724Ssos ATA_OUTL(ctlr->r_res2, 0x148 + (unit01 << 7) + (unit10 << 8),(1 << 16)); 333183724Ssos } 334183724Ssos 335183724Ssos if (ctlr->chip->cfg2 & SII_BUG) { 336183724Ssos /* work around errata in early chips */ 337183724Ssos ch->dma.boundary = 8192; 338183724Ssos ch->dma.segsize = 15 * DEV_BSIZE; 339183724Ssos } 340183724Ssos 341183724Ssos ata_pci_hw(dev); 342183724Ssos ch->hw.status = ata_sii_status; 343200171Smav if (ctlr->chip->cfg2 & SII_SETCLK) 344200171Smav ch->flags |= ATA_CHECKS_CABLE; 345216013Smarius 346216013Smarius ata_pci_dmainit(dev); 347216013Smarius 348183724Ssos return 0; 349183724Ssos} 350183724Ssos 351183724Ssosstatic int 352188769Smavata_sii_ch_detach(device_t dev) 353188769Smav{ 354188769Smav 355188769Smav ata_pci_dmafini(dev); 356188769Smav return (0); 357188769Smav} 358188769Smav 359188769Smavstatic int 360183724Ssosata_sii_status(device_t dev) 361183724Ssos{ 362183724Ssos struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 363183724Ssos struct ata_channel *ch = device_get_softc(dev); 364183724Ssos int offset0 = ((ch->unit & 1) << 3) + ((ch->unit & 2) << 8); 365183724Ssos int offset1 = ((ch->unit & 1) << 6) + ((ch->unit & 2) << 8); 366183724Ssos 367183724Ssos /* do we have any PHY events ? */ 368183724Ssos if (ctlr->chip->max_dma >= ATA_SA150 && 369183724Ssos (ATA_INL(ctlr->r_res2, 0x10 + offset0) & 0x00000010)) 370214016Smav ata_sata_phy_check_events(dev, -1); 371183724Ssos 372183724Ssos if (ATA_INL(ctlr->r_res2, 0xa0 + offset1) & 0x00000800) 373183724Ssos return ata_pci_status(dev); 374183724Ssos else 375183724Ssos return 0; 376183724Ssos} 377183724Ssos 378183724Ssosstatic void 379183724Ssosata_sii_reset(device_t dev) 380183724Ssos{ 381212146Smav struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 382209884Smav struct ata_channel *ch = device_get_softc(dev); 383212146Smav int offset = ((ch->unit & 1) << 7) + ((ch->unit & 2) << 8); 384212146Smav uint32_t val; 385209884Smav 386212146Smav /* Apply R_ERR on DMA activate FIS errata workaround. */ 387212146Smav val = ATA_INL(ctlr->r_res2, 0x14c + offset); 388212146Smav if ((val & 0x3) == 0x1) 389212146Smav ATA_OUTL(ctlr->r_res2, 0x14c + offset, val & ~0x3); 390212146Smav 391190581Smav if (ata_sata_phy_reset(dev, -1, 1)) 392183724Ssos ata_generic_reset(dev); 393209884Smav else 394209884Smav ch->devices = 0; 395183724Ssos} 396183724Ssos 397200171Smavstatic int 398200171Smavata_sii_setmode(device_t dev, int target, int mode) 399183724Ssos{ 400200171Smav device_t parent = device_get_parent(dev); 401200171Smav struct ata_pci_controller *ctlr = device_get_softc(parent); 402200171Smav struct ata_channel *ch = device_get_softc(dev); 403200171Smav int rego = (ch->unit << 4) + (target << 1); 404200171Smav int mreg = ch->unit ? 0x84 : 0x80; 405200171Smav int mask = 0x03 << (target << 2); 406200171Smav int mval = pci_read_config(parent, mreg, 1) & ~mask; 407200171Smav int piomode; 408200171Smav u_int8_t preg = 0xa4 + rego; 409200171Smav u_int8_t dreg = 0xa8 + rego; 410200171Smav u_int8_t ureg = 0xac + rego; 411233282Smarius static const uint16_t piotimings[] = 412233282Smarius { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 }; 413233282Smarius static const uint16_t dmatimings[] = { 0x2208, 0x10c2, 0x10c1 }; 414233282Smarius static const uint8_t udmatimings[] = 415233282Smarius { 0xf, 0xb, 0x7, 0x5, 0x3, 0x2, 0x1 }; 416183724Ssos 417200171Smav mode = min(mode, ctlr->chip->max_dma); 418183724Ssos 419200171Smav if (ctlr->chip->cfg2 & SII_SETCLK) { 420209872Smav if (ata_dma_check_80pin && mode > ATA_UDMA2 && 421209872Smav (pci_read_config(parent, 0x79, 1) & 422183724Ssos (ch->unit ? 0x02 : 0x01))) { 423200171Smav ata_print_cable(dev, "controller"); 424200171Smav mode = ATA_UDMA2; 425200171Smav } 426183724Ssos } 427200171Smav if (mode >= ATA_UDMA0) { 428200171Smav pci_write_config(parent, mreg, 429200171Smav mval | (0x03 << (target << 2)), 1); 430200171Smav pci_write_config(parent, ureg, 431200171Smav (pci_read_config(parent, ureg, 1) & ~0x3f) | 432183724Ssos udmatimings[mode & ATA_MODE_MASK], 1); 433200171Smav piomode = ATA_PIO4; 434200171Smav } else if (mode >= ATA_WDMA0) { 435200171Smav pci_write_config(parent, mreg, 436200171Smav mval | (0x02 << (target << 2)), 1); 437200171Smav pci_write_config(parent, dreg, dmatimings[mode & ATA_MODE_MASK], 2); 438200171Smav piomode = (mode == ATA_WDMA0) ? ATA_PIO0 : 439200171Smav (mode == ATA_WDMA1) ? ATA_PIO3 : ATA_PIO4; 440200171Smav } else { 441200171Smav pci_write_config(parent, mreg, 442200171Smav mval | (0x01 << (target << 2)), 1); 443200171Smav piomode = mode; 444200171Smav } 445200171Smav pci_write_config(parent, preg, piotimings[ata_mode2idx(piomode)], 2); 446200171Smav return (mode); 447183724Ssos} 448183724Ssos 449183724Ssosstruct ata_siiprb_dma_prdentry { 450183724Ssos u_int64_t addr; 451183724Ssos u_int32_t count; 452183724Ssos u_int32_t control; 453183724Ssos} __packed; 454183724Ssos 455198717Smav#define ATA_SIIPRB_DMA_ENTRIES 129 456183724Ssosstruct ata_siiprb_ata_command { 457183724Ssos struct ata_siiprb_dma_prdentry prd[ATA_SIIPRB_DMA_ENTRIES]; 458183724Ssos} __packed; 459183724Ssos 460183724Ssosstruct ata_siiprb_atapi_command { 461183724Ssos u_int8_t ccb[16]; 462183724Ssos struct ata_siiprb_dma_prdentry prd[ATA_SIIPRB_DMA_ENTRIES]; 463183724Ssos} __packed; 464183724Ssos 465183724Ssosstruct ata_siiprb_command { 466183724Ssos u_int16_t control; 467183724Ssos u_int16_t protocol_override; 468183724Ssos u_int32_t transfer_count; 469183724Ssos u_int8_t fis[24]; 470183724Ssos union { 471183724Ssos struct ata_siiprb_ata_command ata; 472183724Ssos struct ata_siiprb_atapi_command atapi; 473183724Ssos } u; 474183724Ssos} __packed; 475183724Ssos 476183724Ssosstatic int 477188765Smavata_siiprb_ch_attach(device_t dev) 478183724Ssos{ 479183724Ssos struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 480183724Ssos struct ata_channel *ch = device_get_softc(dev); 481183724Ssos int offset = ch->unit * 0x2000; 482183724Ssos 483188765Smav ata_siiprb_dmainit(dev); 484188765Smav 485183724Ssos /* set the SATA resources */ 486183724Ssos ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 487183724Ssos ch->r_io[ATA_SSTATUS].offset = 0x1f04 + offset; 488183724Ssos ch->r_io[ATA_SERROR].res = ctlr->r_res2; 489183724Ssos ch->r_io[ATA_SERROR].offset = 0x1f08 + offset; 490183724Ssos ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 491183724Ssos ch->r_io[ATA_SCONTROL].offset = 0x1f00 + offset; 492183724Ssos ch->r_io[ATA_SACTIVE].res = ctlr->r_res2; 493183724Ssos ch->r_io[ATA_SACTIVE].offset = 0x1f0c + offset; 494183724Ssos 495183724Ssos ch->hw.status = ata_siiprb_status; 496183724Ssos ch->hw.begin_transaction = ata_siiprb_begin_transaction; 497183724Ssos ch->hw.end_transaction = ata_siiprb_end_transaction; 498183724Ssos ch->hw.command = NULL; /* not used here */ 499183724Ssos ch->hw.softreset = ata_siiprb_softreset; 500183724Ssos ch->hw.pm_read = ata_siiprb_pm_read; 501183724Ssos ch->hw.pm_write = ata_siiprb_pm_write; 502203525Smav ch->flags |= ATA_NO_SLAVE; 503203525Smav ch->flags |= ATA_SATA; 504183724Ssos return 0; 505183724Ssos} 506183724Ssos 507183724Ssosstatic int 508188769Smavata_siiprb_ch_detach(device_t dev) 509188769Smav{ 510219338Smarius struct ata_channel *ch = device_get_softc(dev); 511188769Smav 512219338Smarius if (ch->dma.work_tag && ch->dma.work_map) 513219338Smarius bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, 514219338Smarius BUS_DMASYNC_POSTWRITE); 515188769Smav ata_dmafini(dev); 516188769Smav return 0; 517188769Smav} 518188769Smav 519188769Smavstatic int 520183724Ssosata_siiprb_status(device_t dev) 521183724Ssos{ 522183724Ssos struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 523183724Ssos struct ata_channel *ch = device_get_softc(dev); 524183724Ssos u_int32_t action = ATA_INL(ctlr->r_res1, 0x0044); 525183724Ssos int offset = ch->unit * 0x2000; 526183724Ssos 527183724Ssos if (action & (1 << ch->unit)) { 528183724Ssos u_int32_t istatus = ATA_INL(ctlr->r_res2, 0x1008 + offset); 529183724Ssos 530183724Ssos /* do we have any PHY events ? */ 531214016Smav ata_sata_phy_check_events(dev, -1); 532183724Ssos 533183724Ssos /* clear interrupt(s) */ 534183724Ssos ATA_OUTL(ctlr->r_res2, 0x1008 + offset, istatus); 535183724Ssos 536183724Ssos /* do we have any device action ? */ 537183724Ssos return (istatus & 0x00000003); 538183724Ssos } 539183724Ssos return 0; 540183724Ssos} 541183724Ssos 542183724Ssosstatic int 543183724Ssosata_siiprb_begin_transaction(struct ata_request *request) 544183724Ssos{ 545198717Smav struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent)); 546183724Ssos struct ata_channel *ch = device_get_softc(request->parent); 547183724Ssos struct ata_siiprb_command *prb; 548183724Ssos struct ata_siiprb_dma_prdentry *prd; 549183724Ssos int offset = ch->unit * 0x2000; 550183724Ssos u_int64_t prb_bus; 551183724Ssos 552183724Ssos /* SOS XXX */ 553183724Ssos if (request->u.ata.command == ATA_DEVICE_RESET) { 554183724Ssos request->result = 0; 555183724Ssos return ATA_OP_FINISHED; 556183724Ssos } 557183724Ssos 558183724Ssos /* get a piece of the workspace for this request */ 559198717Smav prb = (struct ata_siiprb_command *)ch->dma.work; 560183724Ssos 561183724Ssos /* clear the prb structure */ 562183724Ssos bzero(prb, sizeof(struct ata_siiprb_command)); 563183724Ssos 564183724Ssos /* setup the FIS for this request */ 565183724Ssos if (!ata_request2fis_h2d(request, &prb->fis[0])) { 566198717Smav device_printf(request->parent, "setting up SATA FIS failed\n"); 567183724Ssos request->result = EIO; 568183724Ssos return ATA_OP_FINISHED; 569183724Ssos } 570183724Ssos 571183724Ssos /* setup transfer type */ 572183724Ssos if (request->flags & ATA_R_ATAPI) { 573183724Ssos bcopy(request->u.atapi.ccb, prb->u.atapi.ccb, 16); 574198717Smav if (request->flags & ATA_R_ATAPI16) 575198717Smav ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000020); 576198717Smav else 577183724Ssos ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000020); 578183724Ssos if (request->flags & ATA_R_READ) 579183724Ssos prb->control = htole16(0x0010); 580183724Ssos if (request->flags & ATA_R_WRITE) 581183724Ssos prb->control = htole16(0x0020); 582183724Ssos prd = &prb->u.atapi.prd[0]; 583183724Ssos } 584183724Ssos else 585183724Ssos prd = &prb->u.ata.prd[0]; 586183724Ssos 587183724Ssos /* if request moves data setup and load SG list */ 588183724Ssos if (request->flags & (ATA_R_READ | ATA_R_WRITE)) { 589183724Ssos if (ch->dma.load(request, prd, NULL)) { 590198717Smav device_printf(request->parent, "setting up DMA failed\n"); 591183724Ssos request->result = EIO; 592183724Ssos return ATA_OP_FINISHED; 593183724Ssos } 594183724Ssos } 595183724Ssos 596219338Smarius bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, BUS_DMASYNC_PREWRITE); 597219338Smarius 598183724Ssos /* activate the prb */ 599198717Smav prb_bus = ch->dma.work_bus; 600198717Smav ATA_OUTL(ctlr->r_res2, 0x1c00 + offset, prb_bus); 601198717Smav ATA_OUTL(ctlr->r_res2, 0x1c04 + offset, prb_bus>>32); 602183724Ssos 603183724Ssos /* start the timeout */ 604183724Ssos callout_reset(&request->callout, request->timeout * hz, 605183724Ssos (timeout_t*)ata_timeout, request); 606183724Ssos return ATA_OP_CONTINUES; 607183724Ssos} 608183724Ssos 609183724Ssosstatic int 610183724Ssosata_siiprb_end_transaction(struct ata_request *request) 611183724Ssos{ 612198717Smav struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent)); 613183724Ssos struct ata_channel *ch = device_get_softc(request->parent); 614183724Ssos struct ata_siiprb_command *prb; 615183724Ssos int offset = ch->unit * 0x2000; 616183724Ssos int error, timeout; 617183724Ssos 618183724Ssos /* kill the timeout */ 619183724Ssos callout_stop(&request->callout); 620219338Smarius 621219338Smarius bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, BUS_DMASYNC_POSTWRITE); 622219338Smarius 623183724Ssos prb = (struct ata_siiprb_command *) 624198717Smav ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset); 625183724Ssos 626183724Ssos /* any controller errors flagged ? */ 627183724Ssos if ((error = ATA_INL(ctlr->r_res2, 0x1024 + offset))) { 628183724Ssos if (bootverbose) 629183724Ssos printf("ata_siiprb_end_transaction %s error=%08x\n", 630183724Ssos ata_cmd2str(request), error); 631183724Ssos 632183724Ssos /* if device error status get details */ 633183724Ssos if (error == 1 || error == 2) { 634183724Ssos request->status = prb->fis[2]; 635183724Ssos if (request->status & ATA_S_ERROR) 636183724Ssos request->error = prb->fis[3]; 637183724Ssos } 638183724Ssos 639183724Ssos /* SOS XXX handle other controller errors here */ 640183724Ssos 641183724Ssos /* initialize port */ 642183724Ssos ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000004); 643183724Ssos 644183724Ssos /* poll for port ready */ 645183724Ssos for (timeout = 0; timeout < 1000; timeout++) { 646183724Ssos DELAY(1000); 647183724Ssos if (ATA_INL(ctlr->r_res2, 0x1008 + offset) & 0x00040000) 648183724Ssos break; 649183724Ssos } 650183724Ssos if (bootverbose) { 651183724Ssos if (timeout >= 1000) 652183724Ssos device_printf(ch->dev, "port initialize timeout\n"); 653183724Ssos else 654183724Ssos device_printf(ch->dev, "port initialize time=%dms\n", timeout); 655183724Ssos } 656183724Ssos } 657183724Ssos 658242156Smav /* Read back registers to the request struct. */ 659242156Smav if ((request->flags & ATA_R_ATAPI) == 0 && 660242156Smav ((request->status & ATA_S_ERROR) || 661242156Smav (request->flags & (ATA_R_CONTROL | ATA_R_NEEDRESULT)))) { 662183724Ssos request->u.ata.count = prb->fis[12] | ((u_int16_t)prb->fis[13] << 8); 663183724Ssos request->u.ata.lba = prb->fis[4] | ((u_int64_t)prb->fis[5] << 8) | 664183724Ssos ((u_int64_t)prb->fis[6] << 16); 665198717Smav if (request->flags & ATA_R_48BIT) 666183724Ssos request->u.ata.lba |= ((u_int64_t)prb->fis[8] << 24) | 667183724Ssos ((u_int64_t)prb->fis[9] << 32) | 668183724Ssos ((u_int64_t)prb->fis[10] << 40); 669183724Ssos else 670183724Ssos request->u.ata.lba |= ((u_int64_t)(prb->fis[7] & 0x0f) << 24); 671183724Ssos } 672183724Ssos 673183724Ssos /* update progress */ 674183724Ssos if (!(request->status & ATA_S_ERROR) && !(request->flags & ATA_R_TIMEOUT)) { 675183724Ssos if (request->flags & ATA_R_READ) 676213047Sjchandra request->donecount = le32toh(prb->transfer_count); 677183724Ssos else 678183724Ssos request->donecount = request->bytecount; 679183724Ssos } 680183724Ssos 681183724Ssos /* release SG list etc */ 682183724Ssos ch->dma.unload(request); 683183724Ssos 684183724Ssos return ATA_OP_FINISHED; 685183724Ssos} 686183724Ssos 687183724Ssosstatic int 688183724Ssosata_siiprb_issue_cmd(device_t dev) 689183724Ssos{ 690183724Ssos struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 691183724Ssos struct ata_channel *ch = device_get_softc(dev); 692183724Ssos u_int64_t prb_bus = ch->dma.work_bus; 693183724Ssos u_int32_t status; 694183724Ssos int offset = ch->unit * 0x2000; 695183724Ssos int timeout; 696183724Ssos 697219338Smarius bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, BUS_DMASYNC_PREWRITE); 698219338Smarius 699183724Ssos /* issue command to chip */ 700183724Ssos ATA_OUTL(ctlr->r_res2, 0x1c00 + offset, prb_bus); 701183724Ssos ATA_OUTL(ctlr->r_res2, 0x1c04 + offset, prb_bus >> 32); 702183724Ssos 703183724Ssos /* poll for command finished */ 704183724Ssos for (timeout = 0; timeout < 10000; timeout++) { 705183724Ssos DELAY(1000); 706183724Ssos if ((status = ATA_INL(ctlr->r_res2, 0x1008 + offset)) & 0x00010000) 707183724Ssos break; 708183724Ssos } 709219338Smarius 710219338Smarius bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, BUS_DMASYNC_POSTWRITE); 711219338Smarius 712183724Ssos // SOS XXX ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x00010000); 713183724Ssos ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x08ff08ff); 714183724Ssos 715183724Ssos if (timeout >= 1000) 716183724Ssos return EIO; 717183724Ssos 718183724Ssos if (bootverbose) 719183724Ssos device_printf(dev, "siiprb_issue_cmd time=%dms status=%08x\n", 720183724Ssos timeout, status); 721183724Ssos return 0; 722183724Ssos} 723183724Ssos 724183724Ssosstatic int 725183724Ssosata_siiprb_pm_read(device_t dev, int port, int reg, u_int32_t *result) 726183724Ssos{ 727183724Ssos struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 728183724Ssos struct ata_channel *ch = device_get_softc(dev); 729183724Ssos struct ata_siiprb_command *prb = (struct ata_siiprb_command *)ch->dma.work; 730183724Ssos int offset = ch->unit * 0x2000; 731183724Ssos 732214016Smav if (port < 0) { 733214016Smav *result = ATA_IDX_INL(ch, reg); 734214016Smav return (0); 735214016Smav } 736214016Smav if (port < ATA_PM) { 737214016Smav switch (reg) { 738214016Smav case ATA_SSTATUS: 739214016Smav reg = 0; 740214016Smav break; 741214016Smav case ATA_SERROR: 742214016Smav reg = 1; 743214016Smav break; 744214016Smav case ATA_SCONTROL: 745214016Smav reg = 2; 746214016Smav break; 747214016Smav default: 748214016Smav return (EINVAL); 749214016Smav } 750214016Smav } 751183724Ssos bzero(prb, sizeof(struct ata_siiprb_command)); 752183724Ssos prb->fis[0] = 0x27; /* host to device */ 753183724Ssos prb->fis[1] = 0x8f; /* command FIS to PM port */ 754183724Ssos prb->fis[2] = ATA_READ_PM; 755183724Ssos prb->fis[3] = reg; 756183724Ssos prb->fis[7] = port; 757183724Ssos if (ata_siiprb_issue_cmd(dev)) { 758183724Ssos device_printf(dev, "error reading PM port\n"); 759183724Ssos return EIO; 760183724Ssos } 761183724Ssos prb = (struct ata_siiprb_command *) 762183724Ssos ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset); 763183724Ssos *result = prb->fis[12]|(prb->fis[4]<<8)|(prb->fis[5]<<16)|(prb->fis[6]<<24); 764183724Ssos return 0; 765183724Ssos} 766183724Ssos 767183724Ssosstatic int 768183724Ssosata_siiprb_pm_write(device_t dev, int port, int reg, u_int32_t value) 769183724Ssos{ 770183724Ssos struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 771183724Ssos struct ata_channel *ch = device_get_softc(dev); 772183724Ssos struct ata_siiprb_command *prb = (struct ata_siiprb_command *)ch->dma.work; 773183724Ssos int offset = ch->unit * 0x2000; 774183724Ssos 775214016Smav if (port < 0) { 776214016Smav ATA_IDX_OUTL(ch, reg, value); 777214016Smav return (0); 778214016Smav } 779214016Smav if (port < ATA_PM) { 780214016Smav switch (reg) { 781214016Smav case ATA_SSTATUS: 782214016Smav reg = 0; 783214016Smav break; 784214016Smav case ATA_SERROR: 785214016Smav reg = 1; 786214016Smav break; 787214016Smav case ATA_SCONTROL: 788214016Smav reg = 2; 789214016Smav break; 790214016Smav default: 791214016Smav return (EINVAL); 792214016Smav } 793214016Smav } 794183724Ssos bzero(prb, sizeof(struct ata_siiprb_command)); 795183724Ssos prb->fis[0] = 0x27; /* host to device */ 796183724Ssos prb->fis[1] = 0x8f; /* command FIS to PM port */ 797183724Ssos prb->fis[2] = ATA_WRITE_PM; 798183724Ssos prb->fis[3] = reg; 799183724Ssos prb->fis[7] = port; 800183724Ssos prb->fis[12] = value & 0xff; 801201758Smbr prb->fis[4] = (value >> 8) & 0xff; 802201758Smbr prb->fis[5] = (value >> 16) & 0xff; 803201758Smbr prb->fis[6] = (value >> 24) & 0xff; 804183724Ssos if (ata_siiprb_issue_cmd(dev)) { 805183724Ssos device_printf(dev, "error writing PM port\n"); 806183724Ssos return ATA_E_ABORT; 807183724Ssos } 808183724Ssos prb = (struct ata_siiprb_command *) 809183724Ssos ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset); 810183724Ssos return prb->fis[3]; 811183724Ssos} 812183724Ssos 813183724Ssosstatic u_int32_t 814183724Ssosata_siiprb_softreset(device_t dev, int port) 815183724Ssos{ 816183724Ssos struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 817183724Ssos struct ata_channel *ch = device_get_softc(dev); 818183724Ssos struct ata_siiprb_command *prb = (struct ata_siiprb_command *)ch->dma.work; 819183724Ssos u_int32_t signature; 820183724Ssos int offset = ch->unit * 0x2000; 821183724Ssos 822183724Ssos /* setup the workspace for a soft reset command */ 823183724Ssos bzero(prb, sizeof(struct ata_siiprb_command)); 824183724Ssos prb->control = htole16(0x0080); 825183724Ssos prb->fis[1] = port & 0x0f; 826183724Ssos 827183724Ssos /* issue soft reset */ 828183724Ssos if (ata_siiprb_issue_cmd(dev)) 829183724Ssos return -1; 830183724Ssos 831183724Ssos ata_udelay(150000); 832183724Ssos 833183724Ssos /* get possible signature */ 834183724Ssos prb = (struct ata_siiprb_command *) 835183724Ssos ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset); 836183724Ssos signature=prb->fis[12]|(prb->fis[4]<<8)|(prb->fis[5]<<16)|(prb->fis[6]<<24); 837183724Ssos 838183724Ssos /* clear error bits/interrupt */ 839183724Ssos ATA_IDX_OUTL(ch, ATA_SERROR, 0xffffffff); 840183724Ssos 841183724Ssos return signature; 842183724Ssos} 843183724Ssos 844183724Ssosstatic void 845183724Ssosata_siiprb_reset(device_t dev) 846183724Ssos{ 847183724Ssos struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 848183724Ssos struct ata_channel *ch = device_get_softc(dev); 849183724Ssos int offset = ch->unit * 0x2000; 850183724Ssos u_int32_t status, signature; 851183724Ssos int timeout; 852183724Ssos 853183724Ssos /* disable interrupts */ 854183724Ssos ATA_OUTL(ctlr->r_res2, 0x1014 + offset, 0x000000ff); 855183724Ssos 856183724Ssos /* reset channel HW */ 857183724Ssos ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000001); 858183724Ssos DELAY(1000); 859183724Ssos ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000001); 860183724Ssos DELAY(10000); 861183724Ssos 862183724Ssos /* poll for channel ready */ 863183724Ssos for (timeout = 0; timeout < 1000; timeout++) { 864183724Ssos if ((status = ATA_INL(ctlr->r_res2, 0x1008 + offset)) & 0x00040000) 865183724Ssos break; 866183724Ssos DELAY(1000); 867183724Ssos } 868183724Ssos 869183724Ssos if (bootverbose) { 870183724Ssos if (timeout >= 1000) 871183724Ssos device_printf(dev, "channel HW reset timeout\n"); 872183724Ssos else 873183724Ssos device_printf(dev, "channel HW reset time=%dms\n", timeout); 874183724Ssos } 875183724Ssos 876183724Ssos /* reset phy */ 877190581Smav if (!ata_sata_phy_reset(dev, -1, 1)) { 878183724Ssos if (bootverbose) 879183724Ssos device_printf(dev, "phy reset found no device\n"); 880183724Ssos ch->devices = 0; 881183724Ssos goto finish; 882183724Ssos } 883183724Ssos 884183724Ssos /* issue soft reset */ 885183724Ssos signature = ata_siiprb_softreset(dev, ATA_PM); 886183724Ssos if (bootverbose) 887183724Ssos device_printf(dev, "SIGNATURE=%08x\n", signature); 888183724Ssos 889183724Ssos /* figure out whats there */ 890188906Smav switch (signature >> 16) { 891188906Smav case 0x0000: 892183724Ssos ch->devices = ATA_ATA_MASTER; 893183724Ssos break; 894188906Smav case 0x9669: 895183724Ssos ch->devices = ATA_PORTMULTIPLIER; 896183724Ssos ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x2000); /* enable PM support */ 897183724Ssos //SOS XXX need to clear all PM status and interrupts!!!! 898183724Ssos ata_pm_identify(dev); 899183724Ssos break; 900188906Smav case 0xeb14: 901183724Ssos ch->devices = ATA_ATAPI_MASTER; 902183724Ssos break; 903183724Ssos default: 904183724Ssos ch->devices = 0; 905183724Ssos } 906183724Ssos if (bootverbose) 907183724Ssos device_printf(dev, "siiprb_reset devices=%08x\n", ch->devices); 908183724Ssos 909183724Ssosfinish: 910183724Ssos /* clear interrupt(s) */ 911183724Ssos ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x000008ff); 912183724Ssos 913183724Ssos /* require explicit interrupt ack */ 914183724Ssos ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000008); 915183724Ssos 916183724Ssos /* 64bit mode */ 917183724Ssos ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000400); 918183724Ssos 919183724Ssos /* enable interrupts wanted */ 920183724Ssos ATA_OUTL(ctlr->r_res2, 0x1010 + offset, 0x000000ff); 921183724Ssos} 922183724Ssos 923183724Ssosstatic void 924183724Ssosata_siiprb_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 925183724Ssos{ 926183724Ssos struct ata_dmasetprd_args *args = xsc; 927183724Ssos struct ata_siiprb_dma_prdentry *prd = args->dmatab; 928183724Ssos int i; 929183724Ssos 930183724Ssos if ((args->error = error)) 931183724Ssos return; 932183724Ssos 933183724Ssos for (i = 0; i < nsegs; i++) { 934183724Ssos prd[i].addr = htole64(segs[i].ds_addr); 935183724Ssos prd[i].count = htole32(segs[i].ds_len); 936183724Ssos } 937183724Ssos prd[i - 1].control = htole32(ATA_DMA_EOT); 938183724Ssos KASSERT(nsegs <= ATA_SIIPRB_DMA_ENTRIES,("too many DMA segment entries\n")); 939183724Ssos args->nsegs = nsegs; 940183724Ssos} 941183724Ssos 942183724Ssosstatic void 943183724Ssosata_siiprb_dmainit(device_t dev) 944183724Ssos{ 945183724Ssos struct ata_channel *ch = device_get_softc(dev); 946183724Ssos 947183724Ssos /* note start and stop are not used here */ 948183724Ssos ch->dma.setprd = ata_siiprb_dmasetprd; 949183724Ssos ch->dma.max_address = BUS_SPACE_MAXADDR; 950198717Smav ch->dma.max_iosize = (ATA_SIIPRB_DMA_ENTRIES - 1) * PAGE_SIZE; 951216013Smarius ata_dmainit(dev); 952183724Ssos} 953183724Ssos 954183724SsosATA_DECLARE_DRIVER(ata_sii); 955